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463 lines
8.7 KiB
463 lines
8.7 KiB
8 months ago
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// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
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/*
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* Copyright (c) 2024 FriendlyElec Computer Tech. Co., Ltd.
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* (http://www.friendlyelec.com)
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*
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* Copyright (c) 2021 Rockchip Electronics Co., Ltd.
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*/
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/dts-v1/;
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#include "rk3588-nanopi6-common.dtsi"
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/ {
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model = "FriendlyElec NanoPi M6";
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compatible = "friendlyelec,nanopi-m6", "rockchip,rk3588";
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aliases {
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ethernet0 = &gmac1;
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};
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rt5616_sound: rt5616-sound {
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status = "okay";
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compatible = "simple-audio-card";
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pinctrl-names = "default";
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pinctrl-0 = <&hp_det>;
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simple-audio-card,name = "realtek,rt5616-codec";
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simple-audio-card,format = "i2s";
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simple-audio-card,mclk-fs = <256>;
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simple-audio-card,hp-det-gpio = <&gpio1 RK_PC4 GPIO_ACTIVE_LOW>;
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simple-audio-card,hp-pin-name = "Headphone Jack";
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simple-audio-card,widgets =
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"Headphone", "Headphone Jack",
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"Microphone", "Microphone Jack";
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simple-audio-card,routing =
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"Headphone Jack", "HPOL",
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"Headphone Jack", "HPOR",
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"MIC1", "Microphone Jack",
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"Microphone Jack", "micbias1";
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simple-audio-card,cpu {
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sound-dai = <&i2s0_8ch>;
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};
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simple-audio-card,codec {
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sound-dai = <&rt5616>;
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};
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};
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fan: pwm-fan {
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status = "okay";
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compatible = "pwm-fan";
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#cooling-cells = <2>;
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fan-supply = <&vcc5v0_sys>;
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pwms = <&pwm5 0 50000 0>;
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cooling-levels = <0 45 70 110 160 255>;
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rockchip,hold-time-ms = <2000>;
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rockchip,temp-trips = <
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50000 1
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55000 2
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60000 3
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65000 4
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70000 5
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>;
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};
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adc_keys: adc-keys {
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compatible = "adc-keys";
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io-channels = <&saradc 1>;
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io-channel-names = "buttons";
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keyup-threshold-microvolt = <1800000>;
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poll-interval = <100>;
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vol-up-key {
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label = "volume up";
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linux,code = <KEY_VOLUMEUP>;
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press-threshold-microvolt = <17000>;
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};
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};
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gpio_leds: gpio-leds {
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compatible = "gpio-leds";
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sys_led: led-0 {
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gpios = <&gpio1 RK_PA4 GPIO_ACTIVE_HIGH>;
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label = "sys_led";
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linux,default-trigger = "heartbeat";
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pinctrl-names = "default";
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pinctrl-0 = <&sys_led_pin>;
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};
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user_led: led-1 {
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gpios = <&gpio1 RK_PA6 GPIO_ACTIVE_HIGH>;
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label = "user_led";
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pinctrl-names = "default";
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pinctrl-0 = <&user_led_pin>;
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};
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};
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vcc3v3_pcie_m2: vcc3v3-pcie30 {
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compatible = "regulator-fixed";
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enable-active-high;
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gpios = <&gpio3 RK_PC6 GPIO_ACTIVE_HIGH>;
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pinctrl-names = "default";
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pinctrl-0 = <&pcie_m2_0_pwren>;
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regulator-name = "vcc3v3_pcie_m2";
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regulator-min-microvolt = <3300000>;
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regulator-max-microvolt = <3300000>;
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vin-supply = <&vcc5v0_sys>;
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};
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vcc5v0_host_20: vcc5v0-host-20 {
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compatible = "regulator-fixed";
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enable-active-high;
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gpio = <&gpio4 RK_PB5 GPIO_ACTIVE_HIGH>;
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pinctrl-names = "default";
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pinctrl-0 = <&vcc5v0_host20_en>;
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regulator-name = "vcc5v0_host_20";
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regulator-min-microvolt = <5000000>;
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regulator-max-microvolt = <5000000>;
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vin-supply = <&vcc5v0_usb>;
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};
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vbus5v0_typec: vbus5v0-typec {
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compatible = "regulator-fixed";
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enable-active-high;
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gpio = <&gpio3 RK_PD4 GPIO_ACTIVE_HIGH>;
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pinctrl-names = "default";
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pinctrl-0 = <&typec5v_pwren>;
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regulator-name = "vbus5v0_typec";
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regulator-min-microvolt = <5000000>;
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regulator-max-microvolt = <5000000>;
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vin-supply = <&vcc5v0_usb>;
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};
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};
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&mach {
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hwrev = <0x0a>;
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model = "NanoPi M6";
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};
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&pcie2x1l1 {
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rockchip,skip-hw-retry;
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};
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&pcie2x1l2 {
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pinctrl-names = "default";
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pinctrl-0 = <&pcie_m2_0_prsnt>;
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prsnt-gpios = <&gpio4 RK_PA5 GPIO_ACTIVE_HIGH>;
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phys = <&combphy0_ps PHY_TYPE_PCIE 0>;
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rockchip,skip-hw-retry;
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vpcie3v3-supply = <&vcc3v3_pcie_m2>;
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status = "okay";
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};
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&combphy0_ps {
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#phy-cells = <2>;
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rockchip,ebuff-mode;
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status = "okay";
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};
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&sata0 {
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phys = <&combphy0_ps PHY_TYPE_SATA 1>;
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target-supply = <&vcc3v3_pcie_m2>;
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status = "okay";
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};
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&pinctrl {
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gpio-leds {
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sys_led_pin: sys-led-pin {
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rockchip,pins =
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<1 RK_PA4 RK_FUNC_GPIO &pcfg_pull_none>;
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};
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user_led_pin: lan1-led-pin {
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rockchip,pins =
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<1 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>;
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};
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};
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headphone {
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hp_det: hp-det {
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rockchip,pins = <1 RK_PC4 RK_FUNC_GPIO &pcfg_pull_none>;
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};
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};
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lcd {
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/omit-if-no-ref/
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lcd_rst0_gpio: lcd-rst0-gpio {
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rockchip,pins = <3 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>;
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};
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/omit-if-no-ref/
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lcd_rst1_gpio: lcd-rst1-gpio {
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rockchip,pins = <4 RK_PA1 RK_FUNC_GPIO &pcfg_pull_none>;
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};
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/omit-if-no-ref/
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touch_dsi0_gpio: touch-dsi0-gpio {
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rockchip,pins =
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<3 RK_PC0 RK_FUNC_GPIO &pcfg_pull_up>,
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<3 RK_PC1 RK_FUNC_GPIO &pcfg_pull_none>;
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};
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/omit-if-no-ref/
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touch_dsi1_gpio: touch-dsi1-gpio {
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rockchip,pins =
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<4 RK_PA0 RK_FUNC_GPIO &pcfg_pull_up>,
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<4 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>;
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};
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};
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pcie {
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pcie_m2_0_pwren: pcie-m20-pwren {
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rockchip,pins = <3 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>;
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};
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pcie_m2_0_prsnt: pcie-m20-prsnt {
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rockchip,pins = <4 RK_PA5 RK_FUNC_GPIO &pcfg_pull_up>;
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};
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};
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usb {
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typec5v_pwren: typec5v-pwren {
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rockchip,pins = <3 RK_PD4 RK_FUNC_GPIO &pcfg_pull_none>;
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};
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vcc5v0_host20_en: vcc5v0-host20-en {
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rockchip,pins = <4 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>;
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};
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};
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};
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dsi0_i2c: &i2c4 {
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clock-frequency = <200000>;
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pinctrl-0 = <&i2c4m3_xfer>;
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};
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dsi1_i2c: &i2c5 {
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clock-frequency = <200000>;
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pinctrl-0 = <&i2c5m2_xfer>;
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};
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&i2c6 {
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clock-frequency = <200000>;
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status = "okay";
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eeprom@53 {
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compatible = "microchip,24c02", "atmel,24c02";
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reg = <0x53>;
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#address-cells = <2>;
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#size-cells = <0>;
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pagesize = <16>;
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size = <256>;
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eui_48: eui-48@fa {
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reg = <0xfa 0x06>;
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};
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};
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};
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&i2c7 {
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clock-frequency = <200000>;
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status = "okay";
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rt5616: rt5616@1b {
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status = "okay";
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#sound-dai-cells = <0>;
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compatible = "rt5616";
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reg = <0x1b>;
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clocks = <&mclkout_i2s0>;
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clock-names = "mclk";
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assigned-clocks = <&mclkout_i2s0>;
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assigned-clock-rates = <12288000>;
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pinctrl-names = "default";
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pinctrl-0 = <&i2s0_mclk>;
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};
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/* connected with MIPI-CSI1 */
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};
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&i2s0_8ch {
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status = "okay";
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pinctrl-0 = <&i2s0_lrck
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&i2s0_sclk
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&i2s0_sdi0
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&i2s0_sdo0>;
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rockchip,trcm-sync-tx-only;
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};
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&pwm5 {
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pinctrl-0 = <&pwm5m1_pins>;
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status = "okay";
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};
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dsi0_pwm: &pwm10 {
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pinctrl-0 = <&pwm10m2_pins>;
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};
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dsi1_pwm: &pwm11 {
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pinctrl-0 = <&pwm11m3_pins>;
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};
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&u2phy0 {
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status = "okay";
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};
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&u2phy0_otg {
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phy-supply = <&vbus5v0_typec>;
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status = "okay";
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};
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&u2phy2 {
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status = "okay";
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};
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&u2phy2_host {
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phy-supply = <&vcc5v0_host_20>;
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status = "okay";
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};
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&u2phy3 {
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status = "okay";
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};
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&u2phy3_host {
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status = "okay";
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};
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&usb_host1_ehci {
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status = "okay";
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};
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&usb_host1_ohci {
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status = "okay";
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};
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/* MIPI-CSI */
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#define ENABLE_MIPI_DCSI0 0
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#if (ENABLE_MIPI_CSI0)
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#include "rk3588-nanopi6-csi0-imx415.dtsi"
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&imx415p0 {
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power-gpios = <&gpio1 RK_PD5 GPIO_ACTIVE_HIGH>;
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reset-gpios = <&gpio1 RK_PC6 GPIO_ACTIVE_LOW>;
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};
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#endif
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#if (ENABLE_MIPI_DCSI0)
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#include "rk3588-nanopi6-dcsi0-imx415.dtsi"
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#endif
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/* MIPI-DSI */
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#define ENABLE_MIPI_DSI1 1
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#include "rk3588-nanopi6-mipi-lcd-yx35.dtsi"
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#include "rk3588-nanopi6-mipi-dsi-sel.dtsi"
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#if defined(ENABLE_MIPI_DSI0)
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&dsi0_panel {
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reset-gpios = <&gpio3 RK_PD2 GPIO_ACTIVE_LOW>;
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};
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&dsi0_gt1x {
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compatible = "goodix,gt1x", "goodix,gt9xx";
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interrupt-parent = <&gpio3>;
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interrupts = <RK_PC0 IRQ_TYPE_EDGE_FALLING>;
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goodix,irq-gpio = <&gpio3 RK_PC0 IRQ_TYPE_EDGE_FALLING>;
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goodix,rst-gpio = <&gpio3 RK_PC1 GPIO_ACTIVE_HIGH>;
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status = "okay";
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};
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&dsi0_gt9xx {
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||
|
|
interrupt-parent = <&gpio3>;
|
||
|
|
interrupts = <RK_PC0 IRQ_TYPE_EDGE_FALLING>;
|
||
|
|
goodix,irq-gpio = <&gpio3 RK_PC0 IRQ_TYPE_EDGE_FALLING>;
|
||
|
|
goodix,rst-gpio = <&gpio3 RK_PC1 GPIO_ACTIVE_HIGH>;
|
||
|
|
};
|
||
|
|
#endif
|
||
|
|
|
||
|
|
#if defined(ENABLE_MIPI_DSI1)
|
||
|
|
&dsi1_panel {
|
||
|
|
reset-gpios = <&gpio4 RK_PA1 GPIO_ACTIVE_LOW>;
|
||
|
|
};
|
||
|
|
|
||
|
|
&dsi1_gt1x {
|
||
|
|
compatible = "goodix,gt1x", "goodix,gt9xx";
|
||
|
|
interrupt-parent = <&gpio4>;
|
||
|
|
interrupts = <RK_PA0 IRQ_TYPE_EDGE_FALLING>;
|
||
|
|
goodix,irq-gpio = <&gpio4 RK_PA0 IRQ_TYPE_EDGE_FALLING>;
|
||
|
|
goodix,rst-gpio = <&gpio4 RK_PA2 GPIO_ACTIVE_HIGH>;
|
||
|
|
status = "okay";
|
||
|
|
};
|
||
|
|
|
||
|
|
&dsi1_gt9xx {
|
||
|
|
interrupt-parent = <&gpio4>;
|
||
|
|
interrupts = <RK_PA0 IRQ_TYPE_EDGE_FALLING>;
|
||
|
|
goodix,irq-gpio = <&gpio4 RK_PA0 IRQ_TYPE_EDGE_FALLING>;
|
||
|
|
goodix,rst-gpio = <&gpio4 RK_PA2 GPIO_ACTIVE_HIGH>;
|
||
|
|
};
|
||
|
|
#endif
|
||
|
|
|
||
|
|
#undef ENABLE_MIPI_DSI1
|
||
|
|
|
||
|
|
/* GPIO Connector */
|
||
|
|
&i2c1 {
|
||
|
|
pinctrl-0 = <&i2c1m2_xfer>;
|
||
|
|
status = "disabled";
|
||
|
|
};
|
||
|
|
|
||
|
|
&i2c8 {
|
||
|
|
pinctrl-0 = <&i2c8m2_xfer>;
|
||
|
|
status = "okay";
|
||
|
|
};
|
||
|
|
|
||
|
|
&spi0 {
|
||
|
|
pinctrl-0 = <&spi0m2_cs0 &spi0m2_pins>;
|
||
|
|
status = "disabled";
|
||
|
|
|
||
|
|
spidev0: spidev@0 {
|
||
|
|
compatible = "rockchip,spidev";
|
||
|
|
reg = <0>;
|
||
|
|
spi-max-frequency = <10000000>;
|
||
|
|
status = "disabled";
|
||
|
|
};
|
||
|
|
};
|
||
|
|
|
||
|
|
&uart0 {
|
||
|
|
pinctrl-0 = <&uart0m0_xfer>;
|
||
|
|
status = "disabled";
|
||
|
|
};
|
||
|
|
|
||
|
|
&uart4 {
|
||
|
|
pinctrl-0 = <&uart4m2_xfer>;
|
||
|
|
status = "disabled";
|
||
|
|
};
|
||
|
|
|
||
|
|
&uart5 {
|
||
|
|
pinctrl-0 = <&uart5m1_xfer>;
|
||
|
|
status = "okay";
|
||
|
|
};
|
||
|
|
|
||
|
|
&uart6 {
|
||
|
|
pinctrl-0 = <&uart6m1_xfer>;
|
||
|
|
status = "okay";
|
||
|
|
};
|
||
|
|
|
||
|
|
&uart7 {
|
||
|
|
pinctrl-0 = <&uart7m2_xfer>;
|
||
|
|
status = "disabled";
|
||
|
|
};
|
||
|
|
|
||
|
|
&uart8 {
|
||
|
|
pinctrl-0 = <&uart8m0_xfer>;
|
||
|
|
status = "disabled";
|
||
|
|
};
|
||
|
|
|
||
|
|
&pwm2 {
|
||
|
|
pinctrl-0 = <&pwm2m0_pins>;
|
||
|
|
status = "okay";
|
||
|
|
};
|