diff --git a/kernel-5.10/arch/arm64/boot/dts/rockchip/Makefile b/kernel-5.10/arch/arm64/boot/dts/rockchip/Makefile
index 60647a95c19..53eae5a81cd 100644
--- a/kernel-5.10/arch/arm64/boot/dts/rockchip/Makefile
+++ b/kernel-5.10/arch/arm64/boot/dts/rockchip/Makefile
@@ -30,7 +30,8 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += \
 	rk3588-nanopi6-rev06.dtb \
 	rk3588-nanopi6-rev07.dtb \
 	rk3588-nanopi6-rev08.dtb \
-	rk3588-nanopi6-rev09.dtb
+	rk3588-nanopi6-rev09.dtb \
+	rk3588-nanopi6-rev0a.dtb
 
 else
 
diff --git a/kernel-5.10/arch/arm64/boot/dts/rockchip/rk3588-nanopi6-dcsi0-imx415.dtsi b/kernel-5.10/arch/arm64/boot/dts/rockchip/rk3588-nanopi6-dcsi0-imx415.dtsi
new file mode 100644
index 00000000000..5ff529ecd88
--- /dev/null
+++ b/kernel-5.10/arch/arm64/boot/dts/rockchip/rk3588-nanopi6-dcsi0-imx415.dtsi
@@ -0,0 +1,152 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2022 FriendlyElec Computer Tech. Co., Ltd.
+ * (http://www.friendlyelec.com)
+ *
+ * Copyright (c) 2022 Rockchip Electronics Co., Ltd.
+ */
+
+&csi2_dcphy0 {
+	status = "okay";
+
+	ports {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		port@0 {
+			reg = <0>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			csidcphy0_in: endpoint@1 {
+				reg = <1>;
+				remote-endpoint = <&imx415_out1>;
+				data-lanes = <1 2 3 4>;
+			};
+		};
+
+		port@1 {
+			reg = <1>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			csidcphy0_out: endpoint@0 {
+				reg = <0>;
+				remote-endpoint = <&mipi0_csi2_input>;
+			};
+		};
+	};
+};
+
+&i2c7 {
+	status = "okay";
+
+	imx415p1: imx415@1a {
+		compatible = "sony,imx415";
+		reg = <0x1a>;
+		clocks = <&cru CLK_MIPI_CAMARAOUT_M2>;
+		clock-names = "xvclk";
+		power-domains = <&power RK3588_PD_VI>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&mipim0_camera2_clk>;
+
+		power-gpios = <&gpio1 RK_PD3 GPIO_ACTIVE_HIGH>;
+		reset-gpios = <&gpio1 RK_PD2 GPIO_ACTIVE_LOW>;
+		rockchip,camera-module-index = <0>;
+		rockchip,camera-module-facing = "back";
+		rockchip,camera-module-name = "CMK-OT2022-PX1";
+		rockchip,camera-module-lens-name = "IR0147-50IRC-8M-F20";
+
+		port {
+			imx415_out1: endpoint {
+				remote-endpoint = <&csidcphy0_in>;
+				data-lanes = <1 2 3 4>;
+			};
+		};
+	};
+};
+
+&mipi_dcphy0 {
+    status = "okay";
+};
+
+&mipi0_csi2 {
+	status = "okay";
+
+	ports {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		port@0 {
+			reg = <0>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			mipi0_csi2_input: endpoint@1 {
+				reg = <1>;
+				remote-endpoint = <&csidcphy0_out>;
+			};
+		};
+
+		port@1 {
+			reg = <1>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			mipi0_csi2_output: endpoint@0 {
+				reg = <0>;
+				remote-endpoint = <&cif_mipi_in0>;
+			};
+		};
+	};
+};
+
+&rkcif {
+	status = "okay";
+};
+
+&rkcif_mipi_lvds {
+	status = "okay";
+
+	port {
+		cif_mipi_in0: endpoint {
+			remote-endpoint = <&mipi0_csi2_output>;
+		};
+	};
+};
+
+&rkcif_mipi_lvds_sditf {
+	status = "okay";
+
+	port {
+		mipi2_lvds_sditf: endpoint {
+			remote-endpoint = <&isp0_vir0>;
+		};
+	};
+};
+
+&rkcif_mmu {
+	status = "okay";
+};
+
+&rkisp0 {
+	status = "okay";
+};
+
+&isp0_mmu {
+	status = "okay";
+};
+
+&rkisp0_vir0 {
+	status = "okay";
+
+	port {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		isp0_vir0: endpoint@0 {
+			reg = <0>;
+			remote-endpoint = <&mipi2_lvds_sditf>;
+		};
+	};
+};
diff --git a/kernel-5.10/arch/arm64/boot/dts/rockchip/rk3588-nanopi6-mipi-dsi-sel.dtsi b/kernel-5.10/arch/arm64/boot/dts/rockchip/rk3588-nanopi6-mipi-dsi-sel.dtsi
new file mode 100644
index 00000000000..752fe72c1f8
--- /dev/null
+++ b/kernel-5.10/arch/arm64/boot/dts/rockchip/rk3588-nanopi6-mipi-dsi-sel.dtsi
@@ -0,0 +1,75 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2024 FriendlyElec Computer Tech. Co., Ltd.
+ * (http://www.friendlyelec.com)
+ */
+
+#if (ENABLE_MIPI_DSI0)
+
+&mipi_dcphy0 {
+	status = "okay";
+};
+
+&dsi0 {
+	status = "okay";
+};
+
+&dsi0_i2c {
+	status = "okay";
+};
+
+#if (HAS_PWM_BACKLIGHT)
+&dsi0_pwm {
+	status = "okay";
+};
+
+&pwm_backlight {
+	status = "okay";
+	pwms = <&dsi0_pwm 0 25000 0>;
+};
+#endif
+
+&dsi0_in_vp2 {
+	status = "okay";
+};
+
+&route_dsi0 {
+	status = "okay";
+	connect = <&vp2_out_dsi0>;
+};
+
+#elif (ENABLE_MIPI_DSI1)
+
+&mipi_dcphy1 {
+	status = "okay";
+};
+
+&dsi1 {
+	status = "okay";
+};
+
+&dsi1_i2c {
+	status = "okay";
+};
+
+#if (HAS_PWM_BACKLIGHT)
+&dsi1_pwm {
+	status = "okay";
+};
+
+&pwm_backlight {
+	status = "okay";
+	pwms = <&dsi1_pwm 0 25000 0>;
+};
+#endif
+
+&dsi1_in_vp2 {
+	status = "okay";
+};
+
+&route_dsi1 {
+	status = "okay";
+	connect = <&vp2_out_dsi1>;
+};
+
+#endif
diff --git a/kernel-5.10/arch/arm64/boot/dts/rockchip/rk3588-nanopi6-mipi-evb-v10.dtsi b/kernel-5.10/arch/arm64/boot/dts/rockchip/rk3588-nanopi6-mipi-evb-v10.dtsi
index 89223ba56ca..94b417e80ad 100644
--- a/kernel-5.10/arch/arm64/boot/dts/rockchip/rk3588-nanopi6-mipi-evb-v10.dtsi
+++ b/kernel-5.10/arch/arm64/boot/dts/rockchip/rk3588-nanopi6-mipi-evb-v10.dtsi
@@ -1,52 +1,14 @@
 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
 /*
- * Copyright (c) 2022 FriendlyElec Computer Tech. Co., Ltd.
+ * Copyright (c) 2024 FriendlyElec Computer Tech. Co., Ltd.
  * (http://www.friendlyelec.com)
  *
  * Copyright (c) 2022 Rockchip Electronics Co., Ltd.
  */
 
-&i2c4 {
-	status = "okay";
-
-	gt1x_dsi1: gt1x@14 {
-		status = "okay";
-		compatible = "goodix,gt1x";
-		reg = <0x14>;
-		pinctrl-names = "default";
-		pinctrl-0 = <&touch_dsi1_gpio>;
-		interrupt-parent = <&gpio4>;
-		interrupts = <0 IRQ_TYPE_EDGE_FALLING>;
-		goodix,irq-gpio = <&gpio4 RK_PA0 IRQ_TYPE_EDGE_FALLING>;
-		goodix,rst-gpio = <&gpio4 RK_PA1 GPIO_ACTIVE_HIGH>;
-	};
-};
-
-&i2c5 {
-	status = "disabled";
-
-	gt1x_dsi0: gt1x@14 {
-		status = "disabled";
-		compatible = "goodix,gt1x";
-		reg = <0x14>;
-		pinctrl-names = "default";
-		pinctrl-0 = <&touch_dsi0_gpio>;
-		goodix,irq-gpio = <&gpio3 RK_PC0 IRQ_TYPE_LEVEL_LOW>;
-		goodix,rst-gpio = <&gpio3 RK_PC1 GPIO_ACTIVE_HIGH>;
-	};
-};
-
-&pwm2 {
-	status = "disabled";
-};
-
-&pwm11 {
-	status = "okay";
-};
+#define HAS_PWM_BACKLIGHT	1
 
 &pwm_backlight {
-	status = "okay";
-	pwms = <&pwm11 0 25000 0>;
 	brightness-levels = <
 		  0  20  20  21  21  22  22  23
 		 23  24  24  25  25  26  26  27
@@ -84,23 +46,358 @@
 	default-brightness-level = <200>;
 };
 
-&mipi_dcphy0 {
-	status = "okay";
-};
+#if defined(ENABLE_MIPI_DSI0)
+&dsi0 {
+	dsi0_panel: panel@0 {
+		compatible = "simple-panel-dsi";
+		reg = <0>;
+
+		backlight = <&pwm_backlight>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&lcd_rst0_gpio>;
+		reset-gpios = <&gpio4 RK_PA3 GPIO_ACTIVE_LOW>;
+		panel-name = "EVB10a,400dpi";
+
+		reset-delay-ms = <10>;
+		enable-delay-ms = <10>;
+		prepare-delay-ms = <10>;
+		unprepare-delay-ms = <10>;
+		disable-delay-ms = <60>;
+
+		dsi,flags = <(MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_BURST |
+			      MIPI_DSI_MODE_LPM | MIPI_DSI_MODE_EOT_PACKET)>;
+		dsi,format = <MIPI_DSI_FMT_RGB888>;
+		dsi,lanes  = <4>;
+		panel-init-sequence = [
+			23 00 02 FE 21
+			23 00 02 04 00
+			23 00 02 00 64
+			23 00 02 2A 00
+			23 00 02 26 64
+			23 00 02 54 00
+			23 00 02 50 64
+			23 00 02 7B 00
+			23 00 02 77 64
+			23 00 02 A2 00
+			23 00 02 9D 64
+			23 00 02 C9 00
+			23 00 02 C5 64
+			23 00 02 01 71
+			23 00 02 27 71
+			23 00 02 51 71
+			23 00 02 78 71
+			23 00 02 9E 71
+			23 00 02 C6 71
+			23 00 02 02 89
+			23 00 02 28 89
+			23 00 02 52 89
+			23 00 02 79 89
+			23 00 02 9F 89
+			23 00 02 C7 89
+			23 00 02 03 9E
+			23 00 02 29 9E
+			23 00 02 53 9E
+			23 00 02 7A 9E
+			23 00 02 A0 9E
+			23 00 02 C8 9E
+			23 00 02 09 00
+			23 00 02 05 B0
+			23 00 02 31 00
+			23 00 02 2B B0
+			23 00 02 5A 00
+			23 00 02 55 B0
+			23 00 02 80 00
+			23 00 02 7C B0
+			23 00 02 A7 00
+			23 00 02 A3 B0
+			23 00 02 CE 00
+			23 00 02 CA B0
+			23 00 02 06 C0
+			23 00 02 2D C0
+			23 00 02 56 C0
+			23 00 02 7D C0
+			23 00 02 A4 C0
+			23 00 02 CB C0
+			23 00 02 07 CF
+			23 00 02 2F CF
+			23 00 02 58 CF
+			23 00 02 7E CF
+			23 00 02 A5 CF
+			23 00 02 CC CF
+			23 00 02 08 DD
+			23 00 02 30 DD
+			23 00 02 59 DD
+			23 00 02 7F DD
+			23 00 02 A6 DD
+			23 00 02 CD DD
+			23 00 02 0E 15
+			23 00 02 0A E9
+			23 00 02 36 15
+			23 00 02 32 E9
+			23 00 02 5F 15
+			23 00 02 5B E9
+			23 00 02 85 15
+			23 00 02 81 E9
+			23 00 02 AD 15
+			23 00 02 A9 E9
+			23 00 02 D3 15
+			23 00 02 CF E9
+			23 00 02 0B 14
+			23 00 02 33 14
+			23 00 02 5C 14
+			23 00 02 82 14
+			23 00 02 AA 14
+			23 00 02 D0 14
+			23 00 02 0C 36
+			23 00 02 34 36
+			23 00 02 5D 36
+			23 00 02 83 36
+			23 00 02 AB 36
+			23 00 02 D1 36
+			23 00 02 0D 6B
+			23 00 02 35 6B
+			23 00 02 5E 6B
+			23 00 02 84 6B
+			23 00 02 AC 6B
+			23 00 02 D2 6B
+			23 00 02 13 5A
+			23 00 02 0F 94
+			23 00 02 3B 5A
+			23 00 02 37 94
+			23 00 02 64 5A
+			23 00 02 60 94
+			23 00 02 8A 5A
+			23 00 02 86 94
+			23 00 02 B2 5A
+			23 00 02 AE 94
+			23 00 02 D8 5A
+			23 00 02 D4 94
+			23 00 02 10 D1
+			23 00 02 38 D1
+			23 00 02 61 D1
+			23 00 02 87 D1
+			23 00 02 AF D1
+			23 00 02 D5 D1
+			23 00 02 11 04
+			23 00 02 39 04
+			23 00 02 62 04
+			23 00 02 88 04
+			23 00 02 B0 04
+			23 00 02 D6 04
+			23 00 02 12 05
+			23 00 02 3A 05
+			23 00 02 63 05
+			23 00 02 89 05
+			23 00 02 B1 05
+			23 00 02 D7 05
+			23 00 02 18 AA
+			23 00 02 14 36
+			23 00 02 42 AA
+			23 00 02 3D 36
+			23 00 02 69 AA
+			23 00 02 65 36
+			23 00 02 8F AA
+			23 00 02 8B 36
+			23 00 02 B7 AA
+			23 00 02 B3 36
+			23 00 02 DD AA
+			23 00 02 D9 36
+			23 00 02 15 74
+			23 00 02 3F 74
+			23 00 02 66 74
+			23 00 02 8C 74
+			23 00 02 B4 74
+			23 00 02 DA 74
+			23 00 02 16 9F
+			23 00 02 40 9F
+			23 00 02 67 9F
+			23 00 02 8D 9F
+			23 00 02 B5 9F
+			23 00 02 DB 9F
+			23 00 02 17 DC
+			23 00 02 41 DC
+			23 00 02 68 DC
+			23 00 02 8E DC
+			23 00 02 B6 DC
+			23 00 02 DC DC
+			23 00 02 1D FF
+			23 00 02 19 03
+			23 00 02 47 FF
+			23 00 02 43 03
+			23 00 02 6E FF
+			23 00 02 6A 03
+			23 00 02 94 FF
+			23 00 02 90 03
+			23 00 02 BC FF
+			23 00 02 B8 03
+			23 00 02 E2 FF
+			23 00 02 DE 03
+			23 00 02 1A 35
+			23 00 02 44 35
+			23 00 02 6B 35
+			23 00 02 91 35
+			23 00 02 B9 35
+			23 00 02 DF 35
+			23 00 02 1B 45
+			23 00 02 45 45
+			23 00 02 6C 45
+			23 00 02 92 45
+			23 00 02 BA 45
+			23 00 02 E0 45
+			23 00 02 1C 55
+			23 00 02 46 55
+			23 00 02 6D 55
+			23 00 02 93 55
+			23 00 02 BB 55
+			23 00 02 E1 55
+			23 00 02 22 FF
+			23 00 02 1E 68
+			23 00 02 4C FF
+			23 00 02 48 68
+			23 00 02 73 FF
+			23 00 02 6F 68
+			23 00 02 99 FF
+			23 00 02 95 68
+			23 00 02 C1 FF
+			23 00 02 BD 68
+			23 00 02 E7 FF
+			23 00 02 E3 68
+			23 00 02 1F 7E
+			23 00 02 49 7E
+			23 00 02 70 7E
+			23 00 02 96 7E
+			23 00 02 BE 7E
+			23 00 02 E4 7E
+			23 00 02 20 97
+			23 00 02 4A 97
+			23 00 02 71 97
+			23 00 02 97 97
+			23 00 02 BF 97
+			23 00 02 E5 97
+			23 00 02 21 B5
+			23 00 02 4B B5
+			23 00 02 72 B5
+			23 00 02 98 B5
+			23 00 02 C0 B5
+			23 00 02 E6 B5
+			23 00 02 25 F0
+			23 00 02 23 E8
+			23 00 02 4F F0
+			23 00 02 4D E8
+			23 00 02 76 F0
+			23 00 02 74 E8
+			23 00 02 9C F0
+			23 00 02 9A E8
+			23 00 02 C4 F0
+			23 00 02 C2 E8
+			23 00 02 EA F0
+			23 00 02 E8 E8
+			23 00 02 24 FF
+			23 00 02 4E FF
+			23 00 02 75 FF
+			23 00 02 9B FF
+			23 00 02 C3 FF
+			23 00 02 E9 FF
+			23 00 02 FE 3D
+			23 00 02 00 04
+			23 00 02 FE 23
+			23 00 02 08 82
+			23 00 02 0A 00
+			23 00 02 0B 00
+			23 00 02 0C 01
+			23 00 02 16 00
+			23 00 02 18 02
+			23 00 02 1B 04
+			23 00 02 19 04
+			23 00 02 1C 81
+			23 00 02 1F 00
+			23 00 02 20 03
+			23 00 02 23 04
+			23 00 02 21 01
+			23 00 02 54 63
+			23 00 02 55 54
+			23 00 02 6E 45
+			23 00 02 6D 36
+			23 00 02 FE 3D
+			23 00 02 55 78
+			23 00 02 FE 20
+			23 00 02 26 30
+			23 00 02 FE 3D
+			23 00 02 20 71
+			23 00 02 50 8F
+			23 00 02 51 8F
+			23 00 02 FE 00
+			23 00 02 35 00
+			05 78 01 11
+			05 00 01 29
+		];
+
+		panel-exit-sequence = [
+			05 00 01 28
+			05 00 01 10
+		];
+
+		disp_timings0: display-timings {
+			native-mode = <&dsi_timing0>;
+			dsi_timing0: timing0 {
+				clock-frequency = <132000000>;
+				hactive = <1080>;
+				vactive = <1920>;
+				hfront-porch = <15>;
+				hsync-len = <4>;
+				hback-porch = <30>;
+				vfront-porch = <15>;
+				vsync-len = <2>;
+				vback-porch = <15>;
+				hsync-active = <0>;
+				vsync-active = <0>;
+				de-active = <0>;
+				pixelclk-active = <0>;
+			};
+		};
 
-&mipi_dcphy1 {
-	status = "okay";
+		ports {
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			port@0 {
+				reg = <0>;
+				panel_in_dsi0: endpoint {
+					remote-endpoint = <&dsi0_out_panel>;
+				};
+			};
+		};
+	};
+
+	ports {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		port@1 {
+			reg = <1>;
+			dsi0_out_panel: endpoint {
+				remote-endpoint = <&panel_in_dsi0>;
+			};
+		};
+	};
 };
 
-&dsi1_in_vp3 {
-	status = "okay";
+&dsi0_i2c {
+	dsi0_gt1x: gt1x@14 {
+		compatible = "goodix,gt1x";
+		reg = <0x14>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&touch_dsi0_gpio>;
+		goodix,irq-gpio = <&gpio3 RK_PC0 IRQ_TYPE_LEVEL_LOW>;
+		goodix,rst-gpio = <&gpio3 RK_PC1 GPIO_ACTIVE_HIGH>;
+		keep-otp-config;
+	};
 };
+#endif
 
+#if defined(ENABLE_MIPI_DSI1)
 &dsi1 {
-	status = "okay";
-
-	dsi_panel: panel@0 {
-		status = "okay";
+	dsi1_panel: panel@0 {
 		compatible = "simple-panel-dsi";
 		reg = <0>;
 
@@ -108,6 +405,7 @@
 		pinctrl-names = "default";
 		pinctrl-0 = <&lcd_rst1_gpio>;
 		reset-gpios = <&gpio4 RK_PA3 GPIO_ACTIVE_LOW>;
+		panel-name = "EVB10b,400dpi";
 
 		reset-delay-ms = <10>;
 		enable-delay-ms = <10>;
@@ -388,9 +686,9 @@
 			05 00 01 10
 		];
 
-		disp_timings0: display-timings {
-			native-mode = <&dsi_timing0>;
-			dsi_timing0: timing0 {
+		display-timings {
+			native-mode = <&dsi1_timing0>;
+			dsi1_timing0: timing0 {
 				clock-frequency = <132000000>;
 				hactive = <1080>;
 				vactive = <1920>;
@@ -413,8 +711,8 @@
 
 			port@0 {
 				reg = <0>;
-				panel_in_dsi: endpoint {
-					remote-endpoint = <&dsi_out_panel>;
+				panel_in_dsi1: endpoint {
+					remote-endpoint = <&dsi1_out_panel>;
 				};
 			};
 		};
@@ -426,9 +724,22 @@
 
 		port@1 {
 			reg = <1>;
-			dsi_out_panel: endpoint {
-				remote-endpoint = <&panel_in_dsi>;
+			dsi1_out_panel: endpoint {
+				remote-endpoint = <&panel_in_dsi1>;
 			};
 		};
 	};
 };
+
+&dsi1_i2c {
+	dsi1_gt1x: gt1x@14 {
+		compatible = "goodix,gt1x";
+		reg = <0x14>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&touch_dsi1_gpio>;
+		goodix,irq-gpio = <&gpio4 RK_PA0 IRQ_TYPE_EDGE_FALLING>;
+		goodix,rst-gpio = <&gpio4 RK_PA1 GPIO_ACTIVE_HIGH>;
+		keep-otp-config;
+	};
+};
+#endif
diff --git a/kernel-5.10/arch/arm64/boot/dts/rockchip/rk3588-nanopi6-mipi-lcd-yx35.dtsi b/kernel-5.10/arch/arm64/boot/dts/rockchip/rk3588-nanopi6-mipi-lcd-yx35.dtsi
new file mode 100644
index 00000000000..fc649ca5d14
--- /dev/null
+++ b/kernel-5.10/arch/arm64/boot/dts/rockchip/rk3588-nanopi6-mipi-lcd-yx35.dtsi
@@ -0,0 +1,358 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2024 FriendlyElec Computer Tech. Co., Ltd.
+ * (http://www.friendlyelec.com)
+ *
+ * Copyright (c) 2022 Rockchip Electronics Co., Ltd.
+ */
+
+#define HAS_PWM_BACKLIGHT	1
+
+&pwm_backlight {
+	brightness-levels = <
+		  0  20  20  21  21  22  22  23
+		 23  24  24  25  25  26  26  27
+		 27  28  28  29  29  30  30  31
+		 31  32  32  33  33  34  34  35
+		 35  36  36  37  37  38  38  39
+		 40  41  42  43  44  45  46  47
+		 48  49  50  51  52  53  54  55
+		 56  57  58  59  60  61  62  63
+		 64  65  66  67  68  69  70  71
+		 72  73  74  75  76  77  78  79
+		 80  81  82  83  84  85  86  87
+		 88  89  90  91  92  93  94  95
+		 96  97  98  99 100 101 102 103
+		104 105 106 107 108 109 110 111
+		112 113 114 115 116 117 118 119
+		120 121 122 123 124 125 126 127
+		128 129 130 131 132 133 134 135
+		136 137 138 139 140 141 142 143
+		144 145 146 147 148 149 150 151
+		152 153 154 155 156 157 158 159
+		160 161 162 163 164 165 166 167
+		168 169 170 171 172 173 174 175
+		176 177 178 179 180 181 182 183
+		184 185 186 187 188 189 190 191
+		192 193 194 195 196 197 198 199
+		200 201 202 203 204 205 206 207
+		208 209 210 211 212 213 214 215
+		216 217 218 219 220 221 222 223
+		224 225 226 227 228 229 230 231
+		232 233 234 235 236 237 238 239
+		240 241 242 243 244 245 246 247
+		248 249 250 251 252 253 254 255
+	>;
+	default-brightness-level = <200>;
+};
+
+#if defined(ENABLE_MIPI_DSI0)
+&dsi0 {
+	dsi0_panel: panel@0 {
+		compatible = "simple-panel-dsi";
+		reg = <0>;
+
+		backlight = <&pwm_backlight>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&lcd_rst0_gpio>;
+		reset-gpios = <&gpio4 RK_PA3 GPIO_ACTIVE_LOW>;
+		panel-name = "yx35,210dpi";
+		nvmems = <&dsi0_i2c 0x50 0xe0 0x10>;
+		nvmem-status = <1>;
+
+		reset-delay-ms = <20>;
+		init-delay-ms = <120>;
+		enable-delay-ms = <5>;
+		prepare-delay-ms = <0>;
+		unprepare-delay-ms = <10>;
+		disable-delay-ms = <5>;
+		width-mm = <45>;
+		height-mm = <75>;
+
+		dsi,flags = <(MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_BURST |
+			      MIPI_DSI_MODE_LPM | MIPI_DSI_CLOCK_NON_CONTINUOUS)>;
+		dsi,format = <MIPI_DSI_FMT_RGB888>;
+		dsi,lanes  = <2>;
+		panel-init-sequence = [
+			15 0A 02 01 00
+			15 7D 02 11 00
+			39 00 06 FF 77 01 00 00 13
+			15 00 02 EF 08
+			39 00 06 FF 77 01 00 00 10
+			39 00 03 C0 63 00
+			39 00 03 C1 14 14
+			39 00 03 C2 37 02
+			15 00 02 CC 10
+			39 00 11 B0 C5 11 1B 0D 11 07 0A 09 08 24 05 12 10 A9 32 DF
+			39 00 11 B1 C5 19 21 0B 0E 03 0C 07 07 26 04 12 11 AA 32 DF
+			39 00 06 FF 77 01 00 00 11
+			15 00 02 B0 4D
+			15 00 02 B1 59
+			15 00 02 B2 81
+			15 00 02 B3 80
+			15 00 02 B5 4E
+			15 00 02 B7 85
+			15 00 02 B8 32
+			15 00 02 BB 03
+			15 00 02 C1 08
+			15 00 02 C2 08
+			15 00 02 D0 88
+			39 00 04 E0 00 00 02
+			39 00 0C E1 06 28 08 28 05 28 07 28 0E 33 33
+			39 00 0D E2 30 30 33 33 34 00 00 00 34 00 00 00
+			39 00 05 E3 00 00 33 33
+			39 00 03 E4 44 44
+			39 00 11 E5 09 2F 2C 8C 0B 31 2C 8C 0D 33 2C 8C 0F 35 2C 8C
+			39 00 05 E6 00 00 33 33
+			39 00 03 E7 44 44
+			39 00 11 E8 08 2E 2C 8C 0A 30 2C 8C 0C 32 2C 8C 0E 34 2C 8C
+			39 00 03 E9 36 00
+			39 00 08 EB 00 01 E4 E4 44 88 40
+			39 00 11 ED FF FC B2 45 67 FA 01 FF FF 10 AF 76 54 2B CF FF
+			39 00 07 EF 08 08 08 45 3F 54
+			39 00 06 FF 77 01 00 00 13
+			39 00 03 E8 00 0E
+			15 78 02 11 00
+			39 0A 03 E8 00 0C
+			39 00 03 E8 00 00
+			39 00 06 FF 77 01 00 00 00
+			15 00 02 36 00
+			15 00 02 29 00
+		];
+
+		panel-exit-sequence = [
+			15 00 02 28 00
+			15 3C 02 10 00
+		];
+
+		disp_timings0: display-timings {
+			native-mode = <&dsi_timing0>;
+			dsi_timing0: timing0 {
+				clock-frequency = <29700000>;
+				hactive = <480>;
+				vactive = <800>;
+				hfront-porch = <40>;
+				hsync-len = <32>;
+				hback-porch = <30>;
+				vfront-porch = <20>;
+				vsync-len = <10>;
+				vback-porch = <20>;
+				hsync-active = <0>;
+				vsync-active = <0>;
+				de-active = <0>;
+				pixelclk-active = <0>;
+			};
+		};
+
+		ports {
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			port@0 {
+				reg = <0>;
+				panel_in_dsi0: endpoint {
+					remote-endpoint = <&dsi0_out_panel>;
+				};
+			};
+		};
+	};
+
+	ports {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		port@1 {
+			reg = <1>;
+			dsi0_out_panel: endpoint {
+				remote-endpoint = <&panel_in_dsi0>;
+			};
+		};
+	};
+};
+
+&dsi0_i2c {
+	dsi0_gt1x: gt1x@14 {
+		compatible = "goodix,gt1x";
+		reg = <0x14>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&touch_dsi0_gpio>;
+		goodix,irq-gpio = <&gpio3 RK_PC0 IRQ_TYPE_LEVEL_LOW>;
+		goodix,rst-gpio = <&gpio3 RK_PC1 GPIO_ACTIVE_HIGH>;
+		keep-otp-config;
+		status = "disabled";
+	};
+
+	dsi0_gt9xx: gt9xx@5d {
+		compatible = "goodix,gt9xx";
+		reg = <0x5d>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&touch_dsi0_gpio>;
+		interrupt-parent = <&gpio3>;
+		interrupts = <RK_PC0 IRQ_TYPE_EDGE_FALLING>;
+		goodix,irq-gpio = <&gpio3 RK_PC0 IRQ_TYPE_LEVEL_LOW>;
+		goodix,rst-gpio = <&gpio3 RK_PC1 GPIO_ACTIVE_HIGH>;
+		keep-otp-config;
+		status = "disabled";
+	};
+};
+#endif
+
+#if defined(ENABLE_MIPI_DSI1)
+&dsi1 {
+	dsi1_panel: panel@0 {
+		compatible = "simple-panel-dsi";
+		reg = <0>;
+
+		backlight = <&pwm_backlight>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&lcd_rst1_gpio>;
+		reset-gpios = <&gpio4 RK_PA1 GPIO_ACTIVE_LOW>;
+		panel-name = "yx35,210dpi";
+		nvmems = <&dsi1_i2c 0x50 0xe0 0x10>;
+		nvmem-status = <1>;
+
+		reset-delay-ms = <20>;
+		init-delay-ms = <120>;
+		enable-delay-ms = <5>;
+		prepare-delay-ms = <0>;
+		unprepare-delay-ms = <10>;
+		disable-delay-ms = <5>;
+		width-mm = <45>;
+		height-mm = <75>;
+
+		dsi,flags = <(MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_BURST |
+			      MIPI_DSI_MODE_LPM | MIPI_DSI_CLOCK_NON_CONTINUOUS)>;
+		dsi,format = <MIPI_DSI_FMT_RGB888>;
+		dsi,lanes  = <2>;
+		panel-init-sequence = [
+			15 0A 02 01 00
+			15 7D 02 11 00
+			39 00 06 FF 77 01 00 00 13
+			15 00 02 EF 08
+			39 00 06 FF 77 01 00 00 10
+			39 00 03 C0 63 00
+			39 00 03 C1 14 14
+			39 00 03 C2 37 02
+			15 00 02 CC 10
+			39 00 11 B0 C5 11 1B 0D 11 07 0A 09 08 24 05 12 10 A9 32 DF
+			39 00 11 B1 C5 19 21 0B 0E 03 0C 07 07 26 04 12 11 AA 32 DF
+			39 00 06 FF 77 01 00 00 11
+			15 00 02 B0 4D
+			15 00 02 B1 59
+			15 00 02 B2 81
+			15 00 02 B3 80
+			15 00 02 B5 4E
+			15 00 02 B7 85
+			15 00 02 B8 32
+			15 00 02 BB 03
+			15 00 02 C1 08
+			15 00 02 C2 08
+			15 00 02 D0 88
+			39 00 04 E0 00 00 02
+			39 00 0C E1 06 28 08 28 05 28 07 28 0E 33 33
+			39 00 0D E2 30 30 33 33 34 00 00 00 34 00 00 00
+			39 00 05 E3 00 00 33 33
+			39 00 03 E4 44 44
+			39 00 11 E5 09 2F 2C 8C 0B 31 2C 8C 0D 33 2C 8C 0F 35 2C 8C
+			39 00 05 E6 00 00 33 33
+			39 00 03 E7 44 44
+			39 00 11 E8 08 2E 2C 8C 0A 30 2C 8C 0C 32 2C 8C 0E 34 2C 8C
+			39 00 03 E9 36 00
+			39 00 08 EB 00 01 E4 E4 44 88 40
+			39 00 11 ED FF FC B2 45 67 FA 01 FF FF 10 AF 76 54 2B CF FF
+			39 00 07 EF 08 08 08 45 3F 54
+			39 00 06 FF 77 01 00 00 13
+			39 00 03 E8 00 0E
+			15 78 02 11 00
+			39 0A 03 E8 00 0C
+			39 00 03 E8 00 00
+			39 00 06 FF 77 01 00 00 00
+			15 00 02 36 00
+			15 00 02 29 00
+		];
+
+		panel-exit-sequence = [
+			15 00 02 28 00
+			15 3C 02 10 00
+		];
+
+		display-timings {
+			native-mode = <&dsi1_timing0>;
+			dsi1_timing0: timing0 {
+				clock-frequency = <29700000>;
+				hactive = <480>;
+				vactive = <800>;
+				hfront-porch = <40>;
+				hsync-len = <32>;
+				hback-porch = <30>;
+				vfront-porch = <20>;
+				vsync-len = <10>;
+				vback-porch = <20>;
+				hsync-active = <0>;
+				vsync-active = <0>;
+				de-active = <0>;
+				pixelclk-active = <0>;
+			};
+		};
+
+		ports {
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			port@0 {
+				reg = <0>;
+				panel_in_dsi1: endpoint {
+					remote-endpoint = <&dsi1_out_panel>;
+				};
+			};
+		};
+	};
+
+	ports {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		port@1 {
+			reg = <1>;
+			dsi1_out_panel: endpoint {
+				remote-endpoint = <&panel_in_dsi1>;
+			};
+		};
+	};
+};
+
+&dsi1_i2c {
+	dsi1_gt1x: gt1x@14 {
+		compatible = "goodix,gt1x";
+		reg = <0x14>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&touch_dsi1_gpio>;
+		goodix,irq-gpio = <&gpio4 RK_PA0 IRQ_TYPE_EDGE_FALLING>;
+		goodix,rst-gpio = <&gpio4 RK_PA1 GPIO_ACTIVE_HIGH>;
+		keep-otp-config;
+		status = "disabled";
+	};
+
+	dsi1_gt9xx: gt9xx@5d {
+		compatible = "goodix,gt9xx";
+		reg = <0x5d>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&touch_dsi1_gpio>;
+		interrupt-parent = <&gpio4>;
+		interrupts = <RK_PA0 IRQ_TYPE_EDGE_FALLING>;
+		goodix,irq-gpio = <&gpio4 RK_PA0 IRQ_TYPE_EDGE_FALLING>;
+		goodix,rst-gpio = <&gpio4 RK_PA1 GPIO_ACTIVE_HIGH>;
+		keep-otp-config;
+		status = "disabled";
+	};
+
+	dsi1_e2prom: eeprom@50 {
+		compatible = "microchip,24c02", "atmel,24c02";
+		reg = <0x50>;
+		#address-cells = <2>;
+		#size-cells = <0>;
+		pagesize = <16>;
+		size = <256>;
+	};
+};
+#endif
diff --git a/kernel-5.10/arch/arm64/boot/dts/rockchip/rk3588-nanopi6-rev01.dts b/kernel-5.10/arch/arm64/boot/dts/rockchip/rk3588-nanopi6-rev01.dts
index f75f10a77d0..bb1816a5621 100644
--- a/kernel-5.10/arch/arm64/boot/dts/rockchip/rk3588-nanopi6-rev01.dts
+++ b/kernel-5.10/arch/arm64/boot/dts/rockchip/rk3588-nanopi6-rev01.dts
@@ -291,14 +291,12 @@
 	/* connected with MIPI-CSI0 */
 };
 
-&i2c4 {
+dsi1_i2c: &i2c4 {
 	pinctrl-0 = <&i2c4m3_xfer>;
-	/* connected with MIPI-DSI1 */
 };
 
-&i2c5 {
+dsi0_i2c: &i2c5 {
 	pinctrl-0 = <&i2c5m0_xfer>;
-	/* connected with MIPI-DSI0 */
 };
 
 &i2c6 {
@@ -570,14 +568,12 @@
 	status = "okay";
 };
 
-&pwm2 {
+dsi0_pwm: &pwm2 {
 	pinctrl-0 = <&pwm2m1_pins>;
-	/* connected with MIPI-DSI0 */
 };
 
-&pwm11 {
+dsi1_pwm: &pwm11 {
 	pinctrl-0 = <&pwm11m3_pins>;
-	/* connected with MIPI-DSI1 */
 };
 
 &spdif_tx2 {
diff --git a/kernel-5.10/arch/arm64/boot/dts/rockchip/rk3588-nanopi6-rev08.dts b/kernel-5.10/arch/arm64/boot/dts/rockchip/rk3588-nanopi6-rev08.dts
index 324fdc7f21d..b2e40f39859 100644
--- a/kernel-5.10/arch/arm64/boot/dts/rockchip/rk3588-nanopi6-rev08.dts
+++ b/kernel-5.10/arch/arm64/boot/dts/rockchip/rk3588-nanopi6-rev08.dts
@@ -18,6 +18,20 @@
 		ethernet0 = &r8125_u10;
 	};
 
+	adc_keys: adc-keys {
+		compatible = "adc-keys";
+		io-channels = <&saradc 1>;
+		io-channel-names = "buttons";
+		keyup-threshold-microvolt = <1800000>;
+		poll-interval = <100>;
+
+		vol-up-key {
+			label = "volume up";
+			linux,code = <KEY_VOLUMEUP>;
+			press-threshold-microvolt = <17000>;
+		};
+	};
+
 	dp0_sound: dp0-sound {
 		status = "okay";
 		compatible = "rockchip,hdmi";
diff --git a/kernel-5.10/arch/arm64/boot/dts/rockchip/rk3588-nanopi6-rev09.dts b/kernel-5.10/arch/arm64/boot/dts/rockchip/rk3588-nanopi6-rev09.dts
index ea0a9a80771..5e7f5645ea6 100644
--- a/kernel-5.10/arch/arm64/boot/dts/rockchip/rk3588-nanopi6-rev09.dts
+++ b/kernel-5.10/arch/arm64/boot/dts/rockchip/rk3588-nanopi6-rev09.dts
@@ -319,9 +319,8 @@
 	status = "okay";
 };
 
-&i2c5 {
+dsi0_i2c: &i2c5 {
 	pinctrl-0 = <&i2c5m0_xfer>;
-	/* connected with MIPI-DSI0 */
 };
 
 &i2c6 {
@@ -599,9 +598,8 @@
 	status = "okay";
 };
 
-&pwm2 {
+dsi0_pwm: &pwm2 {
 	pinctrl-0 = <&pwm2m1_pins>;
-	/* connected with MIPI-DSI0 */
 };
 
 &pwm8 {
diff --git a/kernel-5.10/arch/arm64/boot/dts/rockchip/rk3588-nanopi6-rev0a.dts b/kernel-5.10/arch/arm64/boot/dts/rockchip/rk3588-nanopi6-rev0a.dts
new file mode 100644
index 00000000000..280932e7264
--- /dev/null
+++ b/kernel-5.10/arch/arm64/boot/dts/rockchip/rk3588-nanopi6-rev0a.dts
@@ -0,0 +1,462 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2024 FriendlyElec Computer Tech. Co., Ltd.
+ * (http://www.friendlyelec.com)
+ *
+ * Copyright (c) 2021 Rockchip Electronics Co., Ltd.
+ */
+
+/dts-v1/;
+
+#include "rk3588-nanopi6-common.dtsi"
+
+/ {
+	model = "FriendlyElec NanoPi M6";
+	compatible = "friendlyelec,nanopi-m6", "rockchip,rk3588";
+
+	aliases {
+		ethernet0 = &gmac1;
+	};
+
+	rt5616_sound: rt5616-sound {
+		status = "okay";
+		compatible = "simple-audio-card";
+		pinctrl-names = "default";
+		pinctrl-0 = <&hp_det>;
+
+		simple-audio-card,name = "realtek,rt5616-codec";
+		simple-audio-card,format = "i2s";
+		simple-audio-card,mclk-fs = <256>;
+
+		simple-audio-card,hp-det-gpio = <&gpio1 RK_PC4 GPIO_ACTIVE_LOW>;
+		simple-audio-card,hp-pin-name = "Headphone Jack";
+
+		simple-audio-card,widgets =
+			"Headphone", "Headphone Jack",
+			"Microphone", "Microphone Jack";
+		simple-audio-card,routing =
+			"Headphone Jack", "HPOL",
+			"Headphone Jack", "HPOR",
+			"MIC1", "Microphone Jack",
+			"Microphone Jack", "micbias1";
+
+		simple-audio-card,cpu {
+			sound-dai = <&i2s0_8ch>;
+		};
+		simple-audio-card,codec {
+			sound-dai = <&rt5616>;
+		};
+	};
+
+	fan: pwm-fan {
+		status = "okay";
+		compatible = "pwm-fan";
+		#cooling-cells = <2>;
+		fan-supply = <&vcc5v0_sys>;
+		pwms = <&pwm5 0 50000 0>;
+		cooling-levels = <0 45 70 110 160 255>;
+		rockchip,hold-time-ms = <2000>;
+		rockchip,temp-trips = <
+			50000	1
+			55000	2
+			60000	3
+			65000	4
+			70000	5
+		>;
+	};
+
+	adc_keys: adc-keys {
+		compatible = "adc-keys";
+		io-channels = <&saradc 1>;
+		io-channel-names = "buttons";
+		keyup-threshold-microvolt = <1800000>;
+		poll-interval = <100>;
+
+		vol-up-key {
+			label = "volume up";
+			linux,code = <KEY_VOLUMEUP>;
+			press-threshold-microvolt = <17000>;
+		};
+	};
+
+	gpio_leds: gpio-leds {
+		compatible = "gpio-leds";
+
+		sys_led: led-0 {
+			gpios = <&gpio1 RK_PA4 GPIO_ACTIVE_HIGH>;
+			label = "sys_led";
+			linux,default-trigger = "heartbeat";
+			pinctrl-names = "default";
+			pinctrl-0 = <&sys_led_pin>;
+		};
+
+		user_led: led-1 {
+			gpios = <&gpio1 RK_PA6 GPIO_ACTIVE_HIGH>;
+			label = "user_led";
+			pinctrl-names = "default";
+			pinctrl-0 = <&user_led_pin>;
+		};
+	};
+
+	vcc3v3_pcie_m2: vcc3v3-pcie30 {
+		compatible = "regulator-fixed";
+		enable-active-high;
+		gpios = <&gpio3 RK_PC6 GPIO_ACTIVE_HIGH>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&pcie_m2_0_pwren>;
+		regulator-name = "vcc3v3_pcie_m2";
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+		vin-supply = <&vcc5v0_sys>;
+	};
+
+	vcc5v0_host_20: vcc5v0-host-20 {
+		compatible = "regulator-fixed";
+		enable-active-high;
+		gpio = <&gpio4 RK_PB5 GPIO_ACTIVE_HIGH>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&vcc5v0_host20_en>;
+		regulator-name = "vcc5v0_host_20";
+		regulator-min-microvolt = <5000000>;
+		regulator-max-microvolt = <5000000>;
+		vin-supply = <&vcc5v0_usb>;
+	};
+
+	vbus5v0_typec: vbus5v0-typec {
+		compatible = "regulator-fixed";
+		enable-active-high;
+		gpio = <&gpio3 RK_PD4 GPIO_ACTIVE_HIGH>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&typec5v_pwren>;
+		regulator-name = "vbus5v0_typec";
+		regulator-min-microvolt = <5000000>;
+		regulator-max-microvolt = <5000000>;
+		vin-supply = <&vcc5v0_usb>;
+	};
+};
+
+&mach {
+	hwrev = <0x0a>;
+	model = "NanoPi M6";
+};
+
+&pcie2x1l1 {
+	rockchip,skip-hw-retry;
+};
+
+&pcie2x1l2 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pcie_m2_0_prsnt>;
+	prsnt-gpios = <&gpio4 RK_PA5 GPIO_ACTIVE_HIGH>;
+	phys = <&combphy0_ps PHY_TYPE_PCIE 0>;
+	rockchip,skip-hw-retry;
+	vpcie3v3-supply = <&vcc3v3_pcie_m2>;
+	status = "okay";
+};
+
+&combphy0_ps {
+	#phy-cells = <2>;
+	rockchip,ebuff-mode;
+	status = "okay";
+};
+
+&sata0 {
+	phys = <&combphy0_ps PHY_TYPE_SATA 1>;
+	target-supply = <&vcc3v3_pcie_m2>;
+	status = "okay";
+};
+
+&pinctrl {
+	gpio-leds {
+		sys_led_pin: sys-led-pin {
+			rockchip,pins =
+				<1 RK_PA4 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+
+		user_led_pin: lan1-led-pin {
+			rockchip,pins =
+				<1 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+	};
+
+	headphone {
+		hp_det: hp-det {
+			rockchip,pins = <1 RK_PC4 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+	};
+
+	lcd {
+		/omit-if-no-ref/
+		lcd_rst0_gpio: lcd-rst0-gpio {
+			rockchip,pins = <3 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+
+		/omit-if-no-ref/
+		lcd_rst1_gpio: lcd-rst1-gpio {
+			rockchip,pins = <4 RK_PA1 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+
+		/omit-if-no-ref/
+		touch_dsi0_gpio: touch-dsi0-gpio {
+			rockchip,pins =
+				<3 RK_PC0 RK_FUNC_GPIO &pcfg_pull_up>,
+				<3 RK_PC1 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+
+		/omit-if-no-ref/
+		touch_dsi1_gpio: touch-dsi1-gpio {
+			rockchip,pins =
+				<4 RK_PA0 RK_FUNC_GPIO &pcfg_pull_up>,
+				<4 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+	};
+
+	pcie {
+		pcie_m2_0_pwren: pcie-m20-pwren {
+			rockchip,pins = <3 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+		pcie_m2_0_prsnt: pcie-m20-prsnt {
+			rockchip,pins = <4 RK_PA5 RK_FUNC_GPIO &pcfg_pull_up>;
+		};
+	};
+
+	usb {
+		typec5v_pwren: typec5v-pwren {
+			rockchip,pins = <3 RK_PD4 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+
+		vcc5v0_host20_en: vcc5v0-host20-en {
+			rockchip,pins = <4 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+	};
+};
+
+dsi0_i2c: &i2c4 {
+	clock-frequency = <200000>;
+	pinctrl-0 = <&i2c4m3_xfer>;
+};
+
+dsi1_i2c: &i2c5 {
+	clock-frequency = <200000>;
+	pinctrl-0 = <&i2c5m2_xfer>;
+};
+
+&i2c6 {
+	clock-frequency = <200000>;
+	status = "okay";
+
+	eeprom@53 {
+		compatible = "microchip,24c02", "atmel,24c02";
+		reg = <0x53>;
+		#address-cells = <2>;
+		#size-cells = <0>;
+		pagesize = <16>;
+		size = <256>;
+
+		eui_48: eui-48@fa {
+			reg = <0xfa 0x06>;
+		};
+	};
+};
+
+&i2c7 {
+	clock-frequency = <200000>;
+	status = "okay";
+
+	rt5616: rt5616@1b {
+		status = "okay";
+		#sound-dai-cells = <0>;
+		compatible = "rt5616";
+		reg = <0x1b>;
+		clocks = <&mclkout_i2s0>;
+		clock-names = "mclk";
+		assigned-clocks = <&mclkout_i2s0>;
+		assigned-clock-rates = <12288000>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&i2s0_mclk>;
+	};
+
+	/* connected with MIPI-CSI1 */
+};
+
+&i2s0_8ch {
+	status = "okay";
+	pinctrl-0 = <&i2s0_lrck
+		     &i2s0_sclk
+		     &i2s0_sdi0
+		     &i2s0_sdo0>;
+	rockchip,trcm-sync-tx-only;
+};
+
+&pwm5 {
+	pinctrl-0 = <&pwm5m1_pins>;
+	status = "okay";
+};
+
+dsi0_pwm: &pwm10 {
+	pinctrl-0 = <&pwm10m2_pins>;
+};
+
+dsi1_pwm: &pwm11 {
+	pinctrl-0 = <&pwm11m3_pins>;
+};
+
+&u2phy0 {
+	status = "okay";
+};
+
+&u2phy0_otg {
+	phy-supply = <&vbus5v0_typec>;
+	status = "okay";
+};
+
+&u2phy2 {
+	status = "okay";
+};
+
+&u2phy2_host {
+	phy-supply = <&vcc5v0_host_20>;
+	status = "okay";
+};
+
+&u2phy3 {
+	status = "okay";
+};
+
+&u2phy3_host {
+	status = "okay";
+};
+
+&usb_host1_ehci {
+	status = "okay";
+};
+
+&usb_host1_ohci {
+	status = "okay";
+};
+
+/* MIPI-CSI */
+#define ENABLE_MIPI_DCSI0	0
+
+#if (ENABLE_MIPI_CSI0)
+#include "rk3588-nanopi6-csi0-imx415.dtsi"
+
+&imx415p0 {
+	power-gpios = <&gpio1 RK_PD5 GPIO_ACTIVE_HIGH>;
+	reset-gpios = <&gpio1 RK_PC6 GPIO_ACTIVE_LOW>;
+};
+#endif
+
+#if (ENABLE_MIPI_DCSI0)
+#include "rk3588-nanopi6-dcsi0-imx415.dtsi"
+#endif
+
+/* MIPI-DSI */
+#define ENABLE_MIPI_DSI1	1
+
+#include "rk3588-nanopi6-mipi-lcd-yx35.dtsi"
+#include "rk3588-nanopi6-mipi-dsi-sel.dtsi"
+
+#if defined(ENABLE_MIPI_DSI0)
+&dsi0_panel {
+	reset-gpios = <&gpio3 RK_PD2 GPIO_ACTIVE_LOW>;
+};
+
+&dsi0_gt1x {
+	compatible = "goodix,gt1x", "goodix,gt9xx";
+	interrupt-parent = <&gpio3>;
+	interrupts = <RK_PC0 IRQ_TYPE_EDGE_FALLING>;
+	goodix,irq-gpio = <&gpio3 RK_PC0 IRQ_TYPE_EDGE_FALLING>;
+	goodix,rst-gpio = <&gpio3 RK_PC1 GPIO_ACTIVE_HIGH>;
+	status = "okay";
+};
+
+&dsi0_gt9xx {
+	interrupt-parent = <&gpio3>;
+	interrupts = <RK_PC0 IRQ_TYPE_EDGE_FALLING>;
+	goodix,irq-gpio = <&gpio3 RK_PC0 IRQ_TYPE_EDGE_FALLING>;
+	goodix,rst-gpio = <&gpio3 RK_PC1 GPIO_ACTIVE_HIGH>;
+};
+#endif
+
+#if defined(ENABLE_MIPI_DSI1)
+&dsi1_panel {
+	reset-gpios = <&gpio4 RK_PA1 GPIO_ACTIVE_LOW>;
+};
+
+&dsi1_gt1x {
+	compatible = "goodix,gt1x", "goodix,gt9xx";
+	interrupt-parent = <&gpio4>;
+	interrupts = <RK_PA0 IRQ_TYPE_EDGE_FALLING>;
+	goodix,irq-gpio = <&gpio4 RK_PA0 IRQ_TYPE_EDGE_FALLING>;
+	goodix,rst-gpio = <&gpio4 RK_PA2 GPIO_ACTIVE_HIGH>;
+	status = "okay";
+};
+
+&dsi1_gt9xx {
+	interrupt-parent = <&gpio4>;
+	interrupts = <RK_PA0 IRQ_TYPE_EDGE_FALLING>;
+	goodix,irq-gpio = <&gpio4 RK_PA0 IRQ_TYPE_EDGE_FALLING>;
+	goodix,rst-gpio = <&gpio4 RK_PA2 GPIO_ACTIVE_HIGH>;
+};
+#endif
+
+#undef ENABLE_MIPI_DSI1
+
+/* GPIO Connector */
+&i2c1 {
+	pinctrl-0 = <&i2c1m2_xfer>;
+	status = "disabled";
+};
+
+&i2c8 {
+	pinctrl-0 = <&i2c8m2_xfer>;
+	status = "okay";
+};
+
+&spi0 {
+	pinctrl-0 = <&spi0m2_cs0 &spi0m2_pins>;
+	status = "disabled";
+
+	spidev0: spidev@0 {
+		compatible = "rockchip,spidev";
+		reg = <0>;
+		spi-max-frequency = <10000000>;
+		status = "disabled";
+	};
+};
+
+&uart0 {
+	pinctrl-0 = <&uart0m0_xfer>;
+	status = "disabled";
+};
+
+&uart4 {
+	pinctrl-0 = <&uart4m2_xfer>;
+	status = "disabled";
+};
+
+&uart5 {
+	pinctrl-0 = <&uart5m1_xfer>;
+	status = "okay";
+};
+
+&uart6 {
+	pinctrl-0 = <&uart6m1_xfer>;
+	status = "okay";
+};
+
+&uart7 {
+	pinctrl-0 = <&uart7m2_xfer>;
+	status = "disabled";
+};
+
+&uart8 {
+	pinctrl-0 = <&uart8m0_xfer>;
+	status = "disabled";
+};
+
+&pwm2 {
+	pinctrl-0 = <&pwm2m0_pins>;
+	status = "okay";
+};
diff --git a/kernel-5.10/drivers/gpu/drm/panel/panel-simple.c b/kernel-5.10/drivers/gpu/drm/panel/panel-simple.c
index bd1b7e10bba..628170bf01f 100644
--- a/kernel-5.10/drivers/gpu/drm/panel/panel-simple.c
+++ b/kernel-5.10/drivers/gpu/drm/panel/panel-simple.c
@@ -138,6 +138,8 @@ struct panel_simple {
 
 	struct regulator *supply;
 	struct i2c_adapter *ddc;
+	int force_status;
+	int nvmem_status;
 
 	struct gpio_desc *enable_gpio;
 	struct gpio_desc *reset_gpio;
@@ -489,6 +491,9 @@ static int panel_simple_prepare(struct drm_panel *panel)
 	int err;
 	int hpd_asserted;
 
+	if (!p->nvmem_status && p->force_status != connector_status_connected)
+		return -ENODEV;
+
 	if (p->prepared)
 		return 0;
 
@@ -566,6 +571,10 @@ static int panel_simple_get_modes(struct drm_panel *panel,
 	struct panel_simple *p = to_panel_simple(panel);
 	int num = 0;
 
+	/* be aware of connector (force) status */
+	if (connector)
+		p->force_status = connector->status;
+
 	/* probe EDID if a DDC bus is available */
 	if (p->ddc) {
 		struct edid *edid = drm_get_edid(connector, p->ddc);
@@ -798,6 +807,10 @@ static int panel_simple_probe(struct device *dev, const struct panel_desc *desc)
 		if (err != -EPROBE_DEFER)
 			dev_err(dev, "failed to get reset GPIO: %d\n", err);
 		return err;
+	} else {
+		/* ensure reset gpio as output */
+		gpiod_direction_output_raw(panel->reset_gpio,
+				gpiod_get_raw_value(panel->reset_gpio));
 	}
 
 	err = of_drm_get_panel_orientation(dev->of_node, &panel->orientation);
@@ -5021,6 +5034,33 @@ static int panel_simple_dsi_of_get_desc_data(struct device *dev,
 	return 0;
 }
 
+static int panel_simple_nvm_detect(struct panel_simple *panel)
+{
+	struct device *dev = panel->base.dev;
+	struct of_phandle_args args;
+	u8 chip, addr, nlen;
+	int ret;
+
+	panel->force_status = connector_status_unknown;
+	panel->nvmem_status = 1;
+
+	ret = of_parse_phandle_with_fixed_args(dev->of_node, "nvmems",
+					       3, 0, &args);
+	if (ret)
+		return 1;
+
+	chip = args.args[0];
+	addr = args.args[1];
+	nlen = args.args[2];
+	if (!chip || !addr)
+		return 1;
+
+	device_property_read_u32(dev, "nvmem-status", &panel->nvmem_status);
+	dev_dbg(dev, "panel nvmem status %d\n", panel->nvmem_status);
+
+	return panel->nvmem_status;
+}
+
 static int panel_simple_dsi_probe(struct mipi_dsi_device *dsi)
 {
 	struct panel_simple *panel;
@@ -5055,6 +5095,8 @@ static int panel_simple_dsi_probe(struct mipi_dsi_device *dsi)
 	panel = dev_get_drvdata(dev);
 	panel->dsi = dsi;
 
+	panel_simple_nvm_detect(panel);
+
 	if (!panel->base.backlight) {
 		struct backlight_properties props;
 
diff --git a/kernel-5.10/drivers/gpu/drm/rockchip/dw-mipi-dsi-rockchip.c b/kernel-5.10/drivers/gpu/drm/rockchip/dw-mipi-dsi-rockchip.c
index 9030b9e5d37..dde987fc2dc 100644
--- a/kernel-5.10/drivers/gpu/drm/rockchip/dw-mipi-dsi-rockchip.c
+++ b/kernel-5.10/drivers/gpu/drm/rockchip/dw-mipi-dsi-rockchip.c
@@ -1115,6 +1115,13 @@ static int dw_mipi_dsi_rockchip_probe(struct platform_device *pdev)
 	if (!dsi)
 		return -ENOMEM;
 
+	ret = drm_of_find_panel_or_bridge(dev->of_node, 1, -1,
+					  &dsi->panel, &dsi->bridge);
+	if (ret == -ENODEV) {
+		dev_err(dev, "failed to find panel or bridge: %d\n", ret);
+		return ret;
+	}
+
 	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 	dsi->base = devm_ioremap_resource(dev, res);
 	if (IS_ERR(dsi->base)) {
diff --git a/kernel-5.10/drivers/gpu/drm/rockchip/dw-mipi-dsi2-rockchip.c b/kernel-5.10/drivers/gpu/drm/rockchip/dw-mipi-dsi2-rockchip.c
index c04d1fb713c..6a53cc257d3 100644
--- a/kernel-5.10/drivers/gpu/drm/rockchip/dw-mipi-dsi2-rockchip.c
+++ b/kernel-5.10/drivers/gpu/drm/rockchip/dw-mipi-dsi2-rockchip.c
@@ -245,6 +245,7 @@ struct dw_mipi_dsi2 {
 	bool phy_enabled;
 	struct phy *dcphy;
 	union phy_configure_opts phy_opts;
+	int c_status;
 
 	bool c_option;
 	bool scrambling_en;
@@ -1058,7 +1059,14 @@ dw_mipi_dsi2_connector_detect(struct drm_connector *connector, bool force)
 	if (dsi2->bridge && (dsi2->bridge->ops & DRM_BRIDGE_OP_DETECT))
 		return drm_bridge_detect(dsi2->bridge);
 
-	return connector_status_connected;
+	if (dsi2->c_status == connector_status_unknown) {
+		if (drm_panel_prepare(dsi2->panel) == -ENODEV)
+			dsi2->c_status = connector_status_disconnected;
+		else
+			dsi2->c_status = connector_status_connected;
+	}
+
+	return dsi2->c_status;;
 }
 
 static void dw_mipi_dsi2_drm_connector_destroy(struct drm_connector *connector)
@@ -1276,6 +1284,8 @@ static int dw_mipi_dsi2_bind(struct device *dev, struct device *master,
 		return ret;
 	}
 
+	dsi2->c_status = connector_status_unknown;
+
 	dw_mipi_dsi2_get_dsc_params_from_sink(dsi2, dsi2->panel, dsi2->bridge);
 	encoder->possible_crtcs = rockchip_drm_of_find_possible_crtcs(drm_dev,
 								      of_node);
@@ -1557,6 +1567,13 @@ static int dw_mipi_dsi2_probe(struct platform_device *pdev)
 	if (!dsi2)
 		return -ENOMEM;
 
+	ret = drm_of_find_panel_or_bridge(dev->of_node, 1, -1,
+					  &dsi2->panel, &dsi2->bridge);
+	if (ret == -ENODEV) {
+		dev_err(dev, "Failed to find panel or bridge: %d\n", ret);
+		return ret;
+	}
+
 	id = of_alias_get_id(dev->of_node, "dsi");
 	if (id < 0)
 		id = 0;
diff --git a/kernel-5.10/drivers/gpu/drm/rockchip/rockchip_drm_logo.c b/kernel-5.10/drivers/gpu/drm/rockchip/rockchip_drm_logo.c
index 51fefdf8032..6f191197b20 100644
--- a/kernel-5.10/drivers/gpu/drm/rockchip/rockchip_drm_logo.c
+++ b/kernel-5.10/drivers/gpu/drm/rockchip/rockchip_drm_logo.c
@@ -786,6 +786,9 @@ static int setup_initial_state(struct drm_device *drm_dev,
 		if (set->fb->height >= vdisplay) {
 			primary_state->crtc_y = 0;
 			primary_state->crtc_h = vdisplay;
+		} else if (set->fb->width > hdisplay) {
+			primary_state->crtc_h = (set->fb->height * hdisplay) / set->fb->width;
+			primary_state->crtc_y = (vdisplay - primary_state->crtc_h) / 2;
 		} else {
 			primary_state->crtc_y = (vdisplay - fb_height) / 2;
 			primary_state->crtc_h = fb_height;
diff --git a/kernel-5.10/drivers/input/touchscreen/friendlyelec/gt9xx.c b/kernel-5.10/drivers/input/touchscreen/friendlyelec/gt9xx.c
index 59f2c935378..4c49827583c 100644
--- a/kernel-5.10/drivers/input/touchscreen/friendlyelec/gt9xx.c
+++ b/kernel-5.10/drivers/input/touchscreen/friendlyelec/gt9xx.c
@@ -38,6 +38,8 @@ u8 config[GTP_CONFIG_MAX_LENGTH + GTP_ADDR_LENGTH] = {
 	GTP_REG_CONFIG_DATA & 0xff
 };
 
+static bool gtp_keep_otp_config;
+
 #if GTP_HAVE_TOUCH_KEY
 static const u16 touch_key_array[] = GTP_KEY_TAB;
 #define GTP_MAX_KEY_NUM		ARRAY_SIZE(touch_key_array)
@@ -1410,13 +1412,22 @@ static s32 gtp_init_panel(struct goodix_ts_data *ts)
 	memcpy(&config[GTP_ADDR_LENGTH], send_cfg_buf[sensor_id], ts->gtp_cfg_len);
 #endif
 
-    GTP_INFO("Config group%d used,length: %d", sensor_id, ts->gtp_cfg_len);
+    if (gtp_keep_otp_config) {
+        ts->gtp_cfg_len = 0;
+        memset(&config[GTP_ADDR_LENGTH], 0, GTP_CONFIG_MAX_LENGTH);
+    } else {
+        GTP_INFO("Config group%d used,length: %d", sensor_id, ts->gtp_cfg_len);
+    }
 
     if (ts->gtp_cfg_len < GTP_CONFIG_MIN_LENGTH)
     {
-        GTP_ERROR("Config Group%d is INVALID CONFIG GROUP(Len: %d)! NO Config Sent! You need to check you header file CFG_GROUP section!", sensor_id, ts->gtp_cfg_len);
         ts->pnl_init_error = 1;
 
+        if (!gtp_keep_otp_config) {
+            GTP_ERROR("Config Group%d is INVALID CONFIG GROUP(Len: %d)! NO Config Sent!\n", sensor_id, ts->gtp_cfg_len);
+            GTP_ERROR("You need to check you header file CFG_GROUP section!\n");
+        }
+
         ts->gtp_cfg_len = GTP_CONFIG_MAX_LENGTH;
         ret = gtp_i2c_read(ts->client, config, ts->gtp_cfg_len + GTP_ADDR_LENGTH);
         if (ret < 0)
@@ -2325,6 +2336,12 @@ static void gtp_parse_dt(struct device *dev)
 
 	gtp_int_gpio = of_get_named_gpio(np, "goodix,irq-gpio", 0);
 	gtp_rst_gpio = of_get_named_gpio(np, "goodix,rst-gpio", 0);
+
+#if GTP_DRIVER_SEND_CFG
+	gtp_keep_otp_config = of_property_read_bool(dev->of_node, "keep-otp-config");
+#else
+	gtp_keep_otp_config = true;
+#endif
 }
 
 #ifdef GTP_CONFIG_OF
diff --git a/kernel-5.10/drivers/input/touchscreen/friendlyelec/gt9xx.h b/kernel-5.10/drivers/input/touchscreen/friendlyelec/gt9xx.h
index e91ebe16e2c..c3685c78b4b 100644
--- a/kernel-5.10/drivers/input/touchscreen/friendlyelec/gt9xx.h
+++ b/kernel-5.10/drivers/input/touchscreen/friendlyelec/gt9xx.h
@@ -151,24 +151,6 @@ extern int gtp_int_gpio;
 // TODO: define your own default or for Sensor_ID == 0 config here. 
 // The predefined one is just a sample config, which is not suitable for your tp in most cases.
 #define CTP_CFG_GROUP0 {\
-	/* HD101B */ \
-	0x00,0x00,0x05,0x20,0x03,0x05,0x3D,0x00,0x01,0x08,0x28,\
-	0x05,0x50,0x32,0x03,0x05,0x00,0x00,0x00,0x00,0x00,0x00,\
-	0x01,0x1A,0x1C,0x1E,0x14,0x8E,0x2E,0x88,0x20,0x1E,0x31,\
-	0x0D,0x00,0x00,0x00,0x9C,0x03,0x1D,0x00,0x00,0x00,0x00,\
-	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x28,0x64,0x94,0xC5,\
-	0x02,0x07,0x00,0x00,0x04,0x51,0x2C,0x00,0x4A,0x34,0x00,\
-	0x44,0x3F,0x00,0x40,0x4C,0x00,0x3E,0x5B,0x00,0x3E,0x00,\
-	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,\
-	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,\
-	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,\
-	0x00,0x00,0x00,0x01,0x04,0x05,0x06,0x07,0x08,0x09,0x0C,\
-	0x0D,0x0E,0x0F,0x10,0x11,0x14,0x15,0xFF,0xFF,0xFF,0xFF,\
-	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,\
-	0x02,0x04,0x06,0x07,0x08,0x0A,0x0C,0x0D,0x0F,0x10,0x11,\
-	0x12,0x13,0x19,0x1B,0x1C,0x1E,0x1F,0x20,0x21,0x22,0x23,\
-	0x24,0x25,0x26,0x27,0x28,0xFF,0xFF,0xFF,0xFF,0x00,0x00,\
-	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x1A,0x01\
     }
 
 // TODO: define your config for Sensor_ID == 1 here, if needed
diff --git a/kernel-5.10/drivers/input/touchscreen/gt1x/gt1x_generic.c b/kernel-5.10/drivers/input/touchscreen/gt1x/gt1x_generic.c
index 244d5772d09..4d9c172da7a 100644
--- a/kernel-5.10/drivers/input/touchscreen/gt1x/gt1x_generic.c
+++ b/kernel-5.10/drivers/input/touchscreen/gt1x/gt1x_generic.c
@@ -74,6 +74,7 @@ u32 gt1x_abs_y_max;
 int gt1x_halt;
 bool gt1x_ics_slot_report;
 bool gt1x_keep_otp_config;
+static bool gtp_is_gt911;
 
 #if GTP_DEBUG_NODE
 static ssize_t gt1x_debug_read_proc(struct file *, char __user *, size_t, loff_t *);
@@ -633,12 +634,14 @@ s32 gt1x_init_panel(void)
 #endif /* END GTP_DRIVER_SEND_CFG */
 
 	if (gt1x_keep_otp_config) {
+		u16 cfg_reg = gtp_is_gt911 ? 0x8047 : GTP_REG_CONFIG_DATA;
+
 		cfg_len = GTP_CONFIG_MAX_LENGTH;
-		ret = gt1x_i2c_read(GTP_REG_CONFIG_DATA, gt1x_config, cfg_len);
+		ret = gt1x_i2c_read(cfg_reg, gt1x_config, cfg_len);
 		if (ret < 0) {
 			GTP_ERROR("Failed to read CONFIG data, sensor_id %d", gt1x_version.sensor_id);
 			return ret;
-		} else {
+		} else if (!gtp_is_gt911) {
 			int i;
 			u16 checksum = 0;
 			for (i = 0; i < cfg_len - 4; i += 2) {
@@ -876,6 +879,7 @@ s32 gt1x_read_version(struct gt1x_version_info *ver_info)
 	sensor_id = buf[10] & 0x0F;
 	match_opt = (buf[10] >> 4) & 0x0F;
 
+	gtp_is_gt911 = !strncmp(product_id, "911", 3);
 	GTP_INFO("IC VERSION:GT%s_%06X(Patch)_%04X(Mask)_%02X(SensorID)", product_id, patch_id, mask_id >> 8, sensor_id);
 
 	if (ver_info != NULL) {
@@ -1184,6 +1188,8 @@ s32 gt1x_touch_event_handler(u8 *data, struct input_dev *dev, struct input_dev *
 		if (ret) {
 			return ret;
 		}
+		if (gtp_is_gt911)
+			goto skip_checksum;
 
 		for (i = 0, check_sum = 0; i < 3 + 8 * touch_num; i++) {
 			check_sum += touch_data[i];
@@ -1193,6 +1199,8 @@ s32 gt1x_touch_event_handler(u8 *data, struct input_dev *dev, struct input_dev *
 			return ERROR_VALUE;
 		}
 	}
+
+skip_checksum:
 	/*
 	 * cur_event , pre_event bit defination
 	 * bits:     bit4	bit3		    bit2	 bit1	   bit0
diff --git a/kernel-5.10/drivers/net/phy/realtek.c b/kernel-5.10/drivers/net/phy/realtek.c
index e3c77485f9a..915a627f910 100644
--- a/kernel-5.10/drivers/net/phy/realtek.c
+++ b/kernel-5.10/drivers/net/phy/realtek.c
@@ -8,6 +8,7 @@
  * Copyright (c) 2004 Freescale Semiconductor, Inc.
  */
 #include <linux/bitops.h>
+#include <linux/of.h>
 #include <linux/phy.h>
 #include <linux/module.h>
 #include <linux/delay.h>
@@ -72,6 +73,15 @@ static int rtl821x_write_page(struct phy_device *phydev, int page)
 	return __phy_write(phydev, RTL821x_PAGE_SELECT, page);
 }
 
+static void rtl821x_led_of_init(struct phy_device *phydev)
+{
+	struct device *dev = &phydev->mdio.dev;
+	u32 val;
+
+	if (!of_property_read_u32(dev->of_node, "realtek,ledsel", &val))
+		phy_write_paged(phydev, 0xd04, 0x10, val);
+}
+
 static int rtl8201_ack_interrupt(struct phy_device *phydev)
 {
 	int err;
@@ -243,6 +253,8 @@ static int rtl8211f_config_init(struct phy_device *phydev)
 			val_rxdly ? "enabled" : "disabled");
 	}
 
+	rtl821x_led_of_init(phydev);
+
 	return 0;
 }
 
diff --git a/kernel-5.10/drivers/phy/rockchip/phy-rockchip-naneng-combphy.c b/kernel-5.10/drivers/phy/rockchip/phy-rockchip-naneng-combphy.c
index 36b84206040..6c8e380e0bd 100644
--- a/kernel-5.10/drivers/phy/rockchip/phy-rockchip-naneng-combphy.c
+++ b/kernel-5.10/drivers/phy/rockchip/phy-rockchip-naneng-combphy.c
@@ -35,6 +35,7 @@ struct rockchip_combphy_grfcfg {
 	struct combphy_reg usb_mode_set;
 	struct combphy_reg sgmii_mode_set;
 	struct combphy_reg qsgmii_mode_set;
+	struct combphy_reg pipe_ebuff_mode;
 	struct combphy_reg pipe_rxterm_set;
 	struct combphy_reg pipe_txelec_set;
 	struct combphy_reg pipe_txcomp_set;
@@ -297,15 +298,23 @@ static struct phy *rockchip_combphy_xlate(struct device *dev,
 					  struct of_phandle_args *args)
 {
 	struct rockchip_combphy_priv *priv = dev_get_drvdata(dev);
+	bool no_overwrite = false;
 
-	if (args->args_count != 1) {
+	if (args->args_count < 1) {
 		dev_err(dev, "invalid number of arguments\n");
 		return ERR_PTR(-EINVAL);
 	}
 
-	if (priv->mode != PHY_NONE && priv->mode != args->args[0])
-		dev_warn(dev, "phy type select %d overwriting type %d\n",
-			 args->args[0], priv->mode);
+	if (args->args_count == 2 && args->args[1] == 1)
+		no_overwrite = true;
+
+	if (priv->mode != PHY_NONE && priv->mode != args->args[0]) {
+		dev_warn(dev, "phy type select %d %soverwriting type %d\n",
+			 args->args[0], no_overwrite ? "no-" : "", priv->mode);
+
+		if (no_overwrite)
+			return ERR_PTR(-EBUSY);
+	}
 
 	priv->mode = args->args[0];
 
@@ -1079,12 +1088,21 @@ static int rk3588_combphy_cfg(struct rockchip_combphy_priv *priv)
 		/* Set tx_rterm = 50 ohm and rx_rterm = 43.5 ohm */
 		writel(0x8F, priv->mmio + (0x06 << 2));
 
+		/* Invert RX output data polarity (TBC) */
+		val = readl(priv->mmio + 0x4c);
+		val |= BIT(4);
+		writel(val, priv->mmio + 0x4c);
+
 		param_write(priv->phy_grf, &cfg->con0_for_sata, true);
 		param_write(priv->phy_grf, &cfg->con1_for_sata, true);
 		param_write(priv->phy_grf, &cfg->con2_for_sata, true);
 		param_write(priv->phy_grf, &cfg->con3_for_sata, true);
 		param_write(priv->pipe_grf, &cfg->pipe_con0_for_sata, true);
 		param_write(priv->pipe_grf, &cfg->pipe_con1_for_sata, true);
+
+		if (device_property_read_bool(priv->dev, "rockchip,ebuff-mode"))
+			param_write(priv->phy_grf, &cfg->pipe_ebuff_mode, true);
+
 		break;
 	case PHY_TYPE_SGMII:
 	case PHY_TYPE_QSGMII:
@@ -1228,6 +1246,7 @@ static const struct rockchip_combphy_grfcfg rk3588_combphy_grfcfgs = {
 	/* pipe-phy-grf */
 	.pcie_mode_set		= { 0x0000, 5, 0, 0x00, 0x11 },
 	.usb_mode_set		= { 0x0000, 5, 0, 0x00, 0x04 },
+	.pipe_ebuff_mode	= { 0x0000, 10, 10, 0x00, 0x01 },
 	.pipe_rxterm_set	= { 0x0000, 12, 12, 0x00, 0x01 },
 	.pipe_txelec_set	= { 0x0004, 1, 1, 0x00, 0x01 },
 	.pipe_txcomp_set	= { 0x0004, 4, 4, 0x00, 0x01 },
@@ -1246,7 +1265,7 @@ static const struct rockchip_combphy_grfcfg rk3588_combphy_grfcfgs = {
 	.con0_for_sata		= { 0x0000, 15, 0, 0x00, 0x0129 },
 	.con1_for_sata		= { 0x0004, 15, 0, 0x00, 0x0000 },
 	.con2_for_sata		= { 0x0008, 15, 0, 0x00, 0x80c1 },
-	.con3_for_sata		= { 0x000c, 15, 0, 0x00, 0x0407 },
+	.con3_for_sata		= { 0x000c, 15, 0, 0x00, 0x4407 },
 	/* pipe-grf */
 	.pipe_con0_for_sata	= { 0x0000, 11, 5, 0x00, 0x22 },
 	.pipe_con1_for_sata	= { 0x0004, 2, 0, 0x00, 0x2 },