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rk35xx-android12
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[u-boot] merge commit '353b697041..f594019f90'

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Signed-off-by: hmz007 <hmz007@gmail.com>
master
hmz007 11 months ago
parent 03b0305f47
commit dc650502af
6 changed files with 136 additions and 4 deletions
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6
u-boot/arch/arm/mach-rockchip/fit_nodes.sh
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@ -171,6 +171,12 @@ function gen_bl32_node()
# If not AArch32 mode
if ! grep -q '^CONFIG_ARM64_BOOT_AARCH32=y' .config ; then
ENTRY="entry = <"${TEE_LOAD_ADDR}">;"
# if disable packing tee.bin
if ! grep -q '^CONFIG_SPL_OPTEE=y' .config ; then
return
fi
fi
fi

17
u-boot/arch/arm/mach-rockchip/rk3568/rk3568.c
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@ -777,6 +777,23 @@ void board_debug_uart_init(void)
#endif
}
int fit_standalone_release(char *id, uintptr_t entry_point)
{
/* risc-v configuration: */
/* Reset the scr1 */
writel(0x04000400, CRU_BASE + CRU_SOFTRST_CON26);
udelay(100);
/* set the scr1 addr */
writel((0xffff0000) | (entry_point >> 16), GRF_BASE + GRF_SOC_CON4);
udelay(10);
/* release the scr1 */
writel(0x04000000, CRU_BASE + CRU_SOFTRST_CON26);
return 0;
}
#if defined(CONFIG_SPL_BUILD) && !defined(CONFIG_TPL_BUILD)
static void qos_priority_init(void)
{

23
u-boot/board/rockchip/nanopi5/board.c
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@ -41,6 +41,29 @@ int board_usb_init(int index, enum usb_init_type init)
}
#endif
/* Supported panels and dpi for nanopi5 series */
static char *panels[] = {
"HDMI1024x768,165dpi",
"HDMI1280x800,168dpi",
};
char *board_get_panel_name(void)
{
char *name;
int i;
name = env_get("panel");
if (!name)
return NULL;
for (i = 0; i < ARRAY_SIZE(panels); i++) {
if (!strncmp(panels[i], name, strlen(name)))
return panels[i];
}
return name;
}
int board_select_fdt_index(ulong dt_table_hdr, struct blk_desc *dev_desc)
{
return (dev_desc ? dev_desc->devnum : 0);

3
u-boot/cmd/fdt.c
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@ -32,6 +32,9 @@ static int fdt_parse_prop(char *const*newval, int count, char *data, int *len);
static int fdt_print(const char *pathp, char *prop, int depth);
static int is_printable_string(const void *data, int len);
#undef isprint
#define isprint(c) (((c) > 0x1f) && ((c) < 0x7f))
/*
* The working_fdt points to our working flattened device tree.
*/

3
u-boot/drivers/video/drm/dw_hdmi_qp.c
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@ -1093,7 +1093,10 @@ static int dw_hdmi_setup(struct dw_hdmi_qp *hdmi,
hdmi_modb(hdmi, PKTSCHED_GCP_TX_EN, PKTSCHED_GCP_TX_EN,
PKTSCHED_PKT_EN);
} else {
hdmi_modb(hdmi, HDCP2_BYPASS, HDCP2_BYPASS, HDCP2LOGIC_CONFIG0);
hdmi_modb(hdmi, OPMODE_DVI, OPMODE_DVI, LINK_CONFIG0);
hdmi_writel(hdmi, 2, PKTSCHED_PKT_CONTROL0);
hdmi_modb(hdmi, PKTSCHED_GCP_TX_EN, PKTSCHED_GCP_TX_EN, PKTSCHED_PKT_EN);
ret = hdmi->phy.ops->init(conn, hdmi->rk_hdmi, state);
if (ret)
return ret;

88
u-boot/drivers/video/drm/phy-rockchip-samsung-hdptx-hdmi.c
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@ -693,6 +693,16 @@ struct ropll_config {
u8 cd_tx_ser_rate_sel;
};
struct phy_config {
unsigned long pixelclk;
u8 tx_ctrl_ln0;
u8 tx_ctrl_ln1;
u8 tx_ctrl_ln2;
u8 tx_ctrl_ln3;
};
#define PHY_TAB_LEN 5
struct rockchip_hdptx_phy {
struct udevice *dev;
void __iomem *base;
@ -712,6 +722,8 @@ struct rockchip_hdptx_phy {
struct reset_ctl phy_reset;
struct reset_ctl ropll_reset;
struct reset_ctl lcpll_reset;
struct phy_config *phy_cfg;
};
struct clk_hdptx {
@ -819,6 +831,68 @@ struct ropll_config ropll_tmds_cfg[] = {
},
};
static int rockchip_hdptx_parse_phy_table(struct rockchip_hdptx_phy *hdptx)
{
struct udevice *dev = hdptx->dev;
struct phy_config *phy_cfg;
u32 *phy_table;
int i, num_cfg;
dev_read_prop(dev, "rockchip,phy-table", &i);
if (i >= PHY_TAB_LEN) {
phy_table = malloc(i);
if (!phy_table)
return -ENOMEM;
num_cfg = i / (sizeof(u32) * PHY_TAB_LEN);
phy_cfg = malloc(sizeof(*phy_cfg) * (num_cfg + 1));
if (!phy_cfg) {
free(phy_table);
return -ENOMEM;
}
dev_read_u32_array(dev, "rockchip,phy-table",
phy_table, i / sizeof(u32));
for (i = 0; i < num_cfg; i++) {
if (phy_table[i * PHY_TAB_LEN] != 0)
phy_cfg[i].pixelclk = phy_table[i * PHY_TAB_LEN];
else
phy_cfg[i].pixelclk = ~0UL;
phy_cfg[i].tx_ctrl_ln0 = (u8)phy_table[i * PHY_TAB_LEN + 1];
phy_cfg[i].tx_ctrl_ln1 = (u8)phy_table[i * PHY_TAB_LEN + 2];
phy_cfg[i].tx_ctrl_ln2 = (u8)phy_table[i * PHY_TAB_LEN + 3];
phy_cfg[i].tx_ctrl_ln3 = (u8)phy_table[i * PHY_TAB_LEN + 4];
}
phy_cfg[i].pixelclk = ~0UL;
hdptx->phy_cfg = phy_cfg;
free(phy_table);
}
return 0;
}
static void rockchip_hdptx_get_tx_ctrl(struct rockchip_hdptx_phy *hdptx, u8 *tx_ctrl)
{
struct phy_config *pcfg = hdptx->phy_cfg;
if (!pcfg || !tx_ctrl)
return;
for (; pcfg->pixelclk != ~0UL; pcfg++) {
if (hdptx->rate <= pcfg->pixelclk) {
tx_ctrl[0] = pcfg->tx_ctrl_ln0;
tx_ctrl[1] = pcfg->tx_ctrl_ln1;
tx_ctrl[2] = pcfg->tx_ctrl_ln2;
tx_ctrl[3] = pcfg->tx_ctrl_ln3;
return;
}
}
}
static inline void hdptx_write(struct rockchip_hdptx_phy *hdptx, uint reg,
uint val)
{
@ -1372,6 +1446,9 @@ static int hdptx_ropll_tmds_mode_config(struct rockchip_hdptx_phy *hdptx, u32 ra
{
u32 bit_rate = rate & DATA_RATE_MASK;
u8 color_depth = (rate & COLOR_DEPTH_MASK) ? 1 : 0;
u8 tx_ctrl[4] = { 0x2f, 0x2f, 0x2f, 0x2f };
rockchip_hdptx_get_tx_ctrl(hdptx, tx_ctrl);
if (color_depth)
bit_rate = bit_rate * 5 / 4;
@ -1460,10 +1537,11 @@ static int hdptx_ropll_tmds_mode_config(struct rockchip_hdptx_phy *hdptx, u32 ra
hdptx_write(hdptx, LANE_REG061F, 0x15);
hdptx_write(hdptx, LANE_REG0620, 0xa0);
hdptx_write(hdptx, LANE_REG0303, 0x2f);
hdptx_write(hdptx, LANE_REG0403, 0x2f);
hdptx_write(hdptx, LANE_REG0503, 0x2f);
hdptx_write(hdptx, LANE_REG0603, 0x2f);
hdptx_write(hdptx, LANE_REG0303, tx_ctrl[0]);
hdptx_write(hdptx, LANE_REG0403, tx_ctrl[1]);
hdptx_write(hdptx, LANE_REG0503, tx_ctrl[2]);
hdptx_write(hdptx, LANE_REG0603, tx_ctrl[3]);
hdptx_write(hdptx, LANE_REG0305, 0x03);
hdptx_write(hdptx, LANE_REG0405, 0x03);
hdptx_write(hdptx, LANE_REG0505, 0x03);
@ -1954,6 +2032,8 @@ static int rockchip_hdptx_phy_hdmi_probe(struct udevice *dev)
return ret;
}
rockchip_hdptx_parse_phy_table(hdptx);
return 0;
}

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