// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
 * Copyright (c) 2021 FriendlyElec Computer Tech. Co., Ltd.
 * (http://www.friendlyarm.com)
 *
 * Copyright (c) 2020 Rockchip Electronics Co., Ltd.
 */

/dts-v1/;

#include "rk3568.dtsi"
#include "rk3568-nanopi5-common.dtsi"

/ {
	model = "FriendlyElec NanoPi R5S";
	compatible = "friendlyelec,nanopi-r5s", "rockchip,rk3568";

	aliases {
		ethernet1 = &r8125_1;
	};

	fan: pwm-fan {
		compatible = "pwm-fan";
		cooling-levels = <0 18 102 170 255>;
		#cooling-cells = <2>;
		fan-supply = <&vcc5v0_sysp>;
		pwms = <&pwm0 0 50000 0>;
	};

	gpio_leds: gpio-leds {
		compatible = "gpio-leds";

		sys_led: led-0 {
			gpios = <&gpio4 RK_PD2 GPIO_ACTIVE_HIGH>;
			label = "sys_led";
			linux,default-trigger = "heartbeat";
			pinctrl-names = "default";
			pinctrl-0 = <&sys_led_pin>;
		};

		wan_led: led-1 {
			gpios = <&gpio2 RK_PC1 GPIO_ACTIVE_HIGH>;
			label = "wan_led";
			pinctrl-names = "default";
			pinctrl-0 = <&wan_led_pin>;
		};

		lan1_led: led-2 {
			gpios = <&gpio3 RK_PD6 GPIO_ACTIVE_HIGH>;
			label = "lan1_led";
			pinctrl-names = "default";
			pinctrl-0 = <&lan1_led_pin>;
		};

		lan2_led: led-3 {
			gpios = <&gpio3 RK_PD7 GPIO_ACTIVE_HIGH>;
			label = "lan2_led";
			pinctrl-names = "default";
			pinctrl-0 = <&lan2_led_pin>;
		};
	};

	pcie30_avdd0v9: pcie30-avdd0v9 {
		compatible = "regulator-fixed";
		regulator-name = "pcie30_avdd0v9";
		regulator-always-on;
		regulator-boot-on;
		regulator-min-microvolt = <900000>;
		regulator-max-microvolt = <900000>;
		vin-supply = <&vcc3v3_sys>;
	};

	pcie30_avdd1v8: pcie30-avdd1v8 {
		compatible = "regulator-fixed";
		regulator-name = "pcie30_avdd1v8";
		regulator-always-on;
		regulator-boot-on;
		regulator-min-microvolt = <1800000>;
		regulator-max-microvolt = <1800000>;
		vin-supply = <&vcc3v3_sys>;
	};

	vcc3v3_pcie: gpio-regulator {
		compatible = "regulator-fixed";
		regulator-name = "vcc3v3_pcie";
		regulator-min-microvolt = <3300000>;
		regulator-max-microvolt = <3300000>;
		enable-active-high;
		gpio = <&gpio0 RK_PD4 GPIO_ACTIVE_HIGH>;
		startup-delay-us = <5000>;
		vin-supply = <&vcc3v3_sysp>;
	};
};

&combphy0_us {
	status = "okay";
};

&combphy1_usq {
	status = "okay";
};

&combphy2_psq {
	status = "okay";
};

&dfi {
	status = "disabled";
};

&dmc {
	status = "disabled";
};

&gmac0 {
	phy-mode = "rgmii";
	clock_in_out = "output";

	snps,reset-gpio = <&gpio0 RK_PC5 GPIO_ACTIVE_LOW>;
	snps,reset-active-low;
	/* Reset time is 15ms, 50ms for rtl8211f */
	snps,reset-delays-us = <0 15000 50000>;

	assigned-clocks = <&cru SCLK_GMAC0_RX_TX>, <&cru SCLK_GMAC0>;
	assigned-clock-parents = <&cru SCLK_GMAC0_RGMII_SPEED>, <&cru CLK_MAC0_2TOP>;
	assigned-clock-rates = <0>, <125000000>;

	pinctrl-names = "default";
	pinctrl-0 = <&gmac0_miim
		     &gmac0_tx_bus2
		     &gmac0_rx_bus2
		     &gmac0_rgmii_clk
		     &gmac0_rgmii_bus>;

	tx_delay = <0x3c>;
	rx_delay = <0x2f>;

	phy-handle = <&rgmii_phy0>;
	status = "okay";
};

&mach {
    hwrev = <1>;
    model = "NanoPi R5S";
};

&mdio0 {
	rgmii_phy0: phy@1 {
		compatible = "ethernet-phy-ieee802.3-c22";
		reg = <0x1>;
		interrupt-parent = <&gpio0>;
		interrupts = <RK_PC4 IRQ_TYPE_LEVEL_LOW>;
		pinctrl-names = "default";
		pinctrl-0 = <&gmac_int>;
	};
};

&i2c5 {
	status = "okay";

	hym8563: hym8563@51 {
		compatible = "haoyu,hym8563";
		reg = <0x51>;
		pinctrl-names = "default";
		pinctrl-0 = <&rtc_int>;
		interrupt-parent = <&gpio0>;
		interrupts = <RK_PD3 IRQ_TYPE_LEVEL_LOW>;
		wakeup-source;
	};
};

&pcie30phy {
	status = "okay";
};

&pcie2x1 {
	num-viewport = <4>;
	reset-gpios = <&gpio0 RK_PB6 GPIO_ACTIVE_HIGH>;
	status = "okay";

	pcie@00 {
		reg = <0x00000000 0 0 0 0>;
		#address-cells = <3>;
		#size-cells = <2>;

		r8125_1: pcie@01,0 {
			reg = <0x000000 0 0 0 0>;
			local-mac-address = [ 00 00 00 00 00 00 ];
		};
	};
};

&pcie3x1 {
	num-viewport = <4>;
	rockchip,bifurcation;
	rockchip,init-delay-ms = <100>;
	reset-gpios = <&gpio0 RK_PA0 GPIO_ACTIVE_HIGH>;
	status = "okay";

	pcie@10 {
		reg = <0x00100000 0 0 0 0>;
		#address-cells = <3>;
		#size-cells = <2>;

		r8125_2: pcie@10,0 {
			reg = <0x000000 0 0 0 0>;
			local-mac-address = [ 00 00 00 00 00 00 ];
		};
	};
};

&pcie3x2 {
	max-link-speed = <2>;
	num-lanes = <1>;
	num-ib-windows = <8>;
	num-ob-windows = <8>;
	num-viewport = <4>;
	rockchip,bifurcation;
	reset-gpios = <&gpio2 RK_PD6 GPIO_ACTIVE_HIGH>;
	vpcie3v3-supply = <&vcc3v3_pcie>;
	status = "okay";
};

&pinctrl {
	gpio-leds {
		sys_led_pin: sys-led-pin {
			rockchip,pins =
				<4 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>;
		};

		wan_led_pin: wan-led-pin {
			rockchip,pins =
				<2 RK_PC1 RK_FUNC_GPIO &pcfg_pull_none>;
		};

		lan1_led_pin: lan1-led-pin {
			rockchip,pins =
				<3 RK_PD6 RK_FUNC_GPIO &pcfg_pull_none>;
		};

		lan2_led_pin: lan2-led-pin {
			rockchip,pins =
				<3 RK_PD7 RK_FUNC_GPIO &pcfg_pull_none>;
		};
	};

	gmac {
		gmac_int: gmac-int {
			rockchip,pins =
				<0 RK_PC4 RK_FUNC_GPIO &pcfg_pull_up>;
		};
	};

	rtc {
		rtc_int: rtc-int {
			rockchip,pins =
				<0 RK_PD3 RK_FUNC_GPIO &pcfg_pull_up>;
		};
	};
};

&sata2 {
	status = "disabled";
};

&soc_thermal {
	trips {
		cpu_warm: cpu_warm {
			temperature = <55000>;
			hysteresis = <2000>;
			type = "active";
		};

		cpu_hot: cpu_hot {
			temperature = <65000>;
			hysteresis = <2000>;
			type = "active";
		};
	};

	cooling-maps {
		map2 {
			trip = <&cpu_warm>;
			cooling-device = <&fan THERMAL_NO_LIMIT 1>;
		};

		map3 {
			trip = <&cpu_hot>;
			cooling-device = <&fan 2 THERMAL_NO_LIMIT>;
		};
	};
};

/* GPIO Connector */
&spi1 {
	num-cs = <1>;
	pinctrl-0 = <&spi1m1_cs0 &spi1m1_pins>;
	pinctrl-1 = <&spi1m1_cs0 &spi1m1_pins_hs>;
	status = "disabled";
};

&uart5 {
	pinctrl-0 = <&uart5m1_xfer>;
	status = "disabled";
};

&uart7 {
	pinctrl-0 = <&uart7m1_xfer>;
	status = "disabled";
};

&uart9 {
	pinctrl-0 = <&uart9m1_xfer>;
	status = "okay";
};