// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
 * Copyright (c) 2020 Rockchip Electronics Co., Ltd.
 *
 */

/dts-v1/;

#include "rk3568.dtsi"
#include "rk3568-evb.dtsi"

/ {
	model = "Rockchip RK3568 EVB6 DDR3 V10 Board";
	compatible = "rockchip,rk3568-evb6-ddr3-v10", "rockchip,rk3568";

	rk_headset: rk-headset {
		compatible = "rockchip_headset";
		headset_gpio = <&gpio3 RK_PC2 GPIO_ACTIVE_LOW>;
		pinctrl-names = "default";
		pinctrl-0 = <&hp_det>;
	};

	vcc3v3_pcie: gpio-regulator {
		compatible = "regulator-fixed";
		regulator-name = "vcc3v3_pcie";
		regulator-min-microvolt = <3300000>;
		regulator-max-microvolt = <3300000>;
		enable-active-high;
		gpio = <&gpio0 RK_PD4 GPIO_ACTIVE_HIGH>;
		startup-delay-us = <5000>;
		vin-supply = <&dc_12v>;
	};

	vcc_camera: vcc-camera-regulator {
		compatible = "regulator-fixed";
		gpio = <&gpio0 RK_PC1 GPIO_ACTIVE_HIGH>;
		pinctrl-names = "default";
		pinctrl-0 = <&camera_pwr>;
		regulator-name = "vcc_camera";
		enable-active-high;
		regulator-always-on;
		regulator-boot-on;
	};
};

&combphy0_us {
	status = "okay";
};

&combphy1_usq {
	rockchip,dis-u3otg1-port;
	status = "okay";
};

&combphy2_psq {
	status = "okay";
};

/*
 * video_phy0 needs to be enabled
 * when dsi0 is enabled
 */
&dsi0 {
	status = "okay";
};

&dsi0_in_vp0 {
	status = "disabled";
};

&dsi0_in_vp1 {
	status = "okay";
};

&dsi0_panel {
	power-supply = <&vcc3v3_lcd0_n>;
};

/*
 * video_phy1 needs to be enabled
 * when dsi1 is enabled
 */
&dsi1 {
	status = "disabled";
};

&dsi1_in_vp0 {
	status = "disabled";
};

&dsi1_in_vp1 {
	status = "disabled";
};

&dsi1_panel {
	power-supply = <&vcc3v3_lcd1_n>;
};

/*
 * power-supply should switche to vcc3v3_lcd1_n
 * when mipi panel is connected to dsi1.
 */
&gt1x {
	power-supply = <&vcc3v3_lcd0_n>;
};

&i2c2 {
	status = "okay";
	pinctrl-names = "default";
	pinctrl-0 = <&i2c2m1_xfer>;

	mxc6655xa: mxc6655xa@15 {
		status = "okay";
		compatible = "gs_mxc6655xa";
		pinctrl-names = "default";
		pinctrl-0 = <&mxc6655xa_irq_gpio>;
		reg = <0x15>;
		irq-gpio = <&gpio3 RK_PC1 IRQ_TYPE_LEVEL_LOW>;
		irq_enable = <0>;
		poll_delay_ms = <30>;
		type = <SENSOR_TYPE_ACCEL>;
		power-off-in-suspend = <1>;
		layout = <4>;
	};
};

&i2c4 {
	status = "okay";
	os04a10: os04a10@36 {
		compatible = "ovti,os04a10";
		reg = <0x36>;
		clocks = <&cru CLK_CAM0_OUT>;
		clock-names = "xvclk";
		power-domains = <&power RK3568_PD_VI>;
		pinctrl-names = "default";
		pinctrl-0 = <&cam_clkout0>;
		reset-gpios = <&gpio2 RK_PD5 GPIO_ACTIVE_LOW>;
		pwdn-gpios = <&gpio4 RK_PA6 GPIO_ACTIVE_HIGH>;
		/* power-gpios = <&gpio0 RK_PC1 GPIO_ACTIVE_HIGH>; */
		rockchip,camera-module-index = <0>;
		rockchip,camera-module-facing = "back";
		rockchip,camera-module-name = "CMK-OT1607-FV1";
		/* rockchip,camera-module-lens-name = "M12-4IR-4MP-F16"; */
		rockchip,camera-module-lens-name = "M12-40IRC-4MP-F16";
		port {
			ucam_out0: endpoint {
				remote-endpoint = <&mipi_in_ucam0>;
				data-lanes = <1 2 3 4>;
			};
		};
	};
	gc8034: gc8034@37 {
		compatible = "galaxycore,gc8034";
		reg = <0x37>;
		clocks = <&cru CLK_CAM0_OUT>;
		clock-names = "xvclk";
		power-domains = <&power RK3568_PD_VI>;
		pinctrl-names = "default";
		pinctrl-0 = <&cam_clkout0>;
		reset-gpios = <&gpio2 RK_PD5 GPIO_ACTIVE_LOW>;
		pwdn-gpios = <&gpio4 RK_PA6 GPIO_ACTIVE_LOW>;
		rockchip,grf = <&grf>;
		rockchip,camera-module-index = <0>;
		rockchip,camera-module-facing = "back";
		rockchip,camera-module-name = "RK-CMK-8M-2-v1";
		rockchip,camera-module-lens-name = "CK8401";
		port {
			gc8034_out: endpoint {
				remote-endpoint = <&mipi_in_ucam1>;
				data-lanes = <1 2 3 4>;
			};
		};
	};
	ov5695: ov5695@36 {
		status = "okay";
		compatible = "ovti,ov5695";
		reg = <0x36>;
		clocks = <&cru CLK_CAM0_OUT>;
		clock-names = "xvclk";
		power-domains = <&power RK3568_PD_VI>;
		pinctrl-names = "default";
		pinctrl-0 = <&cam_clkout0>;
		reset-gpios = <&gpio2 RK_PD5 GPIO_ACTIVE_LOW>;
		pwdn-gpios = <&gpio4 RK_PA6 GPIO_ACTIVE_HIGH>;
		rockchip,camera-module-index = <0>;
		rockchip,camera-module-facing = "back";
		rockchip,camera-module-name = "TongJu";
		rockchip,camera-module-lens-name = "CHT842-MD";
		port {
			ov5695_out: endpoint {
				remote-endpoint = <&mipi_in_ucam2>;
				data-lanes = <1 2>;
			};
		};
	};
};

&i2c5 {
	status = "disabled";

	/delete-node/ mxc6655xa@15;
};

&csi2_dphy_hw {
	status = "okay";
};

&csi2_dphy0 {
	status = "okay";

	ports {
		#address-cells = <1>;
		#size-cells = <0>;
		port@0 {
			reg = <0>;
			#address-cells = <1>;
			#size-cells = <0>;

			mipi_in_ucam0: endpoint@1 {
				reg = <1>;
				remote-endpoint = <&ucam_out0>;
				data-lanes = <1 2 3 4>;
			};
			mipi_in_ucam1: endpoint@2 {
				reg = <2>;
				remote-endpoint = <&gc8034_out>;
				data-lanes = <1 2 3 4>;
			};
			mipi_in_ucam2: endpoint@3 {
				reg = <3>;
				remote-endpoint = <&ov5695_out>;
				data-lanes = <1 2>;
			};
		};
		port@1 {
			reg = <1>;
			#address-cells = <1>;
			#size-cells = <0>;

			csidphy_out: endpoint@0 {
				reg = <0>;
				remote-endpoint = <&isp0_in>;
			};
		};
	};
};

&rkisp {
	status = "okay";
};

&rkisp_mmu {
	status = "okay";
};

&rkisp_vir0 {
	status = "okay";

	port {
		#address-cells = <1>;
		#size-cells = <0>;

		isp0_in: endpoint@0 {
			reg = <0>;
			remote-endpoint = <&csidphy_out>;
		};
	};
};

&video_phy0 {
	status = "okay";
};

&video_phy1 {
	status = "disabled";
};

&pcie30phy {
	status = "okay";
};

&pcie2x1 {
	reset-gpios = <&gpio1 RK_PB2 GPIO_ACTIVE_HIGH>;
	vpcie3v3-supply = <&vcc3v3_pcie>;
	status = "okay";
};

&pcie3x1 {
	rockchip,bifurcation;
	reset-gpios = <&gpio3 RK_PA1 GPIO_ACTIVE_HIGH>;
	vpcie3v3-supply = <&vcc3v3_pcie>;
	status = "okay";
};

&pcie3x2 {
	rockchip,bifurcation;
	reset-gpios = <&gpio2 RK_PD6 GPIO_ACTIVE_HIGH>;
	vpcie3v3-supply = <&vcc3v3_pcie>;
	status = "okay";
};

&pinctrl {
	cam {
		camera_pwr: camera-pwr {
			rockchip,pins =
				/* camera power en */
				<0 RK_PC1 RK_FUNC_GPIO &pcfg_pull_none>;
		};
	};

	headphone {
		hp_det: hp-det {
			rockchip,pins = <3 RK_PC2 RK_FUNC_GPIO &pcfg_pull_down>;
		};
	};

	sdio-pwrseq {
		wifi_enable_h: wifi-enable-h {
			rockchip,pins = <2 RK_PB1 RK_FUNC_GPIO &pcfg_pull_none>;
		};

		wifi_32k: wifi-32k {
			rockchip,pins = <2 RK_PC6 1 &pcfg_pull_none>;
		};
	};

	wireless-wlan {
		wifi_host_wake_irq: wifi-host-wake-irq {
			rockchip,pins = <2 RK_PB2 RK_FUNC_GPIO &pcfg_pull_down>;
		};
	};

	wireless-bluetooth {
		uart1_gpios: uart1-gpios {
			rockchip,pins = <2 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>;
		};
	};
};

&route_dsi0 {
	status = "okay";
	connect = <&vp1_out_dsi0>;
};

&sdmmc1 {
	max-frequency = <150000000>;
	no-sd;
	no-mmc;
	bus-width = <4>;
	disable-wp;
	cap-sd-highspeed;
	cap-sdio-irq;
	keep-power-in-suspend;
	mmc-pwrseq = <&sdio_pwrseq>;
	non-removable;
	pinctrl-names = "default";
	pinctrl-0 = <&sdmmc1_bus4 &sdmmc1_cmd &sdmmc1_clk>;
	sd-uhs-sdr104;
	status = "okay";
};

&sdmmc2 {
	status = "disabled";
};

&sdio_pwrseq {
	clocks = <&pmucru CLK_RTC_32K>;
	pinctrl-0 = <&wifi_enable_h &wifi_32k>;

	/*
	 * On the module itself this is one of these (depending
	 * on the actual card populated):
	 * - SDIO_RESET_L_WL_REG_ON
	 * - PDN (power down when low)
	 */
	reset-gpios = <&gpio2 RK_PB1 GPIO_ACTIVE_LOW>;
};

&spdif_8ch {
	status = "disabled";
};

&uart1 {
	status = "okay";
	pinctrl-names = "default";
	pinctrl-0 = <&uart1m0_xfer &uart1m0_ctsn>;
};

&usbhost_dwc3 {
	phys = <&u2phy0_host>;
	phy-names = "usb2-phy";
	maximum-speed = "high-speed";
	status = "okay";
};

&vcc3v3_lcd0_n {
	gpio = <&gpio0 RK_PC7 GPIO_ACTIVE_HIGH>;
	enable-active-high;
};

&vcc3v3_lcd1_n {
	gpio = <&gpio0 RK_PC5 GPIO_ACTIVE_HIGH>;
	enable-active-high;
};

&wireless_wlan {
	pinctrl-names = "default";
	pinctrl-0 = <&wifi_host_wake_irq>;
	WIFI,host_wake_irq = <&gpio2 RK_PB2 GPIO_ACTIVE_HIGH>;
	WIFI,poweren_gpio = <&gpio2 RK_PB1 GPIO_ACTIVE_HIGH>;
};

&wireless_bluetooth {
	compatible = "bluetooth-platdata";
	clocks = <&pmucru CLK_RTC_32K>;
	clock-names = "ext_clock";
	//wifi-bt-power-toggle;
	uart_rts_gpios = <&gpio2 RK_PB5 GPIO_ACTIVE_LOW>;
	pinctrl-names = "default", "rts_gpio";
	pinctrl-0 = <&uart1m0_rtsn>;
	pinctrl-1 = <&uart1_gpios>;
	BT,reset_gpio    = <&gpio2 RK_PB7 GPIO_ACTIVE_HIGH>;
	BT,wake_gpio     = <&gpio2 RK_PC1 GPIO_ACTIVE_HIGH>;
	BT,wake_host_irq = <&gpio2 RK_PC0 GPIO_ACTIVE_HIGH>;
	status = "okay";
};

&gmac1 {
	phy-mode = "rgmii";
	clock_in_out = "output";

	snps,reset-gpio = <&gpio2 RK_PD1 GPIO_ACTIVE_LOW>;
	snps,reset-active-low;
	/* Reset time is 20ms, 100ms for rtl8211f */
	snps,reset-delays-us = <0 20000 100000>;

	assigned-clocks = <&cru SCLK_GMAC1_RX_TX>, <&cru SCLK_GMAC1>;
	assigned-clock-parents = <&cru SCLK_GMAC1_RGMII_SPEED>, <&cru CLK_MAC1_2TOP>;
	assigned-clock-rates = <0>, <125000000>;

	pinctrl-names = "default";
	pinctrl-0 = <&gmac1m0_miim
		     &gmac1m0_tx_bus2_level3
		     &gmac1m0_rx_bus2
		     &gmac1m0_rgmii_clk_level2
		     &gmac1m0_rgmii_bus_level3>;

	tx_delay = <0x46>;
	rx_delay = <0x2f>;

	phy-handle = <&rgmii_phy1>;
	status = "okay";
};

&mdio1 {
	rgmii_phy1: phy@0 {
		compatible = "ethernet-phy-ieee802.3-c22";
		reg = <0x0>;
	};
};