/* * (C) Copyright 2018 Rockchip Electronics Co., Ltd * * SPDX-License-Identifier: GPL-2.0+ */ / { aliases { mmc0 = &emmc; mmc1 = &sdmmc; }; chosen { stdout-path = &uart2; u-boot,spl-boot-order = &sdmmc, &spi_nand, &spi_nor, &nandc, &emmc; }; }; &psci { u-boot,dm-pre-reloc; status = "okay"; }; &dmc { u-boot,dm-pre-reloc; }; &cru { u-boot,dm-pre-reloc; }; &emmc { u-boot,dm-pre-reloc; }; &grf { u-boot,dm-pre-reloc; }; &nandc { u-boot,dm-pre-reloc; status = "okay"; #address-cells = <1>; #size-cells = <0>; nand@0 { u-boot,dm-spl; reg = <0>; nand-ecc-mode = "hw"; nand-ecc-strength = <16>; nand-ecc-step-size = <1024>; }; }; &pinctrl { u-boot,dm-pre-reloc; }; &pcfg_pull_none_4ma { u-boot,dm-spl; }; &pcfg_pull_up_4ma { u-boot,dm-spl; }; &sdmmc { u-boot,dm-pre-reloc; }; &sdmmc_pin { u-boot,dm-spl; }; &sdmmc_clk { u-boot,dm-spl; }; &sdmmc_cmd { u-boot,dm-spl; }; &sdmmc_bus4 { u-boot,dm-spl; }; &sdmmc_pwren { u-boot,dm-spl; }; &sfc { u-boot,dm-pre-reloc; status = "okay"; #address-cells = <1>; #size-cells = <0>; spi_nand: flash@0 { u-boot,dm-spl; compatible = "spi-nand"; reg = <0>; spi-tx-bus-width = <1>; spi-rx-bus-width = <4>; spi-max-frequency = <96000000>; }; spi_nor: flash@1 { u-boot,dm-spl; compatible = "jedec,spi-nor"; label = "sfc_nor"; reg = <0>; spi-tx-bus-width = <1>; spi-rx-bus-width = <4>; spi-max-frequency = <96000000>; }; }; &crypto { u-boot,dm-pre-reloc; status = "okay"; }; &saradc { u-boot,dm-pre-reloc; status = "okay"; }; &secure_otp { u-boot,dm-pre-reloc; }; &uart0 { u-boot,dm-pre-reloc; }; &uart1 { u-boot,dm-pre-reloc; }; &uart2 { u-boot,dm-pre-reloc; clock-frequency = <24000000>; status = "okay"; }; &uart3 { u-boot,dm-pre-reloc; }; &uart4 { u-boot,dm-pre-reloc; }; &usb2phy_grf { u-boot,dm-pre-reloc; }; &u2phy { u-boot,dm-pre-reloc; status = "okay"; }; &u2phy_otg { u-boot,dm-pre-reloc; status = "okay"; }; &usb20_otg { u-boot,dm-pre-reloc; status = "okay"; }; &route_rgb { status = "disabled"; };