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566 lines
9.2 KiB
566 lines
9.2 KiB
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
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/*
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* Copyright (c) 2021 Rockchip Electronics Co., Ltd.
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*
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*/
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/ {
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vcc_mipicsi0: vcc-mipicsi0-regulator {
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compatible = "regulator-fixed";
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gpio = <&gpio1 RK_PB1 GPIO_ACTIVE_HIGH>;
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pinctrl-names = "default";
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pinctrl-0 = <&mipicsi0_pwr>;
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regulator-name = "vcc_mipicsi0";
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enable-active-high;
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};
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vcc_mipicsi1: vcc-mipicsi1-regulator {
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compatible = "regulator-fixed";
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gpio = <&gpio1 RK_PB2 GPIO_ACTIVE_HIGH>;
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pinctrl-names = "default";
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pinctrl-0 = <&mipicsi1_pwr>;
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regulator-name = "vcc_mipicsi1";
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enable-active-high;
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};
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};
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&pinctrl {
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cam {
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mipicsi0_pwr: mipicsi0-pwr {
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rockchip,pins =
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<1 RK_PB1 RK_FUNC_GPIO &pcfg_pull_none>;
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};
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mipicsi1_pwr: mipicsi1-pwr {
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rockchip,pins =
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<1 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>;
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};
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};
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};
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&csi2_dphy0_hw {
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status = "okay";
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};
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&csi2_dphy1_hw {
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status = "okay";
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};
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&csi2_dphy1 {
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status = "okay";
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ports {
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#address-cells = <1>;
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#size-cells = <0>;
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port@0 {
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reg = <0>;
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#address-cells = <1>;
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#size-cells = <0>;
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mipi_in_ucam2: endpoint@1 {
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reg = <1>;
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remote-endpoint = <&imx464_out2>;
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data-lanes = <1 2>;
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};
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};
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port@1 {
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reg = <1>;
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#address-cells = <1>;
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#size-cells = <0>;
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csidphy1_out: endpoint@0 {
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reg = <0>;
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remote-endpoint = <&mipi2_csi2_input>;
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};
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};
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};
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};
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&csi2_dphy2 {
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status = "okay";
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ports {
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#address-cells = <1>;
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#size-cells = <0>;
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port@0 {
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reg = <0>;
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#address-cells = <1>;
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#size-cells = <0>;
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mipi_in_ucam3: endpoint@1 {
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reg = <1>;
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remote-endpoint = <&imx464_out3>;
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data-lanes = <1 2>;
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};
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};
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port@1 {
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reg = <1>;
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#address-cells = <1>;
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#size-cells = <0>;
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csidphy2_out: endpoint@0 {
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reg = <0>;
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remote-endpoint = <&mipi3_csi2_input>;
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};
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};
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};
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};
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&csi2_dphy4 {
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status = "okay";
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ports {
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#address-cells = <1>;
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#size-cells = <0>;
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port@0 {
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reg = <0>;
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#address-cells = <1>;
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#size-cells = <0>;
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mipi_in_ucam4: endpoint@1 {
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reg = <1>;
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remote-endpoint = <&imx464_out4>;
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data-lanes = <1 2>;
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};
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};
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port@1 {
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reg = <1>;
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#address-cells = <1>;
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#size-cells = <0>;
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csidphy4_out: endpoint@0 {
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reg = <0>;
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remote-endpoint = <&mipi4_csi2_input>;
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};
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};
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};
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};
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&csi2_dphy5 {
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status = "okay";
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ports {
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#address-cells = <1>;
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#size-cells = <0>;
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port@0 {
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reg = <0>;
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#address-cells = <1>;
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#size-cells = <0>;
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mipi_in_ucam5: endpoint@1 {
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reg = <1>;
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remote-endpoint = <&imx464_out5>;
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data-lanes = <1 2>;
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};
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};
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port@1 {
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reg = <1>;
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#address-cells = <1>;
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#size-cells = <0>;
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csidphy5_out: endpoint@0 {
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reg = <0>;
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remote-endpoint = <&mipi5_csi2_input>;
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};
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};
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};
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};
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&i2c5 {
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status = "okay";
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pinctrl-0 = <&i2c5m3_xfer>;
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/* module 77/79 0x1a 78/80 0x36 */
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imx464_2: imx464-2@1a {
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compatible = "sony,imx464";
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status = "okay";
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reg = <0x1a>;
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clocks = <&cru CLK_MIPI_CAMARAOUT_M3>;
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clock-names = "xvclk";
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power-domains = <&power RK3588_PD_VI>;
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pinctrl-names = "default";
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pinctrl-0 = <&mipim0_camera3_clk>;
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avdd-supply = <&vcc_mipicsi0>;
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reset-gpios = <&gpio1 RK_PA4 GPIO_ACTIVE_HIGH>;
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pwdn-gpios = <&gpio1 RK_PB3 GPIO_ACTIVE_HIGH>;
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rockchip,camera-module-sync-mode = "internal_master";
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rockchip,camera-module-index = <2>;
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rockchip,camera-module-facing = "back";
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rockchip,camera-module-name = "CMK-OT1980-PX1";
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rockchip,camera-module-lens-name = "SHG102";
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port {
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imx464_out2: endpoint {
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remote-endpoint = <&mipi_in_ucam2>;
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data-lanes = <1 2>;
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};
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};
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};
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imx464_3: imx464-3@36 {
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compatible = "sony,imx464";
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status = "okay";
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reg = <0x36>;
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clocks = <&cru CLK_MIPI_CAMARAOUT_M3>;
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clock-names = "xvclk";
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power-domains = <&power RK3588_PD_VI>;
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avdd-supply = <&vcc_mipicsi0>;
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pwdn-gpios = <&gpio1 RK_PA7 GPIO_ACTIVE_HIGH>;
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rockchip,camera-module-sync-mode = "external_master";
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rockchip,camera-module-index = <3>;
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rockchip,camera-module-facing = "back";
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rockchip,camera-module-name = "CMK-OT1980-PX1";
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rockchip,camera-module-lens-name = "SHG102";
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port {
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imx464_out3: endpoint {
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remote-endpoint = <&mipi_in_ucam3>;
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data-lanes = <1 2>;
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};
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};
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};
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};
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&i2c4 {
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status = "okay";
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pinctrl-0 = <&i2c4m3_xfer>;
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/* 77/79 0x1a 78/80 0x36 */
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imx464_4: imx464-4@1a {
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compatible = "sony,imx464";
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status = "okay";
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reg = <0x1a>;
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clocks = <&cru CLK_MIPI_CAMARAOUT_M4>;
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clock-names = "xvclk";
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power-domains = <&power RK3588_PD_VI>;
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pinctrl-names = "default";
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pinctrl-0 = <&mipim0_camera4_clk>;
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avdd-supply = <&vcc_mipicsi1>;
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reset-gpios = <&gpio1 RK_PB5 GPIO_ACTIVE_HIGH>;
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pwdn-gpios = <&gpio1 RK_PB4 GPIO_ACTIVE_HIGH>;
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rockchip,camera-module-sync-mode = "external_master";
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rockchip,camera-module-index = <0>;
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rockchip,camera-module-facing = "back";
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rockchip,camera-module-name = "CMK-OT1980-PX1";
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rockchip,camera-module-lens-name = "SHG102";
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port {
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imx464_out4: endpoint {
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remote-endpoint = <&mipi_in_ucam4>;
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data-lanes = <1 2>;
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};
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};
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};
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imx464_5: imx464-5@36 {
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compatible = "sony,imx464";
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status = "okay";
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reg = <0x36>;
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clocks = <&cru CLK_MIPI_CAMARAOUT_M4>;
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clock-names = "xvclk";
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power-domains = <&power RK3588_PD_VI>;
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avdd-supply = <&vcc_mipicsi1>;
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pwdn-gpios = <&gpio1 RK_PB0 GPIO_ACTIVE_HIGH>;
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rockchip,camera-module-sync-mode = "external_master";
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rockchip,camera-module-index = <1>;
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rockchip,camera-module-facing = "back";
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rockchip,camera-module-name = "CMK-OT1980-PX1";
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rockchip,camera-module-lens-name = "SHG102";
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port {
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imx464_out5: endpoint {
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remote-endpoint = <&mipi_in_ucam5>;
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data-lanes = <1 2>;
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};
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};
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};
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};
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&mipi2_csi2 {
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status = "okay";
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ports {
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#address-cells = <1>;
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#size-cells = <0>;
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port@0 {
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reg = <0>;
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#address-cells = <1>;
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#size-cells = <0>;
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mipi2_csi2_input: endpoint@1 {
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reg = <1>;
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remote-endpoint = <&csidphy1_out>;
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};
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};
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port@1 {
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reg = <1>;
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#address-cells = <1>;
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#size-cells = <0>;
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mipi2_csi2_output: endpoint@0 {
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reg = <0>;
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remote-endpoint = <&cif_mipi_in2>;
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};
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};
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};
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};
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&mipi3_csi2 {
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status = "okay";
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ports {
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#address-cells = <1>;
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#size-cells = <0>;
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port@0 {
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reg = <0>;
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#address-cells = <1>;
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#size-cells = <0>;
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mipi3_csi2_input: endpoint@1 {
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reg = <1>;
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remote-endpoint = <&csidphy2_out>;
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};
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};
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port@1 {
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reg = <1>;
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#address-cells = <1>;
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#size-cells = <0>;
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mipi3_csi2_output: endpoint@0 {
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reg = <0>;
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remote-endpoint = <&cif_mipi_in3>;
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};
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};
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};
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};
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&mipi4_csi2 {
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status = "okay";
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ports {
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#address-cells = <1>;
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#size-cells = <0>;
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port@0 {
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reg = <0>;
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#address-cells = <1>;
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#size-cells = <0>;
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mipi4_csi2_input: endpoint@1 {
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reg = <1>;
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remote-endpoint = <&csidphy4_out>;
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};
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};
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port@1 {
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reg = <1>;
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#address-cells = <1>;
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#size-cells = <0>;
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mipi4_csi2_output: endpoint@0 {
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reg = <0>;
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remote-endpoint = <&cif_mipi_in4>;
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};
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};
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};
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};
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&mipi5_csi2 {
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status = "okay";
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ports {
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#address-cells = <1>;
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#size-cells = <0>;
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port@0 {
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reg = <0>;
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#address-cells = <1>;
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#size-cells = <0>;
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mipi5_csi2_input: endpoint@1 {
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reg = <1>;
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remote-endpoint = <&csidphy5_out>;
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};
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};
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port@1 {
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reg = <1>;
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#address-cells = <1>;
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#size-cells = <0>;
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mipi5_csi2_output: endpoint@0 {
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reg = <0>;
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remote-endpoint = <&cif_mipi_in5>;
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};
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};
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};
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};
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&rkcif {
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status = "okay";
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};
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&rkcif_mipi_lvds2 {
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status = "okay";
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port {
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cif_mipi_in2: endpoint {
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remote-endpoint = <&mipi2_csi2_output>;
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};
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};
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};
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&rkcif_mipi_lvds2_sditf {
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status = "okay";
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port {
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mipi2_lvds_sditf: endpoint {
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remote-endpoint = <&isp0_vir0>;
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};
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};
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};
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&rkcif_mipi_lvds3 {
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status = "okay";
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port {
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cif_mipi_in3: endpoint {
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remote-endpoint = <&mipi3_csi2_output>;
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};
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};
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};
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&rkcif_mipi_lvds3_sditf {
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status = "okay";
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port {
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mipi3_lvds_sditf: endpoint {
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remote-endpoint = <&isp1_vir0>;
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};
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};
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};
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&rkcif_mipi_lvds4 {
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status = "okay";
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port {
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cif_mipi_in4: endpoint {
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remote-endpoint = <&mipi4_csi2_output>;
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};
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};
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};
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&rkcif_mipi_lvds4_sditf {
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status = "okay";
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port {
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mipi4_lvds_sditf: endpoint {
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remote-endpoint = <&isp0_vir1>;
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};
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};
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};
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&rkcif_mipi_lvds5 {
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status = "okay";
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port {
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cif_mipi_in5: endpoint {
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remote-endpoint = <&mipi5_csi2_output>;
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};
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};
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};
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&rkcif_mipi_lvds5_sditf {
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status = "okay";
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port {
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mipi5_lvds_sditf: endpoint {
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remote-endpoint = <&isp1_vir1>;
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};
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};
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};
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&rkcif_mmu {
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status = "okay";
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};
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&rkisp0 {
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status = "okay";
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};
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&isp0_mmu {
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status = "okay";
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};
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|
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&rkisp0_vir0 {
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status = "okay";
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|
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port {
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#address-cells = <1>;
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#size-cells = <0>;
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isp0_vir0: endpoint@0 {
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reg = <0>;
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remote-endpoint = <&mipi2_lvds_sditf>;
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};
|
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};
|
|
};
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|
|
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&rkisp0_vir1 {
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status = "okay";
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port {
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#address-cells = <1>;
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#size-cells = <0>;
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|
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isp0_vir1: endpoint@0 {
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reg = <0>;
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remote-endpoint = <&mipi4_lvds_sditf>;
|
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};
|
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};
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};
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|
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&rkisp1 {
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status = "okay";
|
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};
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|
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&isp1_mmu {
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status = "okay";
|
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};
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&rkisp1_vir0 {
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status = "okay";
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|
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port {
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#address-cells = <1>;
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#size-cells = <0>;
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|
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isp1_vir0: endpoint@0 {
|
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reg = <0>;
|
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remote-endpoint = <&mipi3_lvds_sditf>;
|
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};
|
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};
|
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};
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&rkisp1_vir1 {
|
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status = "okay";
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|
|
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port {
|
|
#address-cells = <1>;
|
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#size-cells = <0>;
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|
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isp1_vir1: endpoint@0 {
|
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reg = <0>;
|
|
remote-endpoint = <&mipi5_lvds_sditf>;
|
|
};
|
|
};
|
|
};
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