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136 lines
3.4 KiB
136 lines
3.4 KiB
/*
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* Copyright (C) 2015 Rockchip Electronics Co., Ltd.
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*/
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#ifndef _RK29_IPP_DRIVER_H_
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#define _RK29_IPP_DRIVER_H_
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#define IPP_BLIT_SYNC 0x5017
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#define IPP_BLIT_ASYNC 0x5018
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#define IPP_GET_RESULT 0x5019
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/* Image data */
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struct rk29_ipp_image
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{
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uint32_t YrgbMst; // image Y/rgb address
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uint32_t CbrMst; // image CbCr address
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uint32_t w; // image full width
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uint32_t h; // image full height
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uint32_t fmt; // color format
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};
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struct rk29_ipp_req {
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struct rk29_ipp_image src0; // source0 image
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struct rk29_ipp_image dst0; // destination0 image
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//struct rk29_ipp_image src1; // source1 image
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//struct rk29_ipp_image dst1; // destination1 image
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uint32_t src_vir_w;
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uint32_t dst_vir_w;
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uint32_t timeout;
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uint32_t flag; //rotate
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/*store_clip_mode
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0:when src width is not 64-bits aligned,use dummy data make it 64-bits aligned 1:packed
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we usually set to 0
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*/
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uint8_t store_clip_mode;
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//deinterlace_enable 1:enable 0:disable
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uint8_t deinterlace_enable;
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//the sum of three paras should be 32,and single para should be less than 32
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uint8_t deinterlace_para0;
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uint8_t deinterlace_para1;
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uint8_t deinterlace_para2;
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/* completion is reported through a callback */
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void (*complete)(int retval);
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};
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//format enum
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enum
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{
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IPP_XRGB_8888 = 0,
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IPP_RGB_565 =1 ,
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IPP_Y_CBCR_H2V1 = 2, //yuv 422sp
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IPP_Y_CBCR_H2V2 = 3, //yuv 420sp
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IPP_Y_CBCR_H1V1 =6, //yuv 444sp
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IPP_IMGTYPE_LIMIT
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};
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typedef enum
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{
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IPP_ROT_90,
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IPP_ROT_180,
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IPP_ROT_270,
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IPP_ROT_X_FLIP,
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IPP_ROT_Y_FLIP,
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IPP_ROT_0,
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IPP_ROT_LIMIT
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} ROT_DEG;
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struct ipp_regs {
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uint32_t ipp_config;
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uint32_t ipp_src_img_info;
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uint32_t ipp_dst_img_info;
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uint32_t ipp_img_vir;
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uint32_t ipp_int;
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uint32_t ipp_src0_y_mst;
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uint32_t ipp_src0_Cbr_mst;
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uint32_t ipp_src1_y_mst;
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uint32_t ipp_src1_Cbr_mst;
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uint32_t ipp_dst0_y_mst;
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uint32_t ipp_dst0_Cbr_mst;
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uint32_t ipp_dst1_y_mst;
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uint32_t ipp_dst1_Cbr_mst;
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uint32_t ipp_pre_scl_para;
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uint32_t ipp_post_scl_para;
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uint32_t ipp_swap_ctrl;
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uint32_t ipp_pre_img_info;
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uint32_t ipp_axi_id;
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uint32_t ipp_process_st;
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};
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#define IPP_CONFIG (0x00)
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#define IPP_SRC_IMG_INFO (0x04)
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#define IPP_DST_IMG_INFO (0x08)
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#define IPP_IMG_VIR (0x0c)
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#define IPP_INT (0x10)
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#define IPP_SRC0_Y_MST (0x14)
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#define IPP_SRC0_CBR_MST (0x18)
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#define IPP_SRC1_Y_MST (0x1c)
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#define IPP_SRC1_CBR_MST (0x20)
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#define IPP_DST0_Y_MST (0x24)
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#define IPP_DST0_CBR_MST (0x28)
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#define IPP_DST1_Y_MST (0x2c)
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#define IPP_DST1_CBR_MST (0x30)
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#define IPP_PRE_SCL_PARA (0x34)
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#define IPP_POST_SCL_PARA (0x38)
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#define IPP_SWAP_CTRL (0x3c)
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#define IPP_PRE_IMG_INFO (0x40)
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#define IPP_AXI_ID (0x44)
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#define IPP_SRESET (0x48)
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#define IPP_PROCESS_ST (0x50)
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/*ipp config*/
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#define STORE_CLIP_MODE (1<<26)
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#define DEINTERLACE_ENABLE (1<<24)
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#define ROT_ENABLE (1<<8)
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#define PRE_SCALE (1<<4)
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#define POST_SCALE (1<<3)
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#define IPP_BLIT_COMPLETE_EVENT BIT(1)
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#define IS_YCRCB(img) ((img == IPP_Y_CBCR_H2V1) | (img == IPP_Y_CBCR_H2V2) | \
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(img == IPP_Y_CBCR_H1V1) )
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#define IS_RGB(img) ((img == IPP_RGB_565) | (img == IPP_ARGB_8888) | \
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(img == IPP_XRGB_8888) ))
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#define HAS_ALPHA(img) (img == IPP_ARGB_8888)
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int ipp_blit_async(const struct rk29_ipp_req *req);
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int ipp_blit_sync(const struct rk29_ipp_req *req);
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#endif /*_RK29_IPP_DRIVER_H_*/
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