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298 lines
7.2 KiB
298 lines
7.2 KiB
/****************************************************************************
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****************************************************************************
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***
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*** This header was automatically generated from a Linux kernel header
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*** of the same name, to make information necessary for userspace to
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*** call into the kernel available to libc. It contains only constants,
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*** structures, and macros generated from the original header, and thus,
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*** contains no copyrightable information.
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***
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*** To edit the content of this header, modify the corresponding
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*** source file (e.g. under external/kernel-headers/original/) then
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*** run bionic/libc/kernel/tools/update_all.py
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***
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*** Any manual change here will be lost the next time this script will
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*** be run. You've been warned!
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***
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****************************************************************************
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****************************************************************************/
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#ifndef _MSM_DRM_PP_H_
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#define _MSM_DRM_PP_H_
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#include <linux/types.h>
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struct drm_msm_pcc_coeff {
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__u32 c;
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__u32 r;
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__u32 g;
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__u32 b;
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__u32 rg;
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__u32 gb;
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__u32 rb;
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__u32 rgb;
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};
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#define DRM_MSM_PCC3
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struct drm_msm_pcc {
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__u64 flags;
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struct drm_msm_pcc_coeff r;
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struct drm_msm_pcc_coeff g;
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struct drm_msm_pcc_coeff b;
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__u32 r_rr;
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__u32 r_gg;
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__u32 r_bb;
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__u32 g_rr;
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__u32 g_gg;
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__u32 g_bb;
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__u32 b_rr;
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__u32 b_gg;
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__u32 b_bb;
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};
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#define PA_VLUT_SIZE 256
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struct drm_msm_pa_vlut {
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__u64 flags;
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__u32 val[PA_VLUT_SIZE];
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};
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#define PA_HSIC_HUE_ENABLE (1 << 0)
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#define PA_HSIC_SAT_ENABLE (1 << 1)
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#define PA_HSIC_VAL_ENABLE (1 << 2)
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#define PA_HSIC_CONT_ENABLE (1 << 3)
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#define DRM_MSM_PA_HSIC
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struct drm_msm_pa_hsic {
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__u64 flags;
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__u32 hue;
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__u32 saturation;
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__u32 value;
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__u32 contrast;
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};
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#define MEMCOL_PROT_HUE (1 << 0)
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#define MEMCOL_PROT_SAT (1 << 1)
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#define MEMCOL_PROT_VAL (1 << 2)
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#define MEMCOL_PROT_CONT (1 << 3)
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#define MEMCOL_PROT_SIXZONE (1 << 4)
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#define MEMCOL_PROT_BLEND (1 << 5)
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#define DRM_MSM_MEMCOL
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struct drm_msm_memcol {
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__u64 prot_flags;
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__u32 color_adjust_p0;
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__u32 color_adjust_p1;
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__u32 color_adjust_p2;
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__u32 blend_gain;
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__u32 sat_hold;
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__u32 val_hold;
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__u32 hue_region;
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__u32 sat_region;
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__u32 val_region;
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};
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#define DRM_MSM_SIXZONE
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#define SIXZONE_LUT_SIZE 384
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#define SIXZONE_HUE_ENABLE (1 << 0)
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#define SIXZONE_SAT_ENABLE (1 << 1)
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#define SIXZONE_VAL_ENABLE (1 << 2)
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struct drm_msm_sixzone_curve {
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__u32 p1;
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__u32 p0;
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};
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struct drm_msm_sixzone {
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__u64 flags;
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__u32 threshold;
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__u32 adjust_p0;
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__u32 adjust_p1;
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__u32 sat_hold;
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__u32 val_hold;
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struct drm_msm_sixzone_curve curve[SIXZONE_LUT_SIZE];
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};
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#define GAMUT_3D_MODE_17 1
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#define GAMUT_3D_MODE_5 2
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#define GAMUT_3D_MODE_13 3
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#define GAMUT_3D_MODE17_TBL_SZ 1229
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#define GAMUT_3D_MODE5_TBL_SZ 32
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#define GAMUT_3D_MODE13_TBL_SZ 550
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#define GAMUT_3D_SCALE_OFF_SZ 16
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#define GAMUT_3D_SCALEB_OFF_SZ 12
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#define GAMUT_3D_TBL_NUM 4
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#define GAMUT_3D_SCALE_OFF_TBL_NUM 3
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#define GAMUT_3D_MAP_EN (1 << 0)
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struct drm_msm_3d_col {
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__u32 c2_c1;
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__u32 c0;
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};
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struct drm_msm_3d_gamut {
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__u64 flags;
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__u32 mode;
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__u32 scale_off[GAMUT_3D_SCALE_OFF_TBL_NUM][GAMUT_3D_SCALE_OFF_SZ];
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struct drm_msm_3d_col col[GAMUT_3D_TBL_NUM][GAMUT_3D_MODE17_TBL_SZ];
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};
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#define PGC_TBL_LEN 512
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#define PGC_8B_ROUND (1 << 0)
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struct drm_msm_pgc_lut {
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__u64 flags;
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__u32 c0[PGC_TBL_LEN];
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__u32 c1[PGC_TBL_LEN];
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__u32 c2[PGC_TBL_LEN];
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};
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#define IGC_TBL_LEN 256
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#define IGC_DITHER_ENABLE (1 << 0)
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struct drm_msm_igc_lut {
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__u64 flags;
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__u32 c0[IGC_TBL_LEN];
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__u32 c1[IGC_TBL_LEN];
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__u32 c2[IGC_TBL_LEN];
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__u32 strength;
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};
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#define HIST_V_SIZE 256
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struct drm_msm_hist {
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__u64 flags;
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__u32 data[HIST_V_SIZE];
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};
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#define AD4_LUT_GRP0_SIZE 33
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#define AD4_LUT_GRP1_SIZE 32
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struct drm_msm_ad4_init {
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__u32 init_param_001[AD4_LUT_GRP0_SIZE];
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__u32 init_param_002[AD4_LUT_GRP0_SIZE];
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__u32 init_param_003[AD4_LUT_GRP0_SIZE];
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__u32 init_param_004[AD4_LUT_GRP0_SIZE];
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__u32 init_param_005[AD4_LUT_GRP1_SIZE];
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__u32 init_param_006[AD4_LUT_GRP1_SIZE];
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__u32 init_param_007[AD4_LUT_GRP0_SIZE];
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__u32 init_param_008[AD4_LUT_GRP0_SIZE];
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__u32 init_param_009;
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__u32 init_param_010;
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__u32 init_param_011;
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__u32 init_param_012;
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__u32 init_param_013;
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__u32 init_param_014;
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__u32 init_param_015;
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__u32 init_param_016;
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__u32 init_param_017;
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__u32 init_param_018;
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__u32 init_param_019;
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__u32 init_param_020;
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__u32 init_param_021;
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__u32 init_param_022;
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__u32 init_param_023;
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__u32 init_param_024;
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__u32 init_param_025;
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__u32 init_param_026;
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__u32 init_param_027;
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__u32 init_param_028;
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__u32 init_param_029;
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__u32 init_param_030;
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__u32 init_param_031;
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__u32 init_param_032;
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__u32 init_param_033;
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__u32 init_param_034;
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__u32 init_param_035;
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__u32 init_param_036;
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__u32 init_param_037;
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__u32 init_param_038;
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__u32 init_param_039;
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__u32 init_param_040;
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__u32 init_param_041;
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__u32 init_param_042;
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__u32 init_param_043;
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__u32 init_param_044;
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__u32 init_param_045;
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__u32 init_param_046;
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__u32 init_param_047;
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__u32 init_param_048;
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__u32 init_param_049;
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__u32 init_param_050;
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__u32 init_param_051;
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__u32 init_param_052;
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__u32 init_param_053;
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__u32 init_param_054;
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__u32 init_param_055;
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__u32 init_param_056;
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__u32 init_param_057;
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__u32 init_param_058;
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__u32 init_param_059;
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__u32 init_param_060;
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__u32 init_param_061;
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__u32 init_param_062;
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__u32 init_param_063;
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__u32 init_param_064;
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__u32 init_param_065;
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__u32 init_param_066;
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__u32 init_param_067;
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__u32 init_param_068;
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__u32 init_param_069;
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__u32 init_param_070;
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__u32 init_param_071;
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__u32 init_param_072;
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__u32 init_param_073;
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__u32 init_param_074;
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__u32 init_param_075;
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};
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struct drm_msm_ad4_cfg {
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__u32 cfg_param_001;
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__u32 cfg_param_002;
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__u32 cfg_param_003;
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__u32 cfg_param_004;
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__u32 cfg_param_005;
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__u32 cfg_param_006;
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__u32 cfg_param_007;
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__u32 cfg_param_008;
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__u32 cfg_param_009;
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__u32 cfg_param_010;
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__u32 cfg_param_011;
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__u32 cfg_param_012;
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__u32 cfg_param_013;
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__u32 cfg_param_014;
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__u32 cfg_param_015;
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__u32 cfg_param_016;
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__u32 cfg_param_017;
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__u32 cfg_param_018;
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__u32 cfg_param_019;
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__u32 cfg_param_020;
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__u32 cfg_param_021;
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__u32 cfg_param_022;
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__u32 cfg_param_023;
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__u32 cfg_param_024;
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__u32 cfg_param_025;
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__u32 cfg_param_026;
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__u32 cfg_param_027;
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__u32 cfg_param_028;
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__u32 cfg_param_029;
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__u32 cfg_param_030;
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__u32 cfg_param_031;
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__u32 cfg_param_032;
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__u32 cfg_param_033;
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__u32 cfg_param_034;
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__u32 cfg_param_035;
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__u32 cfg_param_036;
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__u32 cfg_param_037;
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__u32 cfg_param_038;
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__u32 cfg_param_039;
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__u32 cfg_param_040;
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__u32 cfg_param_041;
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__u32 cfg_param_042;
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__u32 cfg_param_043;
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__u32 cfg_param_044;
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__u32 cfg_param_045;
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__u32 cfg_param_046;
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__u32 cfg_param_047;
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__u32 cfg_param_048;
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__u32 cfg_param_049;
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__u32 cfg_param_050;
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__u32 cfg_param_051;
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__u32 cfg_param_052;
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__u32 cfg_param_053;
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};
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#define DITHER_MATRIX_SZ 16
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struct drm_msm_dither {
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__u64 flags;
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__u32 temporal_en;
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__u32 c0_bitdepth;
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__u32 c1_bitdepth;
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__u32 c2_bitdepth;
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__u32 c3_bitdepth;
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__u32 matrix[DITHER_MATRIX_SZ];
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};
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#define DRM_MSM_PA_DITHER
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struct drm_msm_pa_dither {
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__u64 flags;
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__u32 strength;
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__u32 offset_en;
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__u32 matrix[DITHER_MATRIX_SZ];
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};
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#endif
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