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159 lines
4.2 KiB
159 lines
4.2 KiB
/*
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* Copyright (c) 2015-2017, ARM Limited and Contributors. All rights reserved.
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* Copyright (c) 2020, NVIDIA Corporation. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <assert.h>
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#include <errno.h>
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#include <arch.h>
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#include <arch_helpers.h>
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#include <common/bl_common.h>
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#include <common/debug.h>
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#include <common/runtime_svc.h>
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#include <lib/mmio.h>
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#include <memctrl.h>
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#include <tegra_platform.h>
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#include <tegra_private.h>
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/*******************************************************************************
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* Common Tegra SiP SMCs
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******************************************************************************/
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#define TEGRA_SIP_NEW_VIDEOMEM_REGION 0x82000003
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#define TEGRA_SIP_FIQ_NS_ENTRYPOINT 0x82000005
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#define TEGRA_SIP_FIQ_NS_GET_CONTEXT 0x82000006
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/*******************************************************************************
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* This function is responsible for handling all SiP calls
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******************************************************************************/
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uintptr_t tegra_sip_handler(uint32_t smc_fid,
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u_register_t x1,
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u_register_t x2,
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u_register_t x3,
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u_register_t x4,
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void *cookie,
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void *handle,
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u_register_t flags)
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{
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uint32_t regval, local_x2_32 = (uint32_t)x2;
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int32_t err;
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/* Check if this is a SoC specific SiP */
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err = plat_sip_handler(smc_fid, x1, x2, x3, x4, cookie, handle, flags);
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if (err == 0) {
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SMC_RET1(handle, (uint64_t)err);
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} else {
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switch (smc_fid) {
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case TEGRA_SIP_NEW_VIDEOMEM_REGION:
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/* Check whether Video memory resize is enabled */
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if (mmio_read_32(TEGRA_MC_BASE + MC_VIDEO_PROTECT_REG_CTRL)
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!= MC_VIDEO_PROTECT_WRITE_ACCESS_ENABLED) {
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ERROR("Video Memory Resize isn't enabled! \n");
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SMC_RET1(handle, (uint64_t)-ENOTSUP);
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}
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/*
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* Check if Video Memory overlaps TZDRAM (contains bl31/bl32)
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* or falls outside of the valid DRAM range
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*/
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err = bl31_check_ns_address(x1, local_x2_32);
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if (err != 0) {
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SMC_RET1(handle, (uint64_t)err);
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}
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/*
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* Check if Video Memory is aligned to 1MB.
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*/
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if (((x1 & 0xFFFFFU) != 0U) || ((local_x2_32 & 0xFFFFFU) != 0U)) {
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ERROR("Unaligned Video Memory base address!\n");
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SMC_RET1(handle, (uint64_t)-ENOTSUP);
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}
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/*
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* The GPU is the user of the Video Memory region. In order to
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* transition to the new memory region smoothly, we program the
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* new base/size ONLY if the GPU is in reset mode.
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*/
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regval = mmio_read_32(TEGRA_CAR_RESET_BASE +
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TEGRA_GPU_RESET_REG_OFFSET);
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if ((regval & GPU_RESET_BIT) == 0U) {
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ERROR("GPU not in reset! Video Memory setup failed\n");
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SMC_RET1(handle, (uint64_t)-ENOTSUP);
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}
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/* new video memory carveout settings */
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tegra_memctrl_videomem_setup(x1, local_x2_32);
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/*
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* Ensure again that GPU is still in reset after VPR resize
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*/
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regval = mmio_read_32(TEGRA_CAR_RESET_BASE +
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TEGRA_GPU_RESET_REG_OFFSET);
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if ((regval & GPU_RESET_BIT) == 0U) {
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mmio_write_32(TEGRA_CAR_RESET_BASE + TEGRA_GPU_RESET_GPU_SET_OFFSET,
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GPU_SET_BIT);
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}
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SMC_RET1(handle, 0);
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/*
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* The NS world registers the address of its handler to be
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* used for processing the FIQ. This is normally used by the
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* NS FIQ debugger driver to detect system hangs by programming
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* a watchdog timer to fire a FIQ interrupt.
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*/
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case TEGRA_SIP_FIQ_NS_ENTRYPOINT:
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if (x1 == 0U) {
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SMC_RET1(handle, SMC_UNK);
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}
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/*
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* TODO: Check if x1 contains a valid DRAM address
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*/
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/* store the NS world's entrypoint */
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tegra_fiq_set_ns_entrypoint(x1);
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SMC_RET1(handle, 0);
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/*
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* The NS world's FIQ handler issues this SMC to get the NS EL1/EL0
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* CPU context when the FIQ interrupt was triggered. This allows the
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* NS world to understand the CPU state when the watchdog interrupt
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* triggered.
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*/
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case TEGRA_SIP_FIQ_NS_GET_CONTEXT:
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/* retrieve context registers when FIQ triggered */
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(void)tegra_fiq_get_intr_context();
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SMC_RET0(handle);
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default:
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ERROR("%s: unhandled SMC (0x%x)\n", __func__, smc_fid);
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break;
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}
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}
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SMC_RET1(handle, SMC_UNK);
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}
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/* Define a runtime service descriptor for fast SMC calls */
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DECLARE_RT_SVC(
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tegra_sip_fast,
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(OEN_SIP_START),
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(OEN_SIP_END),
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(SMC_TYPE_FAST),
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(NULL),
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(tegra_sip_handler)
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);
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