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120 lines
3.9 KiB
120 lines
3.9 KiB
6 months ago
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/*
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* Copyright (c) 2021-2022 Rockchip Eletronics Co., Ltd.
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*
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* Licensed under the Apache License, Version 2.0 (the "License");
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* you may not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS,
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* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*/
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#include "rk_aiq_isp33_modules.h"
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RKAIQ_BEGIN_DECLARE
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void rk_aiq_hsv10_params_cvt(void* attr, isp_params_t* isp_params, common_cvt_info_t* cvtinfo)
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{
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struct isp33_hsv_cfg *cfg = &isp_params->isp_cfg->others.hsv_cfg;
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hsv_param_t* hsv_param = (hsv_param_t*) attr;
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hsv_param_static_t* psta = &hsv_param->sta;
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hsv_param_dyn_t* pdyn = &hsv_param->dyn;
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cfg->hsv_1dlut0_en = psta->hw_hsvT_lut1d0_en;
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cfg->hsv_1dlut1_en = psta->hw_hsvT_lut1d1_en;
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cfg->hsv_2dlut_en = psta->hw_hsvT_lut2d_en;
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switch ((uint8_t)pdyn->lut1d0.hw_hsvT_lut1d_mode) {
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case hsv_lut1d_h2hDiff_mode: {
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cfg->hsv_1dlut0_idx_mode = 0;
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cfg->hsv_1dlut0_item_mode = 0;
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} break;
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case hsv_lut1d_h2sDiff_mode: {
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cfg->hsv_1dlut0_idx_mode = 0;
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cfg->hsv_1dlut0_item_mode = 1;
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} break;
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case hsv_lut1d_h2vDiff_mode: {
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cfg->hsv_1dlut0_idx_mode = 0;
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cfg->hsv_1dlut0_item_mode = 2;
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} break;
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case hsv_lut1d_s2sDiff_mode: {
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cfg->hsv_1dlut0_idx_mode = 1;
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cfg->hsv_1dlut0_item_mode = 1;
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} break;
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default:
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break;
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}
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switch ((uint8_t)pdyn->lut1d1.hw_hsvT_lut1d_mode) {
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case hsv_lut1d_h2hDiff_mode: {
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cfg->hsv_1dlut1_idx_mode = 0;
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cfg->hsv_1dlut1_item_mode = 0;
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} break;
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case hsv_lut1d_h2sDiff_mode: {
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cfg->hsv_1dlut1_idx_mode = 0;
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cfg->hsv_1dlut1_item_mode = 1;
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} break;
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case hsv_lut1d_h2vDiff_mode: {
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cfg->hsv_1dlut1_idx_mode = 0;
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cfg->hsv_1dlut1_item_mode = 2;
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} break;
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case hsv_lut1d_s2sDiff_mode: {
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cfg->hsv_1dlut1_idx_mode = 1;
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cfg->hsv_1dlut1_item_mode = 1;
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} break;
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default:
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break;
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}
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switch (pdyn->lut2d.hw_hsvT_lut2d_mode) {
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case hsv_lut2d_hs2h_mode: {
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cfg->hsv_2dlut_idx_mode = 0;
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cfg->hsv_2dlut_item_mode = 0;
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} break;
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case hsv_lut2d_hv2h_mode: {
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cfg->hsv_2dlut_idx_mode = 1;
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cfg->hsv_2dlut_item_mode = 0;
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} break;
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case hsv_lut2d_sv2s_mode: {
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cfg->hsv_2dlut_idx_mode = 2;
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cfg->hsv_2dlut_item_mode = 1;
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} break;
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case hsv_lut2d_hs2s_mode: {
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cfg->hsv_2dlut_idx_mode = 0;
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cfg->hsv_2dlut_item_mode = 1;
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} break;
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case hsv_lut2d_hv2v_mode: {
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cfg->hsv_2dlut_idx_mode = 1;
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cfg->hsv_2dlut_item_mode = 2;
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} break;
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case hsv_lut2d_sv2v_mode: {
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cfg->hsv_2dlut_idx_mode = 2;
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cfg->hsv_2dlut_item_mode = 2;
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} break;
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default:
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break;
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}
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for (int i = 0; i < ISP33_HSV_1DLUT_NUM; i++)
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cfg->lut0_1d[i] = ((uint16_t)pdyn->lut1d0.hw_hsvT_lut1d_val[i]) << 2;
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for (int i = 0; i < ISP33_HSV_1DLUT_NUM; i++)
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cfg->lut1_1d[i] = ((uint16_t)pdyn->lut1d1.hw_hsvT_lut1d_val[i]) << 2;
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int count = 0;
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for (int i = 0; i < ISP33_HSV_2DLUT_ROW; i++){
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for (int j = 0; j < ISP33_HSV_2DLUT_COL; j++) {
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cfg->lut_2d[i][j] = ((uint16_t)pdyn->lut2d.hw_hsvT_lut2d_val[count]) << 2;
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count ++;
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}
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}
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}
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RKAIQ_END_DECLARE
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