From 38aac8204372db25225474dd44b92209b3c6453d Mon Sep 17 00:00:00 2001 From: hmz007 Date: Thu, 31 Jul 2025 17:28:28 +0800 Subject: [PATCH] [kernel] merge commit 'ceb609ae2c..2e1cc5bd1f' Signed-off-by: hmz007 Change-Id: I31a0cc46e80691c44b7c1d8b5af5022ac0a4172d --- .../dts/rockchip/rk3566-nanopi-r3-rev01.dts | 6 +- .../dts/rockchip/rk3566-nanopi-r3-rev02.dts | 6 +- .../dts/rockchip/rk3568-nanopi5-rev01.dts | 32 ++++ .../dts/rockchip/rk3568-nanopi5-rev07.dts | 34 ++++ .../rockchip/rk3576-nanopi5-csi0-imx415.dtsi | 167 ++++++++++++++++++ .../rockchip/rk3576-nanopi5-csi1-imx415.dtsi | 151 ++++++++++++++++ .../dts/rockchip/rk3576-nanopi5-rev01.dts | 94 ++++++++++ .../dts/rockchip/rk3576-nanopi5-rev02.dts | 18 ++ .../dts/rockchip/rk3588-nanopi6-rev01.dts | 89 ++++++++++ .../dts/rockchip/rk3588-nanopi6-rev02.dts | 32 ++++ .../dts/rockchip/rk3588-nanopi6-rev04.dts | 80 +++++++++ .../dts/rockchip/rk3588-nanopi6-rev05.dts | 80 +++++++++ .../dts/rockchip/rk3588-nanopi6-rev09.dts | 82 +++++++++ .../dts/rockchip/rk3588-nanopi6-rev0a.dts | 84 ++++++++- .../arm64/configs/nanopi5_android_defconfig | 1 + .../arm64/configs/nanopi5_linux_defconfig | 1 + .../drivers/dma-buf/heaps/rk_system_heap.c | 49 ++++- .../media/platform/rockchip/cif/capture.c | 16 +- .../drivers/media/platform/rockchip/cif/dev.c | 1 + .../drivers/media/platform/rockchip/cif/dev.h | 3 + .../media/platform/rockchip/cif/subdev-itf.c | 1 + .../pci/controller/dwc/pcie-dw-rockchip.c | 26 ++- 22 files changed, 1034 insertions(+), 19 deletions(-) create mode 100644 kernel-6.1/arch/arm64/boot/dts/rockchip/rk3576-nanopi5-csi0-imx415.dtsi create mode 100644 kernel-6.1/arch/arm64/boot/dts/rockchip/rk3576-nanopi5-csi1-imx415.dtsi diff --git a/kernel-6.1/arch/arm64/boot/dts/rockchip/rk3566-nanopi-r3-rev01.dts b/kernel-6.1/arch/arm64/boot/dts/rockchip/rk3566-nanopi-r3-rev01.dts index 1fd62a63159..6dba3a1427c 100644 --- a/kernel-6.1/arch/arm64/boot/dts/rockchip/rk3566-nanopi-r3-rev01.dts +++ b/kernel-6.1/arch/arm64/boot/dts/rockchip/rk3566-nanopi-r3-rev01.dts @@ -327,8 +327,10 @@ dsi1_pwm: &pwm4 { }; &vp2 { - /delete-property/ rockchip,plane-mask; - /delete-property/ rockchip,primary-plane; + rockchip,plane-mask = <( + 1 << ROCKCHIP_VOP2_CLUSTER1 | 1 << ROCKCHIP_VOP2_ESMART1 | + 1 << ROCKCHIP_VOP2_SMART1)>; + rockchip,primary-plane = ; status = "disabled"; }; diff --git a/kernel-6.1/arch/arm64/boot/dts/rockchip/rk3566-nanopi-r3-rev02.dts b/kernel-6.1/arch/arm64/boot/dts/rockchip/rk3566-nanopi-r3-rev02.dts index b359edfeef4..e06f3962165 100644 --- a/kernel-6.1/arch/arm64/boot/dts/rockchip/rk3566-nanopi-r3-rev02.dts +++ b/kernel-6.1/arch/arm64/boot/dts/rockchip/rk3566-nanopi-r3-rev02.dts @@ -40,8 +40,10 @@ }; &vp1 { - /delete-property/ rockchip,plane-mask; - /delete-property/ rockchip,primary-plane; + rockchip,plane-mask = <( + 1 << ROCKCHIP_VOP2_CLUSTER1 | 1 << ROCKCHIP_VOP2_ESMART1 | + 1 << ROCKCHIP_VOP2_SMART1)>; + rockchip,primary-plane = ; status = "disabled"; }; diff --git a/kernel-6.1/arch/arm64/boot/dts/rockchip/rk3568-nanopi5-rev01.dts b/kernel-6.1/arch/arm64/boot/dts/rockchip/rk3568-nanopi5-rev01.dts index 290ed0b158e..083b23023f4 100644 --- a/kernel-6.1/arch/arm64/boot/dts/rockchip/rk3568-nanopi5-rev01.dts +++ b/kernel-6.1/arch/arm64/boot/dts/rockchip/rk3568-nanopi5-rev01.dts @@ -292,6 +292,38 @@ }; /* GPIO Connector */ +&gpio3 { + gpio-line-names = + /* GPIO3 A0-A7 */ + "", "PIN_06", "", "", + "", "", "", "", + /* GPIO3 B0-B7 */ + "", "", "", "", + "", "", "", "", + /* GPIO3 C0-C7 */ + "", "PIN_07", "PIN_05", "PIN_03", + "PIN_11", "PIN_12", "", "", + /* GPIO3 D0-D7 */ + "", "", "", "", + "", "", "", ""; +}; + +&gpio4 { + gpio-line-names = + /* GPIO4 A0-A7 */ + "", "", "", "", + "", "", "", "", + /* GPIO4 B0-B7 */ + "", "", "", "", + "", "", "", "", + /* GPIO4 C0-C7 */ + "", "", "", "", + "", "PIN_09 [UART9_TX_M1]", "PIN_10 [UART9_RX_M1]", "", + /* GPIO4 D0-D7 */ + "", "", "", "", + "", "", "", ""; +}; + &spi1 { num-cs = <1>; pinctrl-0 = <&spi1m1_cs0 &spi1m1_pins>; diff --git a/kernel-6.1/arch/arm64/boot/dts/rockchip/rk3568-nanopi5-rev07.dts b/kernel-6.1/arch/arm64/boot/dts/rockchip/rk3568-nanopi5-rev07.dts index e59628356f0..405a127581f 100644 --- a/kernel-6.1/arch/arm64/boot/dts/rockchip/rk3568-nanopi5-rev07.dts +++ b/kernel-6.1/arch/arm64/boot/dts/rockchip/rk3568-nanopi5-rev07.dts @@ -70,3 +70,37 @@ pinctrl-0 = <&uart7m1_xfer>; status = "disabled"; }; + +&gpio3 { + gpio-line-names = + /* GPIO3 A0-A7 */ + "", "PIN_07 [SPI1_CS0_M1]", "", "", + "", "", "", "", + /* GPIO3 B0-B7 */ + "", "", "", "", + "", "", "", "", + /* GPIO3 C0-C7 */ + "", "PIN_04 [SPI1_MOSI_M1]", + "", "PIN_03 [SPI1_CLK_M1]", + "PIN_05 [OLED_RST]", "PIN_06 [OLED_DC]", + "", "", + /* GPIO3 D0-D7 */ + "", "", "", "", + "", "", "", ""; +}; + +&gpio4 { + gpio-line-names = + /* GPIO4 A0-A7 */ + "", "", "", "", + "", "", "", "", + /* GPIO4 B0-B7 */ + "", "", "", "", + "", "", "", "", + /* GPIO4 C0-C7 */ + "", "", "", "", + "", "", "", "", + /* GPIO4 D0-D7 */ + "", "", "", "", + "", "", "", ""; +}; diff --git a/kernel-6.1/arch/arm64/boot/dts/rockchip/rk3576-nanopi5-csi0-imx415.dtsi b/kernel-6.1/arch/arm64/boot/dts/rockchip/rk3576-nanopi5-csi0-imx415.dtsi new file mode 100644 index 00000000000..e2caa501f02 --- /dev/null +++ b/kernel-6.1/arch/arm64/boot/dts/rockchip/rk3576-nanopi5-csi0-imx415.dtsi @@ -0,0 +1,167 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2025 FriendlyElec Computer Tech. Co., Ltd. + * (http://www.friendlyelec.com) + */ + +&csi2_dphy0_hw { + status = "okay"; +}; + +&csi2_dphy0 { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + mipidphy0_in_ucam0: endpoint@1 { + reg = <1>; + remote-endpoint = <&imx415_out0>; + data-lanes = <1 2 3 4>; + }; + }; + + port@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + + csidphy0_out: endpoint@0 { + reg = <0>; + remote-endpoint = <&mipi1_csi2_input>; + }; + }; + }; +}; + +&i2c4 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c4m3_xfer>; + + imx415_dphy0: imx415@1a { + compatible = "sony,imx415"; + reg = <0x1a>; + clocks = <&cru CLK_MIPI_CAMERAOUT_M1>; + clock-names = "xvclk"; + pinctrl-names = "default"; + pinctrl-0 = <&cam_clk1m0_clk1>; + power-domains = <&power RK3576_PD_VI>; + power-gpios = <&gpio3 RK_PC6 GPIO_ACTIVE_HIGH>; + reset-gpios = <&gpio3 RK_PC5 GPIO_ACTIVE_LOW>; + rockchip,camera-module-index = <0>; + rockchip,camera-module-facing = "back"; + rockchip,camera-module-name = "CMK-OT2022-PX1"; + rockchip,camera-module-lens-name = "IR0147-50IRC-8M-F20"; + + port { + imx415_out0: endpoint { + remote-endpoint = <&mipidphy0_in_ucam0>; + data-lanes = <1 2 3 4>; + }; + }; + }; +}; + +&mipi1_csi2 { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + mipi1_csi2_input: endpoint@1 { + reg = <1>; + remote-endpoint = <&csidphy0_out>; + }; + }; + + port@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + + mipi1_csi2_output: endpoint@0 { + reg = <0>; + remote-endpoint = <&cif_mipi1_in>; + }; + }; + }; +}; + +&rkcif { + status = "okay"; +}; + +&rkcif_mipi_lvds1 { + status = "okay"; + + port { + cif_mipi1_in: endpoint { + remote-endpoint = <&mipi1_csi2_output>; + }; + }; +}; + +&rkcif_mipi_lvds1_sditf { + status = "okay"; + + port { + mipi_lvds1_sditf: endpoint { + remote-endpoint = <&isp_vir0>; + }; + }; +}; + +&rkcif_mmu { + status = "okay"; +}; + +&rkisp { + status = "okay"; +}; + +&rkisp_mmu { + status = "okay"; +}; + +&rkisp_vir0 { + status = "okay"; + + port { + #address-cells = <1>; + #size-cells = <0>; + + isp_vir0: endpoint@0 { + reg = <0>; + remote-endpoint = <&mipi_lvds1_sditf>; + }; + }; +}; + +&rkisp_vir0_sditf { + status = "okay"; +}; + +&rkvpss { + status = "okay"; +}; + +&rkvpss_mmu { + status = "okay"; +}; + +&rkvpss_vir0 { + status = "okay"; +}; diff --git a/kernel-6.1/arch/arm64/boot/dts/rockchip/rk3576-nanopi5-csi1-imx415.dtsi b/kernel-6.1/arch/arm64/boot/dts/rockchip/rk3576-nanopi5-csi1-imx415.dtsi new file mode 100644 index 00000000000..4c0e0afbda5 --- /dev/null +++ b/kernel-6.1/arch/arm64/boot/dts/rockchip/rk3576-nanopi5-csi1-imx415.dtsi @@ -0,0 +1,151 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2025 FriendlyElec Computer Tech. Co., Ltd. + * (http://www.friendlyelec.com) + */ + +&csi2_dphy1_hw { + status = "okay"; +}; + +&csi2_dphy3 { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + mipidphy3_in_ucam0: endpoint@1 { + reg = <1>; + remote-endpoint = <&imx415_out1>; + data-lanes = <1 2 3 4>; + }; + }; + + port@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + + csidphy3_out: endpoint@0 { + reg = <0>; + remote-endpoint = <&mipi3_csi2_input>; + }; + }; + }; +}; + +&i2c5 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c5m3_xfer>; + + imx415_dphy3: imx415@1a { + compatible = "sony,imx415"; + reg = <0x1a>; + clocks = <&cru CLK_MIPI_CAMERAOUT_M2>; + clock-names = "xvclk"; + pinctrl-names = "default"; + pinctrl-0 = <&cam_clk2m0_clk2>; + power-domains = <&power RK3576_PD_VI>; + power-gpios = <&gpio4 RK_PC7 GPIO_ACTIVE_HIGH>; + reset-gpios = <&gpio3 RK_PA4 GPIO_ACTIVE_LOW>; + rockchip,camera-module-index = <0>; + rockchip,camera-module-facing = "back"; + rockchip,camera-module-name = "CMK-OT2022-PX1"; + rockchip,camera-module-lens-name = "IR0147-50IRC-8M-F20"; + + port { + imx415_out1: endpoint { + remote-endpoint = <&mipidphy3_in_ucam0>; + data-lanes = <1 2 3 4>; + }; + }; + }; +}; + +&mipi3_csi2 { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + mipi3_csi2_input: endpoint@1 { + reg = <1>; + remote-endpoint = <&csidphy3_out>; + }; + }; + + port@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + + mipi3_csi2_output: endpoint@0 { + reg = <0>; + remote-endpoint = <&cif_mipi3_in>; + }; + }; + }; +}; + +&rkcif { + status = "okay"; +}; + +&rkcif_mipi_lvds3 { + status = "okay"; + + port { + cif_mipi3_in: endpoint { + remote-endpoint = <&mipi3_csi2_output>; + }; + }; +}; + +&rkcif_mipi_lvds3_sditf { + status = "okay"; + + port { + mipi_lvds3_sditf: endpoint { + remote-endpoint = <&isp_vir1>; + }; + }; +}; + +&rkcif_mmu { + status = "okay"; +}; + +&rkisp { + status = "okay"; +}; + +&rkisp_mmu { + status = "okay"; +}; + +&rkisp_vir1 { + status = "okay"; + + port { + #address-cells = <1>; + #size-cells = <0>; + + isp_vir1: endpoint@0 { + reg = <0>; + remote-endpoint = <&mipi_lvds3_sditf>; + }; + }; +}; diff --git a/kernel-6.1/arch/arm64/boot/dts/rockchip/rk3576-nanopi5-rev01.dts b/kernel-6.1/arch/arm64/boot/dts/rockchip/rk3576-nanopi5-rev01.dts index 3fb18bbbace..c74895a1a51 100644 --- a/kernel-6.1/arch/arm64/boot/dts/rockchip/rk3576-nanopi5-rev01.dts +++ b/kernel-6.1/arch/arm64/boot/dts/rockchip/rk3576-nanopi5-rev01.dts @@ -275,7 +275,101 @@ dsi0_pwm: &pwm1_6ch_0 { #include "rk3576-nanopi5-mipi-lcd-yx70.dtsi" #endif +/* MIPI-CSI */ +#define ENABLE_MIPI_CSI0 1 + +#if (ENABLE_MIPI_CSI0) +#include "rk3576-nanopi5-csi0-imx415.dtsi" +#endif +#if (ENABLE_MIPI_CSI1) +#include "rk3576-nanopi5-csi1-imx415.dtsi" +#endif + /* GPIO Connector */ +&gpio0 { + gpio-line-names = + /* GPIO0 A0-A7 */ + "", "", "", "", + "", "", "", "", + /* GPIO0 B0-B7 */ + "", "", "", "", + "", "PIN_12", "", "", + /* GPIO0 C0-C7 */ + "", "PIN_05 [I2C0_SCL_M1]", "PIN_03 [I2C0_SDA_M1]", "", + "PIN_22", "", "", "", + /* GPIO0 D0-D7 */ + "", "", "", "", + "", "", "", ""; +}; + +&gpio1 { + gpio-line-names = + /* GPIO1 A0-A7 */ + "", "", "", "", + "", "", "", "", + /* GPIO1 B0-B7 */ + "", "", "", "", + "", "", "", "", + /* GPIO1 C0-C7 */ + "", "", "", "", + "", "", "", "", + /* GPIO1 D0-D7 */ + "", "", "", "", + "", "", "", ""; +}; + +&gpio2 { + gpio-line-names = + /* GPIO2 A0-A7 */ + "", "", "", "", + "", "", "PIN_11 [UART8_TX_M1]", "PIN_13 [UART8_RX_M1]", + /* GPIO2 B0-B7 */ + "", "", "", "", + "", "", "", "", + /* GPIO2 C0-C7 */ + "", "", "", "", + "", "", "", "", + /* GPIO2 D0-D7 */ + "", "", "", "", + "", "", "", ""; +}; + +&gpio3 { + gpio-line-names = + /* GPIO3 A0-A7 */ + "PIN_16 [UART3_TX_M0]", "PIN_18 [UART3_RX_M0]", "", "", + "", "", "", "", + /* GPIO3 B0-B7 */ + "", "", "", "", + "", "", "", "", + /* GPIO3 C0-C7 */ + "", "", "", "", + "", "", "", "", + /* GPIO3 D0-D7 */ + "", "", "", "", + "", "", "", ""; +}; + +&gpio4 { + gpio-line-names = + /* GPIO4 A0-A7 */ + "", "", + "PIN_15", "PIN_29", + "PIN_28", "PIN_07", + "PIN_26", "PIN_27", + /* GPIO4 B0-B7 */ + "PIN_23", "PIN_19", + "PIN_21", "PIN_24", + "PIN_10", "PIN_08", + "", "", + /* GPIO4 C0-C7 */ + "", "", "", "", + "", "", "", "", + /* GPIO4 D0-D7 */ + "", "", "", "", + "", "", "", ""; +}; + &spi3 { status = "disabled"; pinctrl-0 = <&spi3m2_csn0 &spi3m2_csn1 &spi3m2_pins>; diff --git a/kernel-6.1/arch/arm64/boot/dts/rockchip/rk3576-nanopi5-rev02.dts b/kernel-6.1/arch/arm64/boot/dts/rockchip/rk3576-nanopi5-rev02.dts index 8ab1b9d1c59..1f9b52efb3e 100644 --- a/kernel-6.1/arch/arm64/boot/dts/rockchip/rk3576-nanopi5-rev02.dts +++ b/kernel-6.1/arch/arm64/boot/dts/rockchip/rk3576-nanopi5-rev02.dts @@ -259,6 +259,24 @@ }; /* GPIO Connector */ +&gpio4 { + gpio-line-names = + /* GPIO4 A0-A7 */ + "", "", + "", "PIN_03", + "PIN_04 [UART6_TX_M0]", "PIN_05", + "PIN_06 [UART6_RX_M0]", "PIN_07", + /* GPIO4 B0-B7 */ + "", "", "", "", + "", "", "", "", + /* GPIO4 C0-C7 */ + "", "", "", "", + "", "", "", "", + /* GPIO4 D0-D7 */ + "", "", "", "", + "", "", "", ""; +}; + &spi0 { status = "disabled"; diff --git a/kernel-6.1/arch/arm64/boot/dts/rockchip/rk3588-nanopi6-rev01.dts b/kernel-6.1/arch/arm64/boot/dts/rockchip/rk3588-nanopi6-rev01.dts index f7c3aca0f55..408b029236e 100644 --- a/kernel-6.1/arch/arm64/boot/dts/rockchip/rk3588-nanopi6-rev01.dts +++ b/kernel-6.1/arch/arm64/boot/dts/rockchip/rk3588-nanopi6-rev01.dts @@ -750,7 +750,96 @@ dsi1_pwm: &pwm11 { #undef ENABLE_MIPI_DSI1 +/* MIPI-CSI */ +#define ENABLE_MIPI_CSI0 1 + +#if (ENABLE_MIPI_CSI0) +#include "rk3588-nanopi6-csi0-imx415.dtsi" +#endif + /* GPIO Connector */ +&gpio0 { + gpio-line-names = + /* GPIO0 A0-A7 */ + "", "", "", "", + "", "", "", "", + /* GPIO0 B0-B7 */ + "", "", "", "", + "", "", "", "", + /* GPIO0 C0-C7 */ + "", "", "", "", + "PIN_10", "PIN_08", "PIN_32", "", + /* GPIO0 D0-D7 */ + "", "", "", "", + "", "", "", ""; +}; + +&gpio1 { + gpio-line-names = + /* GPIO1 A0-A7 */ + "PIN_27 [UART6_RX_M1]", "PIN_28 [UART6_TX_M1]", "", "", + "", "", "", "PIN_15", + /* GPIO1 B0-B7 */ + "PIN_26", "PIN_21", "PIN_19", "PIN_23", + "PIN_24", "PIN_22", "", "", + /* GPIO1 C0-C7 */ + "", "", "", "", + "", "", "", "", + /* GPIO1 D0-D7 */ + "", "", "", "", + "", "", "PIN_05", "PIN_03"; +}; + +&gpio2 { + gpio-line-names = + /* GPIO2 A0-A7 */ + "", "", "", "", + "", "", "", "", + /* GPIO2 B0-B7 */ + "", "", "", "", + "", "", "", "", + /* GPIO2 C0-C7 */ + "", "", "", "", + "", "", "", "", + /* GPIO2 D0-D7 */ + "", "", "", "", + "", "", "", ""; +}; + +&gpio3 { + gpio-line-names = + /* GPIO3 A0-A7 */ + "PIN_35", "PIN_38", "PIN_40", "PIN_36", + "PIN_37", "", "", "", + /* GPIO3 B0-B7 */ + "PIN_33", "", + "PIN_07", "PIN_16", + "PIN_18", "PIN_29", + "PIN_31", "PIN_12", + /* GPIO3 C0-C7 */ + "", "", "PIN_11", "PIN_13", + "", "", "", "", + /* GPIO3 D0-D7 */ + "", "", "", "", + "", "", "", ""; +}; + +&gpio4 { + gpio-line-names = + /* GPIO4 A0-A7 */ + "", "", "", "", + "", "", "", "", + /* GPIO4 B0-B7 */ + "", "", "", "", + "", "", "", "", + /* GPIO4 C0-C7 */ + "", "", "", "", + "", "", "", "", + /* GPIO4 D0-D7 */ + "", "", "", "", + "", "", "", ""; +}; + &pwm5 { pinctrl-0 = <&pwm5m1_pins>; status = "okay"; diff --git a/kernel-6.1/arch/arm64/boot/dts/rockchip/rk3588-nanopi6-rev02.dts b/kernel-6.1/arch/arm64/boot/dts/rockchip/rk3588-nanopi6-rev02.dts index 9888130a3c1..aff5336ce07 100644 --- a/kernel-6.1/arch/arm64/boot/dts/rockchip/rk3588-nanopi6-rev02.dts +++ b/kernel-6.1/arch/arm64/boot/dts/rockchip/rk3588-nanopi6-rev02.dts @@ -212,6 +212,38 @@ }; /* GPIO Connector */ +&gpio1 { + gpio-line-names = + /* GPIO1 A0-A7 */ + "", "", "", "", + "", "", "", "", + /* GPIO1 B0-B7 */ + "", "PIN_05", "PIN_07", "PIN_03", + "PIN_06", "", "PIN_10", "PIN_09", + /* GPIO1 C0-C7 */ + "", "", "", "", + "", "", "", "", + /* GPIO1 D0-D7 */ + "", "", "", "", + "", "", "", ""; +}; + +&gpio3 { + gpio-line-names = + /* GPIO3 A0-A7 */ + "", "", "", "", + "", "", "", "", + /* GPIO3 B0-B7 */ + "", "", "", "", + "", "", "", "", + /* GPIO3 C0-C7 */ + "", "", "", "", + "PIN_11 [UART5_TX_M1]", "PIN_12 [UART5_RX_M1]", "", "", + /* GPIO3 D0-D7 */ + "", "", "", "", + "", "", "", ""; +}; + &spi0 { pinctrl-0 = <&spi0m2_cs0 &spi0m2_pins>; status = "disabled"; diff --git a/kernel-6.1/arch/arm64/boot/dts/rockchip/rk3588-nanopi6-rev04.dts b/kernel-6.1/arch/arm64/boot/dts/rockchip/rk3588-nanopi6-rev04.dts index 496f427b22d..b1c6cf11d58 100644 --- a/kernel-6.1/arch/arm64/boot/dts/rockchip/rk3588-nanopi6-rev04.dts +++ b/kernel-6.1/arch/arm64/boot/dts/rockchip/rk3588-nanopi6-rev04.dts @@ -35,6 +35,86 @@ }; /* GPIO Connector */ +&gpio0 { + gpio-line-names = + /* GPIO0 A0-A7 */ + "", "", "", "", + "", "", "", "", + /* GPIO0 B0-B7 */ + "", "", "", "", + "", "", "", "", + /* GPIO0 C0-C7 */ + "", "", "", "", + "", "", "", "", + /* GPIO0 D0-D7 */ + "", "", "", "", + "PIN_12", "", "", ""; +}; + +&gpio1 { + gpio-line-names = + /* GPIO1 A0-A7 */ + "", "", "PIN_26", "PIN_29", + "", "", "", "", + /* GPIO1 B0-B7 */ + "", "PIN_21", "PIN_19", "PIN_23", + "PIN_24", "", "PIN_27", "PIN_28", + /* GPIO1 C0-C7 */ + "", "", "", "", + "", "", "", "", + /* GPIO1 D0-D7 */ + "", "", "", "", + "", "", "PIN_05", "PIN_03"; +}; + +&gpio2 { + gpio-line-names = + /* GPIO2 A0-A7 */ + "", "", "", "", + "", "", "", "", + /* GPIO2 B0-B7 */ + "", "", "", "", + "", "", "", "", + /* GPIO2 C0-C7 */ + "", "", "", "", + "", "", "", "", + /* GPIO2 D0-D7 */ + "", "", "", "", + "", "", "", ""; +}; + +&gpio3 { + gpio-line-names = + /* GPIO3 A0-A7 */ + "", "", "", "", + "", "", "", "", + /* GPIO3 B0-B7 */ + "", "", "", "", + "", "", "", "", + /* GPIO3 C0-C7 */ + "", "", "", "", + "PIN_08 [UART5_TX_M1]", "PIN_10 [UART5_RX_M1]", "", "", + /* GPIO3 D0-D7 */ + "", "", "", "", + "", "", "", ""; +}; + +&gpio4 { + gpio-line-names = + /* GPIO4 A0-A7 */ + "PIN_07", "PIN_11", "PIN_13", "", + "", "PIN_15", "PIN_16", "", + /* GPIO4 B0-B7 */ + "", "PIN_18", "PIN_22", "", + "", "", "", "", + /* GPIO4 C0-C7 */ + "", "", "", "", + "", "", "", "", + /* GPIO4 D0-D7 */ + "", "", "", "", + "", "", "", ""; +}; + &pwm0 { pinctrl-0 = <&pwm0m2_pins>; status = "okay"; diff --git a/kernel-6.1/arch/arm64/boot/dts/rockchip/rk3588-nanopi6-rev05.dts b/kernel-6.1/arch/arm64/boot/dts/rockchip/rk3588-nanopi6-rev05.dts index 40b95b5ea8e..c02d19de772 100644 --- a/kernel-6.1/arch/arm64/boot/dts/rockchip/rk3588-nanopi6-rev05.dts +++ b/kernel-6.1/arch/arm64/boot/dts/rockchip/rk3588-nanopi6-rev05.dts @@ -35,6 +35,86 @@ }; /* GPIO Connector */ +&gpio0 { + gpio-line-names = + /* GPIO0 A0-A7 */ + "", "", "", "", + "", "", "", "", + /* GPIO0 B0-B7 */ + "", "", "", "", + "", "", "", "", + /* GPIO0 C0-C7 */ + "", "", "", "", + "", "", "", "", + /* GPIO0 D0-D7 */ + "", "", "", "", + "PIN_12", "", "", ""; +}; + +&gpio1 { + gpio-line-names = + /* GPIO1 A0-A7 */ + "", "", "PIN_26", "PIN_29", + "", "", "", "", + /* GPIO1 B0-B7 */ + "", "PIN_21", "PIN_19", "PIN_23", + "PIN_24", "", "PIN_27", "PIN_28", + /* GPIO1 C0-C7 */ + "", "", "", "", + "", "", "", "", + /* GPIO1 D0-D7 */ + "", "", "", "", + "", "", "PIN_05", "PIN_03"; +}; + +&gpio2 { + gpio-line-names = + /* GPIO2 A0-A7 */ + "", "", "", "", + "", "", "", "", + /* GPIO2 B0-B7 */ + "", "", "", "", + "", "", "", "", + /* GPIO2 C0-C7 */ + "", "", "", "", + "", "", "", "", + /* GPIO2 D0-D7 */ + "", "", "", "", + "", "", "", ""; +}; + +&gpio3 { + gpio-line-names = + /* GPIO3 A0-A7 */ + "", "", "", "", + "", "", "", "", + /* GPIO3 B0-B7 */ + "", "", "", "", + "", "", "", "", + /* GPIO3 C0-C7 */ + "", "", "", "", + "PIN_08 [UART5_TX_M1]", "PIN_10 [UART5_RX_M1]", "", "", + /* GPIO3 D0-D7 */ + "", "", "", "", + "", "", "", ""; +}; + +&gpio4 { + gpio-line-names = + /* GPIO4 A0-A7 */ + "PIN_07", "PIN_11", "PIN_13", "", + "", "PIN_15", "PIN_16", "", + /* GPIO4 B0-B7 */ + "", "PIN_18", "PIN_22", "", + "", "", "", "", + /* GPIO4 C0-C7 */ + "", "", "", "", + "", "", "", "", + /* GPIO4 D0-D7 */ + "", "", "", "", + "", "", "", ""; +}; + &pwm0 { pinctrl-0 = <&pwm0m2_pins>; status = "okay"; diff --git a/kernel-6.1/arch/arm64/boot/dts/rockchip/rk3588-nanopi6-rev09.dts b/kernel-6.1/arch/arm64/boot/dts/rockchip/rk3588-nanopi6-rev09.dts index 2bbf160669a..1a579edc9fe 100644 --- a/kernel-6.1/arch/arm64/boot/dts/rockchip/rk3588-nanopi6-rev09.dts +++ b/kernel-6.1/arch/arm64/boot/dts/rockchip/rk3588-nanopi6-rev09.dts @@ -799,6 +799,88 @@ dsi0_pwm: &pwm2 { }; /* GPIO Connector */ +&gpio0 { + gpio-line-names = + /* GPIO0 A0-A7 */ + "", "", "", "", + "", "", "", "", + /* GPIO0 B0-B7 */ + "", "", "", "", + "", "", "", "", + /* GPIO0 C0-C7 */ + "", "", "", "", + "PIN_10", "PIN_08", "PIN_32", "", + /* GPIO0 D0-D7 */ + "", "", "", "", + "", "", "", ""; +}; + +&gpio1 { + gpio-line-names = + /* GPIO1 A0-A7 */ + "PIN_27 [UART6_RX_M1]", "PIN_28 [UART6_TX_M1]", "", "", + "", "", "", "PIN_15", + /* GPIO1 B0-B7 */ + "PIN_26", "PIN_21", "PIN_19", "PIN_23", + "PIN_24", "PIN_22", "", "", + /* GPIO1 C0-C7 */ + "", "", "", "", + "", "", "", "", + /* GPIO1 D0-D7 */ + "", "", "", "", + "", "", "PIN_05", "PIN_03"; +}; + +&gpio2 { + gpio-line-names = + /* GPIO2 A0-A7 */ + "", "", "", "", + "", "", "", "", + /* GPIO2 B0-B7 */ + "", "", "", "", + "", "", "", "", + /* GPIO2 C0-C7 */ + "", "", "", "", + "", "", "", "", + /* GPIO2 D0-D7 */ + "", "", "", "", + "", "", "", ""; +}; + +&gpio3 { + gpio-line-names = + /* GPIO3 A0-A7 */ + "PIN_35", "PIN_38", "PIN_40", "PIN_36", + "PIN_37", "", "", "", + /* GPIO3 B0-B7 */ + "PIN_33", "", + "PIN_07", "PIN_16", + "PIN_18", "PIN_29", + "PIN_31", "PIN_12", + /* GPIO3 C0-C7 */ + "", "", "PIN_11", "PIN_13", + "", "", "", "", + /* GPIO3 D0-D7 */ + "", "", "", "", + "", "", "", ""; +}; + +&gpio4 { + gpio-line-names = + /* GPIO4 A0-A7 */ + "", "", "", "", + "", "", "", "", + /* GPIO4 B0-B7 */ + "", "", "", "", + "", "", "", "", + /* GPIO4 C0-C7 */ + "", "", "", "", + "", "", "", "", + /* GPIO4 D0-D7 */ + "", "", "", "", + "", "", "", ""; +}; + &pwm5 { pinctrl-0 = <&pwm5m1_pins>; status = "okay"; diff --git a/kernel-6.1/arch/arm64/boot/dts/rockchip/rk3588-nanopi6-rev0a.dts b/kernel-6.1/arch/arm64/boot/dts/rockchip/rk3588-nanopi6-rev0a.dts index cf976503199..e1a89bb767b 100644 --- a/kernel-6.1/arch/arm64/boot/dts/rockchip/rk3588-nanopi6-rev0a.dts +++ b/kernel-6.1/arch/arm64/boot/dts/rockchip/rk3588-nanopi6-rev0a.dts @@ -391,7 +391,7 @@ dsi1_pwm: &pwm11 { }; /* MIPI-CSI */ -#define ENABLE_MIPI_DCSI0 0 +#define ENABLE_MIPI_CSI0 1 #if (ENABLE_MIPI_CSI0) #include "rk3588-nanopi6-csi0-imx415.dtsi" @@ -459,6 +459,88 @@ dsi1_pwm: &pwm11 { #undef ENABLE_MIPI_DSI1 /* GPIO Connector */ +&gpio0 { + gpio-line-names = + /* GPIO0 A0-A7 */ + "", "", "", "", + "", "", "", "", + /* GPIO0 B0-B7 */ + "", "", "", "", + "", "", "", "", + /* GPIO0 C0-C7 */ + "", "", "", "", + "PIN_27", "", "", "", + /* GPIO0 D0-D7 */ + "", "", "", "", + "PIN_16", "PIN_18", "", ""; +}; + +&gpio1 { + gpio-line-names = + /* GPIO1 A0-A7 */ + "PIN_28 [UART6_RX_M1]", "PIN_29 [UART6_TX_M1]", "", "", + "", "", "", "", + /* GPIO1 B0-B7 */ + "", "PIN_21", + "PIN_19", "PIN_23", + "PIN_24", "PIN_26", + "", "", + /* GPIO1 C0-C7 */ + "", "", "", "", + "", "", "", "", + /* GPIO1 D0-D7 */ + "", "", "", "", + "", "", "PIN_05 [I2C8_SCL_M2]", "PIN_03 [I2C8_SDA_M2]"; +}; + +&gpio2 { + gpio-line-names = + /* GPIO2 A0-A7 */ + "", "", "", "", + "", "", "", "", + /* GPIO2 B0-B7 */ + "", "", "", "", + "", "", "", "", + /* GPIO2 C0-C7 */ + "", "", "", "", + "", "", "", "", + /* GPIO2 D0-D7 */ + "", "", "", "", + "", "", "", ""; +}; + +&gpio3 { + gpio-line-names = + /* GPIO3 A0-A7 */ + "", "", "", "", + "", "", "", "", + /* GPIO3 B0-B7 */ + "", "", "", "", + "", "", "", "", + /* GPIO3 C0-C7 */ + "", "", "", "", + "PIN_08 [UART5_TX_M1]", "PIN_10 [UART5_RX_M1]", "", "", + /* GPIO3 D0-D7 */ + "", "", "", "", + "", "", "", ""; +}; + +&gpio4 { + gpio-line-names = + /* GPIO4 A0-A7 */ + "", "", "", "PIN_13", + "PIN_15", "", "", "", + /* GPIO4 B0-B7 */ + "PIN_07", "PIN_11", "PIN_22", "PIN_12", + "", "", "", "", + /* GPIO4 C0-C7 */ + "", "", "", "", + "", "", "", "", + /* GPIO4 D0-D7 */ + "", "", "", "", + "", "", "", ""; +}; + &i2c1 { pinctrl-0 = <&i2c1m2_xfer>; status = "disabled"; diff --git a/kernel-6.1/arch/arm64/configs/nanopi5_android_defconfig b/kernel-6.1/arch/arm64/configs/nanopi5_android_defconfig index 0b2197adbb4..7cf274a561d 100644 --- a/kernel-6.1/arch/arm64/configs/nanopi5_android_defconfig +++ b/kernel-6.1/arch/arm64/configs/nanopi5_android_defconfig @@ -562,6 +562,7 @@ CONFIG_VIDEO_ROCKCHIP_ISP=y CONFIG_VIDEO_ROCKCHIP_ISPP=y CONFIG_VIDEO_ROCKCHIP_VPSS=y CONFIG_VIDEO_ROCKCHIP_HDMIRX=y +CONFIG_VIDEO_IMX415=y CONFIG_DRM=y CONFIG_DRM_IGNORE_IOTCL_PERMIT=y CONFIG_DRM_LOAD_EDID_FIRMWARE=y diff --git a/kernel-6.1/arch/arm64/configs/nanopi5_linux_defconfig b/kernel-6.1/arch/arm64/configs/nanopi5_linux_defconfig index b332fd6cf86..4fc5a6fddbb 100644 --- a/kernel-6.1/arch/arm64/configs/nanopi5_linux_defconfig +++ b/kernel-6.1/arch/arm64/configs/nanopi5_linux_defconfig @@ -1119,6 +1119,7 @@ CONFIG_VIDEO_ROCKCHIP_ISPP=y CONFIG_VIDEO_ROCKCHIP_RGA=y CONFIG_VIDEO_ROCKCHIP_VPSS=y # CONFIG_VIDEO_IR_I2C is not set +CONFIG_VIDEO_IMX415=m CONFIG_DRM=y CONFIG_DRM_IGNORE_IOTCL_PERMIT=y CONFIG_DRM_LOAD_EDID_FIRMWARE=y diff --git a/kernel-6.1/drivers/dma-buf/heaps/rk_system_heap.c b/kernel-6.1/drivers/dma-buf/heaps/rk_system_heap.c index b3a89969fff..e936ad8b15d 100644 --- a/kernel-6.1/drivers/dma-buf/heaps/rk_system_heap.c +++ b/kernel-6.1/drivers/dma-buf/heaps/rk_system_heap.c @@ -58,6 +58,13 @@ struct dma_heap_attachment { bool uncached; }; +struct system_heap_work { + struct work_struct work; + struct system_heap_buffer *buffer; +}; + +static struct workqueue_struct *system_heap_wq; + #define LOW_ORDER_GFP (GFP_HIGHUSER | __GFP_ZERO) #define HIGH_ORDER_GFP (((GFP_HIGHUSER | __GFP_ZERO | __GFP_NOWARN \ | __GFP_NORETRY) & ~__GFP_RECLAIM) \ @@ -436,9 +443,8 @@ static int system_heap_zero_buffer(struct system_heap_buffer *buffer) return ret; } -static void system_heap_dma_buf_release(struct dma_buf *dmabuf) +static void system_heap_dma_buf_release_sync(struct system_heap_buffer *buffer) { - struct system_heap_buffer *buffer = dmabuf->priv; struct sg_table *table; struct scatterlist *sg; int i, j; @@ -460,6 +466,29 @@ static void system_heap_dma_buf_release(struct dma_buf *dmabuf) kfree(buffer); } +static void system_heap_worker(struct work_struct *w) +{ + struct system_heap_work *heap_work = container_of(w, struct system_heap_work, work); + struct system_heap_buffer *buffer = heap_work->buffer; + + system_heap_dma_buf_release_sync(buffer); + kfree(heap_work); +} + +static void system_heap_dma_buf_release(struct dma_buf *dmabuf) +{ + struct system_heap_buffer *buffer = dmabuf->priv; + struct system_heap_work *heap_work = kzalloc(sizeof(*heap_work), GFP_KERNEL); + + if (heap_work) { + INIT_WORK(&heap_work->work, system_heap_worker); + heap_work->buffer = buffer; + queue_work(system_heap_wq, &heap_work->work); + } else { + system_heap_dma_buf_release_sync(buffer); + } +} + static const struct dma_buf_ops system_heap_buf_ops = { .attach = system_heap_attach, .detach = system_heap_detach, @@ -547,8 +576,14 @@ static struct dma_buf *system_heap_do_allocate(struct dma_heap *heap, page = system_heap_alloc_largest_available(heap, buffer->pools, size_remaining, max_order); - if (!page) - goto free_buffer; + if (!page) { + flush_workqueue(system_heap_wq); + page = system_heap_alloc_largest_available(heap, buffer->pools, + size_remaining, + max_order); + if (!page) + goto free_buffer; + } size_remaining -= page_size(page); max_order = compound_order(page); @@ -847,6 +882,12 @@ static int system_heap_create(void) bank_bit_mask = ddr_map_info->bank_bit_mask; } + system_heap_wq = create_singlethread_workqueue("system_heap_wq"); + if (!system_heap_wq) { + pr_err("Failed to create system heap workqueue\n"); + goto err_dma32_pool; + } + return 0; err_dma32_pool: for (i = 0; i < NUM_ORDERS; i++) diff --git a/kernel-6.1/drivers/media/platform/rockchip/cif/capture.c b/kernel-6.1/drivers/media/platform/rockchip/cif/capture.c index 6fda40cdc31..49a80dadd7d 100644 --- a/kernel-6.1/drivers/media/platform/rockchip/cif/capture.c +++ b/kernel-6.1/drivers/media/platform/rockchip/cif/capture.c @@ -8561,7 +8561,7 @@ int rkcif_do_start_stream(struct rkcif_stream *stream, enum rkcif_stream_mode mo } } if (dev->chip_id >= CHIP_RK1808_CIF) { - if (dev->active_sensor && + if (dev->active_sensor && (dev->active_sensor->mbus.type == V4L2_MBUS_CSI2_DPHY || dev->active_sensor->mbus.type == V4L2_MBUS_CSI2_CPHY || dev->active_sensor->mbus.type == V4L2_MBUS_CCP2)) { @@ -8997,12 +8997,18 @@ void rkcif_stream_init(struct rkcif_device *dev, u32 id) stream->frame_loss = 0; } -static int rkcif_sensor_set_power(struct rkcif_stream *stream, int on) +int rkcif_sensor_set_power(struct rkcif_stream *stream, int on) { struct rkcif_device *cif_dev = stream->cifdev; struct sditf_priv *priv = cif_dev->sditf[0]; int i = 0; + if (!on && atomic_dec_if_positive(&cif_dev->sd_power_cnt)) + return 0; + + if (on && atomic_inc_return(&cif_dev->sd_power_cnt) > 1) + return 0; + if (cif_dev->terminal_sensor.sd) v4l2_subdev_call(cif_dev->terminal_sensor.sd, core, s_power, on); @@ -9068,11 +9074,11 @@ static int rkcif_fh_open(struct file *filp) ret = v4l2_pipeline_pm_get(&vnode->vdev.entity); v4l2_dbg(1, rkcif_debug, vdev, "open video, entity use_count %d\n", vnode->vdev.entity.use_count); + ret = rkcif_sensor_set_power(stream, on); mutex_unlock(&cifdev->stream_lock); if (ret < 0) vb2_fop_release(filp); } - ret = rkcif_sensor_set_power(stream, on); return ret; } @@ -9088,6 +9094,7 @@ static int rkcif_fh_release(struct file *filp) ret = vb2_fop_release(filp); if (!ret) { mutex_lock(&cifdev->stream_lock); + ret = rkcif_sensor_set_power(stream, on); v4l2_pipeline_pm_put(&vnode->vdev.entity); v4l2_dbg(1, rkcif_debug, vdev, "close video, entity use_count %d\n", vnode->vdev.entity.use_count); @@ -9095,7 +9102,6 @@ static int rkcif_fh_release(struct file *filp) } pm_runtime_put_sync(cifdev->dev); - ret = rkcif_sensor_set_power(stream, on); return ret; } @@ -10819,7 +10825,7 @@ void rkcif_irq_oneframe(struct rkcif_device *cif_dev) /* There are two irqs enabled: * - PST_INF_FRAME_END: cif FIFO is ready, this is prior to FRAME_END - * - FRAME_END: cif has saved frame to memory, a frame ready + * - FRAME_END: cif has saved frame to memory, a frame ready */ stream = &cif_dev->stream[RKCIF_STREAM_CIF]; diff --git a/kernel-6.1/drivers/media/platform/rockchip/cif/dev.c b/kernel-6.1/drivers/media/platform/rockchip/cif/dev.c index 24b33d0ec9e..27d7a3da08c 100644 --- a/kernel-6.1/drivers/media/platform/rockchip/cif/dev.c +++ b/kernel-6.1/drivers/media/platform/rockchip/cif/dev.c @@ -2876,6 +2876,7 @@ int rkcif_plat_init(struct rkcif_device *cif_dev, struct device_node *node, int atomic_set(&cif_dev->power_cnt, 0); atomic_set(&cif_dev->streamoff_cnt, 0); atomic_set(&cif_dev->sensor_off, 1); + atomic_set(&cif_dev->sd_power_cnt, 0); cif_dev->is_start_hdr = false; cif_dev->pipe.open = rkcif_pipeline_open; cif_dev->pipe.close = rkcif_pipeline_close; diff --git a/kernel-6.1/drivers/media/platform/rockchip/cif/dev.h b/kernel-6.1/drivers/media/platform/rockchip/cif/dev.h index 67bebcee90c..89522611533 100644 --- a/kernel-6.1/drivers/media/platform/rockchip/cif/dev.h +++ b/kernel-6.1/drivers/media/platform/rockchip/cif/dev.h @@ -967,6 +967,7 @@ struct rkcif_device { atomic_t power_cnt; atomic_t streamoff_cnt; atomic_t sensor_off; + atomic_t sd_power_cnt; struct mutex stream_lock; /* lock between streams */ struct mutex scale_lock; /* lock between scale dev */ struct mutex tools_lock; /* lock between tools dev */ @@ -1179,4 +1180,6 @@ void rkcif_modify_line_int(struct rkcif_stream *stream, bool en); void rkcif_set_sof(struct rkcif_device *cif_dev, u32 seq); void rkcif_set_sensor_streamon_in_sync_mode(struct rkcif_device *cif_dev); +int rkcif_sensor_set_power(struct rkcif_stream *stream, int on); + #endif diff --git a/kernel-6.1/drivers/media/platform/rockchip/cif/subdev-itf.c b/kernel-6.1/drivers/media/platform/rockchip/cif/subdev-itf.c index ec01bfd83c0..d88c1f1ddec 100644 --- a/kernel-6.1/drivers/media/platform/rockchip/cif/subdev-itf.c +++ b/kernel-6.1/drivers/media/platform/rockchip/cif/subdev-itf.c @@ -1244,6 +1244,7 @@ static int sditf_s_power(struct v4l2_subdev *sd, int on) pm_runtime_put_sync(cif_dev->dev); priv->mode.rdbk_mode = RKISP_VICAP_RDBK_AIQ; } + ret |= rkcif_sensor_set_power(&cif_dev->stream[0], on); v4l2_dbg(1, rkcif_debug, &node->vdev, "s_power %d, entity use_count %d\n", on, node->vdev.entity.use_count); mutex_unlock(&cif_dev->stream_lock); diff --git a/kernel-6.1/drivers/pci/controller/dwc/pcie-dw-rockchip.c b/kernel-6.1/drivers/pci/controller/dwc/pcie-dw-rockchip.c index 3291c1dea11..77231ebcd46 100644 --- a/kernel-6.1/drivers/pci/controller/dwc/pcie-dw-rockchip.c +++ b/kernel-6.1/drivers/pci/controller/dwc/pcie-dw-rockchip.c @@ -950,14 +950,21 @@ static const struct dw_pcie_ops dw_pcie_ops = { .link_up = rk_pcie_link_up, }; -static void rk_pcie_fast_link_setup(struct rk_pcie *rk_pcie) +static void rk_pcie_fast_link_setup(struct rk_pcie *rk_pcie, bool enable_dly2_en) { u32 val; /* LTSSM EN ctrl mode */ val = rk_pcie_readl_apb(rk_pcie, PCIE_CLIENT_HOT_RESET_CTRL); - val |= (PCIE_LTSSM_ENABLE_ENHANCE | PCIE_LTSSM_APP_DLY2_EN) - | ((PCIE_LTSSM_APP_DLY2_EN | PCIE_LTSSM_ENABLE_ENHANCE) << 16); + val |= PCIE_LTSSM_ENABLE_ENHANCE | (PCIE_LTSSM_ENABLE_ENHANCE << 16); + + if (enable_dly2_en) { + val |= PCIE_LTSSM_APP_DLY2_EN | (PCIE_LTSSM_APP_DLY2_EN << 16); + } else { + val &= ~PCIE_LTSSM_APP_DLY2_EN; + val |= PCIE_LTSSM_APP_DLY2_EN << 16; + } + rk_pcie_writel_apb(rk_pcie, PCIE_CLIENT_HOT_RESET_CTRL, val); } @@ -1359,7 +1366,7 @@ static int rk_pcie_slot_enable(struct gpio_hotplug_slot *slot) dev_info(rk_pcie->pci->dev, "%s\n", __func__); rk_pcie->hp_no_link = true; rk_pcie_enable_power(rk_pcie); - rk_pcie_fast_link_setup(rk_pcie); + rk_pcie_fast_link_setup(rk_pcie, true); ret = rk_pcie_establish_link(rk_pcie->pci); if (ret) dev_err(rk_pcie->pci->dev, "fail to enable slot\n"); @@ -1507,6 +1514,7 @@ static int rk_pcie_hardware_io_config(struct rk_pcie *rk_pcie) phy_power_on(rk_pcie->phy); + /* Release resets after PHY is working */ reset_control_deassert(rk_pcie->rsts); ret = phy_calibrate(rk_pcie->phy); @@ -1586,7 +1594,14 @@ static int rk_pcie_host_config(struct rk_pcie *rk_pcie) dw_pcie_writel_dbi(rk_pcie->pci, rk_pcie->linkcap_off, val); } - rk_pcie_fast_link_setup(rk_pcie); + /* + * S2R is in noirq phase which couldn't ack hot reset or link down event. + * But we need to deal with dly2_en enable case, otherwise the ltssm will + * be stuck waiting for dlye_done. We could set dly2_done in advance, + * however, it's slef-clear. So the only option here is to disable dly2_en + * when resuming. + */ + rk_pcie_fast_link_setup(rk_pcie, !rk_pcie->in_suspend); rk_pcie_set_power_limit(rk_pcie); @@ -2043,6 +2058,7 @@ static int __maybe_unused rockchip_dw_pcie_resume(struct device *dev) dw_pcie_dbi_ro_wr_dis(pci); rk_pcie->in_suspend = false; + rk_pcie_fast_link_setup(rk_pcie, true); return 0;