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@ -264,6 +264,10 @@ static int rockchip_p3phy_probe(struct platform_device *pdev)
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return -EINVAL;
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}
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priv->num_clks = devm_clk_bulk_get_all(dev, &priv->clks);
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if (priv->num_clks < 1)
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return -ENODEV;
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priv->phy_grf = syscon_regmap_lookup_by_phandle(np, "rockchip,phy-grf");
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if (IS_ERR(priv->phy_grf)) {
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dev_err(dev, "failed to find rockchip,phy_grf regmap\n");
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@ -275,6 +279,13 @@ static int rockchip_p3phy_probe(struct platform_device *pdev)
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if (IS_ERR(priv->pipe_grf))
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dev_info(dev, "failed to find rockchip,pipe_grf regmap\n");
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/* Configuring grf with clk enabled. */
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ret = clk_bulk_prepare_enable(priv->num_clks, priv->clks);
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if (ret) {
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pr_err("failed to enable PCIe bulk clks %d\n", ret);
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return ret;
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}
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ret = device_property_read_u32(dev, "rockchip,pcie30-phymode", &val);
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if (!ret) {
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priv->pcie30_phymode = val;
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@ -294,6 +305,8 @@ static int rockchip_p3phy_probe(struct platform_device *pdev)
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(reg << 16) | reg);
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};
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clk_bulk_disable_unprepare(priv->num_clks, priv->clks);
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priv->phy = devm_phy_create(dev, NULL, &rockchip_p3phy_ops);
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if (IS_ERR(priv->phy)) {
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dev_err(dev, "failed to create combphy\n");
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@ -306,10 +319,6 @@ static int rockchip_p3phy_probe(struct platform_device *pdev)
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priv->p30phy = NULL;
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}
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priv->num_clks = devm_clk_bulk_get_all(dev, &priv->clks);
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if (priv->num_clks < 1)
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return -ENODEV;
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dev_set_drvdata(dev, priv);
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phy_set_drvdata(priv->phy, priv);
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phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate);
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