friendlyelec
/
rk35xx-android14
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

[kernel] merge commit 'e90c925691..38b6a98f8d'

Browse Source 
Signed-off-by: hmz007 <hmz007@gmail.com>
master
hmz007 3 months ago
parent fa918e3b1d
commit 79499badc9
15 changed files with 238 additions and 72 deletions
Show Stats Download Patch File Download Diff File

3
kernel-6.1/arch/arm64/boot/dts/rockchip/Makefile
Unescape View File

@ -44,7 +44,8 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += \
rk3588-nanopi6-rev07.dtb \
rk3588-nanopi6-rev08.dtb \
rk3588-nanopi6-rev09.dtb \
rk3588-nanopi6-rev0a.dtb
rk3588-nanopi6-rev0a.dtb \
rk3588-nanopi6-rev0b.dtb
else

2
kernel-6.1/arch/arm64/boot/dts/rockchip/rk3576-nanopi5-csi1-imx415.dtsi
Unescape View File

@ -55,7 +55,7 @@
power-domains = <&power RK3576_PD_VI>;
power-gpios = <&gpio4 RK_PC7 GPIO_ACTIVE_HIGH>;
reset-gpios = <&gpio3 RK_PA4 GPIO_ACTIVE_LOW>;
rockchip,camera-module-index = <0>;
rockchip,camera-module-index = <1>;
rockchip,camera-module-facing = "back";
rockchip,camera-module-name = "CMK-OT2022-PX1";
rockchip,camera-module-lens-name = "IR0147-50IRC-8M-F20";

2
kernel-6.1/arch/arm64/boot/dts/rockchip/rk3576-nanopi5-rev01.dts
Unescape View File

@ -277,10 +277,12 @@ dsi0_pwm: &pwm1_6ch_0 {
/* MIPI-CSI */
#define ENABLE_MIPI_CSI0 1
#define ENABLE_MIPI_CSI1 1
#if (ENABLE_MIPI_CSI0)
#include "rk3576-nanopi5-csi0-imx415.dtsi"
#endif
#if (ENABLE_MIPI_CSI1)
#include "rk3576-nanopi5-csi1-imx415.dtsi"
#endif

6
kernel-6.1/arch/arm64/boot/dts/rockchip/rk3576-nanopi5-rev02.dts
Unescape View File

@ -277,6 +277,12 @@
"", "", "", "";
};
&i2c4 {
status = "disabled";
pinctrl-names = "default";
pinctrl-0 = <&i2c4m1_xfer>;
};
&spi0 {
status = "disabled";

2
kernel-6.1/arch/arm64/boot/dts/rockchip/rk3588-nanopi6-csi1-imx415.dtsi
Unescape View File

@ -56,7 +56,7 @@
power-gpios = <&gpio2 RK_PC2 GPIO_ACTIVE_HIGH>;
reset-gpios = <&gpio2 RK_PC1 GPIO_ACTIVE_LOW>;
rockchip,camera-module-index = <0>;
rockchip,camera-module-index = <1>;
rockchip,camera-module-facing = "back";
rockchip,camera-module-name = "CMK-OT2022-PX1";
rockchip,camera-module-lens-name = "IR0147-50IRC-8M-F20";

12
kernel-6.1/arch/arm64/boot/dts/rockchip/rk3588-nanopi6-dcsi0-imx415.dtsi
Unescape View File

@ -52,7 +52,7 @@
power-gpios = <&gpio1 RK_PD3 GPIO_ACTIVE_HIGH>;
reset-gpios = <&gpio1 RK_PD2 GPIO_ACTIVE_LOW>;
rockchip,camera-module-index = <0>;
rockchip,camera-module-index = <1>;
rockchip,camera-module-facing = "back";
rockchip,camera-module-name = "CMK-OT2022-PX1";
rockchip,camera-module-lens-name = "IR0147-50IRC-8M-F20";
@ -120,7 +120,7 @@
port {
mipi2_lvds_sditf: endpoint {
remote-endpoint = <&isp0_vir0>;
remote-endpoint = <&isp1_vir0>;
};
};
};
@ -129,22 +129,22 @@
status = "okay";
};
&rkisp0 {
&rkisp1 {
status = "okay";
};
&isp0_mmu {
&isp1_mmu {
status = "okay";
};
&rkisp0_vir0 {
&rkisp1_vir0 {
status = "okay";
port {
#address-cells = <1>;
#size-cells = <0>;
isp0_vir0: endpoint@0 {
isp1_vir0: endpoint@0 {
reg = <0>;
remote-endpoint = <&mipi2_lvds_sditf>;
};

5
kernel-6.1/arch/arm64/boot/dts/rockchip/rk3588-nanopi6-rev01.dts
Unescape View File

@ -752,11 +752,16 @@ dsi1_pwm: &pwm11 {
/* MIPI-CSI */
#define ENABLE_MIPI_CSI0 1
#define ENABLE_MIPI_CSI1 1
#if (ENABLE_MIPI_CSI0)
#include "rk3588-nanopi6-csi0-imx415.dtsi"
#endif
#if (ENABLE_MIPI_CSI1)
#include "rk3588-nanopi6-csi1-imx415.dtsi"
#endif
/* GPIO Connector */
&gpio0 {
gpio-line-names =

1
kernel-6.1/arch/arm64/boot/dts/rockchip/rk3588-nanopi6-rev0a.dts
Unescape View File

@ -392,6 +392,7 @@ dsi1_pwm: &pwm11 {
/* MIPI-CSI */
#define ENABLE_MIPI_CSI0 1
#define ENABLE_MIPI_DCSI0 1
#if (ENABLE_MIPI_CSI0)
#include "rk3588-nanopi6-csi0-imx415.dtsi"

74
kernel-6.1/arch/arm64/boot/dts/rockchip/rk3588-nanopi6-rev0b.dts
Unescape View File

@ -0,0 +1,74 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright (c) 2025 FriendlyElec Computer Tech. Co., Ltd.
* (http://www.friendlyelec.com)
*/
/dts-v1/;
#include "rk3588-nanopi6-rev01.dts"
/delete-node/ &rt5616;
/delete-node/ &rt5616_sound;
/ {
model = "FriendlyElec NanoPC-T6 Plus";
compatible = "friendlyelec,nanopc-t6", "rockchip,rk3588";
es8389_sound: es8389-sound {
status = "okay";
compatible = "rockchip,multicodecs-card";
pinctrl-names = "default";
pinctrl-0 = <&hp_det>;
rockchip,card-name = "rockchip-es8389";
hp-det-gpio = <&gpio1 RK_PC4 GPIO_ACTIVE_LOW>;
rockchip,pre-power-on-delay-ms = <30>;
rockchip,post-power-down-delay-ms = <40>;
rockchip,format = "i2s";
rockchip,mclk-fs = <256>;
rockchip,cpu = <&i2s0_8ch>;
rockchip,codec = <&es8389>;
rockchip,audio-routing =
"Headphone", "HPOL",
"Headphone", "HPOR",
"Headphone", "Headphone Power",
"Headphone", "Headphone Power",
"INPUT1", "Main Mic",
"INPUT2", "Main Mic";
};
vcc5v0_host_20: vcc5v0-host-20 {
compatible = "regulator-fixed";
enable-active-high;
gpio = <&gpio1 RK_PA4 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&vcc5v0_host20_en>;
regulator-name = "vcc5v0_host_20";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
vin-supply = <&vcc5v0_usb>;
};
};
&mach {
hwrev = <0x0b>;
model = "NanoPC-T6 Plus";
};
&i2c7 {
es8389: es8389@10 {
status = "okay";
#sound-dai-cells = <0>;
compatible = "everest,es8389";
reg = <0x10>;
clocks = <&mclkout_i2s0>;
clock-names = "mclk";
assigned-clocks = <&mclkout_i2s0>;
assigned-clock-rates = <12288000>;
pinctrl-names = "default";
pinctrl-0 = <&i2s0_mclk>;
};
};
&u2phy3_host {
phy-supply = <&vcc5v0_host_20>;
};

1
kernel-6.1/arch/arm64/configs/nanopi5_android_defconfig
Unescape View File

@ -644,6 +644,7 @@ CONFIG_SND_SOC_ROCKCHIP_MULTICODECS=y
CONFIG_SND_SOC_ROCKCHIP_HDMI=y
CONFIG_SND_SOC_BT_SCO=y
CONFIG_SND_SOC_DUMMY_CODEC=y
CONFIG_SND_SOC_ES8389=y
CONFIG_SND_SOC_RK3328=y
CONFIG_SND_SOC_RK3528=y
CONFIG_SND_SOC_RK_CODEC_DIGITAL=y

1
kernel-6.1/arch/arm64/configs/nanopi5_linux_defconfig
Unescape View File

@ -1227,6 +1227,7 @@ CONFIG_SND_SOC_ES7243E=m
CONFIG_SND_SOC_ES8311=m
CONFIG_SND_SOC_ES8316=m
CONFIG_SND_SOC_ES8323=m
CONFIG_SND_SOC_ES8389=y
CONFIG_SND_SOC_PCM179X_I2C=m
CONFIG_SND_SOC_PCM512x_I2C=m
CONFIG_SND_SOC_RK3308=m

1
kernel-6.1/arch/arm64/configs/nanopi6_android_defconfig
Unescape View File

@ -633,6 +633,7 @@ CONFIG_SND_SOC_ROCKCHIP_MULTICODECS=y
CONFIG_SND_SOC_ROCKCHIP_HDMI=y
CONFIG_SND_SOC_BT_SCO=y
CONFIG_SND_SOC_DUMMY_CODEC=y
CONFIG_SND_SOC_ES8389=y
CONFIG_SND_SOC_RK3328=y
CONFIG_SND_SOC_RK_CODEC_DIGITAL=y
CONFIG_SND_SOC_RK_DSM=y

1
kernel-6.1/arch/arm64/configs/nanopi6_linux_defconfig
Unescape View File

@ -1219,6 +1219,7 @@ CONFIG_SND_SOC_ES7243E=m
CONFIG_SND_SOC_ES8311=m
CONFIG_SND_SOC_ES8316=m
CONFIG_SND_SOC_ES8323=m
CONFIG_SND_SOC_ES8389=y
CONFIG_SND_SOC_PCM179X_I2C=m
CONFIG_SND_SOC_PCM512x_I2C=m
CONFIG_SND_SOC_RK3308=m

87
kernel-6.1/drivers/phy/rockchip/phy-rockchip-samsung-hdptx-hdmi.c
Unescape View File

@ -704,6 +704,16 @@ struct ropll_config {
u8 cd_tx_ser_rate_sel;
};
struct phy_config {
unsigned long pixelclk;
u8 tx_ctrl_ln0;
u8 tx_ctrl_ln1;
u8 tx_ctrl_ln2;
u8 tx_ctrl_ln3;
};
#define PHY_TAB_LEN 5
struct rockchip_hdptx_phy {
struct device *dev;
struct regmap *regmap;
@ -827,6 +837,67 @@ static const struct ffe_cfg ffe_cfg_table[FFE_CFG_TAB_LEN] = {
{ 0x3, 0x9 },
};
static int rockchip_hdptx_parse_phy_table(struct rockchip_hdptx_phy *hdptx)
{
struct device_node *np = hdptx->dev->of_node;
struct phy_config *phy_cfg;
u32 *phy_table;
int i, num_cfg;
if (of_get_property(np, "rockchip,phy-table", &i)) {
phy_table = kmalloc(i, GFP_KERNEL);
if (!phy_table)
return -ENOMEM;
num_cfg = i / (sizeof(u32) * PHY_TAB_LEN);
phy_cfg = devm_kmalloc(hdptx->dev,
sizeof(*phy_cfg) * (num_cfg + 1), GFP_KERNEL);
if (!phy_cfg) {
kfree(phy_table);
return -ENOMEM;
}
of_property_read_u32_array(np, "rockchip,phy-table",
phy_table, i / sizeof(u32));
for (i = 0; i < num_cfg; i++) {
if (phy_table[i * PHY_TAB_LEN] != 0)
phy_cfg[i].pixelclk = phy_table[i * PHY_TAB_LEN];
else
phy_cfg[i].pixelclk = ~0UL;
phy_cfg[i].tx_ctrl_ln0 = (u8)phy_table[i * PHY_TAB_LEN + 1];
phy_cfg[i].tx_ctrl_ln1 = (u8)phy_table[i * PHY_TAB_LEN + 2];
phy_cfg[i].tx_ctrl_ln2 = (u8)phy_table[i * PHY_TAB_LEN + 3];
phy_cfg[i].tx_ctrl_ln3 = (u8)phy_table[i * PHY_TAB_LEN + 4];
}
phy_cfg[i].pixelclk = ~0UL;
hdptx->phy_cfg = phy_cfg;
kfree(phy_table);
}
return 0;
}
static void rockchip_hdptx_get_tx_ctrl(struct rockchip_hdptx_phy *hdptx, u8 *tx_ctrl)
{
struct phy_config *pcfg = hdptx->phy_cfg;
if (!pcfg || !tx_ctrl)
return;
for (; pcfg->pixelclk != ~0UL; pcfg++) {
if (hdptx->rate <= pcfg->pixelclk) {
tx_ctrl[0] = pcfg->tx_ctrl_ln0;
tx_ctrl[1] = pcfg->tx_ctrl_ln1;
tx_ctrl[2] = pcfg->tx_ctrl_ln2;
tx_ctrl[3] = pcfg->tx_ctrl_ln3;
return;
}
}
}
static bool rockchip_hdptx_phy_is_accissible_reg(struct device *dev,
unsigned int reg)
{
@ -1351,6 +1422,9 @@ static int hdptx_ropll_cmn_config(struct rockchip_hdptx_phy *hdptx, unsigned lon
static int hdptx_ropll_tmds_mode_config(struct rockchip_hdptx_phy *hdptx, u32 rate)
{
u32 bit_rate = rate & DATA_RATE_MASK;
u8 tx_ctrl[4] = { 0x2f, 0x2f, 0x2f, 0x2f };
rockchip_hdptx_get_tx_ctrl(hdptx, tx_ctrl);
hdptx_write(hdptx, SB_REG0114, 0x00);
hdptx_write(hdptx, SB_REG0115, 0x00);
@ -1440,10 +1514,11 @@ static int hdptx_ropll_tmds_mode_config(struct rockchip_hdptx_phy *hdptx, u32 ra
hdptx_write(hdptx, LANE_REG061F, 0x15);
hdptx_write(hdptx, LANE_REG0620, 0xa0);
hdptx_write(hdptx, LANE_REG0303, 0x2f);
hdptx_write(hdptx, LANE_REG0403, 0x2f);
hdptx_write(hdptx, LANE_REG0503, 0x2f);
hdptx_write(hdptx, LANE_REG0603, 0x2f);
hdptx_write(hdptx, LANE_REG0303, tx_ctrl[0]);
hdptx_write(hdptx, LANE_REG0403, tx_ctrl[1]);
hdptx_write(hdptx, LANE_REG0503, tx_ctrl[2]);
hdptx_write(hdptx, LANE_REG0603, tx_ctrl[3]);
hdptx_write(hdptx, LANE_REG0305, 0x03);
hdptx_write(hdptx, LANE_REG0405, 0x03);
hdptx_write(hdptx, LANE_REG0505, 0x03);
@ -1850,6 +1925,7 @@ static int hdptx_lcpll_ropll_frl_mode_config(struct rockchip_hdptx_phy *hdptx)
hdptx_write(hdptx, LANE_REG0403, 0x2f);
hdptx_write(hdptx, LANE_REG0503, 0x2f);
hdptx_write(hdptx, LANE_REG0603, 0x2f);
hdptx_write(hdptx, LANE_REG0305, 0x03);
hdptx_write(hdptx, LANE_REG0405, 0x03);
hdptx_write(hdptx, LANE_REG0505, 0x03);
@ -1953,6 +2029,7 @@ static int hdptx_lcpll_frl_mode_config(struct rockchip_hdptx_phy *hdptx, u32 rat
hdptx_write(hdptx, LANE_REG0403, 0x2f);
hdptx_write(hdptx, LANE_REG0503, 0x2f);
hdptx_write(hdptx, LANE_REG0603, 0x2f);
hdptx_write(hdptx, LANE_REG0305, 0x03);
hdptx_write(hdptx, LANE_REG0405, 0x03);
hdptx_write(hdptx, LANE_REG0505, 0x03);
@ -2382,6 +2459,8 @@ static int rockchip_hdptx_phy_probe(struct platform_device *pdev)
goto err_regsmap;
}
rockchip_hdptx_parse_phy_table(hdptx);
phy_set_drvdata(hdptx->phy, hdptx);
pm_runtime_enable(dev);

68
kernel-6.1/sound/soc/codecs/es8389.c
Unescape View File

@ -24,7 +24,6 @@
#include "es8389.h"
/* codec private data */
struct es8389_private {
@ -163,7 +162,6 @@ static const struct soc_enum es8389_dmic_mux_enum =
static const struct snd_kcontrol_new es8389_dmic_mux_controls =
SOC_DAPM_ENUM("ADC MUX", es8389_dmic_mux_enum);
static const struct snd_kcontrol_new es8389_left_mixer_controls[] = {
SOC_DAPM_SINGLE("DACR DACL Mixer", ES8389_DAC_MIX_REG44, 3, 1, 0),
};
@ -172,7 +170,6 @@ static const struct snd_kcontrol_new es8389_right_mixer_controls[] = {
SOC_DAPM_SINGLE("DACL DACR Mixer", ES8389_DAC_MIX_REG44, 2, 1, 0),
};
static const struct snd_kcontrol_new es8389_adc_mixer_controls[] = {
SOC_DAPM_SINGLE("DACL ADCL Mixer", ES8389_ADC_RESET_REG31, 7, 1, 0),
SOC_DAPM_SINGLE("DACR ADCR Mixer", ES8389_ADC_RESET_REG31, 6, 1, 0),
@ -252,7 +249,6 @@ static const struct snd_soc_dapm_widget es8389_dapm_widgets[] = {
SND_SOC_DAPM_MUX("OUTR MUX", SND_SOC_NOPM, 0, 0, &es8389_outr_mux_controls),
};
static const struct snd_soc_dapm_route es8389_dapm_routes[] = {
{"PGAL", NULL, "INPUT1"},
{"PGAR", NULL, "INPUT2"},
@ -280,7 +276,6 @@ static const struct snd_soc_dapm_route es8389_dapm_routes[] = {
{"IF DACL3", NULL, "DACL"},
{"IF DACR3", NULL, "DACR"},
{"IF DACL Mixer", NULL, "IF DACL2"},
{"IF DACL Mixer", "DACR DACL Mixer", "IF DACR1"},
{"IF DACR Mixer", NULL, "IF DACR2"},
@ -293,7 +288,6 @@ static const struct snd_soc_dapm_route es8389_dapm_routes[] = {
{"HPOL", NULL, "OUTL MUX"},
{"HPOR", NULL, "OUTR MUX"},
};
struct _coeff_div {
@ -316,7 +310,6 @@ struct _coeff_div {
u8 Reg0x44;
};
/* codec hifi mclk clock divider coefficients */
static const struct _coeff_div coeff_div[] = {
{32 ,256000 ,8000 , 0x00, 0x57, 0x84, 0xD0, 0x03, 0xC1, 0xB0, 0x00, 0x1F, 0x7F, 0xFF, 0x7F, 0x01, 0x80},
@ -400,7 +393,7 @@ static int es8389_set_dai_sysclk(struct snd_soc_dai *dai,
struct snd_soc_component *codec = dai->component;
struct es8389_private *es8389 = snd_soc_component_get_drvdata(codec);
printk("Enter into %s()\n", __func__);
dev_dbg(codec->dev, "Enter into %s()\n", __func__);
switch (freq) {
case 11289600:
case 22579200:
@ -434,7 +427,7 @@ static int es8389_set_dai_fmt(struct snd_soc_dai *codec_dai, unsigned int fmt)
dev_dbg(codec->dev, "Enter into %s()\n", __func__);
switch(fmt & SND_SOC_DAIFMT_MASTER_MASK)
switch (fmt & SND_SOC_DAIFMT_MASTER_MASK)
{
case SND_SOC_DAIFMT_CBM_CFM:
regmap_update_bits(es8389->regmap, ES8389_MASTER_MODE_REG01,
@ -446,7 +439,7 @@ static int es8389_set_dai_fmt(struct snd_soc_dai *codec_dai, unsigned int fmt)
return -EINVAL;
}
switch(fmt & SND_SOC_DAIFMT_FORMAT_MASK)
switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK)
{
case SND_SOC_DAIFMT_I2S:
state |= ES8389_DAIFMT_I2S;
@ -466,6 +459,7 @@ static int es8389_set_dai_fmt(struct snd_soc_dai *codec_dai, unsigned int fmt)
default:
break;
}
regmap_update_bits(es8389->regmap, ES8389_ADC_REG20, ES8389_DAIFMT_MASK, state);
regmap_update_bits(es8389->regmap, ES8389_DAC_REG40, ES8389_DAIFMT_MASK, state);
@ -495,9 +489,9 @@ static int es8389_pcm_hw_params(struct snd_pcm_substream *substream,
int coeff;
u8 state = 0;
printk("Enter into %s()\n", __func__);
dev_dbg(codec->dev, "Enter into %s()\n", __func__);
switch (params_format(params)){
switch (params_format(params)) {
case SNDRV_PCM_FORMAT_S16_LE:
state |= ES8389_S16_LE;
break;
@ -521,8 +515,7 @@ static int es8389_pcm_hw_params(struct snd_pcm_substream *substream,
regmap_update_bits(es8389->regmap, ES8389_DAC_REG40, ES8389_DATA_LEN_MASK, state);
coeff = get_coeff(es8389->sysclk, params_rate(params));
if(coeff >= 0)
{
if (coeff >= 0) {
regmap_write(es8389->regmap, ES8389_CLK_DIV1_REG04, coeff_div[coeff].Reg0x04);
regmap_write(es8389->regmap, ES8389_CLK_MUL_REG05, coeff_div[coeff].Reg0x05);
regmap_write(es8389->regmap, ES8389_CLK_MUX1_REG06, coeff_div[coeff].Reg0x06);
@ -548,10 +541,10 @@ static int es8389_set_bias_level(struct snd_soc_component *codec,
{
int ret;
struct es8389_private *es8389 = snd_soc_component_get_drvdata(codec);
printk("Enter into %s(), level = %d\n", __func__, level);
dev_dbg(codec->dev, "Enter into %s(), level = %d\n", __func__, level);
switch (level) {
case SND_SOC_BIAS_ON:
printk("%s on\n",__func__);
dev_dbg(codec->dev, "%s on\n",__func__);
ret = clk_prepare_enable(es8389->mclk);
if (ret)
return ret;
@ -565,10 +558,10 @@ static int es8389_set_bias_level(struct snd_soc_component *codec,
regmap_write(es8389->regmap, ES8389_DAC_RESET_REG4D, 0X00);
break;
case SND_SOC_BIAS_PREPARE:
printk("%s prepare\n",__func__);
dev_dbg(codec->dev, "%s prepare\n",__func__);
break;
case SND_SOC_BIAS_STANDBY:
printk("%s standby\n",__func__);
dev_dbg(codec->dev, "%s standby\n",__func__);
regmap_write(es8389->regmap, ES8389_CSM_JUMP_REG10, 0xD4);
usleep_range(70000,72000); //20MS
regmap_write(es8389->regmap, ES8389_ANA_CTL1_REG61, 0x59);
@ -577,22 +570,20 @@ static int es8389_set_bias_level(struct snd_soc_component *codec,
regmap_write(es8389->regmap, ES8389_RESET_REG00, 0x7E);
break;
case SND_SOC_BIAS_OFF:
printk("%s off\n",__func__);
dev_dbg(codec->dev, "%s off\n",__func__);
clk_disable_unprepare(es8389->mclk);
break;
}
return 0;
}
static int es8389_mute(struct snd_soc_dai *dai, int mute, int direction)
{
struct snd_soc_component *codec = dai->component;
struct es8389_private *es8389 = snd_soc_component_get_drvdata(codec);
printk("Enter into %s(), mute = %d\n", __func__, mute);
if(mute) {
dev_dbg(codec->dev, "Enter into %s(), mute = %d\n", __func__, mute);
if (mute) {
if (direction == SNDRV_PCM_STREAM_PLAYBACK) {
regmap_update_bits(es8389->regmap, ES8389_DAC_REG40,
0x03, 0x03);
@ -647,18 +638,18 @@ static struct snd_soc_dai_driver es8389_dai = {
.symmetric_rate = 1
};
static void es8389_state_delay_work(struct work_struct *work)
{
struct es8389_private *es8389 =
container_of(work, struct es8389_private, state_work.work);
struct snd_soc_component *codec = es8389->component;
unsigned int state;
mutex_lock(&es8389->lock);
regmap_read(es8389->regmap, ES8389_CSM_STATE1_REGF1, &state);
state &= 0x1F;
if (state == ES8389_STATE_STANDBY){
printk("Enter into %s()\n", __func__);
if (state == ES8389_STATE_STANDBY) {
dev_dbg(codec->dev, "Enter into %s()\n", __func__);
regmap_write(es8389->regmap, ES8389_HPSW_REG69, 0x23);
regmap_write(es8389->regmap, ES8389_ANA_CTL1_REG61, 0xF9);
regmap_write(es8389->regmap, ES8389_ADC_EN_REG64, 0x8F);
@ -674,7 +665,7 @@ static void es8389_state_delay_work(struct work_struct *work)
static int es8389_suspend(struct snd_soc_component *codec)
{
//struct es8389_private *es8389 = snd_soc_component_get_drvdata(codec);
printk("Enter into %s()\n", __func__);
dev_dbg(codec->dev, "Enter into %s()\n", __func__);
es8389_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
@ -684,7 +675,7 @@ static int es8389_suspend(struct snd_soc_component *codec)
static int es8389_resume(struct snd_soc_component *codec)
{
//struct es8389_private *es8389 = snd_soc_component_get_drvdata(codec);
printk("Enter into %s()\n", __func__);
dev_dbg(codec->dev, "Enter into %s()\n", __func__);
es8389_set_bias_level(codec, SND_SOC_BIAS_ON);
@ -695,10 +686,12 @@ static int es8389_probe(struct snd_soc_component *codec)
{
int ret = 0;
struct es8389_private *es8389 = snd_soc_component_get_drvdata(codec);
printk("Enter into %s()\n", __func__);
dev_dbg(codec->dev, "Enter into %s()\n", __func__);
es8389_codec = codec;
#if 1
es8389->component = codec;
#if 1
es8389->mclk = devm_clk_get(codec->dev, "mclk");
if (IS_ERR(es8389->mclk)) {
dev_err(codec->dev, "%s,unable to get mclk\n", __func__);
@ -776,7 +769,7 @@ static void es8389_remove(struct snd_soc_component *codec)
{
struct es8389_private *es8389 = snd_soc_component_get_drvdata(codec);
printk("Enter into %s()\n", __func__);
dev_dbg(codec->dev, "Enter into %s()\n", __func__);
regmap_write(es8389->regmap, ES8389_MASTER_MODE_REG01, 0x28);
regmap_write(es8389->regmap, ES8389_HPSW_REG69, 0x00);
regmap_write(es8389->regmap, ES8389_VMID_REG60, 0x00);
@ -846,7 +839,8 @@ static void es8389_i2c_shutdown(struct i2c_client *i2c)
regmap_write(es8389->regmap, ES8389_ISO_CTL_REGF3, 0xC1);
regmap_write(es8389->regmap, ES8389_PULL_DOWN_REGF2, 0x00);
}
static u32 cur_reg=0;
static u32 cur_reg = 0;
static ssize_t es8389_show(struct device *dev,
struct device_attribute *attr, char *_buf)
@ -919,11 +913,13 @@ static int es8389_read(struct i2c_client *client, u8 reg, u8 *value, int count)
pr_err("es8389_read error1 ret = %d.\n", ret);
return -1;
}
ret = i2c_master_recv(client, value, count);
if (ret != 1) {
pr_err("es8389_read error2, ret = %d.\n", ret);
return -1;
}
return 0;
}
@ -935,7 +931,7 @@ static int es8389_i2c_probe(struct i2c_client *i2c_client,
//unsigned int val;
u8 value[2];
printk("Enter into %s\n", __func__);
dev_dbg(&i2c_client->dev, "Enter into %s\n", __func__);
es8389 = devm_kzalloc(&i2c_client->dev,
sizeof(*es8389), GFP_KERNEL);
if (es8389 == NULL)
@ -975,14 +971,13 @@ static int es8389_i2c_probe(struct i2c_client *i2c_client,
return ret;
}
printk("Enter into %s-----4\n", __func__);
ret = sysfs_create_group(&i2c_client->dev.kobj,
&es8389_debug_attr_group);
if (ret) {
pr_err("failed to create attr group\n");
dev_err(&i2c_client->dev, "failed to create attr group\n");
}
printk("Exit %s\n", __func__);
dev_dbg(&i2c_client->dev, "Exit %s\n", __func__);
return ret;
}
@ -1015,4 +1010,3 @@ MODULE_DESCRIPTION("ASoC es8389 driver");
MODULE_AUTHOR("David Yang <yangxiaohua@everest-semi.com>");
MODULE_LICENSE("GPL");

Write Preview
Loading…
Cancel
Save