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rk35xx-android14
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[u-boot] f2813a7d7f: Merge tag 'android-14.0-ms-rkr2'

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Signed-off-by: hmz007 <hmz007@gmail.com>
master
hmz007 7 months ago
parent 6ed7f19e59
commit ea5b08db35
211 changed files with 34375 additions and 15431 deletions
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3
u-boot/arch/arm/Kconfig
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@ -98,6 +98,9 @@ config ARM_ERRATA_798870
config ARM_ERRATA_801819
bool
config ARM_ERRATA_814220
bool
config ARM_ERRATA_826974
bool

3
u-boot/arch/arm/cpu/armv7/cache_v7_asm.S
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@ -65,6 +65,9 @@ loop2:
skip:
add r10, r10, #2 @ increment cache number
cmp r3, r10
#ifdef CONFIG_ARM_ERRATA_814220
dsb
#endif
bgt flush_levels
finished:
mov r10, #0 @ swith back to cache level 0

3
u-boot/arch/arm/cpu/armv7/psci.S
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@ -226,6 +226,9 @@ loop2:
skip:
add r10, r10, #2 @ increment cache number
cmp r3, r10
#ifdef CONFIG_ARM_ERRATA_814220
dsb
#endif
bgt flush_levels
finished:
mov r10, #0 @ swith back to cache level 0

20
u-boot/arch/arm/dts/rk1808-u-boot.dtsi
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@ -148,23 +148,3 @@
u-boot,dm-pre-reloc;
status = "okay";
};
&usb_host0_ehci {
u-boot,dm-pre-reloc;
status = "okay";
};
&usb_host0_ohci {
u-boot,dm-pre-reloc;
status = "okay";
};
&usbdrd3 {
u-boot,dm-pre-reloc;
status = "okay";
};
&usbdrd_dwc3 {
u-boot,dm-pre-reloc;
status = "okay";
};

20
u-boot/arch/arm/dts/rk3568-u-boot.dtsi
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@ -73,26 +73,6 @@
status = "okay";
};
&usbdrd30 {
u-boot,dm-pre-reloc;
status = "okay";
};
&usbdrd_dwc3 {
u-boot,dm-pre-reloc;
status = "okay";
};
&usbhost30 {
u-boot,dm-pre-reloc;
status = "okay";
};
&usbhost_dwc3 {
u-boot,dm-pre-reloc;
status = "okay";
};
&usb2phy0 {
u-boot,dm-pre-reloc;
status = "okay";

9
u-boot/arch/arm/dts/rv1103b-u-boot.dtsi
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@ -127,12 +127,3 @@
status = "okay";
};
&usbdrd {
u-boot,dm-pre-reloc;
status = "okay";
};
&usbdrd_dwc3 {
u-boot,dm-pre-reloc;
status = "okay";
};

10
u-boot/arch/arm/dts/rv1106-u-boot.dtsi
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@ -202,13 +202,3 @@
u-boot,dm-pre-reloc;
status = "okay";
};
&usbdrd {
u-boot,dm-pre-reloc;
status = "okay";
};
&usbdrd_dwc3 {
u-boot,dm-pre-reloc;
status = "okay";
};

5
u-boot/arch/arm/dts/rv1106b-evb2.dts
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@ -33,6 +33,11 @@
};
};
&emmc {
bus-width = <4>;
mmc-hs200-1_8v;
};
/delete-node/ &gmac;
&pinctrl {

10
u-boot/arch/arm/dts/rv1126-u-boot.dtsi
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@ -184,16 +184,6 @@
status = "okay";
};
&usbdrd {
u-boot,dm-pre-reloc;
status = "okay";
};
&usbdrd_dwc3 {
u-boot,dm-pre-reloc;
status = "okay";
};
&pinctrl {
u-boot,dm-spl;
status = "okay";

30
u-boot/arch/arm/dts/rv1126b-evb.dts
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@ -0,0 +1,30 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright (c) 2025 Rockchip Electronics Co., Ltd.
*/
/dts-v1/;
#include "rv1126b.dtsi"
#include "rv1126b-u-boot.dtsi"
#include <dt-bindings/input/input.h>
/ {
model = "Rockchip RV1126B Evaluation board";
compatible = "rockchip,rv1126b-evb", "rockchip,rv1126b";
adc-keys {
compatible = "adc-keys";
io-channels = <&saradc0 0>;
io-channel-names = "buttons";
keyup-threshold-microvolt = <1800000>;
u-boot,dm-pre-reloc;
status = "okay";
volumeup-key {
u-boot,dm-pre-reloc;
linux,code = <KEY_VOLUMEUP>;
label = "volume up";
press-threshold-microvolt = <1750>;
};
};
};

2940
u-boot/arch/arm/dts/rv1126b-pinctrl.dtsi
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File diff suppressed because it is too large Load Diff

173
u-boot/arch/arm/dts/rv1126b-u-boot.dtsi
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@ -0,0 +1,173 @@
/*
* (C) Copyright 2025 Rockchip Electronics Co., Ltd
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <dt-bindings/gpio/gpio.h>
/ {
aliases {
mmc0 = &emmc;
mmc1 = &sdmmc0;
};
chosen {
stdout-path = &uart0;
u-boot,spl-boot-order = &sdmmc0, &spi_nand, &spi_nor, &emmc;
};
};
&gpio0 {
u-boot,dm-spl;
status = "okay";
};
&gpio1 {
u-boot,dm-pre-reloc;
status = "okay";
};
&gpio2 {
u-boot,dm-spl;
status = "okay";
};
&gpio3 {
u-boot,dm-pre-reloc;
status = "okay";
};
&gpio4 {
u-boot,dm-pre-reloc;
status = "okay";
};
&grf {
u-boot,dm-spl;
status = "okay";
};
&ioc_grf {
u-boot,dm-spl;
status = "okay";
};
&cru {
u-boot,dm-spl;
status = "okay";
};
&crypto {
u-boot,dm-spl;
status = "okay";
};
&psci {
u-boot,dm-pre-reloc;
status = "okay";
};
&uart0 {
u-boot,dm-spl;
status = "okay";
};
&hw_decompress {
u-boot,dm-spl;
status = "okay";
};
&rng {
u-boot,dm-pre-reloc;
status = "okay";
};
&fspi0 {
u-boot,dm-spl;
status = "okay";
#address-cells = <1>;
#size-cells = <0>;
spi_nand: flash@0 {
u-boot,dm-spl;
compatible = "spi-nand";
reg = <0>;
spi-tx-bus-width = <1>;
spi-rx-bus-width = <4>;
spi-max-frequency = <80000000>;
};
spi_nor: flash@1 {
u-boot,dm-spl;
compatible = "jedec,spi-nor";
label = "sfc_nor";
reg = <0>;
spi-tx-bus-width = <1>;
spi-rx-bus-width = <4>;
spi-max-frequency = <80000000>;
};
};
&saradc0 {
u-boot,dm-pre-reloc;
status = "okay";
};
&sdmmc0 {
bus-width = <4>;
pinctrl-names = "default";
pinctrl-0 = <&sdmmc0_bus4_pins &sdmmc0_cmd_pins &sdmmc0_clk_pins &sdmmc0_detn_pins>;
u-boot,dm-spl;
status = "okay";
};
&emmc {
bus-width = <8>;
mmc-hs200-1_8v;
u-boot,dm-spl;
status = "okay";
};
&sdmmc0_pins {
u-boot,dm-spl;
};
&sdmmc0_bus4_pins {
u-boot,dm-spl;
};
&sdmmc0_cmd_pins {
u-boot,dm-spl;
};
&sdmmc0_clk_pins {
u-boot,dm-spl;
};
&sdmmc0_detn_pins {
u-boot,dm-spl;
};
&pinctrl {
u-boot,dm-spl;
status = "okay";
};
&pcfg_pull_up {
u-boot,dm-spl;
};
&pcfg_pull_none {
u-boot,dm-spl;
};
&usb2phy {
u-boot,dm-pre-reloc;
status = "okay";
};
&usb2phy_otg {
u-boot,dm-pre-reloc;
status = "okay";
};

3313
u-boot/arch/arm/dts/rv1126b.dtsi
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387
u-boot/arch/arm/include/asm/arch-rockchip/cru_rv1126b.h
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@ -0,0 +1,387 @@
/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (c) 2025 Rockchip Electronics Co. Ltd.
* Author: Elaine Zhang <zhangqing@rock-chips.com>
*/
#ifndef _ASM_ARCH_CRU_RV1126B_H
#define _ASM_ARCH_CRU_RV1126B_H
#include <common.h>
#define MHz 1000000
#define KHz 1000
#define OSC_HZ (24 * MHz)
#define RC_OSC_HZ (125 * MHz)
#define GPLL_HZ (1188 * MHz)
#define AUPLL_HZ (983040000)
#define CPLL_HZ (1000 * MHz)
/* RV1126B pll id */
enum rv1126b_pll_id {
GPLL,
AUPLL,
CPLL,
PLL_COUNT,
};
struct rv1126b_clk_info {
unsigned long id;
char *name;
bool is_cru;
};
struct rv1126b_clk_priv {
struct rv1126b_cru *cru;
struct rv1126b_grf *grf;
ulong gpll_hz;
ulong aupll_hz;
ulong cpll_hz;
ulong armclk_hz;
ulong armclk_enter_hz;
ulong armclk_init_hz;
bool sync_kernel;
bool set_armclk_rate;
};
struct rv1126b_grf_clk_priv {
struct rv1126b_grf *grf;
};
struct rv1126b_pll {
unsigned int con0;
unsigned int con1;
unsigned int con2;
unsigned int con3;
unsigned int con4;
unsigned int reserved0[3];
};
struct rv1126b_cru {
struct rv1126b_pll pll[2];
unsigned int reserved0[176];
unsigned int clksel_con[71];
unsigned int reserved1[249];
unsigned int clkgate_con[16];
unsigned int reserved2[112];
unsigned int softrst_con[16];
unsigned int reserved3[112];
unsigned int glb_cnt_th;
unsigned int glb_rst_st;
unsigned int glb_srst_fst;
unsigned int glb_srst_snd;
unsigned int glb_rst_con[3];
unsigned int reserved4[41];
unsigned int clk_cm_frac0_div_h;
unsigned int clk_cm_frac1_div_h;
unsigned int clk_cm_frac2_div_h;
unsigned int clk_uart_frac0_div_h;
unsigned int clk_uart_frac1_div_h;
unsigned int clk_audio_frac0_div_h;
unsigned int clk_audio_frac1_div_h;
unsigned int reserved5[15753];
unsigned int bus_clksel_con[4];
unsigned int reserved6[316];
unsigned int bus_clkgate_con[7];
unsigned int reserved7[121];
unsigned int bus_softrst_con[8];
unsigned int reserved8[15928];
unsigned int peri_clksel_con[2];
unsigned int reserved9[318];
unsigned int peri_clkgate_con[2];
unsigned int reserved10[126];
unsigned int peri_softrst_con[2];
unsigned int reserved11[15934];
unsigned int core_clksel_con[3];
unsigned int reserved12[317];
unsigned int core_clkgate_con[2];
unsigned int reserved13[126];
unsigned int core_softrst_con[2];
unsigned int reserved14[15934];
unsigned int pmu_clksel_con[9];
unsigned int reserved15[311];
unsigned int pmu_clkgate_con[4];
unsigned int reserved16[124];
unsigned int pmu_softrst_con[4];
unsigned int reserved17[15932];
unsigned int pmu1_clksel_con[2];
unsigned int reserved18[318];
unsigned int pmu1_clkgate_con[2];
unsigned int reserved19[126];
unsigned int pmu1_softrst_con[2];
unsigned int reserved20[32318];
unsigned int vi_clksel_con[1];
unsigned int reserved21[319];
unsigned int vi_clkgate_con[5];
unsigned int reserved22[123];
unsigned int vi_softrst_con[4];
};
check_member(rv1126b_cru, clksel_con[0], 0x300);
check_member(rv1126b_cru, clkgate_con[0], 0x800);
check_member(rv1126b_cru, softrst_con[0], 0xa00);
check_member(rv1126b_cru, clk_cm_frac0_div_h, 0xcc0);
check_member(rv1126b_cru, bus_clksel_con[0], 0x10300);
check_member(rv1126b_cru, bus_clkgate_con[0], 0x10800);
check_member(rv1126b_cru, bus_softrst_con[0], 0x10a00);
check_member(rv1126b_cru, peri_clksel_con[0], 0x20300);
check_member(rv1126b_cru, peri_clkgate_con[0], 0x20800);
check_member(rv1126b_cru, peri_softrst_con[0], 0x20a00);
check_member(rv1126b_cru, core_clksel_con[0], 0x30300);
check_member(rv1126b_cru, core_clkgate_con[0], 0x30800);
check_member(rv1126b_cru, core_softrst_con[0], 0x30a00);
check_member(rv1126b_cru, pmu_clksel_con[0], 0x40300);
check_member(rv1126b_cru, pmu_clkgate_con[0], 0x40800);
check_member(rv1126b_cru, pmu_softrst_con[0], 0x40a00);
check_member(rv1126b_cru, pmu1_clksel_con[0], 0x50300);
check_member(rv1126b_cru, pmu1_clkgate_con[0], 0x50800);
check_member(rv1126b_cru, pmu1_softrst_con[0], 0x50a00);
check_member(rv1126b_cru, vi_clksel_con[0], 0x70300);
check_member(rv1126b_cru, vi_clkgate_con[0], 0x70800);
check_member(rv1126b_cru, vi_softrst_con[0], 0x70a00);
struct pll_rate_table {
unsigned long rate;
unsigned int fbdiv;
unsigned int postdiv1;
unsigned int refdiv;
unsigned int postdiv2;
unsigned int dsmpd;
unsigned int frac;
};
#define RV1126B_CRU_BASE 0x20000000
#define RV1126B_TOPCRU_BASE 0x0
#define RV1126B_BUSCRU_BASE 0x10000
#define RV1126B_PERICRU_BASE 0x20000
#define RV1126B_CORECRU_BASE 0x30000
#define RV1126B_PMUCRU_BASE 0x40000
#define RV1126B_PMU1CRU_BASE 0x50000
#define RV1126B_DDRCRU_BASE 0x60000
#define RV1126B_SUBDDRCRU_BASE 0x68000
#define RV1126B_VICRU_BASE 0x70000
#define RV1126B_VEPUCRU_BASE 0x80000
#define RV1126B_NPUCRU_BASE 0x90000
#define RV1126B_VDOCRU_BASE 0xA0000
#define RV1126B_VCPCRU_BASE 0xB0000
#define RV1126B_PLL_CON(x) ((x) * 0x4 + RV1126B_TOPCRU_BASE)
#define RV1126B_MODE_CON (0x280 + RV1126B_TOPCRU_BASE)
#define RV1126B_CLKSEL_CON(x) ((x) * 0x4 + 0x300 + RV1126B_TOPCRU_BASE)
#define RV1126B_PERIPLL_CON(x) ((x) * 0x4 + RV1126B_PERICRU_BASE)
#define RV1126B_SUBDDRPLL_CON(x) ((x) * 0x4 + RV1126B_SUBDDRCRU_BASE)
enum {
/* CRU_CLK_SEL10_CON */
CLK_AUDIO_FRAC1_SRC_SEL_SHIFT = 12,
CLK_AUDIO_FRAC1_SRC_SEL_MASK = 0x3 << CLK_AUDIO_FRAC1_SRC_SEL_SHIFT,
CLK_AUDIO_FRAC0_SRC_SEL_SHIFT = 10,
CLK_AUDIO_FRAC0_SRC_SEL_MASK = 0x3 << CLK_AUDIO_FRAC0_SRC_SEL_SHIFT,
CLK_UART_FRAC1_SRC_SEL_SHIFT = 8,
CLK_UART_FRAC1_SRC_SEL_MASK = 0x3 << CLK_UART_FRAC1_SRC_SEL_SHIFT,
CLK_UART_FRAC0_SRC_SEL_SHIFT = 6,
CLK_UART_FRAC0_SRC_SEL_MASK = 0x3 << CLK_UART_FRAC0_SRC_SEL_SHIFT,
CLK_CM_FRAC2_SRC_SEL_SHIFT = 4,
CLK_CM_FRAC2_SRC_SEL_MASK = 0x3 << CLK_CM_FRAC2_SRC_SEL_SHIFT,
CLK_CM_FRAC1_SRC_SEL_SHIFT = 2,
CLK_CM_FRAC1_SRC_SEL_MASK = 0x3 << CLK_CM_FRAC1_SRC_SEL_SHIFT,
CLK_CM_FRAC0_SRC_SEL_SHIFT = 0,
CLK_CM_FRAC0_SRC_SEL_MASK = 0x3 << CLK_CM_FRAC0_SRC_SEL_SHIFT,
CLK_FRAC_SRC_SEL_24M = 0,
CLK_FRAC_SRC_SEL_GPLL,
CLK_FRAC_SRC_SEL_AUPLL,
CLK_FRAC_SRC_SEL_CPLL,
/* CRU_CLK_SEL12_CON */
SCLK_UART1_SEL_SHIFT = 13,
SCLK_UART1_SEL_MASK = 0x7 << SCLK_UART1_SEL_SHIFT,
SCLK_UART1_DIV_SHIFT = 8,
SCLK_UART1_DIV_MASK = 0x1f << SCLK_UART1_DIV_SHIFT,
SCLK_UART0_SRC_SEL_SHIFT = 5,
SCLK_UART0_SRC_SEL_MASK = 0x7 << SCLK_UART0_SRC_SEL_SHIFT,
SCLK_UART_SEL_OSC = 0,
SCLK_UART_SEL_CM_FRAC0,
SCLK_UART_SEL_CM_FRAC1,
SCLK_UART_SEL_CM_FRAC2,
SCLK_UART_SEL_UART_FRAC0,
SCLK_UART_SEL_UART_FRAC1,
SCLK_UART0_SRC_DIV_SHIFT = 0,
SCLK_UART0_SRC_DIV_MASK = 0x1f << SCLK_UART0_SRC_DIV_SHIFT,
/* CRU_CLK_SEL13_CON */
SCLK_UART3_SEL_SHIFT = 13,
SCLK_UART3_SEL_MASK = 0x7 << SCLK_UART3_SEL_SHIFT,
SCLK_UART3_DIV_SHIFT = 8,
SCLK_UART3_DIV_MASK = 0x1f << SCLK_UART3_DIV_SHIFT,
SCLK_UART2_SEL_SHIFT = 5,
SCLK_UART2_SEL_MASK = 0x7 << SCLK_UART2_SEL_SHIFT,
SCLK_UART2_DIV_SHIFT = 0,
SCLK_UART2_DIV_MASK = 0x1f << SCLK_UART2_DIV_SHIFT,
/* CRU_CLK_SEL14_CON */
SCLK_UART5_SEL_SHIFT = 13,
SCLK_UART5_SEL_MASK = 0x7 << SCLK_UART5_SEL_SHIFT,
SCLK_UART5_DIV_SHIFT = 8,
SCLK_UART5_DIV_MASK = 0x1f << SCLK_UART5_DIV_SHIFT,
SCLK_UART4_SEL_SHIFT = 5,
SCLK_UART4_SEL_MASK = 0x7 << SCLK_UART4_SEL_SHIFT,
SCLK_UART4_DIV_SHIFT = 0,
SCLK_UART4_DIV_MASK = 0x1f << SCLK_UART4_DIV_SHIFT,
/* CRU_CLK_SEL15_CON */
SCLK_UART7_SEL_SHIFT = 13,
SCLK_UART7_SEL_MASK = 0x7 << SCLK_UART7_SEL_SHIFT,
SCLK_UART7_DIV_SHIFT = 8,
SCLK_UART7_DIV_MASK = 0x1f << SCLK_UART7_DIV_SHIFT,
SCLK_UART6_SEL_SHIFT = 5,
SCLK_UART6_SEL_MASK = 0x7 << SCLK_UART6_SEL_SHIFT,
SCLK_UART6_DIV_SHIFT = 0,
SCLK_UART6_DIV_MASK = 0x1f << SCLK_UART6_DIV_SHIFT,
/* CRU_CLK_SEL25_CON */
CLK_FRAC_NUMERATOR_SHIFT = 16,
CLK_FRAC_NUMERATOR_MASK = 0xffff << 16,
CLK_FRAC_DENOMINATOR_SHIFT = 0,
CLK_FRAC_DENOMINATOR_MASK = 0xffff,
CLK_FRAC_H_NUMERATOR_SHIFT = 8,
CLK_FRAC_H_NUMERATOR_MASK = 0xff << 8,
CLK_FRAC_H_DENOMINATOR_SHIFT = 0,
CLK_FRAC_H_DENOMINATOR_MASK = 0xff,
/* CRU_CLK_SEL43_CON */
DCLK_VOP_SEL_SHIFT = 8,
DCLK_VOP_SEL_MASK = 0x1 << DCLK_VOP_SEL_SHIFT,
DCLK_VOP_SEL_GPLL = 0,
DCLK_VOP_SEL_CPLL,
DCLK_VOP_DIV_SHIFT = 0,
DCLK_VOP_DIV_MASK = 0xff << DCLK_VOP_DIV_SHIFT,
/* CRU_CLK_SEL44_CON */
HCLK_BUS_SEL_SHIFT = 10,
HCLK_BUS_SEL_MASK = 0x1 << HCLK_BUS_SEL_SHIFT,
HCLK_BUS_SEL_200M = 0,
HCLK_BUS_SEL_100M,
ACLK_BUS_SEL_SHIFT = 8,
ACLK_BUS_SEL_MASK = 0x3 << ACLK_BUS_SEL_SHIFT,
ACLK_BUS_SEL_400M = 0,
ACLK_BUS_SEL_300M,
ACLK_BUS_SEL_200M,
ACLK_TOP_SEL_SHIFT = 6,
ACLK_TOP_SEL_MASK = 0x3 << ACLK_TOP_SEL_SHIFT,
ACLK_TOP_SEL_600M = 0,
ACLK_TOP_SEL_400M,
ACLK_TOP_SEL_200M,
/* CRU_CLK_SEL45_CON */
CLK_SDMMC_SEL_SHIFT = 8,
CLK_SDMMC_SEL_MASK = 0x3 << CLK_SDMMC_SEL_SHIFT,
CLK_SDMMC_SEL_GPLL = 0,
CLK_SDMMC_SEL_CPLL,
CLK_SDMMC_SEL_24M,
CLK_SDMMC_DIV_SHIFT = 0,
CLK_SDMMC_DIV_MASK = 0xff << CLK_SDMMC_DIV_SHIFT,
/* CRU_CLK_SEL46_CON */
TCLK_WDT_HPMCU_SEL_SHIFT = 14,
TCLK_WDT_HPMCU_SEL_MASK = 0x1 << TCLK_WDT_HPMCU_SEL_SHIFT,
TCLK_WDT_S_SEL_SHIFT = 13,
TCLK_WDT_S_SEL_MASK = 0x1 << TCLK_WDT_S_SEL_SHIFT,
TCLK_WDT_NS_SEL_SHIFT = 12,
TCLK_WDT_NS_SEL_MASK = 0x1 << TCLK_WDT_NS_SEL_SHIFT,
TCLK_WDT_SEL_100M = 0,
TCLK_WDT_SEL_OSC,
/* CRU_CLK_SEL47_CON */
ACLK_PERI_SEL_SHIFT = 13,
ACLK_PERI_SEL_MASK = 0x1 << ACLK_PERI_SEL_SHIFT,
ACLK_PERI_SEL_200M = 0,
ACLK_PERI_SEL_24M,
PCLK_PERI_SEL_SHIFT = 12,
PCLK_PERI_SEL_MASK = 0x1 << PCLK_PERI_SEL_SHIFT,
PCLK_PERI_SEL_100M = 0,
PCLK_PERI_SEL_24M,
/* CRU_CLK_SEL50_CON */
ACLK_RKCE_SEL_SHIFT = 13,
ACLK_RKCE_SEL_MASK = 0x1 << ACLK_RKCE_SEL_SHIFT,
ACLK_RKCE_SEL_200M = 0,
ACLK_RKCE_SEL_24M,
CLK_PKA_RKCE_SEL_SHIFT = 12,
CLK_PKA_RKCE_SEL_MASK = 0x1 << CLK_PKA_RKCE_SEL_SHIFT,
CLK_PKA_RKCE_SEL_300M = 0,
CLK_PKA_RKCE_SEL_200M,
CLK_PWM3_SEL_SHIFT = 11,
CLK_PWM3_SEL_MASK = 0x1 << CLK_PWM3_SEL_SHIFT,
CLK_PWM2_SEL_SHIFT = 10,
CLK_PWM2_SEL_MASK = 0x1 << CLK_PWM2_SEL_SHIFT,
CLK_PWM0_SEL_SHIFT = 8,
CLK_PWM0_SEL_MASK = 0x1 << CLK_PWM0_SEL_SHIFT,
CLK_PWM_SEL_100M = 0,
CLK_PWM_SEL_24M,
CLK_SPI1_SEL_SHIFT = 4,
CLK_SPI1_SEL_MASK = 0x3 << CLK_SPI1_SEL_SHIFT,
CLK_SPI0_SEL_SHIFT = 2,
CLK_SPI0_SEL_MASK = 0x3 << CLK_SPI0_SEL_SHIFT,
CLK_SPI0_SEL_200M = 0,
CLK_SPI0_SEL_100M,
CLK_SPI0_SEL_50M,
CLK_SPI0_SEL_24M,
CLK_I2C_SEL_SHIFT = 1,
CLK_I2C_SEL_MASK = 0x1 << CLK_I2C_SEL_SHIFT,
CLK_I2C_SEL_200M = 0,
CLK_I2C_SEL_24M,
/* CRU_CLK_SEL63_CON */
CLK_SARADC2_SEL_SHIFT = 14,
CLK_SARADC2_SEL_MASK = 0x1 << CLK_SARADC2_SEL_SHIFT,
CLK_SARADC1_SEL_SHIFT = 13,
CLK_SARADC1_SEL_MASK = 0x1 << CLK_SARADC1_SEL_SHIFT,
CLK_SARADC0_SEL_SHIFT = 12,
CLK_SARADC0_SEL_MASK = 0x1 << CLK_SARADC0_SEL_SHIFT,
CLK_SARADC_SEL_200M = 0,
CLK_SARADC_SEL_24M,
CLK_SARADC2_DIV_SHIFT = 8,
CLK_SARADC2_DIV_MASK = 0x7 << CLK_SARADC2_DIV_SHIFT,
CLK_SARADC1_DIV_SHIFT = 4,
CLK_SARADC1_DIV_MASK = 0x7 << CLK_SARADC1_DIV_SHIFT,
CLK_SARADC0_DIV_SHIFT = 0,
CLK_SARADC0_DIV_MASK = 0x7 << CLK_SARADC0_DIV_SHIFT,
/* PMUCRU_CLK_SEL2_CON */
CLK_I2C2_SEL_SHIFT = 14,
CLK_I2C2_SEL_MASK = 0x3 << CLK_I2C2_SEL_SHIFT,
CLK_I2C2_SEL_24M = 0,
CLK_I2C2_SEL_RCOSC,
CLK_I2C2_SEL_100M,
CLK_PWM1_SEL_SHIFT = 8,
CLK_PWM1_SEL_MASK = 0x3 << CLK_PWM1_SEL_SHIFT,
CLK_PWM1_SEL_24M = 0,
CLK_PWM1_SEL_RCOSC,
CLK_PWM1_SEL_100M,
CLK_PWM1_DIV_SHIFT = 6,
CLK_PWM1_DIV_MASK = 0x3 << CLK_PWM1_DIV_SHIFT,
/* PMUCRU_CLK_SEL3_CON */
TCLK_WDT_LPMCU_SEL_SHIFT = 6,
TCLK_WDT_LPMCU_SEL_MASK = 0x3 << TCLK_WDT_LPMCU_SEL_SHIFT,
TCLK_WDT_LPMCU_SEL_OSC = 0,
TCLK_WDT_LPMCU_SEL_RCOSC,
TCLK_WDT_LPMCU_SEL_100M,
TCLK_WDT_LPMCU_SEL_32K,
SCLK_UART0_SEL_SHIFT = 0,
SCLK_UART0_SEL_MASK = 0x3 << SCLK_UART0_SEL_SHIFT,
SCLK_UART0_SEL_UART0_SRC = 0,
SCLK_UART0_SEL_OSC,
SCLK_UART0_SEL_RCOSC,
/* PMU1CRU_CLK_SEL0_CON */
SCLK_1X_FSPI1_DIV_SHIFT = 2,
SCLK_1X_FSPI1_DIV_MASK = 0x7 << SCLK_1X_FSPI1_DIV_SHIFT,
SCLK_1X_FSPI1_SEL_SHIFT = 0,
SCLK_1X_FSPI1_SEL_MASK = 0x3 << SCLK_1X_FSPI1_SEL_SHIFT,
SCLK_1X_FSPI1_SEL_24M = 0,
SCLK_1X_FSPI1_SEL_RCOSC,
SCLK_1X_FSPI1_SEL_100M,
};
#endif

6
u-boot/arch/arm/include/asm/arch-rockchip/grf_rk3399.h
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@ -439,18 +439,18 @@ enum {
/* GRF_GPIO4C_IOMUX */
GRF_GPIO4C0_SEL_SHIFT = 0,
GRF_GPIO4C0_SEL_MASK = 3 << GRF_GPIO4C0_SEL_SHIFT,
GRF_UART2DGBB_SIN = 2,
GRF_UART2DBGB_SIN = 2,
GRF_HDMII2C_SCL = 3,
GRF_GPIO4C1_SEL_SHIFT = 2,
GRF_GPIO4C1_SEL_MASK = 3 << GRF_GPIO4C1_SEL_SHIFT,
GRF_UART2DGBB_SOUT = 2,
GRF_UART2DBGB_SOUT = 2,
GRF_HDMII2C_SDA = 3,
GRF_GPIO4C2_SEL_SHIFT = 4,
GRF_GPIO4C2_SEL_MASK = 3 << GRF_GPIO4C2_SEL_SHIFT,
GRF_PWM_0 = 1,
GRF_GPIO4C3_SEL_SHIFT = 6,
GRF_GPIO4C3_SEL_MASK = 3 << GRF_GPIO4C3_SEL_SHIFT,
GRF_UART2DGBC_SIN = 1,
GRF_UART2DBGC_SIN = 1,
GRF_GPIO4C4_SEL_SHIFT = 8,
GRF_GPIO4C4_SEL_MASK = 3 << GRF_GPIO4C4_SEL_SHIFT,
GRF_UART2DBGC_SOUT = 1,

327
u-boot/arch/arm/include/asm/arch-rockchip/grf_rv1126b.h
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@ -0,0 +1,327 @@
/*
* (C) Copyright 2025 Rockchip Electronics Co., Ltd.
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef _ASM_ARCH_GRF_RV1126B_H
#define _ASM_ARCH_GRF_RV1126B_H
#include <common.h>
/* cpu_grf register structure define */
struct rv1126b_cpu_grf_reg {
uint32_t con0; /* address offset: 0x0000 */
uint32_t con1; /* address offset: 0x0004 */
uint32_t mem_cfg_uhdspra; /* address offset: 0x0008 */
uint32_t status0; /* address offset: 0x000c */
uint32_t status1; /* address offset: 0x0010 */
};
check_member(rv1126b_cpu_grf_reg, status1, 0x0010);
/* ddr_grf register structure define */
struct rv1126b_ddr_grf_reg {
uint32_t con0; /* address offset: 0x0000 */
uint32_t con1; /* address offset: 0x0004 */
uint32_t reserved0008[2]; /* address offset: 0x0008 */
uint32_t con4; /* address offset: 0x0010 */
uint32_t reserved0014[7]; /* address offset: 0x0014 */
uint32_t con12; /* address offset: 0x0030 */
uint32_t con13; /* address offset: 0x0034 */
uint32_t con14; /* address offset: 0x0038 */
uint32_t con15; /* address offset: 0x003c */
uint32_t con16; /* address offset: 0x0040 */
uint32_t con17; /* address offset: 0x0044 */
uint32_t con18; /* address offset: 0x0048 */
uint32_t reserved004c; /* address offset: 0x004c */
uint32_t con20; /* address offset: 0x0050 */
uint32_t con21; /* address offset: 0x0054 */
uint32_t con22; /* address offset: 0x0058 */
uint32_t con23; /* address offset: 0x005c */
uint32_t reserved0060[8]; /* address offset: 0x0060 */
uint32_t probe_ctrl; /* address offset: 0x0080 */
uint32_t reserved0084[31]; /* address offset: 0x0084 */
uint32_t status0; /* address offset: 0x0100 */
uint32_t status1; /* address offset: 0x0104 */
uint32_t status2; /* address offset: 0x0108 */
uint32_t status3; /* address offset: 0x010c */
uint32_t status4; /* address offset: 0x0110 */
uint32_t status5; /* address offset: 0x0114 */
uint32_t status6; /* address offset: 0x0118 */
uint32_t status7; /* address offset: 0x011c */
uint32_t status8; /* address offset: 0x0120 */
uint32_t status9; /* address offset: 0x0124 */
uint32_t status10; /* address offset: 0x0128 */
uint32_t status11; /* address offset: 0x012c */
uint32_t status12; /* address offset: 0x0130 */
uint32_t status13; /* address offset: 0x0134 */
uint32_t status14; /* address offset: 0x0138 */
uint32_t status15; /* address offset: 0x013c */
uint32_t status16; /* address offset: 0x0140 */
uint32_t status17; /* address offset: 0x0144 */
uint32_t reserved0148; /* address offset: 0x0148 */
uint32_t status19; /* address offset: 0x014c */
uint32_t reserved0150[10]; /* address offset: 0x0150 */
uint32_t status30; /* address offset: 0x0178 */
};
check_member(rv1126b_ddr_grf_reg, status30, 0x0178);
/* pmu_grf register structure define */
struct rv1126b_pmu_grf_reg {
uint32_t soc_con0; /* address offset: 0x0000 */
uint32_t soc_con1; /* address offset: 0x0004 */
uint32_t soc_con2; /* address offset: 0x0008 */
uint32_t soc_con3; /* address offset: 0x000c */
uint32_t soc_con4; /* address offset: 0x0010 */
uint32_t soc_con5; /* address offset: 0x0014 */
uint32_t soc_con6; /* address offset: 0x0018 */
uint32_t soc_con7; /* address offset: 0x001c */
uint32_t soc_con8; /* address offset: 0x0020 */
uint32_t soc_con9; /* address offset: 0x0024 */
uint32_t soc_con10; /* address offset: 0x0028 */
uint32_t soc_con11; /* address offset: 0x002c */
uint32_t soc_con12; /* address offset: 0x0030 */
uint32_t soc_con13; /* address offset: 0x0034 */
uint32_t soc_con14; /* address offset: 0x0038 */
uint32_t soc_con15; /* address offset: 0x003c */
uint32_t reserved0040[16]; /* address offset: 0x0040 */
uint32_t aad_con0; /* address offset: 0x0080 */
uint32_t reserved0084[47]; /* address offset: 0x0084 */
uint32_t men_con0; /* address offset: 0x0140 */
uint32_t men_con1; /* address offset: 0x0144 */
uint32_t men_con2; /* address offset: 0x0148 */
uint32_t reserved014c; /* address offset: 0x014c */
uint32_t soc_special0; /* address offset: 0x0150 */
uint32_t reserved0154[3]; /* address offset: 0x0154 */
uint32_t soc_aov_int_con; /* address offset: 0x0160 */
uint32_t reserved0164[3]; /* address offset: 0x0164 */
uint32_t soc_status0; /* address offset: 0x0170 */
uint32_t soc_status1; /* address offset: 0x0174 */
uint32_t soc_status2; /* address offset: 0x0178 */
uint32_t reserved017c[33]; /* address offset: 0x017c */
uint32_t os_reg0; /* address offset: 0x0200 */
uint32_t os_reg1; /* address offset: 0x0204 */
uint32_t os_reg2; /* address offset: 0x0208 */
uint32_t os_reg3; /* address offset: 0x020c */
uint32_t os_reg4; /* address offset: 0x0210 */
uint32_t os_reg5; /* address offset: 0x0214 */
uint32_t os_reg6; /* address offset: 0x0218 */
uint32_t os_reg7; /* address offset: 0x021c */
uint32_t os_reg8; /* address offset: 0x0220 */
uint32_t os_reg9; /* address offset: 0x0224 */
uint32_t os_reg10; /* address offset: 0x0228 */
uint32_t os_reg11; /* address offset: 0x022c */
uint32_t reset_function_status; /* address offset: 0x0230 */
uint32_t reset_function_clr; /* address offset: 0x0234 */
uint32_t reserved0238[82]; /* address offset: 0x0238 */
uint32_t sig_detect_con; /* address offset: 0x0380 */
uint32_t reserved0384[3]; /* address offset: 0x0384 */
uint32_t sig_detect_status; /* address offset: 0x0390 */
uint32_t reserved0394[3]; /* address offset: 0x0394 */
uint32_t sig_detect_status_clear; /* address offset: 0x03a0 */
uint32_t reserved03a4[3]; /* address offset: 0x03a4 */
uint32_t sdmmc_det_counter; /* address offset: 0x03b0 */
};
check_member(rv1126b_pmu_grf_reg, sdmmc_det_counter, 0x03b0);
/* npu_grf register structure define */
struct rv1126b_npu_grf_reg {
uint32_t mem_grf_spra; /* address offset: 0x0000 */
uint32_t mem_grf_dpra; /* address offset: 0x0004 */
uint32_t npu_grf_cbuf_mem_soft_gate; /* address offset: 0x0008 */
uint32_t npu_grf_cfg_nsp_slv_addr; /* address offset: 0x000c */
uint32_t npu_grf_nsp_mem_soft_gate; /* address offset: 0x0010 */
uint32_t npu_grf_cfg_use_nsp; /* address offset: 0x0014 */
uint32_t npu_grf_shape; /* address offset: 0x0018 */
};
check_member(rv1126b_npu_grf_reg, npu_grf_shape, 0x0018);
/* peri_grf register structure define */
struct rv1126b_peri_grf_reg {
uint32_t mem_grf_spra; /* address offset: 0x0000 */
uint32_t mem_grf_dpra; /* address offset: 0x0004 */
uint32_t reserved0008; /* address offset: 0x0008 */
uint32_t usb3_grf_con_pending; /* address offset: 0x000c */
uint32_t reserved0010; /* address offset: 0x0010 */
uint32_t mem_gate_grf_con; /* address offset: 0x0014 */
uint32_t hprot_grf_con; /* address offset: 0x0018 */
uint32_t usbhostphy_con0; /* address offset: 0x001c */
uint32_t usbotgphy_con0; /* address offset: 0x0020 */
uint32_t usbotgphy_con1; /* address offset: 0x0024 */
uint32_t usbotgphy_con2; /* address offset: 0x0028 */
uint32_t usbotgphy_con3; /* address offset: 0x002c */
uint32_t host0_con0; /* address offset: 0x0030 */
uint32_t host0_con1; /* address offset: 0x0034 */
uint32_t usb3otg0_con0; /* address offset: 0x0038 */
uint32_t usb3otg0_con1; /* address offset: 0x003c */
uint32_t reserved0040[13]; /* address offset: 0x0040 */
uint32_t otgphy_int_en; /* address offset: 0x0074 */
uint32_t otgphy_int_st; /* address offset: 0x0078 */
uint32_t otgphy_int_st_clr; /* address offset: 0x007c */
uint32_t otgphy_ls_con; /* address offset: 0x0080 */
uint32_t otgphy_dis_con; /* address offset: 0x0084 */
uint32_t otgphy_bvalid_con; /* address offset: 0x0088 */
uint32_t otgphy_id_con; /* address offset: 0x008c */
uint32_t hostphy_int_en; /* address offset: 0x0090 */
uint32_t hostphy_int_st; /* address offset: 0x0094 */
uint32_t hostphy_int_st_clr; /* address offset: 0x0098 */
uint32_t hostphy_ls_con; /* address offset: 0x009c */
uint32_t hostphy_dis_con; /* address offset: 0x00a0 */
uint32_t hostphy_bvalid_con; /* address offset: 0x00a4 */
uint32_t hostphy_id_con; /* address offset: 0x00a8 */
uint32_t reserved00ac[21]; /* address offset: 0x00ac */
uint32_t usb3otg0_status; /* address offset: 0x0100 */
uint32_t usb3otg0_status_cb; /* address offset: 0x0104 */
uint32_t usb3otg0_status_lat0; /* address offset: 0x0108 */
uint32_t usb3otg0_status_lat1; /* address offset: 0x010c */
uint32_t usbphy_st; /* address offset: 0x0110 */
uint32_t host0_st; /* address offset: 0x0114 */
uint32_t usb3_host_utmi_st; /* address offset: 0x0118 */
uint32_t rtc_grf_st; /* address offset: 0x011c */
};
check_member(rv1126b_peri_grf_reg, rtc_grf_st, 0x011c);
/* usb3_phy_grf register structure define */
struct rv1126b_usb3_phy_grf_reg {
uint32_t pipe_con0; /* address offset: 0x0000 */
uint32_t pipe_con1; /* address offset: 0x0004 */
uint32_t pipe_con2; /* address offset: 0x0008 */
uint32_t pipe_con3; /* address offset: 0x000c */
uint32_t pipe_con4; /* address offset: 0x0010 */
uint32_t reserved0014[8]; /* address offset: 0x0014 */
uint32_t pipe_status1; /* address offset: 0x0034 */
uint32_t reserved0038[18]; /* address offset: 0x0038 */
uint32_t lfps_det_con; /* address offset: 0x0080 */
uint32_t reserved0084[7]; /* address offset: 0x0084 */
uint32_t phy_int_en; /* address offset: 0x00a0 */
uint32_t phy_int_status; /* address offset: 0x00a4 */
};
check_member(rv1126b_usb3_phy_grf_reg, phy_int_status, 0x00a4);
/* sys_grf register structure define */
struct rv1126b_sys_grf_reg {
uint32_t mem_grf_spra; /* address offset: 0x0000 */
uint32_t mem_grf_dpra; /* address offset: 0x0004 */
uint32_t mem_grf_rom; /* address offset: 0x0008 */
uint32_t bus_grf_misc; /* address offset: 0x000c */
uint32_t mem_con_gate; /* address offset: 0x0010 */
uint32_t bus_grf_hprot_stall; /* address offset: 0x0014 */
uint32_t hpmcu_cache_misc; /* address offset: 0x0018 */
uint32_t hpmcu_cache_addr_start; /* address offset: 0x001c */
uint32_t hpmcu_cache_addr_end; /* address offset: 0x0020 */
uint32_t hpmcu_code_addr_start; /* address offset: 0x0024 */
uint32_t hpmcu_sram_addr_start; /* address offset: 0x0028 */
uint32_t hpmcu_exsram_addr_start; /* address offset: 0x002c */
uint32_t biu_con0; /* address offset: 0x0030 */
uint32_t biu_con1; /* address offset: 0x0034 */
uint32_t uart_grf_rts_cts; /* address offset: 0x0038 */
uint32_t uart_grf_dma_bypass; /* address offset: 0x003c */
uint32_t audio_con0; /* address offset: 0x0040 */
uint32_t reserved0044; /* address offset: 0x0044 */
uint32_t audio_con2; /* address offset: 0x0048 */
uint32_t otp_con; /* address offset: 0x004c */
uint32_t tsadc_grf_con0; /* address offset: 0x0050 */
uint32_t tsadc_grf_con1; /* address offset: 0x0054 */
uint32_t tsadc_grf_con2; /* address offset: 0x0058 */
uint32_t tsadc_grf_con3; /* address offset: 0x005c */
uint32_t tsadc_grf_con4; /* address offset: 0x0060 */
uint32_t tsadc_grf_con5; /* address offset: 0x0064 */
uint32_t tsadc_grf_con6; /* address offset: 0x0068 */
uint32_t reserved006c[37]; /* address offset: 0x006c */
uint32_t biu_status0; /* address offset: 0x0100 */
uint32_t biu_status1; /* address offset: 0x0104 */
uint32_t biu_status2; /* address offset: 0x0108 */
uint32_t hpmcu_cache_status; /* address offset: 0x010c */
uint32_t tsadc_grf_status0; /* address offset: 0x0110 */
uint32_t tsadc_grf_status1; /* address offset: 0x0114 */
uint32_t sys_status; /* address offset: 0x0118 */
uint32_t reserved011c[441]; /* address offset: 0x011c */
uint32_t chip_id; /* address offset: 0x0800 */
uint32_t chip_version; /* address offset: 0x0804 */
};
check_member(rv1126b_sys_grf_reg, chip_version, 0x0804);
/* vcp_grf register structure define */
struct rv1126b_vcp_grf_reg {
uint32_t mem_grf_spra; /* address offset: 0x0000 */
uint32_t mem_grf_dpra; /* address offset: 0x0004 */
uint32_t vcp_grf_aisp_mem_con; /* address offset: 0x0008 */
};
check_member(rv1126b_vcp_grf_reg, vcp_grf_aisp_mem_con, 0x0008);
/* vdo_grf register structure define */
struct rv1126b_vdo_grf_reg {
uint32_t mem_grf_spra; /* address offset: 0x0000 */
uint32_t mem_grf_dpra; /* address offset: 0x0004 */
uint32_t mem_gate_grf_con; /* address offset: 0x0008 */
uint32_t dsi_grf_con; /* address offset: 0x000c */
uint32_t dsiphy_grf_con; /* address offset: 0x0010 */
uint32_t rkmmu_grf_con; /* address offset: 0x0014 */
uint32_t reserved0018[14]; /* address offset: 0x0018 */
uint32_t vdo_grf_status0; /* address offset: 0x0050 */
uint32_t vdo_grf_status1; /* address offset: 0x0054 */
};
check_member(rv1126b_vdo_grf_reg, vdo_grf_status1, 0x0054);
/* vepu_grf register structure define */
struct rv1126b_vepu_grf_reg {
uint32_t mem_grf_spra; /* address offset: 0x0000 */
uint32_t mem_grf_dpra; /* address offset: 0x0004 */
uint32_t vepu_grf_con0; /* address offset: 0x0008 */
uint32_t saradc0_grf_con0; /* address offset: 0x000c */
uint32_t saradc0_grf_con1; /* address offset: 0x0010 */
uint32_t saradc0_grf_con2; /* address offset: 0x0014 */
uint32_t reserved0018[3]; /* address offset: 0x0018 */
uint32_t sdmmc1_det_cnt; /* address offset: 0x0024 */
uint32_t sdmmc1_sig_detect_con; /* address offset: 0x0028 */
uint32_t sdmmc1_sig_detect_status; /* address offset: 0x002c */
uint32_t sdmmc1_status_clr; /* address offset: 0x0030 */
};
check_member(rv1126b_vepu_grf_reg, sdmmc1_status_clr, 0x0030);
/* vi_grf register structure define */
struct rv1126b_vi_grf_reg {
uint32_t mem_con_spra; /* address offset: 0x0000 */
uint32_t mem_con_dpra; /* address offset: 0x0004 */
uint32_t vi_grf_status; /* address offset: 0x0008 */
uint32_t reserved000c; /* address offset: 0x000c */
uint32_t csiphy0_grf_con; /* address offset: 0x0010 */
uint32_t csiphy1_grf_con; /* address offset: 0x0014 */
uint32_t csiphy0_grf_status; /* address offset: 0x0018 */
uint32_t csiphy1_grf_status; /* address offset: 0x001c */
uint32_t misc_grf_con; /* address offset: 0x0020 */
uint32_t reserved0024[11]; /* address offset: 0x0024 */
uint32_t gmac_grf_con0; /* address offset: 0x0050 */
uint32_t gmac_dma_ack; /* address offset: 0x0054 */
uint32_t reserved0058[2]; /* address offset: 0x0058 */
uint32_t gmac_grf_status0; /* address offset: 0x0060 */
uint32_t gmac_grf_status1; /* address offset: 0x0064 */
uint32_t gmac_grf_status2; /* address offset: 0x0068 */
uint32_t reserved006c[5]; /* address offset: 0x006c */
uint32_t saradc1_grf_con0; /* address offset: 0x0080 */
uint32_t saradc1_grf_con1; /* address offset: 0x0084 */
uint32_t saradc1_grf_con2; /* address offset: 0x0088 */
uint32_t reserved008c; /* address offset: 0x008c */
uint32_t saradc2_grf_con0; /* address offset: 0x0090 */
uint32_t saradc2_grf_con1; /* address offset: 0x0094 */
uint32_t saradc2_grf_con2; /* address offset: 0x0098 */
uint32_t reserved009c[6]; /* address offset: 0x009c */
uint32_t rkmacphy_grf_con0; /* address offset: 0x00b4 */
uint32_t rkmacphy_grf_con1; /* address offset: 0x00b8 */
uint32_t rkmacphy_grf_con2; /* address offset: 0x00bc */
uint32_t rkmacphy_grf_status; /* address offset: 0x00c0 */
uint32_t rkmacphy_calib_con; /* address offset: 0x00c4 */
};
check_member(rv1126b_vi_grf_reg, rkmacphy_calib_con, 0x00c4);
#endif /* _ASM_ARCH_GRF_RV1126B_H */

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u-boot/arch/arm/include/asm/arch-rockchip/ioc_rv1126b.h
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/*
* (C) Copyright 2025 Rockchip Electronics Co., Ltd.
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef _ASM_ARCH_IOC_RV1126B_H
#define _ASM_ARCH_IOC_RV1126B_H
#include <common.h>
/* pmuio0_ioc register structure define */
struct rv1126b_pmuio0_ioc_reg {
uint32_t gpio0a_iomux_sel_0; /* address offset: 0x0000 */
uint32_t gpio0a_iomux_sel_1; /* address offset: 0x0004 */
uint32_t gpio0b_iomux_sel_0; /* address offset: 0x0008 */
uint32_t gpio0b_iomux_sel_1; /* address offset: 0x000c */
uint32_t reserved0010[60]; /* address offset: 0x0010 */
uint32_t gpio0a_ds_0; /* address offset: 0x0100 */
uint32_t gpio0a_ds_1; /* address offset: 0x0104 */
uint32_t gpio0a_ds_2; /* address offset: 0x0108 */
uint32_t gpio0a_ds_3; /* address offset: 0x010c */
uint32_t gpio0b_ds_0; /* address offset: 0x0110 */
uint32_t gpio0b_ds_1; /* address offset: 0x0114 */
uint32_t gpio0b_ds_2; /* address offset: 0x0118 */
uint32_t reserved011c[121]; /* address offset: 0x011c */
uint32_t gpio0a_pull; /* address offset: 0x0300 */
uint32_t gpio0b_pull; /* address offset: 0x0304 */
uint32_t reserved0308[62]; /* address offset: 0x0308 */
uint32_t gpio0a_ie; /* address offset: 0x0400 */
uint32_t gpio0b_ie; /* address offset: 0x0404 */
uint32_t reserved0408[62]; /* address offset: 0x0408 */
uint32_t gpio0a_smt; /* address offset: 0x0500 */
uint32_t gpio0b_smt; /* address offset: 0x0504 */
uint32_t reserved0508[62]; /* address offset: 0x0508 */
uint32_t gpio0a_sus; /* address offset: 0x0600 */
uint32_t gpio0b_sus; /* address offset: 0x0604 */
uint32_t reserved0608[62]; /* address offset: 0x0608 */
uint32_t gpio0a_sl; /* address offset: 0x0700 */
uint32_t gpio0b_sl; /* address offset: 0x0704 */
uint32_t reserved0708[62]; /* address offset: 0x0708 */
uint32_t gpio0a_od; /* address offset: 0x0800 */
uint32_t gpio0b_od; /* address offset: 0x0804 */
uint32_t reserved0808[62]; /* address offset: 0x0808 */
uint32_t io_vsel; /* address offset: 0x0900 */
uint32_t grf_jtag_con0; /* address offset: 0x0904 */
uint32_t grf_jtag_con1; /* address offset: 0x0908 */
uint32_t reserved090c; /* address offset: 0x090c */
uint32_t xin_con; /* address offset: 0x0910 */
uint32_t reserved0914[187]; /* address offset: 0x0914 */
uint32_t grf_gpio0_filter_con0; /* address offset: 0x0c00 */
uint32_t grf_gpio0_filter_con1; /* address offset: 0x0c04 */
uint32_t grf_gpio0_filter_con2; /* address offset: 0x0c08 */
uint32_t grf_gpio0_filter_con3; /* address offset: 0x0c0c */
uint32_t grf_gpio0_filter_con4; /* address offset: 0x0c10 */
uint32_t grf_gpio0_filter_con5; /* address offset: 0x0c14 */
};
check_member(rv1126b_pmuio0_ioc_reg, grf_gpio0_filter_con5, 0x0c14);
/* pmuio1_ioc register structure define */
struct rv1126b_pmuio1_ioc_reg {
uint32_t reserved0000[4]; /* address offset: 0x0000 */
uint32_t gpio0c_iomux_sel_0; /* address offset: 0x0010 */
uint32_t gpio0c_iomux_sel_1; /* address offset: 0x0014 */
uint32_t gpio0d_iomux_sel_0; /* address offset: 0x0018 */
uint32_t reserved001c[65]; /* address offset: 0x001c */
uint32_t gpio0c_ds_0; /* address offset: 0x0120 */
uint32_t gpio0c_ds_1; /* address offset: 0x0124 */
uint32_t gpio0c_ds_2; /* address offset: 0x0128 */
uint32_t gpio0c_ds_3; /* address offset: 0x012c */
uint32_t gpio0d_ds_0; /* address offset: 0x0130 */
uint32_t reserved0134[117]; /* address offset: 0x0134 */
uint32_t gpio0c_pull; /* address offset: 0x0308 */
uint32_t gpio0d_pull; /* address offset: 0x030c */
uint32_t reserved0310[62]; /* address offset: 0x0310 */
uint32_t gpio0c_ie; /* address offset: 0x0408 */
uint32_t gpio0d_ie; /* address offset: 0x040c */
uint32_t reserved0410[62]; /* address offset: 0x0410 */
uint32_t gpio0c_smt; /* address offset: 0x0508 */
uint32_t gpio0d_smt; /* address offset: 0x050c */
uint32_t reserved0510[62]; /* address offset: 0x0510 */
uint32_t gpio0c_sus; /* address offset: 0x0608 */
uint32_t gpio0d_sus; /* address offset: 0x060c */
uint32_t reserved0610[62]; /* address offset: 0x0610 */
uint32_t gpio0c_sl; /* address offset: 0x0708 */
uint32_t gpio0d_sl; /* address offset: 0x070c */
uint32_t reserved0710[62]; /* address offset: 0x0710 */
uint32_t gpio0c_od; /* address offset: 0x0808 */
uint32_t gpio0d_od; /* address offset: 0x080c */
uint32_t reserved0810[60]; /* address offset: 0x0810 */
uint32_t io_vsel; /* address offset: 0x0900 */
};
check_member(rv1126b_pmuio1_ioc_reg, io_vsel, 0x0900);
/* vccio1_ioc register structure define */
struct rv1126b_vccio1_ioc_reg {
uint32_t reserved0000[8]; /* address offset: 0x0000 */
uint32_t gpio1a_iomux_sel_0; /* address offset: 0x0020 */
uint32_t gpio1a_iomux_sel_1; /* address offset: 0x0024 */
uint32_t gpio1b_iomux_sel_0; /* address offset: 0x0028 */
uint32_t gpio1b_iomux_sel_1; /* address offset: 0x002c */
uint32_t reserved0030[68]; /* address offset: 0x0030 */
uint32_t gpio1a_ds_0; /* address offset: 0x0140 */
uint32_t gpio1a_ds_1; /* address offset: 0x0144 */
uint32_t gpio1a_ds_2; /* address offset: 0x0148 */
uint32_t gpio1a_ds_3; /* address offset: 0x014c */
uint32_t gpio1b_ds_0; /* address offset: 0x0150 */
uint32_t gpio1b_ds_1; /* address offset: 0x0154 */
uint32_t gpio1b_ds_2; /* address offset: 0x0158 */
uint32_t gpio1b_ds_3; /* address offset: 0x015c */
uint32_t reserved0160[108]; /* address offset: 0x0160 */
uint32_t gpio1a_pull; /* address offset: 0x0310 */
uint32_t gpio1b_pull; /* address offset: 0x0314 */
uint32_t reserved0318[62]; /* address offset: 0x0318 */
uint32_t gpio1a_ie; /* address offset: 0x0410 */
uint32_t gpio1b_ie; /* address offset: 0x0414 */
uint32_t reserved0418[62]; /* address offset: 0x0418 */
uint32_t gpio1a_smt; /* address offset: 0x0510 */
uint32_t gpio1b_smt; /* address offset: 0x0514 */
uint32_t reserved0518[62]; /* address offset: 0x0518 */
uint32_t gpio1a_sus; /* address offset: 0x0610 */
uint32_t gpio1b_sus; /* address offset: 0x0614 */
uint32_t reserved0618[62]; /* address offset: 0x0618 */
uint32_t gpio1a_sl; /* address offset: 0x0710 */
uint32_t gpio1b_sl; /* address offset: 0x0714 */
uint32_t reserved0718[62]; /* address offset: 0x0718 */
uint32_t gpio1a_od; /* address offset: 0x0810 */
uint32_t gpio1b_od; /* address offset: 0x0814 */
uint32_t reserved0818[60]; /* address offset: 0x0818 */
uint32_t io1_vsel; /* address offset: 0x0908 */
uint32_t reserved090c[61]; /* address offset: 0x090c */
uint32_t ioc_misc_con0; /* address offset: 0x0a00 */
uint32_t ioc_misc_con1; /* address offset: 0x0a04 */
uint32_t ioc_misc_con2; /* address offset: 0x0a08 */
uint32_t ioc_misc_con3; /* address offset: 0x0a0c */
uint32_t ioc_misc_con4; /* address offset: 0x0a10 */
uint32_t ioc_misc_con5; /* address offset: 0x0a14 */
uint32_t ioc_misc_con6; /* address offset: 0x0a18 */
};
check_member(rv1126b_vccio1_ioc_reg, ioc_misc_con6, 0x0a18);
/* vccio2_ioc register structure define */
struct rv1126b_vccio2_ioc_reg {
uint32_t reserved0000[16]; /* address offset: 0x0000 */
uint32_t gpio2a_iomux_sel_0; /* address offset: 0x0040 */
uint32_t gpio2a_iomux_sel_1; /* address offset: 0x0044 */
uint32_t reserved0048[78]; /* address offset: 0x0048 */
uint32_t gpio2a_ds_0; /* address offset: 0x0180 */
uint32_t gpio2a_ds_1; /* address offset: 0x0184 */
uint32_t gpio2a_ds_2; /* address offset: 0x0188 */
uint32_t reserved018c[101]; /* address offset: 0x018c */
uint32_t gpio2a_pull; /* address offset: 0x0320 */
uint32_t reserved0324[63]; /* address offset: 0x0324 */
uint32_t gpio2a_ie; /* address offset: 0x0420 */
uint32_t reserved0424[63]; /* address offset: 0x0424 */
uint32_t gpio2a_smt; /* address offset: 0x0520 */
uint32_t reserved0524[63]; /* address offset: 0x0524 */
uint32_t gpio2a_sus; /* address offset: 0x0620 */
uint32_t reserved0624[63]; /* address offset: 0x0624 */
uint32_t gpio2a_sl; /* address offset: 0x0720 */
uint32_t reserved0724[63]; /* address offset: 0x0724 */
uint32_t gpio2a_od; /* address offset: 0x0820 */
uint32_t reserved0824[58]; /* address offset: 0x0824 */
uint32_t io_vsel; /* address offset: 0x090c */
uint32_t reserved0910[159]; /* address offset: 0x0910 */
uint32_t grf_sddet_dly_con; /* address offset: 0x0b8c */
uint32_t grf_jtag_con; /* address offset: 0x0b90 */
uint32_t reserved0b94[27]; /* address offset: 0x0b94 */
uint32_t grf_gpio2_filter_con0; /* address offset: 0x0c00 */
uint32_t grf_gpio2_filter_con1; /* address offset: 0x0c04 */
uint32_t grf_gpio2_filter_con2; /* address offset: 0x0c08 */
uint32_t grf_gpio2_filter_con3; /* address offset: 0x0c0c */
uint32_t grf_gpio2_filter_con4; /* address offset: 0x0c10 */
uint32_t grf_gpio2_filter_con5; /* address offset: 0x0c14 */
};
check_member(rv1126b_vccio2_ioc_reg, grf_gpio2_filter_con5, 0x0c14);
/* vccio3_ioc register structure define */
struct rv1126b_vccio3_ioc_reg {
uint32_t reserved0000[24]; /* address offset: 0x0000 */
uint32_t gpio3a_iomux_sel_0; /* address offset: 0x0060 */
uint32_t gpio3a_iomux_sel_1; /* address offset: 0x0064 */
uint32_t gpio3b_iomux_sel_0; /* address offset: 0x0068 */
uint32_t gpio3b_iomux_sel_1; /* address offset: 0x006c */
uint32_t reserved0070[84]; /* address offset: 0x0070 */
uint32_t gpio3a_ds_0; /* address offset: 0x01c0 */
uint32_t gpio3a_ds_1; /* address offset: 0x01c4 */
uint32_t gpio3a_ds_2; /* address offset: 0x01c8 */
uint32_t gpio3a_ds_3; /* address offset: 0x01cc */
uint32_t gpio3b_ds_0; /* address offset: 0x01d0 */
uint32_t gpio3b_ds_1; /* address offset: 0x01d4 */
uint32_t gpio3b_ds_2; /* address offset: 0x01d8 */
uint32_t gpio3b_ds_3; /* address offset: 0x01dc */
uint32_t reserved01e0[84]; /* address offset: 0x01e0 */
uint32_t gpio3a_pull; /* address offset: 0x0330 */
uint32_t gpio3b_pull; /* address offset: 0x0334 */
uint32_t reserved0338[62]; /* address offset: 0x0338 */
uint32_t gpio3a_ie; /* address offset: 0x0430 */
uint32_t gpio3b_ie; /* address offset: 0x0434 */
uint32_t reserved0438[62]; /* address offset: 0x0438 */
uint32_t gpio3a_smt; /* address offset: 0x0530 */
uint32_t gpio3b_smt; /* address offset: 0x0534 */
uint32_t reserved0538[62]; /* address offset: 0x0538 */
uint32_t gpio3a_sus; /* address offset: 0x0630 */
uint32_t gpio3b_sus; /* address offset: 0x0634 */
uint32_t reserved0638[62]; /* address offset: 0x0638 */
uint32_t gpio3a_sl; /* address offset: 0x0730 */
uint32_t gpio3b_sl; /* address offset: 0x0734 */
uint32_t reserved0738[62]; /* address offset: 0x0738 */
uint32_t gpio3a_od; /* address offset: 0x0830 */
uint32_t gpio3b_od; /* address offset: 0x0834 */
uint32_t reserved0838[54]; /* address offset: 0x0838 */
uint32_t io3_vsel; /* address offset: 0x0910 */
uint32_t reserved0914[59]; /* address offset: 0x0914 */
uint32_t ioc_misc_con0; /* address offset: 0x0a00 */
uint32_t ioc_misc_con1; /* address offset: 0x0a04 */
uint32_t ioc_misc_con2; /* address offset: 0x0a08 */
uint32_t ioc_misc_con3; /* address offset: 0x0a0c */
uint32_t ioc_misc_con4; /* address offset: 0x0a10 */
uint32_t ioc_misc_con5; /* address offset: 0x0a14 */
uint32_t ioc_misc_con6; /* address offset: 0x0a18 */
};
check_member(rv1126b_vccio3_ioc_reg, ioc_misc_con6, 0x0a18);
/* vccio4_ioc register structure define */
struct rv1126b_vccio4_ioc_reg {
uint32_t reserved0000[32]; /* address offset: 0x0000 */
uint32_t gpio4a_iomux_sel_0; /* address offset: 0x0080 */
uint32_t gpio4a_iomux_sel_1; /* address offset: 0x0084 */
uint32_t gpio4b_iomux_sel_0; /* address offset: 0x0088 */
uint32_t reserved008c[93]; /* address offset: 0x008c */
uint32_t gpio4a_ds_0; /* address offset: 0x0200 */
uint32_t gpio4a_ds_1; /* address offset: 0x0204 */
uint32_t gpio4a_ds_2; /* address offset: 0x0208 */
uint32_t gpio4a_ds_3; /* address offset: 0x020c */
uint32_t gpio4b_ds_0; /* address offset: 0x0210 */
uint32_t reserved0214[75]; /* address offset: 0x0214 */
uint32_t gpio4a_pull; /* address offset: 0x0340 */
uint32_t gpio4b_pull; /* address offset: 0x0344 */
uint32_t reserved0348[62]; /* address offset: 0x0348 */
uint32_t gpio4a_ie; /* address offset: 0x0440 */
uint32_t gpio4b_ie; /* address offset: 0x0444 */
uint32_t reserved0448[62]; /* address offset: 0x0448 */
uint32_t gpio4a_smt; /* address offset: 0x0540 */
uint32_t gpio4b_smt; /* address offset: 0x0544 */
uint32_t reserved0548[62]; /* address offset: 0x0548 */
uint32_t gpio4a_sus; /* address offset: 0x0640 */
uint32_t gpio4b_sus; /* address offset: 0x0644 */
uint32_t reserved0648[62]; /* address offset: 0x0648 */
uint32_t gpio4a_sl; /* address offset: 0x0740 */
uint32_t gpio4b_sl; /* address offset: 0x0744 */
uint32_t reserved0748[62]; /* address offset: 0x0748 */
uint32_t gpio4a_od; /* address offset: 0x0840 */
uint32_t gpio4b_od; /* address offset: 0x0844 */
uint32_t reserved0848[51]; /* address offset: 0x0848 */
uint32_t io_vsel; /* address offset: 0x0914 */
uint32_t reserved0918[194]; /* address offset: 0x0918 */
uint32_t grf_gpio4_filter_con0; /* address offset: 0x0c20 */
uint32_t grf_gpio4_filter_con1; /* address offset: 0x0c24 */
uint32_t grf_gpio4_filter_con2; /* address offset: 0x0c28 */
uint32_t grf_gpio4_filter_con3; /* address offset: 0x0c2c */
uint32_t grf_gpio4_filter_con4; /* address offset: 0x0c30 */
uint32_t grf_gpio4_filter_con5; /* address offset: 0x0c34 */
};
check_member(rv1126b_vccio4_ioc_reg, grf_gpio4_filter_con5, 0x0c34);
/* vccio5_ioc register structure define */
struct rv1126b_vccio5_ioc_reg {
uint32_t reserved0000[40]; /* address offset: 0x0000 */
uint32_t gpio5a_iomux_sel_0; /* address offset: 0x00a0 */
uint32_t gpio5a_iomux_sel_1; /* address offset: 0x00a4 */
uint32_t gpio5b_iomux_sel_0; /* address offset: 0x00a8 */
uint32_t gpio5b_iomux_sel_1; /* address offset: 0x00ac */
uint32_t gpio5c_iomux_sel_0; /* address offset: 0x00b0 */
uint32_t gpio5c_iomux_sel_1; /* address offset: 0x00b4 */
uint32_t gpio5d_iomux_sel_0; /* address offset: 0x00b8 */
uint32_t gpio5d_iomux_sel_1; /* address offset: 0x00bc */
uint32_t reserved00c0[96]; /* address offset: 0x00c0 */
uint32_t gpio5a_ds_0; /* address offset: 0x0240 */
uint32_t gpio5a_ds_1; /* address offset: 0x0244 */
uint32_t gpio5a_ds_2; /* address offset: 0x0248 */
uint32_t gpio5a_ds_3; /* address offset: 0x024c */
uint32_t gpio5b_ds_0; /* address offset: 0x0250 */
uint32_t gpio5b_ds_1; /* address offset: 0x0254 */
uint32_t gpio5b_ds_2; /* address offset: 0x0258 */
uint32_t gpio5b_ds_3; /* address offset: 0x025c */
uint32_t gpio5c_ds_0; /* address offset: 0x0260 */
uint32_t gpio5c_ds_1; /* address offset: 0x0264 */
uint32_t gpio5c_ds_2; /* address offset: 0x0268 */
uint32_t gpio5c_ds_3; /* address offset: 0x026c */
uint32_t gpio5d_ds_0; /* address offset: 0x0270 */
uint32_t gpio5d_ds_1; /* address offset: 0x0274 */
uint32_t gpio5d_ds_2; /* address offset: 0x0278 */
uint32_t gpio5d_ds_3; /* address offset: 0x027c */
uint32_t reserved0280[52]; /* address offset: 0x0280 */
uint32_t gpio5a_pull; /* address offset: 0x0350 */
uint32_t gpio5b_pull; /* address offset: 0x0354 */
uint32_t gpio5c_pull; /* address offset: 0x0358 */
uint32_t gpio5d_pull; /* address offset: 0x035c */
uint32_t reserved0360[60]; /* address offset: 0x0360 */
uint32_t gpio5a_ie; /* address offset: 0x0450 */
uint32_t gpio5b_ie; /* address offset: 0x0454 */
uint32_t gpio5c_ie; /* address offset: 0x0458 */
uint32_t gpio5d_ie; /* address offset: 0x045c */
uint32_t reserved0460[60]; /* address offset: 0x0460 */
uint32_t gpio5a_smt; /* address offset: 0x0550 */
uint32_t gpio5b_smt; /* address offset: 0x0554 */
uint32_t gpio5c_smt; /* address offset: 0x0558 */
uint32_t gpio5d_smt; /* address offset: 0x055c */
uint32_t reserved0560[60]; /* address offset: 0x0560 */
uint32_t gpio5a_sus; /* address offset: 0x0650 */
uint32_t gpio5b_sus; /* address offset: 0x0654 */
uint32_t gpio5c_sus; /* address offset: 0x0658 */
uint32_t gpio5d_sus; /* address offset: 0x065c */
uint32_t reserved0660[60]; /* address offset: 0x0660 */
uint32_t gpio5a_sl; /* address offset: 0x0750 */
uint32_t gpio5b_sl; /* address offset: 0x0754 */
uint32_t gpio5c_sl; /* address offset: 0x0758 */
uint32_t gpio5d_sl; /* address offset: 0x075c */
uint32_t reserved0760[60]; /* address offset: 0x0760 */
uint32_t gpio5a_od; /* address offset: 0x0850 */
uint32_t gpio5b_od; /* address offset: 0x0854 */
uint32_t gpio5c_od; /* address offset: 0x0858 */
uint32_t gpio5d_od; /* address offset: 0x085c */
uint32_t reserved0860[46]; /* address offset: 0x0860 */
uint32_t io_vsel; /* address offset: 0x0918 */
uint32_t reserved091c[159]; /* address offset: 0x091c */
uint32_t grf_vicif_m1_con; /* address offset: 0x0b98 */
uint32_t grf_vop_lcdc_con; /* address offset: 0x0b9c */
uint32_t reserved0ba0[2]; /* address offset: 0x0ba0 */
uint32_t grf_gmacio_m1_con0; /* address offset: 0x0ba8 */
uint32_t grf_gmacio_m1_con1; /* address offset: 0x0bac */
uint32_t grf_uart0_dly_con; /* address offset: 0x0bb0 */
uint32_t grf_uart_jtag_con; /* address offset: 0x0bb4 */
uint32_t reserved0bb8[34]; /* address offset: 0x0bb8 */
uint32_t grf_gpio5_filter_con0; /* address offset: 0x0c40 */
uint32_t grf_gpio5_filter_con1; /* address offset: 0x0c44 */
uint32_t grf_gpio5_filter_con2; /* address offset: 0x0c48 */
uint32_t grf_gpio5_filter_con3; /* address offset: 0x0c4c */
uint32_t grf_gpio5_filter_con4; /* address offset: 0x0c50 */
uint32_t grf_gpio5_filter_con5; /* address offset: 0x0c54 */
};
check_member(rv1126b_vccio5_ioc_reg, grf_gpio5_filter_con5, 0x0c54);
/* vccio6_ioc register structure define */
struct rv1126b_vccio6_ioc_reg {
uint32_t reserved0000[48]; /* address offset: 0x0000 */
uint32_t gpio6a_iomux_sel_0; /* address offset: 0x00c0 */
uint32_t gpio6a_iomux_sel_1; /* address offset: 0x00c4 */
uint32_t gpio6b_iomux_sel_0; /* address offset: 0x00c8 */
uint32_t gpio6b_iomux_sel_1; /* address offset: 0x00cc */
uint32_t gpio6c_iomux_sel_0; /* address offset: 0x00d0 */
uint32_t reserved00d4[107]; /* address offset: 0x00d4 */
uint32_t gpio6a_ds_0; /* address offset: 0x0280 */
uint32_t gpio6a_ds_1; /* address offset: 0x0284 */
uint32_t gpio6a_ds_2; /* address offset: 0x0288 */
uint32_t gpio6a_ds_3; /* address offset: 0x028c */
uint32_t gpio6b_ds_0; /* address offset: 0x0290 */
uint32_t gpio6b_ds_1; /* address offset: 0x0294 */
uint32_t gpio6b_ds_2; /* address offset: 0x0298 */
uint32_t gpio6b_ds_3; /* address offset: 0x029c */
uint32_t gpio6c_ds_0; /* address offset: 0x02a0 */
uint32_t gpio6c_ds_1; /* address offset: 0x02a4 */
uint32_t reserved02a8[46]; /* address offset: 0x02a8 */
uint32_t gpio6a_pull; /* address offset: 0x0360 */
uint32_t gpio6b_pull; /* address offset: 0x0364 */
uint32_t gpio6c_pull; /* address offset: 0x0368 */
uint32_t reserved036c[61]; /* address offset: 0x036c */
uint32_t gpio6a_ie; /* address offset: 0x0460 */
uint32_t gpio6b_ie; /* address offset: 0x0464 */
uint32_t gpio6c_ie; /* address offset: 0x0468 */
uint32_t reserved046c[61]; /* address offset: 0x046c */
uint32_t gpio6a_smt; /* address offset: 0x0560 */
uint32_t gpio6b_smt; /* address offset: 0x0564 */
uint32_t gpio6c_smt; /* address offset: 0x0568 */
uint32_t reserved056c[61]; /* address offset: 0x056c */
uint32_t gpio6a_sus; /* address offset: 0x0660 */
uint32_t gpio6b_sus; /* address offset: 0x0664 */
uint32_t gpio6c_sus; /* address offset: 0x0668 */
uint32_t reserved066c[61]; /* address offset: 0x066c */
uint32_t gpio6a_sl; /* address offset: 0x0760 */
uint32_t gpio6b_sl; /* address offset: 0x0764 */
uint32_t gpio6c_sl; /* address offset: 0x0768 */
uint32_t reserved076c[61]; /* address offset: 0x076c */
uint32_t gpio6a_od; /* address offset: 0x0860 */
uint32_t gpio6b_od; /* address offset: 0x0864 */
uint32_t gpio6c_od; /* address offset: 0x0868 */
uint32_t reserved086c[44]; /* address offset: 0x086c */
uint32_t io_vsel; /* address offset: 0x091c */
uint32_t reserved0920[157]; /* address offset: 0x0920 */
uint32_t grf_vicif_m0_con; /* address offset: 0x0b94 */
uint32_t reserved0b98[2]; /* address offset: 0x0b98 */
uint32_t grf_gmacio_m0_con0; /* address offset: 0x0ba0 */
uint32_t grf_gmacio_m0_con1; /* address offset: 0x0ba4 */
uint32_t reserved0ba8[46]; /* address offset: 0x0ba8 */
uint32_t grf_gpio6_filter_con0; /* address offset: 0x0c60 */
uint32_t grf_gpio6_filter_con1; /* address offset: 0x0c64 */
uint32_t grf_gpio6_filter_con2; /* address offset: 0x0c68 */
uint32_t grf_gpio6_filter_con3; /* address offset: 0x0c6c */
uint32_t grf_gpio6_filter_con4; /* address offset: 0x0c70 */
uint32_t grf_gpio6_filter_con5; /* address offset: 0x0c74 */
};
check_member(rv1126b_vccio6_ioc_reg, grf_gpio6_filter_con5, 0x0c74);
/* vccio7_ioc register structure define */
struct rv1126b_vccio7_ioc_reg {
uint32_t reserved0000[56]; /* address offset: 0x0000 */
uint32_t gpio7a_iomux_sel_0; /* address offset: 0x00e0 */
uint32_t gpio7a_iomux_sel_1; /* address offset: 0x00e4 */
uint32_t gpio7b_iomux_sel_0; /* address offset: 0x00e8 */
uint32_t reserved00ec[117]; /* address offset: 0x00ec */
uint32_t gpio7a_ds_0; /* address offset: 0x02c0 */
uint32_t gpio7a_ds_1; /* address offset: 0x02c4 */
uint32_t gpio7a_ds_2; /* address offset: 0x02c8 */
uint32_t gpio7a_ds_3; /* address offset: 0x02cc */
uint32_t gpio7b_ds_0; /* address offset: 0x02d0 */
uint32_t reserved02d4[39]; /* address offset: 0x02d4 */
uint32_t gpio7a_pull; /* address offset: 0x0370 */
uint32_t gpio7b_pull; /* address offset: 0x0374 */
uint32_t reserved0378[62]; /* address offset: 0x0378 */
uint32_t gpio7a_ie; /* address offset: 0x0470 */
uint32_t gpio7b_ie; /* address offset: 0x0474 */
uint32_t reserved0478[62]; /* address offset: 0x0478 */
uint32_t gpio7a_smt; /* address offset: 0x0570 */
uint32_t gpio7b_smt; /* address offset: 0x0574 */
uint32_t reserved0578[62]; /* address offset: 0x0578 */
uint32_t gpio7a_sus; /* address offset: 0x0670 */
uint32_t gpio7b_sus; /* address offset: 0x0674 */
uint32_t reserved0678[62]; /* address offset: 0x0678 */
uint32_t gpio7a_sl; /* address offset: 0x0770 */
uint32_t gpio7b_sl; /* address offset: 0x0774 */
uint32_t reserved0778[62]; /* address offset: 0x0778 */
uint32_t gpio7a_od; /* address offset: 0x0870 */
uint32_t gpio7b_od; /* address offset: 0x0874 */
uint32_t reserved0878[42]; /* address offset: 0x0878 */
uint32_t io_vsel; /* address offset: 0x0920 */
uint32_t reserved0924[215]; /* address offset: 0x0924 */
uint32_t grf_gpio7_filter_con0; /* address offset: 0x0c80 */
uint32_t grf_gpio7_filter_con1; /* address offset: 0x0c84 */
uint32_t grf_gpio7_filter_con2; /* address offset: 0x0c88 */
uint32_t grf_gpio7_filter_con3; /* address offset: 0x0c8c */
uint32_t grf_gpio7_filter_con4; /* address offset: 0x0c90 */
uint32_t grf_gpio7_filter_con5; /* address offset: 0x0c94 */
uint32_t reserved0c98[2]; /* address offset: 0x0c98 */
uint32_t grf_dsm_ioc_con; /* address offset: 0x0ca0 */
};
check_member(rv1126b_vccio7_ioc_reg, grf_dsm_ioc_con, 0x0ca0);
#endif /* _ASM_ARCH_GRF_RV1126B_H */

62
u-boot/arch/arm/mach-rockchip/Kconfig
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@ -32,11 +32,18 @@ config TPL_MAX_SIZE
default 10240
config ROCKCHIP_RK3326
bool "Support Rockchip RK3326 "
bool "Support Rockchip RK3326"
help
RK3326 can use most code from PX30, but at some situations we have
to distinguish between RK3326 and PX30, so this macro gives help.
It is usually selected in rk3326 board defconfig.
config ROCKCHIP_RK3358
bool "Support Rockchip RK3358"
help
RK3358 can use most code from PX30, but at some situations we have
to distinguish between RK3358 and PX30, so this macro gives help.
It is usually selected in rk3358 board defconfig.
endif
config ROCKCHIP_RK3036
@ -51,6 +58,7 @@ config ROCKCHIP_RK3036
select TPL_NEEDS_SEPARATE_TEXT_BASE if TPL
select TPL_NEEDS_SEPARATE_STACK if TPL
select ARM_SMCCC
select ARM_ERRATA_814220
help
The Rockchip RK3036 is a ARM-based SoC with a dual-core Cortex-A7
including NEON and GPU, Mali-400 graphics, several DDR3 options
@ -62,6 +70,7 @@ config ROCKCHIP_RK3128
select CPU_V7
select GICV2
select ARM_SMCCC
select ARM_ERRATA_814220
help
The Rockchip RK3128 is a ARM-based SoC with a quad-core Cortex-A7
including NEON and GPU, Mali-400 graphics, several DDR3 options
@ -138,6 +147,7 @@ config ROCKCHIP_RK322X
select TPL_LIBGENERIC_SUPPORT
select GICV2
select ARM_SMCCC
select ARM_ERRATA_814220
help
The Rockchip RK3229 is a ARM-based SoC with a dual-core Cortex-A7
including NEON and GPU, Mali-400 graphics, several DDR3 options
@ -388,6 +398,7 @@ config ROCKCHIP_RK3506
select DEBUG_UART_BOARD_INIT
select ARM_SMCCC
select GICV2
select ARM_ERRATA_814220
imply SUPPORT_SPL
imply SUPPORT_TPL
imply SPL
@ -443,15 +454,15 @@ endif
config ROCKCHIP_RK3562
bool "Support Rockchip RK3562"
select GICV2
select ARM64
select ARM_SMCCC
select SUPPORT_TPL
select SUPPORT_SPL
select ARM64 if !ARM64_BOOT_AARCH32
select GICV2 if !ARM64_BOOT_AARCH32
select SUPPORT_TPL if !ARM64_BOOT_AARCH32
select SUPPORT_SPL if !ARM64_BOOT_AARCH32
select TPL_TINY_FRAMEWORK if TPL
select DEBUG_UART_BOARD_INIT
imply TPL
imply SPL
imply TPL if !ARM64_BOOT_AARCH32
imply SPL if !ARM64_BOOT_AARCH32
imply TPL_SERIAL_SUPPORT
help
The Rockchip RK3562 is a ARM-based SoC with a quad-core Cortex-A53.
@ -590,6 +601,7 @@ config ROCKCHIP_RV1103B
select ARM_ZERO_CNTVOFF
select ROCKCHIP_BROM_HELPER
select DEBUG_UART_BOARD_INIT
select ARM_ERRATA_814220
imply SUPPORT_SPL
imply SUPPORT_TPL
imply SPL
@ -619,6 +631,7 @@ config ROCKCHIP_RV1106
bool "Support Rockchip RV1106"
select CPU_V7
select DEBUG_UART_BOARD_INIT
select ARM_ERRATA_814220
imply SUPPORT_SPL
imply SUPPORT_TPL
imply SPL
@ -651,6 +664,7 @@ config ROCKCHIP_RV1108
select SPL
select TPL
select BOARD_LATE_INIT
select ARM_ERRATA_814220
help
The Rockchip RV1108 is a ARM-based SoC with a single-core Cortex-A7
and a DSP.
@ -678,6 +692,7 @@ config ROCKCHIP_RV1126
imply SUPPORT_SPL
imply TPL_TINY_FRAMEWORK if TPL
select DEBUG_UART_BOARD_INIT
select ARM_ERRATA_814220
imply TPL
imply SPL
imply GICV2
@ -701,6 +716,35 @@ config TPL_MAX_SIZE
default 32768
endif
config ROCKCHIP_RV1126B
bool "Support Rockchip RV1126B"
select ARM64 if !ARM64_BOOT_AARCH32
select GICV2 if !ARM64_BOOT_AARCH32
select ARM_SMCCC
select DEBUG_UART_BOARD_INIT
select ROCKCHIP_BROM_HELPER
select SUPPORT_TPL if !ARM64_BOOT_AARCH32
select SUPPORT_SPL if !ARM64_BOOT_AARCH32
select TPL_TINY_FRAMEWORK if TPL
imply TPL if !ARM64_BOOT_AARCH32
imply SPL if !ARM64_BOOT_AARCH32
imply TPL_SERIAL_SUPPORT
help
The Rockchip RV1126B is a ARM-based SoC with a quad-core Cortex-A53.
if ROCKCHIP_RV1126B
config TPL_LDSCRIPT
default "arch/arm/mach-rockchip/u-boot-tpl-v8.lds"
config TPL_TEXT_BASE
default 0x3ffb1000
config TPL_MAX_SIZE
default 61440
endif
config SPL_ROCKCHIP_BACK_TO_BROM
bool "SPL returns to bootrom"
default y if ROCKCHIP_RK3036
@ -758,6 +802,7 @@ config ROCKCHIP_BOOT_MODE_REG
default 0xff020200 if ROCKCHIP_RV1106
default 0x10300580 if ROCKCHIP_RV1108
default 0xfe020200 if ROCKCHIP_RV1126
default 0x20130220 if ROCKCHIP_RV1126B
default 0
help
The Soc will enter to different boot mode(defined in asm/arch/boot_mode.h)
@ -787,6 +832,7 @@ config ROCKCHIP_STIMER_BASE
default 0xff590020 if ROCKCHIP_RV1106
default 0x10350020 if ROCKCHIP_RV1108
default 0xff670020 if ROCKCHIP_RV1126
default 0x20820000 if ROCKCHIP_RV1126B
default 0
help
The secure timer inited in SPL/TPL in secure word, ARM generic timer
@ -814,6 +860,7 @@ config ROCKCHIP_IRAM_START_ADDR
default 0xff6c0000 if ROCKCHIP_RV1106
default 0x10080000 if ROCKCHIP_RV1108
default 0xff700000 if ROCKCHIP_RV1126
default 0x3ffb0000 if ROCKCHIP_RV1126B
default 0
help
The IRAM start addr is to locate variant of the boot device from
@ -1272,5 +1319,6 @@ source "arch/arm/mach-rockchip/rv1103b/Kconfig"
source "arch/arm/mach-rockchip/rv1106/Kconfig"
source "arch/arm/mach-rockchip/rv1108/Kconfig"
source "arch/arm/mach-rockchip/rv1126/Kconfig"
source "arch/arm/mach-rockchip/rv1126b/Kconfig"
endif

1
u-boot/arch/arm/mach-rockchip/Makefile
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@ -85,6 +85,7 @@ obj-$(CONFIG_ROCKCHIP_RV1103B) += rv1103b/
obj-$(CONFIG_ROCKCHIP_RV1106) += rv1106/
obj-$(CONFIG_ROCKCHIP_RV1108) += rv1108/
obj-$(CONFIG_ROCKCHIP_RV1126) += rv1126/
obj-$(CONFIG_ROCKCHIP_RV1126B) += rv1126b/
# Clear out SPL objects, in case this is a TPL build
obj-spl-$(CONFIG_TPL_BUILD) =

2
u-boot/arch/arm/mach-rockchip/chip_info.c
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@ -105,6 +105,8 @@ int rockchip_rockusb_get_chip_info(unsigned int chip_info[])
chip_info[0] = 0x31383041;
#elif defined(CONFIG_ROCKCHIP_RV1126)
chip_info[0] = 0x31313236;
#elif defined(CONFIG_ROCKCHIP_RV1126B)
chip_info[0] = 0x31313046;
#elif defined(CONFIG_ROCKCHIP_RV1106)
chip_info[0] = 0x31313036;
#endif

31
u-boot/arch/arm/mach-rockchip/fit.c
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@ -236,6 +236,20 @@ static int fit_image_fixup_alloc(const void *fit, const char *prop_name,
if (ret)
return ret;
/*
* 1. When need load HWID dtb, gd->fdt_blob points to HWID dtb
* and U-Boot will re-alloc MEM_FDT based on fdt node in
* ITB instead of resource. So alloc the larger size to
* avoid fail in sysmem. It will already skip load DTB in fdt node.
*
* 2. Additionally increase size with CONFIG_SYS_FDT_PAD to reserve
* some space for adding more props to dtb afterwards.
*/
if (!strcmp(prop_name, FIT_FDT_PROP) && !fdt_check_header(gd->fdt_blob))
size = ((size > fdt_totalsize(gd->fdt_blob)) ?
size : fdt_totalsize(gd->fdt_blob)) +
CONFIG_SYS_FDT_PAD;
if (!sysmem_alloc_base(mem, (phys_addr_t)addr,
ALIGN(size, RK_BLK_SIZE)))
return -ENOMEM;
@ -257,7 +271,7 @@ int fit_image_pre_process(const void *fit)
return ret;
}
#if !defined(CONFIG_ARM64) && defined(CONFIG_CMD_BOOTZ)
#if defined(CONFIG_CMD_BOOTZ)
int cfg_noffset, noffset;
const void *buf;
ulong start, end;
@ -271,10 +285,23 @@ int fit_image_pre_process(const void *fit)
noffset = fit_conf_get_prop_node_index(fit, cfg_noffset, FIT_KERNEL_PROP, 0);
if (noffset < 0) {
printf("Could not find subimage node\n");
printf("Could not find kernel node\n");
return -ENOENT;
}
/*
* "kernel_addr_r" is for 64-bit kernel Image by default.
* Here in case of 64-bit U-Boot load 32-bit kenrel Image.
*/
#ifdef CONFIG_ARM64
char *kernel_addr_r;
if (fit_image_check_arch(fit, noffset, IH_ARCH_ARM)) {
kernel_addr_r = env_get("kernel_addr_aarch32_r");
if (kernel_addr_r)
env_set("kernel_addr_r", kernel_addr_r);
}
#endif
/* get image data address and length */
if (fit_image_get_data(fit, noffset, &buf, &size)) {
printf("Could not find %s subimage data!\n", FIT_KERNEL_PROP);

75
u-boot/arch/arm/mach-rockchip/fit_args.sh
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@ -37,9 +37,12 @@ function help()
echo
}
DRAM_BASE=`sed -n "/CONFIG_SYS_SDRAM_BASE=/s/CONFIG_SYS_SDRAM_BASE=//p" ${srctree}/include/autoconf.mk|tr -d '\r'`
if [ $# -eq 1 ]; then
# default
TEE_OFFSET=0x08400000
TEE_LOAD_ADDR="0x"$(echo "obase=16;$((DRAM_BASE+TEE_OFFSET))"|bc)
else
# args
while [ $# -gt 0 ]; do
@ -52,48 +55,56 @@ else
COMPRESSION=$2
shift 2
;;
-i0)
INIT0_LOAD_ADDR=$2
shift 2
;;
-m0)
MCU0_OFFSET=$2
MCU0_LOAD_ADDR=$2
shift 2
;;
-m1)
MCU1_OFFSET=$2
MCU1_LOAD_ADDR=$2
shift 2
;;
-m2)
MCU2_OFFSET=$2
MCU2_LOAD_ADDR=$2
shift 2
;;
-m3)
MCU3_OFFSET=$2
MCU3_LOAD_ADDR=$2
shift 2
;;
-m4)
MCU4_OFFSET=$2
MCU4_LOAD_ADDR=$2
shift 2
;;
-l0)
LOAD0_OFFSET=$2
LOAD0_LOAD_ADDR=$2
shift 2
;;
-l1)
LOAD1_OFFSET=$2
LOAD1_LOAD_ADDR=$2
shift 2
;;
-l2)
LOAD2_OFFSET=$2
LOAD2_LOAD_ADDR=$2
shift 2
;;
-l3)
LOAD3_OFFSET=$2
LOAD3_LOAD_ADDR=$2
shift 2
;;
-l4)
LOAD4_OFFSET=$2
LOAD4_LOAD_ADDR=$2
shift 2
;;
-t)
TEE_OFFSET=$2
TEE_LOAD_ADDR=$2
# Compatible leagcy: Offset
if ((TEE_LOAD_ADDR < DRAM_BASE)); then
TEE_LOAD_ADDR="0x"$(echo "obase=16;$((DRAM_BASE+$2))"|bc)
fi
shift 2
;;
*)
@ -105,8 +116,6 @@ else
done
fi
# Base
DARM_BASE=`sed -n "/CONFIG_SYS_SDRAM_BASE=/s/CONFIG_SYS_SDRAM_BASE=//p" ${srctree}/include/autoconf.mk|tr -d '\r'`
if ! grep -q '^CONFIG_FIT_OMIT_UBOOT=y' .config ; then
UBOOT_LOAD_ADDR=`sed -n "/CONFIG_SYS_TEXT_BASE=/s/CONFIG_SYS_TEXT_BASE=//p" ${srctree}/include/autoconf.mk|tr -d '\r'`
fi
@ -121,43 +130,3 @@ elif grep -q '^CONFIG_ARM64_BOOT_AARCH32=y' .config ; then
else
ARCH="arm"
fi
# tee
if [ ! -z "${TEE_OFFSET}" ]; then
TEE_LOAD_ADDR="0x"$(echo "obase=16;$((DARM_BASE+TEE_OFFSET))"|bc)
fi
# mcu
if [ ! -z "${MCU0_OFFSET}" ]; then
MCU0_LOAD_ADDR="0x"$(echo "obase=16;$((DARM_BASE+$MCU0_OFFSET))"|bc)
fi
if [ ! -z "${MCU1_OFFSET}" ]; then
MCU1_LOAD_ADDR="0x"$(echo "obase=16;$((DARM_BASE+$MCU1_OFFSET))"|bc)
fi
if [ ! -z "${MCU2_OFFSET}" ]; then
MCU2_LOAD_ADDR="0x"$(echo "obase=16;$((DARM_BASE+$MCU2_OFFSET))"|bc)
fi
if [ ! -z "${MCU3_OFFSET}" ]; then
MCU3_LOAD_ADDR="0x"$(echo "obase=16;$((DARM_BASE+$MCU3_OFFSET))"|bc)
fi
if [ ! -z "${MCU4_OFFSET}" ]; then
MCU4_LOAD_ADDR="0x"$(echo "obase=16;$$((DARM_BASE+$MCU4_OFFSET))"|bc)
fi
# loadables
if [ ! -z "${LOAD0_OFFSET}" ]; then
LOAD0_LOAD_ADDR="0x"$(echo "obase=16;$((DARM_BASE+$LOAD0_OFFSET))"|bc)
fi
if [ ! -z "${LOAD1_OFFSET}" ]; then
LOAD1_LOAD_ADDR="0x"$(echo "obase=16;$((DARM_BASE+$LOAD1_OFFSET))"|bc)
fi
if [ ! -z "${LOAD2_OFFSET}" ]; then
LOAD2_LOAD_ADDR="0x"$(echo "obase=16;$((DARM_BASE+$LOAD2_OFFSET))"|bc)
fi
if [ ! -z "${LOAD3_OFFSET}" ]; then
LOAD3_LOAD_ADDR="0x"$(echo "obase=16;$((DARM_BASE+$LOAD3_OFFSET))"|bc)
fi
if [ ! -z "${LOAD4_OFFSET}" ]; then
LOAD4_LOAD_ADDR="0x"$(echo "obase=16;$((DARM_BASE+$LOAD4_OFFSET))"|bc)
fi
# echo " ## $DARM_BASE, $UBOOT_LOAD_ADDR, $TEE_LOAD_ADDR, $MCU0_LOAD_ADDR, $MCU1_LOAD_ADDR, $MCU2_LOAD_ADDR, $MCU3_LOAD_ADDR, $MCU4_LOAD_ADDR"

30
u-boot/arch/arm/mach-rockchip/fit_nodes.sh
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@ -12,6 +12,8 @@ rm -f ${srctree}/*.digest ${srctree}/*.bin.gz ${srctree}/bl31_0x*.bin
# Periph register base
if grep -q '^CONFIG_ROCKCHIP_RK3576=y' .config ; then
MAX_ADDR_VAL=$((0x10000000))
elif grep -q '^CONFIG_ROCKCHIP_RV1126B=y' .config ; then
MAX_ADDR_VAL=$((0x20000000))
elif grep -q '^CONFIG_ROCKCHIP_RV1103B=y' .config ; then
MAX_ADDR_VAL=$((0x20000000))
else
@ -19,7 +21,7 @@ MAX_ADDR_VAL=$((0xf0000000))
fi
# dram base
DRAM_BASE_VAL=$((DRAM_BASE))
DRAM_BASE_VAL=`sed -n "/CONFIG_SYS_SDRAM_BASE=/s/CONFIG_SYS_SDRAM_BASE=//p" ${srctree}/include/autoconf.mk|tr -d '\r'`
# compression
if [ "${COMPRESSION}" == "gzip" ]; then
@ -247,8 +249,8 @@ function gen_mcu_node()
# When allow to be compressed?
# DRAM base < load addr < Periph register base
# Periph register base < DRAM base < load addr
if [ "${COMPRESSION}" != "none" -a ${MCU_ADDR_VAL} -gt ${DRAM_BASE_VAL} ] &&
[ ${DRAM_BASE_VAL} -gt ${MAX_ADDR_VAL} -o ${MCU_ADDR_VAL} -lt ${MAX_ADDR_VAL} ]; then
if [ "${COMPRESSION}" != "none" -a "$((MCU_ADDR_VAL))" -gt "$((DRAM_BASE_VAL))" ] &&
[ "$((DRAM_BASE_VAL))" -gt "$((MAX_ADDR_VAL))" -o "$((MCU_ADDR_VAL))" -lt "$((MAX_ADDR_VAL))" ]; then
openssl dgst -sha256 -binary -out ${MCU}.bin.digest ${MCU}.bin
${COMPRESS_CMD} ${MCU}.bin
echo " data = /incbin/(\"./${MCU}.bin${SUFFIX}\");
@ -277,6 +279,24 @@ function gen_mcu_node()
STANDALONE_SIGN=", \"standalone\""
STANDALONE_MCU="standalone = ${STANDALONE_LIST};"
done
if [ -z ${INIT0_LOAD_ADDR} ]; then
return
fi
INIT="init0"
echo " ${INIT} {
description = \"${INIT}\";
type = \"standalone\";
arch = \"${ARCH}\";
load = <"${INIT0_LOAD_ADDR}">;
data = /incbin/(\"./${INIT}.bin\");
compression = \"none\";
hash {
algo = \"sha256\";
};
};"
STANDALONE_MCU="standalone = \"init0\"${STANDALONE_LIST};"
}
function gen_loadable_node()
@ -310,8 +330,8 @@ function gen_loadable_node()
# When allow to be compressed?
# DRAM base < load addr < Periph register base
# Periph register base < DRAM base < load addr
if [ "${COMPRESSION}" != "none" -a ${LOAD_ADDR_VAL} -gt ${DRAM_BASE_VAL} ] &&
[ ${DRAM_BASE_VAL} -gt ${MAX_ADDR_VAL} -o ${LOAD_ADDR_VAL} -lt ${MAX_ADDR_VAL} ]; then
if [ "${COMPRESSION}" != "none" -a "$((MCU_ADDR_VAL))" -gt "$((DRAM_BASE_VAL))" ] &&
[ "$((DRAM_BASE_VAL))" -gt "$((MAX_ADDR_VAL))" -o "$((MCU_ADDR_VAL))" -lt "$((MAX_ADDR_VAL))" ]; then
openssl dgst -sha256 -binary -out ${LOAD}.bin.digest ${LOAD}.bin
${COMPRESS_CMD} ${LOAD}.bin
echo " data = /incbin/(\"./${LOAD}.bin${SUFFIX}\");

2
u-boot/arch/arm/mach-rockchip/rk3399/rk3399.c
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@ -138,7 +138,7 @@ void board_debug_uart_init(void)
/* Enable early UART2 channel on the RK3399/RK3399PRO */
rk_clrsetreg(&grf->gpio4c_iomux,
GRF_GPIO4C3_SEL_MASK,
GRF_UART2DGBC_SIN << GRF_GPIO4C3_SEL_SHIFT);
GRF_UART2DBGC_SIN << GRF_GPIO4C3_SEL_SHIFT);
rk_clrsetreg(&grf->gpio4c_iomux,
GRF_GPIO4C4_SEL_MASK,
GRF_UART2DBGC_SOUT << GRF_GPIO4C4_SEL_SHIFT);

27
u-boot/arch/arm/mach-rockchip/rk3506/rk3506.c
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@ -16,7 +16,8 @@
DECLARE_GLOBAL_DATA_PTR;
#define GRF_BASE 0xff288000
#define GRF_SOC_CON28 0X0070
#define GRF_SOC_CON6 0x0018
#define GRF_SOC_CON28 0x0070
#define USBPHY_APB_BASE 0xff2b0000
#define USBPHY_DIFF_RECEIVER_0 0x0030
@ -25,6 +26,13 @@ DECLARE_GLOBAL_DATA_PTR;
#define FIREWALL_DDR_BASE 0xff5f0000
#define FW_DDR_MST1_REG 0x24
#define DSI_HOST_BASE 0xff640000
#define MIPS_DSI_PHY_RSTZ 0xa0
#define DPHY_BASE 0xff670000
#define MIPI_TX_PHY_TTL_MODE_CTRL2 0x38c
#define MIPI_TX_PHY_TTL_MODE_CTRL4 0x3ac
#define GPIO0_IOC_BASE 0xff950000
#define GPIO1_IOC_BASE 0xff660000
@ -39,6 +47,7 @@ DECLARE_GLOBAL_DATA_PTR;
#define CRU_BASE 0xff9a0000
#define CRU_GLB_RST_CON 0xc10
#define CRU_GATE_CON1 0x0804
#define CRU_GATE_CON5 0x0814
#define CRU_SOFTRST_CON5 0x0a14
@ -157,6 +166,21 @@ int arch_cpu_init(void)
writel(0x01ff01d1, GRF_BASE + GRF_SOC_CON28);
writel(0x00000079, USBPHY_APB_BASE + USBPHY_DIFF_RECEIVER_0);
writel(0x00000079, USBPHY_APB_BASE + USBPHY_DIFF_RECEIVER_1);
/*
* Set mcu jtag clock un-gate.
* Configure when in use.
*/
//writel(0x00220000, 0xff960000);
/*
* gpio4Ax is used as MIPI by default.
* The following command switches MIPI to gpio.
*/
//writel(0x03000300, GRF_BASE + GRF_SOC_CON6);
//writel(0x4, DSI_HOST_BASE + MIPS_DSI_PHY_RSTZ);
//writel(0x4, DPHY_BASE + MIPI_TX_PHY_TTL_MODE_CTRL2);
//writel(0xfd, DPHY_BASE + MIPI_TX_PHY_TTL_MODE_CTRL4);
#endif
return 0;
}
@ -183,7 +207,6 @@ int fit_standalone_release(char *id, uintptr_t entry_point)
writel(0x00060004, 0xff90000c);
/* select jtag m1 GPIO0C6 GPIO0C7 */
//writel(0x00220000, 0xff960000);
//writel(0x00300020, 0xff288000);
//writel(0x00ff0022, 0xff4d8064);
//writel(0xff002200, 0xff950014);

16
u-boot/arch/arm/mach-rockchip/rk3568/rk3568.c
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@ -61,6 +61,13 @@ DECLARE_GLOBAL_DATA_PTR;
#define EBC_PRIORITY_REG (0xfe158008)
#define SATA0_BASE_ADDR 0xfc000000
#define SATA1_BASE_ADDR 0xfc400000
#define SATA2_BASE_ADDR 0xfc800000
#define SATA_PI 0xC
#define SATA_PORT_CMD 0x118
#define SATA_FBS_ENABLE BIT(22)
enum {
/* PMU_GRF_GPIO0C_IOMUX_L */
GPIO0C1_SHIFT = 4,
@ -945,6 +952,15 @@ int arch_cpu_init(void)
writel((0x77771111), GRF_BASE + GRF_GPIO1C_IOMUX_L);
writel((0x07770111), GRF_BASE + GRF_GPIO1C_IOMUX_H);
#endif
/*
* Set SATA FBSCP and PORTS_IMPL for kernel drivers
*/
writel(SATA_FBS_ENABLE, SATA0_BASE_ADDR + SATA_PORT_CMD);
writel(1, SATA0_BASE_ADDR + SATA_PI);
writel(SATA_FBS_ENABLE, SATA1_BASE_ADDR + SATA_PORT_CMD);
writel(1, SATA1_BASE_ADDR + SATA_PI);
writel(SATA_FBS_ENABLE, SATA2_BASE_ADDR + SATA_PORT_CMD);
writel(1, SATA2_BASE_ADDR + SATA_PI);
#endif
return 0;

16
u-boot/arch/arm/mach-rockchip/rk3576/rk3576.c
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@ -94,6 +94,12 @@ DECLARE_GLOBAL_DATA_PTR;
#define PMU1_CRU_GATE_CON03 0x080C
#define PMU1_CRU_SOFTRST_CON03 0x0a0C
#define SATA0_BASE_ADDR 0x2a240000
#define SATA1_BASE_ADDR 0x2a250000
#define SATA_PI 0xC
#define SATA_PORT_CMD 0x118
#define SATA_FBS_ENABLE BIT(22)
#ifdef CONFIG_ARM64
#include <asm/armv8/mmu.h>
@ -121,7 +127,7 @@ static struct mm_region rk3576_mem_map[] = {
}, {
.virt = 0x100000000UL,
.phys = 0x100000000UL,
.size = 0x300000000UL,
.size = 0x400000000UL,
.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
PTE_BLOCK_INNER_SHARE
}, {
@ -400,6 +406,14 @@ int arch_cpu_init(void)
* Module: GMAC0/1, MMU0/1(PCIe, SATA, USB3)
*/
writel(0xffffff00, SYS_SGRF_BASE + SYS_SGRF_SOC_CON20);
#else
/*
* Set SATA FBSCP and PORTS_IMPL for kernel drivers
*/
writel(SATA_FBS_ENABLE, SATA0_BASE_ADDR + SATA_PORT_CMD);
writel(1, SATA0_BASE_ADDR + SATA_PI);
writel(SATA_FBS_ENABLE, SATA1_BASE_ADDR + SATA_PORT_CMD);
writel(1, SATA1_BASE_ADDR + SATA_PI);
#endif
#if defined(CONFIG_ROCKCHIP_EMMC_IOMUX)

17
u-boot/arch/arm/mach-rockchip/rk3588/rk3588.c
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@ -102,6 +102,13 @@ DECLARE_GLOBAL_DATA_PTR;
#define MMU600PHP_TCU_PRIORITY_REG 0xfdf3a808
#define QOS_PRIORITY_LEVEL(h, l) ((((h) & 7) << 8) | ((l) & 7))
#define SATA0_BASE_ADDR 0xfe210000
#define SATA1_BASE_ADDR 0xfe220000
#define SATA2_BASE_ADDR 0xfe230000
#define SATA_PI 0xC
#define SATA_PORT_CMD 0x118
#define SATA_FBS_ENABLE BIT(22)
#ifdef CONFIG_ARM64
#include <asm/armv8/mmu.h>
@ -1067,6 +1074,16 @@ int arch_cpu_init(void)
*/
writel(QOS_PRIORITY_LEVEL(4, 4), MMU600PHP_TBU_PRIORITY_REG);
writel(QOS_PRIORITY_LEVEL(4, 4), MMU600PHP_TCU_PRIORITY_REG);
/*
* Set SATA FBSCP and PORTS_IMPL for kernel drivers
*/
writel(SATA_FBS_ENABLE, SATA0_BASE_ADDR + SATA_PORT_CMD);
writel(1, SATA0_BASE_ADDR + SATA_PI);
writel(SATA_FBS_ENABLE, SATA1_BASE_ADDR + SATA_PORT_CMD);
writel(1, SATA1_BASE_ADDR + SATA_PI);
writel(SATA_FBS_ENABLE, SATA2_BASE_ADDR + SATA_PORT_CMD);
writel(1, SATA2_BASE_ADDR + SATA_PI);
#endif
/* Select usb otg0 phy status to 0 that make rockusb can work at high-speed */

17
u-boot/arch/arm/mach-rockchip/rv1126b/Kconfig
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@ -0,0 +1,17 @@
if ROCKCHIP_RV1126B
config TARGET_EVB_RV1126B
bool "EVB_RV1126B"
select BOARD_LATE_INIT
help
RV1126B EVB is a evaluation board for Rockchp RV1126B.
config SYS_SOC
default "rockchip"
config SYS_MALLOC_F_LEN
default 0x400
source board/rockchip/evb_rv1126b/Kconfig
endif

11
u-boot/arch/arm/mach-rockchip/rv1126b/Makefile
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@ -0,0 +1,11 @@
#
# (C) Copyright 2025 Rockchip Electronics Co., Ltd
#
# SPDX-License-Identifier: GPL-2.0+
#
ifneq ($(CONFIG_TPL_BUILD)$(CONFIG_TPL_TINY_FRAMEWORK),yy)
obj-y += syscon_rv1126b.o
endif
obj-y += rv1126b.o
obj-y += clk_rv1126b.o

41
u-boot/arch/arm/mach-rockchip/rv1126b/clk_rv1126b.c
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@ -0,0 +1,41 @@
/*
* (C) Copyright 2025 Rockchip Electronics Co., Ltd.
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <dm.h>
#include <syscon.h>
#include <asm/arch/clock.h>
#include <asm/arch/cru_rv1126b.h>
int rockchip_get_clk(struct udevice **devp)
{
return uclass_get_device_by_driver(UCLASS_CLK,
DM_GET_DRIVER(rockchip_rv1126b_cru), devp);
}
#if CONFIG_IS_ENABLED(CLK_SCMI)
int rockchip_get_scmi_clk(struct udevice **devp)
{
return uclass_get_device_by_driver(UCLASS_CLK,
DM_GET_DRIVER(scmi_clock), devp);
}
#endif
void *rockchip_get_cru(void)
{
struct rv1126b_clk_priv *priv;
struct udevice *dev;
int ret;
ret = rockchip_get_clk(&dev);
if (ret)
return ERR_PTR(ret);
priv = dev_get_priv(dev);
return priv->cru;
}

360
u-boot/arch/arm/mach-rockchip/rv1126b/rv1126b.c
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@ -0,0 +1,360 @@
/*
* Copyright (c) 2025 Rockchip Electronics Co., Ltd
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <dm.h>
#include <misc.h>
#include <mmc.h>
#include <spl.h>
#include <asm/io.h>
#include <asm/arch/cpu.h>
#include <asm/arch/hardware.h>
#include <asm/arch/grf_rv1126b.h>
#include <asm/arch/ioc_rv1126b.h>
#include <asm/system.h>
DECLARE_GLOBAL_DATA_PTR;
/* CRU */
#define CRU_BUS_BASE 0x20010000
#define CRU_BUS_GATE_CON06 0x818
#define CRU_BUS_SOFTRST_CON01 0x0a04
#define CRU_PMU_BASE 0x20040000
#define CRU_PMU_SOFTRST_CON03 0x0a0c
#define PERI_CRU_BASE 0x20020000
#define PERICRU_PERI_SOFTRST_CON01 0x0a04
/* GRF */
#define SYS_GRF_BASE 0x20100000
#define TSADC_GRF_CON0 0x50
#define TSADC_GRF_CON1 0x54
#define TSADC_GRF_CON6 0x68
#define GRF_JTAG_CON0 0x904
#define PERI_GRF_BASE 0x20110000
#define PERI_GRF_USB2HOSTPHY_CON0 0x001c
#define PERI_GRF_USB3DRD_CON1 0x003C
#define VI_GRF_BASE 0x20150000
#define SARADC1_GRF_CON0 0x80
#define SARADC2_GRF_CON0 0x90
#define VEPU_GRF_BASE 0x20160000
#define SARADC0_GRF_CON0 0x0C
/* PMU */
#define PMU_GRF_BASE 0x20130000
#define PMU_GRF_SOC_CON0 0x0000
#define PMU2_BASE 0x20838000
#define PMU2_PWR_GATE_SFTCON0 0x0210
/* GPIO/IOC */
#define GPIO0_BASE 0x20600000
#define GPIO_SWPORT_DR_L 0x00
#define GPIO_SWPORT_DDR_L 0x08
#define PMUIO0_IOC_BASE 0x201a0000
#define GPIO0A_IOMUX_SEL_L 0x0
#define GPIO0A_IOMUX_SEL_H 0x4
#define GPIO0B_IOMUX_SEL_L 0x8
#define VCCIO1_IOC_BASE 0x201b0000
#define GPIO1A_IOMUX_SEL_L 0x20
#define GPIO1A_IOMUX_SEL_H 0x24
#define GPIO1B_IOMUX_SEL_L 0x28
#define GPIO1B_IOMUX_SEL_H 0x2c
#define VCCIO2_IOC_BASE 0x201b8000
#define GPIO2A_IOMUX_SEL_L 0x40
#define GPIO2A_IOMUX_SEL_H 0x44
#define GPIO2A_PULL 0x320
#define VCCIO3_IOC_BASE 0x201c0000
#define GPIO3A_IOMUX_SEL_L 0x60
#define GPIO3A_IOMUX_SEL_H 0x64
#define GPIO3B_IOMUX_SEL_H 0x6c
#define GPIO3A_PULL 0x330
/* SGRF/FIREWALL */
#define SGRF_SYS_BASE 0x20220000
#define SGRF_HPMCU_BOOT_ADDR 0x0c
#define SGRF_SYS_AHB_SECURE_SGRF_CON 0x14
#define SGRF_SYS_AXI_SECURE_SGRF_CON0 0x18
#define FIREWALL_SLV_CON0 0x20
#define FIREWALL_SLV_CON1 0x24
#define FIREWALL_SLV_CON2 0x28
#define FIREWALL_SLV_CON3 0x2c
#define FIREWALL_SLV_CON4 0x30
#define FIREWALL_SLV_CON5 0x34
#define OTP_SGRF_CON 0x1c
#define SGRF_PMU_BASE 0x20230000
#define SGRF_PMU_SOC_CON0 0x00
#define SGRF_LPMCU_BOOT_ADDR 0x20
#ifdef CONFIG_ARM64
#include <asm/armv8/mmu.h>
static struct mm_region rv1126b_mem_map[] = {
{
.virt = 0x20000000UL,
.phys = 0x20000000UL,
.size = 0x2800000UL,
.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
PTE_BLOCK_NON_SHARE |
PTE_BLOCK_PXN | PTE_BLOCK_UXN
}, {
.virt = 0x3ff1e000UL,
.phys = 0x3ff1e000UL,
.size = 0xe2000UL,
.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
PTE_BLOCK_NON_SHARE |
PTE_BLOCK_PXN | PTE_BLOCK_UXN
}, {
.virt = 0x40000000UL,
.phys = 0x40000000UL,
.size = 0x100000000UL - 0x40000000UL,
.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
PTE_BLOCK_INNER_SHARE
}, {
/* List terminator */
0,
}
};
struct mm_region *mem_map = rv1126b_mem_map;
#endif
void board_debug_uart_init(void)
{
/* No need to change uart in most time. */
}
void board_set_iomux(enum if_type if_type, int devnum, int routing)
{
switch (if_type) {
case IF_TYPE_MMC:
if (devnum == 0) {
writel(0xffff1111, VCCIO1_IOC_BASE + GPIO1A_IOMUX_SEL_L);
writel(0xffff1111, VCCIO1_IOC_BASE + GPIO1A_IOMUX_SEL_H);
writel(0xf0f01010, VCCIO1_IOC_BASE + GPIO1B_IOMUX_SEL_L);
} else if (devnum == 1) {
#if CONFIG_SPL_BUILD
/* set SDMMC D0-3/CMD/CLK to gpio and pull down */
writel(0xffff0000, VCCIO2_IOC_BASE + GPIO2A_IOMUX_SEL_L);
writel(0x00ff0000, VCCIO2_IOC_BASE + GPIO2A_IOMUX_SEL_H);
writel(0x00f00000, PMUIO0_IOC_BASE + GPIO0A_IOMUX_SEL_H);
writel(0x0fff0aaa, VCCIO2_IOC_BASE + GPIO2A_PULL);
/* SDMMC PWREN GPIO0A4 power down and power up */
writel(0x01000100, GPIO0_BASE + GPIO_SWPORT_DR_L);
writel(0x01000100, GPIO0_BASE + GPIO_SWPORT_DDR_L);
mdelay(50);
writel(0x01000000, GPIO0_BASE + GPIO_SWPORT_DR_L);
#endif
/* set SDMMC D0-3/CMD/CLK and pull up */
writel(0xffff1111, VCCIO2_IOC_BASE + GPIO2A_IOMUX_SEL_L);
writel(0x00ff0011, VCCIO2_IOC_BASE + GPIO2A_IOMUX_SEL_H);
writel(0x00f00010, PMUIO0_IOC_BASE + GPIO0A_IOMUX_SEL_H);
writel(0x0fff0555, VCCIO2_IOC_BASE + GPIO2A_PULL);
} else if (devnum == 2) {
writel(0xffff1111, VCCIO3_IOC_BASE + GPIO3A_IOMUX_SEL_L);
writel(0x00ff0011, VCCIO3_IOC_BASE + GPIO3A_IOMUX_SEL_H);
writel(0x0f000300, VCCIO3_IOC_BASE + GPIO3B_IOMUX_SEL_H);
/* Pull up */
writel(0x0ffc0554, VCCIO2_IOC_BASE + GPIO3A_PULL);
}
break;
case IF_TYPE_MTD:
if (routing == 0) {
/* FSPI0 M0 */
writel(0x0f0f0101, VCCIO1_IOC_BASE + GPIO1B_IOMUX_SEL_L);
writel(0xffff1111, VCCIO1_IOC_BASE + GPIO1B_IOMUX_SEL_H);
writel(0x00f00020, VCCIO1_IOC_BASE + GPIO1A_IOMUX_SEL_H);
} else if (routing == 1) {
/* FSPI1 M0 */
writel(0x0fff0111, PMUIO0_IOC_BASE + GPIO0B_IOMUX_SEL_L);
writel(0xff001100, PMUIO0_IOC_BASE + GPIO0A_IOMUX_SEL_H);
writel(0x00f00010, PMUIO0_IOC_BASE + GPIO0A_IOMUX_SEL_L);
} else if (routing == 2) {
/* FSPI1 M1 */
writel(0xffff2222, VCCIO1_IOC_BASE + GPIO1A_IOMUX_SEL_L);
writel(0xf0f02020, VCCIO1_IOC_BASE + GPIO1B_IOMUX_SEL_L);
}
break;
default:
printf("Bootdev 0x%x is not support\n", if_type);
}
}
void board_unset_iomux(enum if_type if_type, int devnum, int routing)
{
switch (if_type) {
case IF_TYPE_MMC:
if (devnum == 0) {
writel(0xffff0000, VCCIO1_IOC_BASE + GPIO1A_IOMUX_SEL_L);
writel(0xffff0000, VCCIO1_IOC_BASE + GPIO1A_IOMUX_SEL_H);
writel(0xf0f00000, VCCIO1_IOC_BASE + GPIO1B_IOMUX_SEL_L);
} else if (devnum == 1) {
/* SDMMC0_D2,D3 -> JTAG_TMS_M1, JTAG_TCK_M1 */
writel(0xffff4400, VCCIO2_IOC_BASE + GPIO2A_IOMUX_SEL_L);
/* Other SDMMC0 PINS -> GPIO */
writel(0x00ff0000, VCCIO2_IOC_BASE + GPIO2A_IOMUX_SEL_H);
writel(0x00f00000, PMUIO0_IOC_BASE + GPIO0A_IOMUX_SEL_H);
/* Pull down */
writel(0x0fff0aaa, VCCIO2_IOC_BASE + GPIO2A_PULL);
} else if (devnum == 2) {
writel(0xffff0000, VCCIO3_IOC_BASE + GPIO3A_IOMUX_SEL_L);
writel(0x00ff0000, VCCIO3_IOC_BASE + GPIO3A_IOMUX_SEL_H);
writel(0x0f000000, VCCIO3_IOC_BASE + GPIO3B_IOMUX_SEL_H);
/* Pull down */
writel(0x0ffc0000, VCCIO2_IOC_BASE + GPIO3A_PULL);
}
break;
case IF_TYPE_MTD:
if (routing == 0) {
/* FSPI0 M0 */
writel(0x0f0f0000, VCCIO1_IOC_BASE + GPIO1B_IOMUX_SEL_L);
writel(0xffff0000, VCCIO1_IOC_BASE + GPIO1B_IOMUX_SEL_H);
writel(0x00f00000, VCCIO1_IOC_BASE + GPIO1A_IOMUX_SEL_H);
} else if (routing == 1) {
/* FSPI1 M0 */
writel(0x0fff0000, PMUIO0_IOC_BASE + GPIO0B_IOMUX_SEL_L);
writel(0xff000000, PMUIO0_IOC_BASE + GPIO0A_IOMUX_SEL_H);
writel(0x00f00000, PMUIO0_IOC_BASE + GPIO0A_IOMUX_SEL_L);
} else if (routing == 2) {
/* FSPI1 M1 */
writel(0xffff0000, VCCIO1_IOC_BASE + GPIO1A_IOMUX_SEL_L);
writel(0xf0f00000, VCCIO1_IOC_BASE + GPIO1B_IOMUX_SEL_L);
}
break;
default:
break;
}
}
#ifdef CONFIG_SPL_BUILD
void rockchip_stimer_init(void)
{
u32 reg;
/* If Timer already enabled, don't re-init it */
reg = readl(CONFIG_ROCKCHIP_STIMER_BASE + 0x4);
if (reg & 0x1)
return;
#ifdef COUNTER_FREQUENCY
asm volatile("msr CNTFRQ_EL0, %0" : : "r" (COUNTER_FREQUENCY));
#endif
writel(0xffffffff, CONFIG_ROCKCHIP_STIMER_BASE + 0x14);
writel(0xffffffff, CONFIG_ROCKCHIP_STIMER_BASE + 0x18);
writel(0x00010001, CONFIG_ROCKCHIP_STIMER_BASE + 0x04);
}
void spl_board_storages_fixup(struct spl_image_loader *loader)
{
if (!loader)
return;
if (loader->boot_device == BOOT_DEVICE_MMC2)
/* Unset the sdmmc0 iomux */
board_unset_iomux(IF_TYPE_MMC, 1, 0);
}
int spl_fit_standalone_release(char *id, uintptr_t entry_point)
{
if (!strcmp(id, "mcu0")) {
writel(0x1e001e0, CRU_BUS_BASE + CRU_BUS_SOFTRST_CON01);
writel(entry_point, SGRF_SYS_BASE + SGRF_HPMCU_BOOT_ADDR);
writel(0x1 << 20, SGRF_SYS_BASE + SGRF_SYS_AHB_SECURE_SGRF_CON);
writel(0x1e00000, CRU_BUS_BASE + CRU_BUS_SOFTRST_CON01);
} else if (!strcmp(id, "mcu1")) {
writel(0x1c001c, CRU_PMU_BASE + CRU_PMU_SOFTRST_CON03);
writel(entry_point, SGRF_PMU_BASE + SGRF_LPMCU_BOOT_ADDR);
writel(0x1 << 23, SGRF_PMU_BASE + SGRF_PMU_SOC_CON0);
writel(0x1c0000, CRU_PMU_BASE + CRU_PMU_SOFTRST_CON03);
}
return 0;
}
#endif
#ifndef CONFIG_TPL_BUILD
int arch_cpu_init(void)
{
#if defined(CONFIG_SPL_BUILD) || defined(CONFIG_SUPPORT_USBPLUG)
/* Enable npu pd */
writel(0x00010000, PMU2_BASE + PMU2_PWR_GATE_SFTCON0);
/* Set emmc master secure */
writel(0x10000, SGRF_SYS_BASE + SGRF_SYS_AHB_SECURE_SGRF_CON);
/* Set fspi master secure */
writel(0x20000, SGRF_SYS_BASE + SGRF_SYS_AHB_SECURE_SGRF_CON);
/* Set sdmmc0 master secure */
writel(0x40000, SGRF_SYS_BASE + SGRF_SYS_AHB_SECURE_SGRF_CON);
/* Set sdmmc1 master secure */
writel(0x80000, SGRF_SYS_BASE + SGRF_SYS_AHB_SECURE_SGRF_CON);
/* Set rkce master secure */
writel(0x80030000, SGRF_SYS_BASE + SGRF_SYS_AXI_SECURE_SGRF_CON0);
/* Set decom master secure */
writel(0xC00000, SGRF_SYS_BASE + SGRF_SYS_AXI_SECURE_SGRF_CON0);
/* Set all devices slave non-secure */
writel(0xffff0000, SGRF_SYS_BASE + FIREWALL_SLV_CON0);
writel(0xffff0000, SGRF_SYS_BASE + FIREWALL_SLV_CON1);
writel(0xffff0000, SGRF_SYS_BASE + FIREWALL_SLV_CON2);
writel(0xffff0000, SGRF_SYS_BASE + FIREWALL_SLV_CON3);
writel(0xffff0000, SGRF_SYS_BASE + FIREWALL_SLV_CON4);
writel(0xffff0000, SGRF_SYS_BASE + FIREWALL_SLV_CON5);
/* Set OTP to none secure mode */
writel(0x00020000, SGRF_SYS_BASE + OTP_SGRF_CON);
/* Set usb3phy clamp enable */
writel(0x40000000, PMU_GRF_BASE + PMU_GRF_SOC_CON0);
/* Assert the pipe phy reset and de-assert when in use */
writel(0x00800080, PERI_CRU_BASE + PERICRU_PERI_SOFTRST_CON01);
/* Restore pipe phy status to default from phy */
writel(0xffff1100, PERI_GRF_BASE + PERI_GRF_USB3DRD_CON1);
/* Set the USB 2.0 PHY Port1 to enter the sleep mode to save power consumption */
writel(0x01ff01d1, PERI_GRF_BASE + PERI_GRF_USB2HOSTPHY_CON0);
/* Enable tsadc phy */
writel(0x01000000, CRU_BUS_BASE + CRU_BUS_GATE_CON06);
writel(0x80788028, SYS_GRF_BASE + TSADC_GRF_CON0);
writel(0xff000300, SYS_GRF_BASE + TSADC_GRF_CON6);
writel(0x00ff00a5, SYS_GRF_BASE + TSADC_GRF_CON1);
writel(0x01000100, SYS_GRF_BASE + TSADC_GRF_CON1);
writel(0x01000000, SYS_GRF_BASE + TSADC_GRF_CON1);
/* set saradc ibp to 7 */
writel(0x00700070, VEPU_GRF_BASE + SARADC0_GRF_CON0);
writel(0x00700070, VI_GRF_BASE + SARADC1_GRF_CON0);
writel(0x00700070, VI_GRF_BASE + SARADC2_GRF_CON0);
#if defined(CONFIG_ROCKCHIP_EMMC_IOMUX)
board_set_iomux(IF_TYPE_MMC, 0, 0);
#elif defined(CONFIG_ROCKCHIP_SFC_IOMUX)
/*
* (IF_TYPE_MTD, 0, 0) FSPI0
* (IF_TYPE_MTD, 1, 0) FSPI1 M0
* (IF_TYPE_MTD, 2, 0) FSPI1 M1
*/
board_set_iomux(IF_TYPE_MTD, 0, 0);
#endif /* CONFIG_ROCKCHIP_EMMC_IOMUX */
#if defined(CONFIG_MMC_DW_ROCKCHIP)
/* Set the sdmmc iomux and power cycle */
board_set_iomux(IF_TYPE_MMC, 1, 0);
#endif
#endif
return 0;
}
#endif
#if defined(CONFIG_ROCKCHIP_EMMC_IOMUX) && defined(CONFIG_ROCKCHIP_SFC_IOMUX)
#error FSPI0 M0 and eMMC iomux is incompatible for rv1126b Soc. You should close one of them.
#endif

25
u-boot/arch/arm/mach-rockchip/rv1126b/syscon_rv1126b.c
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@ -0,0 +1,25 @@
/*
* (C) Copyright 2025 Rockchip Electronics Co., Ltd
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <dm.h>
#include <syscon.h>
#include <asm/arch/clock.h>
static const struct udevice_id rv1126b_syscon_ids[] = {
{ .compatible = "rockchip,rv1126b-grf", .data = ROCKCHIP_SYSCON_GRF },
{ .compatible = "rockchip,rv1126b-ioc-grf", .data = ROCKCHIP_SYSCON_IOC },
{ }
};
U_BOOT_DRIVER(syscon_rv1126b) = {
.name = "rv1126b_syscon",
.id = UCLASS_SYSCON,
.of_match = rv1126b_syscon_ids,
#if !CONFIG_IS_ENABLED(OF_PLATDATA)
.bind = dm_scan_fdt_dev,
#endif
};

4
u-boot/arch/arm/mach-rockchip/sdram.c
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@ -193,9 +193,9 @@ int dram_init(void)
}
#endif
ulong board_get_usable_ram_top(ulong total_size)
uint64_t board_get_usable_ram_top(ulong total_size)
{
unsigned long top = CONFIG_SYS_SDRAM_BASE + SDRAM_MAX_SIZE;
uint64_t top = CONFIG_SYS_SDRAM_BASE + SDRAM_MAX_SIZE;
return (gd->ram_top > top) ? top : gd->ram_top;
}

5
u-boot/board/rockchip/evb_rk3576/evb_rk3576.c
Unescape View File

@ -16,6 +16,7 @@ DECLARE_GLOBAL_DATA_PTR;
#ifdef CONFIG_USB_DWC3
#define CRU_BASE 0x27200000
#define CRU_SOFTRST_CON47 0x0abc
#define U3PHY_BASE 0x2b010000
static struct dwc3_device dwc3_device_data = {
.maximum_speed = USB_SPEED_SUPER,
@ -57,14 +58,14 @@ int board_usb_init(int index, enum usb_init_type init)
if (rkusb_switch_usb3_enabled()) {
dwc3_device_data.maximum_speed = USB_SPEED_SUPER;
ret = rockchip_u3phy_uboot_init();
ret = rockchip_u3phy_uboot_init(U3PHY_BASE);
if (ret) {
rkusb_force_to_usb2(true);
dwc3_device_data.maximum_speed = USB_SPEED_HIGH;
}
}
#else
ret = rockchip_u3phy_uboot_init();
ret = rockchip_u3phy_uboot_init(U3PHY_BASE);
if (ret) {
rkusb_force_to_usb2(true);
dwc3_device_data.maximum_speed = USB_SPEED_HIGH;

5
u-boot/board/rockchip/evb_rk3588/evb_rk3588.c
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@ -16,6 +16,7 @@ DECLARE_GLOBAL_DATA_PTR;
#ifdef CONFIG_USB_DWC3
#define CRU_BASE 0xfd7c0000
#define CRU_SOFTRST_CON42 0x0aa8
#define U3PHY_BASE 0xfed80000
static struct dwc3_device dwc3_device_data = {
.maximum_speed = USB_SPEED_SUPER,
@ -57,14 +58,14 @@ int board_usb_init(int index, enum usb_init_type init)
if (rkusb_switch_usb3_enabled()) {
dwc3_device_data.maximum_speed = USB_SPEED_SUPER;
ret = rockchip_u3phy_uboot_init();
ret = rockchip_u3phy_uboot_init(U3PHY_BASE);
if (ret) {
rkusb_force_to_usb2(true);
dwc3_device_data.maximum_speed = USB_SPEED_HIGH;
}
}
#else
ret = rockchip_u3phy_uboot_init();
ret = rockchip_u3phy_uboot_init(U3PHY_BASE);
if (ret) {
rkusb_force_to_usb2(true);
dwc3_device_data.maximum_speed = USB_SPEED_HIGH;

15
u-boot/board/rockchip/evb_rv1126b/Kconfig
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@ -0,0 +1,15 @@
if TARGET_EVB_RV1126B
config SYS_BOARD
default "evb_rv1126b"
config SYS_VENDOR
default "rockchip"
config SYS_CONFIG_NAME
default "evb_rv1126b"
config BOARD_SPECIFIC_OPTIONS # dummy
def_bool y
endif

7
u-boot/board/rockchip/evb_rv1126b/Makefile
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@ -0,0 +1,7 @@
#
# SPDX-License-Identifier: GPL-2.0+
#
# Copyright (c) 2025 Rockchip Electronics Co., Ltd
#
obj-y += evb_rv1126b.o

33
u-boot/board/rockchip/evb_rv1126b/evb_rv1126b.c
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@ -0,0 +1,33 @@
/*
* SPDX-License-Identifier: GPL-2.0+
*
* (C) Copyright 2025 Rockchip Electronics Co., Ltd
*/
#include <common.h>
#include <dwc3-uboot.h>
#include <usb.h>
DECLARE_GLOBAL_DATA_PTR;
#ifdef CONFIG_USB_DWC3
static struct dwc3_device dwc3_device_data = {
.maximum_speed = USB_SPEED_HIGH,
.base = 0x21500000,
.dr_mode = USB_DR_MODE_PERIPHERAL,
.index = 0,
.dis_u2_susphy_quirk = 1,
.usb2_phyif_utmi_width = 16,
};
int usb_gadget_handle_interrupts(void)
{
dwc3_uboot_handle_interrupt(0);
return 0;
}
int board_usb_init(int index, enum usb_init_type init)
{
return dwc3_uboot_init(&dwc3_device_data);
}
#endif

13
u-boot/cmd/blk_common.c
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@ -89,6 +89,19 @@ int blk_common_cmd(int argc, char * const argv[], enum if_type if_type,
n = blk_write_devnum(if_type, *cur_devnump, blk, cnt,
(ulong *)addr);
printf("%ld blocks written: %s\n", n,
n == cnt ? "OK" : "ERROR");
return n == cnt ? 0 : 1;
} else if (strcmp(argv[1], "write_zeroes") == 0) {
lbaint_t blk = simple_strtoul(argv[2], NULL, 16);
ulong cnt = simple_strtoul(argv[3], NULL, 16);
ulong n;
printf("\n%s write_zeroes: device %d block # "LBAFU", count %lu ... ",
if_name, *cur_devnump, blk, cnt);
n = blk_write_zeroes_devnum(if_type, *cur_devnump, blk, cnt);
printf("%ld blocks written: %s\n", n,
n == cnt ? "OK" : "ERROR");
return n == cnt ? 0 : 1;

91
u-boot/cmd/crypto.c
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@ -68,6 +68,19 @@ struct rsa_test_data {
u32 sign_out_len;
};
struct ec_test_data {
const char *algo_name;
u32 algo;
const u8 *pub_x;
u32 pub_x_len;
const u8 *pub_y;
u32 pub_y_len;
const u8 *hash_in;
u32 hash_in_len;
const u8 *sign_in;
u32 sign_in_len;
};
#define IS_MAC_MODE(mode) ((mode) == RK_MODE_CBC_MAC || \
(mode) == RK_MODE_CMAC)
@ -152,6 +165,19 @@ struct rsa_test_data {
.sign_out_len = sizeof(out) \
}
#define EC_TEST(name, x, y, hash, sign) { \
.algo_name = #name, \
.algo = CRYPTO_##name, \
.pub_x = (x), \
.pub_x_len = sizeof(x), \
.pub_y = (y), \
.pub_y_len = sizeof(y), \
.hash_in = (hash), \
.hash_in_len = sizeof(hash), \
.sign_in = (sign), \
.sign_in_len = sizeof(sign), \
}
#define EMPTY_TEST() {}
const struct hash_test_data hash_data_set[] = {
@ -236,6 +262,15 @@ const struct rsa_test_data rsa_data_set[] = {
#endif
};
const struct ec_test_data ec_data_set[] = {
#if CONFIG_IS_ENABLED(ROCKCHIP_EC)
EC_TEST(ECC_192R1, ecc192r1_pub_x, ecc192r1_pub_y, ecc192r1_hash, ecc192r1_sign),
EC_TEST(SM2, sm2_pub_x, sm2_pub_y, sm2_hash, sm2_sign),
#else
EMPTY_TEST(),
#endif
};
static void dump_hex(const char *name, const u8 *array, u32 len)
{
int i;
@ -654,6 +689,58 @@ error:
return ret;
}
int test_ec_result(void)
{
const struct ec_test_data *test_data = NULL;
ulong start, time_cost;
struct udevice *dev;
ec_key ec_key;
int ret, i;
printf("\n====================== ec test ========================\n");
for (i = 0; i < ARRAY_SIZE(ec_data_set); i++) {
test_data = &ec_data_set[i];
if (test_data->algo == 0) {
printf("\n");
continue;
}
dev = crypto_get_device(test_data->algo);
if (!dev) {
printf("[%s] %-16s unsupported!!!\n",
test_data->algo_name, "");
continue;
}
/* verify test */
memset(&ec_key, 0x00, sizeof(ec_key));
ec_key.algo = test_data->algo;
ec_key.x = (u32 *)test_data->pub_x;
ec_key.y = (u32 *)test_data->pub_y;
start = get_timer(0);
ret = crypto_ec_verify(dev, &ec_key,
(u8 *)test_data->hash_in,
test_data->hash_in_len,
(u8 *)test_data->sign_in);
if (ret) {
printf("verify test error, ret = %d\n", ret);
goto error;
}
time_cost = get_timer(start);
printf("[%-9s] %-8s PASS (%lums)\n",
test_data->algo_name, "verify", time_cost);
printf("+++++++++++++++++++++++++++++++++++++++++++++++++++\n");
}
return 0;
error:
printf("%s test error!\n", test_data->algo_name);
return ret;
}
static int test_all_result(void)
{
int ret = 0;
@ -670,6 +757,10 @@ static int test_all_result(void)
if (ret)
goto exit;
ret = test_ec_result();
if (ret)
goto exit;
exit:
return 0;
}

1
u-boot/cmd/mmc.c
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@ -647,6 +647,7 @@ static int do_mmc_list(cmd_tbl_t *cmdtp, int flag,
int argc, char * const argv[])
{
print_mmc_devices('\n');
do_mmc_rescan(cmdtp, flag, argc, argv);
return CMD_RET_SUCCESS;
}

1
u-boot/cmd/nvme.c
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@ -54,4 +54,5 @@ U_BOOT_CMD(
" `blk#' to memory address `addr'\n"
"nvme write addr blk# cnt - write `cnt' blocks starting at block\n"
" `blk#' from memory address `addr'"
"nvme write_zeroes blk# cnt - write `cnt' blocks of zeroes starting at block\n"
);

15
u-boot/cmd/pci.c
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@ -507,6 +507,9 @@ static int do_pci(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
value = simple_strtoul(argv[4], NULL, 16);
case 'h': /* header */
case 'b': /* bars */
case 'a': /* AER */
case 'x': /* retrain link */
case 'f': /* FLR */
if (argc < 3)
goto usage;
if ((bdf = get_pci_dev(argv[2])) == -1)
@ -595,6 +598,12 @@ static int do_pci(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
break;
case 'b': /* bars */
return pci_bar_show(dev);
case 'a': /* AER */
return pci_aer_dump(dev, bdf);
case 'x': /* retrain link */
return pci_retrain_link(dev, bdf);
case 'f': /* do FLR */
return pci_reset_function(dev, bdf);
default:
ret = CMD_RET_USAGE;
break;
@ -611,6 +620,12 @@ static int do_pci(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
static char pci_help_text[] =
"[bus|*] [long]\n"
" - short or long list of PCI devices on bus 'bus'\n"
"pci aer b.d.f \n"
" - Dump PCI AER info\n"
"pci x b.d.f \n"
" - Retrain the link\n"
"pci f b.d.f \n"
" - Function level reset\n"
"pci enum\n"
" - Enumerate PCI buses\n"
"pci header b.d.f\n"

4
u-boot/common/android_ab.c
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@ -477,6 +477,7 @@ void ab_update_root_partition(void)
/* Judge the partition device type. */
switch (dev_desc->if_type) {
case IF_TYPE_MMC:
case IF_TYPE_SCSI: /* scsi 0: UFS */
if (strstr(part_type, "ENV"))
snprintf(root_part_dev, 64, "root=/dev/mmcblk0p%d", part_num);
else if (strstr(part_type, "EFI"))
@ -500,7 +501,8 @@ void ab_update_root_partition(void)
}
break;
default:
printf("%s: Not found part type, failed to set root part device.\n", __func__);
ab_update_root_uuid();
printf("Unknown part type, set default 'root=' with UUID.\n");
return;
}

2
u-boot/common/android_bootloader.c
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@ -965,7 +965,7 @@ out:
}
#endif
#if defined(CONFIG_CMD_DTIMG) && defined(CONFIG_OF_LIBFDT_OVERLAY)
#if defined(CONFIG_OF_LIBFDT_OVERLAY)
/*
* Default return index 0.

2
u-boot/common/board_f.c
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@ -272,7 +272,7 @@ __weak int mach_cpu_init(void)
}
/* Get the top of usable RAM */
__weak ulong board_get_usable_ram_top(ulong total_size)
__weak uint64_t board_get_usable_ram_top(ulong total_size)
{
#ifdef CONFIG_SYS_SDRAM_BASE
/*

2
u-boot/common/fdt_support.c
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@ -251,6 +251,8 @@ int fdt_initrd(void *fdt, ulong initrd_start, ulong initrd_end)
}
}
fdt_increase_size(fdt, 512);
err = fdt_add_mem_rsv(fdt, initrd_start, initrd_end - initrd_start);
if (err < 0) {
printf("fdt_initrd: %s\n", fdt_strerror(err));

4
u-boot/common/id_attestation.c
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@ -80,12 +80,10 @@ atap_result write_id_attestation_to_secure_storage(u8* received_data, uint32_t l
sizeof(AttestationIds));
MSG("read id attestation ret=%0x\n", ret);
if (ret == TEEC_SUCCESS) {
printf("id attestation already exsit,you cannot update it!");
printf("id attestation already exsit,let's update it!");
#if DEBUG
printAttestationIds(&ids_read);
#endif
ret = ATAP_RESULT_ERROR_ALREADY_EXSIT;
return ret;
}
ret = write_id_attestation(ids_file, &ids, ids_len);
printf("write id attestation : ret=%d\n", ret);

14
u-boot/common/spl/Kconfig
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@ -310,6 +310,14 @@ config SPL_CRYPTO_SUPPORT
this option to build the drivers in drivers/crypto as part of an
SPL build.
config SPL_KEYLAD_SUPPORT
bool "Support keylad drivers"
help
Enable keylad drivers in SPL. These drivers can be used to pass
otp keys to other IP addresses. (e.g. CRYPTO module). Enable
this option to build the drivers in drivers/keylad as part of an
SPL build.
config SPL_HASH_SUPPORT
bool "Support hashing drivers"
select SHA1
@ -884,12 +892,6 @@ config SPL_ATF_NO_PLATFORM_PARAM
If your ATF is affected, say Y.
config SPL_ATF_AARCH32_BL33
bool "Support BL33 runs as AArch32 mode"
depends on SPL_ATF
help
This option setup the AArch32 Mode for BL33.
config SPL_OPTEE
bool "Support OP-TEE Trusted OS"
depends on ARM

13
u-boot/common/spl/spl_atf.c
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@ -76,13 +76,12 @@ static struct bl31_params *bl2_plat_get_bl31_params(struct spl_image_info *spl_i
bl33_ep_info->args.arg0 = 0xffff & read_mpidr();
bl33_ep_info->pc = bl33_entry;
#ifdef CONFIG_SPL_ATF_AARCH32_BL33
bl33_ep_info->spsr = SPSR_32(MODE32_svc, SPSR_T_ARM, EP_EE_LITTLE,
DISABLE_ALL_EXECPTIONS_32);
#else
bl33_ep_info->spsr = SPSR_64(MODE_EL2, MODE_SP_ELX,
DISABLE_ALL_EXECPTIONS);
#endif
if (spl_image->flags & SPL_ATF_AARCH32_BL33)
bl33_ep_info->spsr = SPSR_32(MODE32_svc, SPSR_T_ARM, EP_EE_LITTLE,
DISABLE_ALL_EXECPTIONS_32);
else
bl33_ep_info->spsr = SPSR_64(MODE_EL2, MODE_SP_ELX,
DISABLE_ALL_EXECPTIONS);
/*
* Reference: arch/arm/lib/bootm.c
* boot_jump_linux(bootm_headers_t *images, int flag)

9
u-boot/common/spl/spl_fit.c
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@ -426,7 +426,7 @@ static void *spl_fit_load_blob(struct spl_load_info *info,
align_len) & ~align_len);
sectors = get_aligned_image_size(info, size, 0);
count = info->read(info, sector, sectors, fit);
#ifdef CONFIG_SPL_MTD_SUPPORT
#if defined(CONFIG_SPL_MTD_SUPPORT) && !defined(CONFIG_FPGA_RAM)
mtd_blk_map_fit(info->dev, sector, fit);
#endif
debug("fit read sector %lx, sectors=%d, dst=%p, count=%lu\n",
@ -614,6 +614,9 @@ static int spl_internal_load_simple_fit(struct spl_image_info *spl_image,
{
struct spl_image_info image_info;
char *desc;
#if CONFIG_IS_ENABLED(ATF)
uint8_t ih_arch;
#endif
int base_offset;
int images, ret;
int index = 0;
@ -787,6 +790,10 @@ static int spl_internal_load_simple_fit(struct spl_image_info *spl_image,
if (os_type == IH_OS_U_BOOT) {
#if CONFIG_IS_ENABLED(ATF)
fit_image_get_arch(fit, node, &ih_arch);
debug("Image ARCH is %s\n", genimg_get_arch_name(ih_arch));
if (ih_arch == IH_ARCH_ARM)
spl_image->flags |= SPL_ATF_AARCH32_BL33;
spl_image->entry_point_bl33 = image_info.load_addr;
#elif CONFIG_IS_ENABLED(OPTEE)
spl_image->entry_point_os = image_info.load_addr;

8
u-boot/configs/evb-px30_defconfig
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@ -7,8 +7,8 @@ CONFIG_ROCKCHIP_PX30=y
CONFIG_SPL_FIT_GENERATOR="arch/arm/mach-rockchip/make_fit_atf.py"
CONFIG_ROCKCHIP_SPL_RESERVE_IRAM=0x0
CONFIG_ROCKCHIP_VENDOR_PARTITION=y
CONFIG_DM_DMC=y
CONFIG_ROCKCHIP_DMC_FSP=y
CONFIG_UBOOT_SIZE_KB=2048
CONFIG_UBOOT_NUM=2
CONFIG_TRUST_RSA_MODE=3
CONFIG_TARGET_EVB_PX30=y
CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
@ -88,6 +88,8 @@ CONFIG_PWM_ROCKCHIP=y
CONFIG_RAM=y
CONFIG_SPL_RAM=y
CONFIG_TPL_RAM=y
CONFIG_DM_DMC=y
CONFIG_ROCKCHIP_DMC_FSP=y
CONFIG_ROCKCHIP_SDRAM_COMMON=y
CONFIG_DM_RESET=y
CONFIG_RKNAND=y
@ -96,8 +98,6 @@ CONFIG_DEBUG_UART_BASE=0xFF160000
CONFIG_DEBUG_UART_CLOCK=24000000
CONFIG_DEBUG_UART_SHIFT=2
CONFIG_DEBUG_UART_SKIP_INIT=y
CONFIG_UBOOT_SIZE_KB=2048
CONFIG_UBOOT_NUM=2
CONFIG_SOUND=y
CONFIG_I2S_ROCKCHIP=y
CONFIG_SOUND_RK817=y

139
u-boot/configs/evb-rk3358_defconfig
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@ -0,0 +1,139 @@
CONFIG_ARM=y
CONFIG_ARCH_ROCKCHIP=y
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_ROCKCHIP_PX30=y
CONFIG_ROCKCHIP_RK3358=y
CONFIG_SPL_FIT_GENERATOR="arch/arm/mach-rockchip/make_fit_atf.py"
CONFIG_ROCKCHIP_SPL_RESERVE_IRAM=0x0
CONFIG_ROCKCHIP_VENDOR_PARTITION=y
CONFIG_UBOOT_SIZE_KB=2048
CONFIG_UBOOT_NUM=2
CONFIG_TRUST_RSA_MODE=3
CONFIG_TARGET_EVB_PX30=y
CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
CONFIG_SPL_STACK_R_ADDR=0x600000
CONFIG_DEFAULT_DEVICE_TREE="px30-evb"
CONFIG_DEBUG_UART=y
CONFIG_TPL_SYS_MALLOC_F_LEN=0x600
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_SPL_LOAD_FIT=y
CONFIG_BOOTDELAY=0
CONFIG_SYS_CONSOLE_INFO_QUIET=y
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_ANDROID_BOOTLOADER=y
CONFIG_SPL_STACK_R=y
CONFIG_SPL_ATF=y
CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y
CONFIG_FASTBOOT_BUF_ADDR=0x800800
CONFIG_FASTBOOT_BUF_SIZE=0x04000000
CONFIG_FASTBOOT_FLASH=y
CONFIG_FASTBOOT_FLASH_MMC_DEV=0
# CONFIG_CMD_ELF is not set
# CONFIG_CMD_IMI is not set
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_XIMG is not set
# CONFIG_CMD_LZMADEC is not set
# CONFIG_CMD_UNZIP is not set
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_FPGA is not set
CONFIG_CMD_GPT=y
# CONFIG_CMD_LOADB is not set
# CONFIG_CMD_LOADS is not set
CONFIG_CMD_BOOT_ANDROID=y
CONFIG_CMD_BOOT_ROCKCHIP=y
CONFIG_CMD_MMC=y
CONFIG_CMD_USB=y
CONFIG_CMD_USB_MASS_STORAGE=y
# CONFIG_CMD_ITEST is not set
# CONFIG_CMD_SETEXPR is not set
# CONFIG_CMD_MISC is not set
# CONFIG_SPL_DOS_PARTITION is not set
# CONFIG_ISO_PARTITION is not set
CONFIG_EFI_PARTITION_ENTRIES_NUMBERS=64
CONFIG_RKPARM_PARTITION=y
CONFIG_SPL_OF_CONTROL=y
CONFIG_OF_LIVE=y
CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
CONFIG_REGMAP=y
CONFIG_SPL_REGMAP=y
CONFIG_SYSCON=y
CONFIG_SPL_SYSCON=y
CONFIG_CLK=y
CONFIG_SPL_CLK=y
CONFIG_ROCKCHIP_GPIO=y
CONFIG_SYS_I2C_ROCKCHIP=y
CONFIG_DM_KEY=y
CONFIG_RK8XX_PWRKEY=y
CONFIG_ADC_KEY=y
CONFIG_MMC_DW=y
CONFIG_MMC_DW_ROCKCHIP=y
CONFIG_DM_ETH=y
CONFIG_ETH_DESIGNWARE=y
CONFIG_GMAC_ROCKCHIP=y
CONFIG_PHY_ROCKCHIP_INNO_USB2=y
CONFIG_PINCTRL=y
CONFIG_DM_FUEL_GAUGE=y
CONFIG_DM_PMIC=y
CONFIG_PMIC_RK8XX=y
CONFIG_REGULATOR_PWM=y
CONFIG_DM_REGULATOR_FIXED=y
CONFIG_REGULATOR_RK8XX=y
CONFIG_DM_DVFS=y
CONFIG_ROCKCHIP_WTEMP_DVFS=y
CONFIG_DM_CHARGE_DISPLAY=y
CONFIG_CHARGE_ANIMATION=y
CONFIG_PWM_ROCKCHIP=y
CONFIG_RAM=y
CONFIG_SPL_RAM=y
CONFIG_TPL_RAM=y
CONFIG_DM_DMC=y
CONFIG_ROCKCHIP_DMC_FSP=y
CONFIG_ROCKCHIP_SDRAM_COMMON=y
CONFIG_DM_RESET=y
CONFIG_RKNAND=y
CONFIG_BAUDRATE=1500000
CONFIG_DEBUG_UART_BASE=0xFF160000
CONFIG_DEBUG_UART_CLOCK=24000000
CONFIG_DEBUG_UART_SHIFT=2
CONFIG_DEBUG_UART_SKIP_INIT=y
CONFIG_SOUND=y
CONFIG_I2S_ROCKCHIP=y
CONFIG_SOUND_RK817=y
CONFIG_SOUND_ROCKCHIP=y
CONFIG_SYSRESET=y
CONFIG_DM_THERMAL=y
CONFIG_ROCKCHIP_THERMAL=y
CONFIG_USB=y
CONFIG_USB_EHCI_HCD=y
CONFIG_USB_EHCI_GENERIC=y
CONFIG_USB_OHCI_HCD=y
CONFIG_USB_OHCI_GENERIC=y
CONFIG_USB_STORAGE=y
CONFIG_USB_GADGET=y
CONFIG_USB_GADGET_MANUFACTURER="Rockchip"
CONFIG_USB_GADGET_VENDOR_NUM=0x2207
CONFIG_USB_GADGET_PRODUCT_NUM=0x330d
CONFIG_USB_GADGET_DWC2_OTG=y
CONFIG_USB_GADGET_DOWNLOAD=y
CONFIG_DM_VIDEO=y
CONFIG_DISPLAY=y
CONFIG_DRM_ROCKCHIP=y
CONFIG_DRM_ROCKCHIP_INNO_VIDEO_COMBO_PHY=y
CONFIG_DRM_ROCKCHIP_DW_MIPI_DSI=y
CONFIG_DRM_ROCKCHIP_LVDS=y
CONFIG_DRM_ROCKCHIP_RGB=y
CONFIG_DRM_ROCKCHIP_RK618=y
CONFIG_VIDEO_BRIDGE_ANALOGIX_ANX6345=y
CONFIG_LCD=y
CONFIG_USE_TINY_PRINTF=y
CONFIG_SPL_TINY_MEMSET=y
CONFIG_LZ4=y
CONFIG_LZO=y
CONFIG_ERRNO_STR=y
# CONFIG_EFI_LOADER is not set
CONFIG_OPTEE_CLIENT=y
CONFIG_OPTEE_V2=y
CONFIG_TEST_ROCKCHIP=y

227
u-boot/configs/nanopi_r3_ab_defconfig
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@ -0,0 +1,227 @@
CONFIG_ARM=y
CONFIG_ARCH_ROCKCHIP=y
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_SYS_MALLOC_F_LEN=0x80000
CONFIG_SPL_FIT_GENERATOR="arch/arm/mach-rockchip/make_fit_atf.sh"
CONFIG_ROCKCHIP_RK3568=y
CONFIG_ROCKCHIP_FIT_IMAGE=y
CONFIG_ROCKCHIP_VENDOR_PARTITION=y
CONFIG_ROCKCHIP_FIT_IMAGE_PACK=y
CONFIG_ROCKCHIP_NEW_IDB=y
CONFIG_LOADER_INI="RK3566MINIALL.ini"
CONFIG_SPL_SERIAL_SUPPORT=y
CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
CONFIG_TARGET_NANOPI_R3=y
CONFIG_SPL_LIBDISK_SUPPORT=y
CONFIG_SPL_NAND_SUPPORT=y
CONFIG_SPL_SPI_FLASH_SUPPORT=y
CONFIG_SPL_SPI_SUPPORT=y
CONFIG_DEFAULT_DEVICE_TREE="rk356x-nanopi-r3"
CONFIG_DEBUG_UART=y
CONFIG_IMAGE_GZIP=y
CONFIG_FIT=y
CONFIG_FIT_IMAGE_POST_PROCESS=y
CONFIG_FIT_HW_CRYPTO=y
CONFIG_SPL_LOAD_FIT=y
CONFIG_SPL_FIT_IMAGE_POST_PROCESS=y
CONFIG_SPL_FIT_HW_CRYPTO=y
# CONFIG_SPL_SYS_DCACHE_OFF is not set
CONFIG_BOOTDELAY=1
CONFIG_SYS_CONSOLE_INFO_QUIET=y
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_ANDROID_BOOTLOADER=y
CONFIG_ANDROID_AB=y
CONFIG_ANDROID_AVB=y
CONFIG_ANDROID_BOOT_IMAGE_HASH=y
CONFIG_BOARD_RNG_SEED=y
CONFIG_SPL_BOARD_INIT=y
# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
# CONFIG_SPL_LEGACY_IMAGE_SUPPORT is not set
CONFIG_SPL_SEPARATE_BSS=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION=y
CONFIG_SPL_SHA256_SUPPORT=y
CONFIG_SPL_CRYPTO_SUPPORT=y
CONFIG_SPL_HASH_SUPPORT=y
CONFIG_SPL_MTD_SUPPORT=y
CONFIG_SPL_SPI_FLASH_SFDP_SUPPORT=y
CONFIG_SPL_ATF=y
CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y
CONFIG_SPL_AB=y
CONFIG_FASTBOOT_BUF_ADDR=0xc00800
CONFIG_FASTBOOT_BUF_SIZE=0x04000000
CONFIG_FASTBOOT_FLASH=y
CONFIG_FASTBOOT_FLASH_MMC_DEV=0
CONFIG_CMD_BOOTZ=y
CONFIG_CMD_DTIMG=y
# CONFIG_CMD_ELF is not set
# CONFIG_CMD_IMI is not set
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_XIMG is not set
# CONFIG_CMD_LZMADEC is not set
# CONFIG_CMD_UNZIP is not set
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_FPGA is not set
CONFIG_CMD_GPT=y
# CONFIG_CMD_LOADB is not set
# CONFIG_CMD_LOADS is not set
CONFIG_CMD_BOOT_ANDROID=y
CONFIG_CMD_BOOT_ROCKCHIP=y
CONFIG_CMD_MMC=y
CONFIG_CMD_MTD=y
CONFIG_CMD_NAND=y
CONFIG_CMD_USB=y
CONFIG_CMD_USB_MASS_STORAGE=y
# CONFIG_CMD_ITEST is not set
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_TFTPPUT=y
CONFIG_CMD_TFTP_BOOTM=y
CONFIG_CMD_TFTP_FLASH=y
# CONFIG_CMD_MISC is not set
# CONFIG_CMD_CHARGE_DISPLAY is not set
CONFIG_CMD_MTD_BLK=y
# CONFIG_SPL_DOS_PARTITION is not set
# CONFIG_ISO_PARTITION is not set
CONFIG_EFI_PARTITION_ENTRIES_NUMBERS=64
CONFIG_SPL_OF_CONTROL=y
CONFIG_SPL_DTB_MINIMUM=y
CONFIG_OF_LIVE=y
CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
# CONFIG_NET_TFTP_VARS is not set
CONFIG_REGMAP=y
CONFIG_SPL_REGMAP=y
CONFIG_SYSCON=y
CONFIG_SPL_SYSCON=y
CONFIG_CLK=y
CONFIG_SPL_CLK=y
CONFIG_CLK_SCMI=y
CONFIG_DM_CRYPTO=y
CONFIG_SPL_DM_CRYPTO=y
CONFIG_ROCKCHIP_CRYPTO_V2=y
CONFIG_SPL_ROCKCHIP_CRYPTO_V2=y
CONFIG_DM_RNG=y
CONFIG_RNG_ROCKCHIP=y
CONFIG_SCMI_FIRMWARE=y
CONFIG_ROCKCHIP_GPIO=y
CONFIG_ROCKCHIP_GPIO_V2=y
CONFIG_SYS_I2C_ROCKCHIP=y
CONFIG_DM_KEY=y
CONFIG_RK8XX_PWRKEY=y
CONFIG_ADC_KEY=y
CONFIG_MISC=y
CONFIG_SPL_MISC=y
CONFIG_ROCKCHIP_OTP=y
CONFIG_SPL_ROCKCHIP_SECURE_OTP=y
CONFIG_MMC_DW=y
CONFIG_MMC_DW_ROCKCHIP=y
CONFIG_MMC_SDHCI=y
CONFIG_MMC_SDHCI_SDMA=y
CONFIG_MMC_SDHCI_ROCKCHIP=y
CONFIG_MTD=y
CONFIG_MTD_BLK=y
CONFIG_MTD_DEVICE=y
CONFIG_NAND=y
CONFIG_NAND_ROCKCHIP_V9=y
CONFIG_SYS_NAND_U_BOOT_LOCATIONS=y
CONFIG_SYS_NAND_U_BOOT_OFFS=0x8000
CONFIG_SYS_NAND_U_BOOT_OFFS_REDUND=0x10000
CONFIG_MTD_SPI_NAND=y
CONFIG_SPI_FLASH=y
CONFIG_SF_DEFAULT_SPEED=20000000
CONFIG_SPI_FLASH_EON=y
CONFIG_SPI_FLASH_GIGADEVICE=y
CONFIG_SPI_FLASH_MACRONIX=y
CONFIG_SPI_FLASH_WINBOND=y
CONFIG_SPI_FLASH_XMC=y
CONFIG_SPI_FLASH_MTD=y
CONFIG_DM_ETH=y
CONFIG_DM_ETH_PHY=y
CONFIG_DWC_ETH_QOS=y
CONFIG_GMAC_ROCKCHIP=y
CONFIG_PHY_ROCKCHIP_INNO_USB2=y
CONFIG_PHY_ROCKCHIP_NANENG_COMBOPHY=y
CONFIG_PHY_ROCKCHIP_NANENG_EDP=y
CONFIG_PINCTRL=y
CONFIG_SPL_PINCTRL=y
CONFIG_DM_FUEL_GAUGE=y
CONFIG_POWER_FG_RK817=y
CONFIG_IO_DOMAIN=y
CONFIG_ROCKCHIP_IO_DOMAIN=y
CONFIG_DM_PMIC=y
CONFIG_PMIC_RK8XX=y
CONFIG_REGULATOR_FAN53555=y
CONFIG_REGULATOR_PWM=y
CONFIG_DM_REGULATOR_FIXED=y
CONFIG_DM_REGULATOR_GPIO=y
CONFIG_REGULATOR_RK8XX=y
CONFIG_DM_CHARGE_DISPLAY=y
CONFIG_CHARGE_ANIMATION=y
CONFIG_PWM_ROCKCHIP=y
CONFIG_RAM=y
CONFIG_SPL_RAM=y
CONFIG_TPL_RAM=y
CONFIG_DM_RAMDISK=y
CONFIG_RAMDISK_RO=y
CONFIG_DM_DMC=y
CONFIG_ROCKCHIP_DMC_FSP=y
CONFIG_ROCKCHIP_SDRAM_COMMON=y
CONFIG_ROCKCHIP_TPL_INIT_DRAM_TYPE=0
CONFIG_DM_RESET=y
CONFIG_SPL_DM_RESET=y
CONFIG_SPL_RESET_ROCKCHIP=y
CONFIG_BAUDRATE=1500000
CONFIG_DEBUG_UART_BASE=0xFE660000
CONFIG_DEBUG_UART_CLOCK=24000000
CONFIG_DEBUG_UART_SHIFT=2
CONFIG_ROCKCHIP_SFC=y
CONFIG_SYSRESET=y
CONFIG_USB=y
CONFIG_USB_XHCI_HCD=y
CONFIG_USB_XHCI_DWC3=y
CONFIG_USB_EHCI_HCD=y
CONFIG_USB_EHCI_GENERIC=y
CONFIG_USB_OHCI_HCD=y
CONFIG_USB_OHCI_GENERIC=y
CONFIG_USB_DWC3=y
CONFIG_USB_DWC3_GADGET=y
CONFIG_USB_DWC3_GENERIC=y
CONFIG_USB_STORAGE=y
CONFIG_USB_GADGET=y
CONFIG_USB_GADGET_MANUFACTURER="Rockchip"
CONFIG_USB_GADGET_VENDOR_NUM=0x2207
CONFIG_USB_GADGET_PRODUCT_NUM=0x350a
CONFIG_USB_GADGET_DOWNLOAD=y
CONFIG_DM_VIDEO=y
CONFIG_DISPLAY=y
CONFIG_DRM_ROCKCHIP=y
CONFIG_DRM_ROCKCHIP_DW_HDMI=y
CONFIG_DRM_ROCKCHIP_INNO_MIPI_PHY=y
CONFIG_DRM_ROCKCHIP_INNO_VIDEO_COMBO_PHY=y
CONFIG_DRM_ROCKCHIP_DW_MIPI_DSI=y
CONFIG_DRM_ROCKCHIP_ANALOGIX_DP=y
CONFIG_DRM_ROCKCHIP_LVDS=y
CONFIG_DRM_ROCKCHIP_RGB=y
CONFIG_ROCKCHIP_CUBIC_LUT_SIZE=9
CONFIG_LCD=y
CONFIG_USE_TINY_PRINTF=y
CONFIG_SPL_TINY_MEMSET=y
CONFIG_RSA=y
CONFIG_SPL_RSA=y
CONFIG_RSA_N_SIZE=0x200
CONFIG_RSA_E_SIZE=0x10
CONFIG_RSA_C_SIZE=0x20
CONFIG_XBC=y
CONFIG_SHA512=y
CONFIG_LZ4=y
CONFIG_LZMA=y
CONFIG_SPL_GZIP=y
CONFIG_ERRNO_STR=y
# CONFIG_EFI_LOADER is not set
CONFIG_AVB_LIBAVB=y
CONFIG_AVB_LIBAVB_AB=y
CONFIG_AVB_LIBAVB_ATX=y
CONFIG_AVB_LIBAVB_USER=y
CONFIG_RK_AVB_LIBAVB_USER=y
CONFIG_OPTEE_CLIENT=y
CONFIG_OPTEE_V2=y
CONFIG_OPTEE_ALWAYS_USE_SECURITY_PARTITION=y

1
u-boot/configs/rk-sfc.config
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@ -1 +1,2 @@
CONFIG_ROCKCHIP_SFC_IOMUX=y
# CONFIG_ROCKCHIP_EMMC_IOMUX is not set

1
u-boot/configs/rk-spl-boot-aarch32.config
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@ -1 +0,0 @@
CONFIG_SPL_ATF_AARCH32_BL33=y

1
u-boot/configs/rk3328_defconfig
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@ -35,7 +35,6 @@ CONFIG_FASTBOOT_BUF_SIZE=0x4000000
CONFIG_FASTBOOT_FLASH=y
CONFIG_FASTBOOT_FLASH_MMC_DEV=0
# CONFIG_CMD_BDI is not set
CONFIG_CMD_DTIMG=y
# CONFIG_CMD_ELF is not set
# CONFIG_CMD_IMI is not set
# CONFIG_CMD_IMLS is not set

2
u-boot/configs/rk3506-rt.config
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@ -0,0 +1,2 @@
CONFIG_BASE_DEFCONFIG="rk3506_defconfig"
CONFIG_LOADER_INI="RK3506MINIALL_RT.ini"

22
u-boot/configs/rk3506_defconfig
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@ -8,6 +8,7 @@ CONFIG_SPL_FIT_GENERATOR="arch/arm/mach-rockchip/make_fit_optee.sh"
CONFIG_ROCKCHIP_RK3506=y
CONFIG_ROCKCHIP_SPL_RESERVE_IRAM=0x0
CONFIG_ROCKCHIP_FIT_IMAGE=y
CONFIG_ROCKCHIP_VENDOR_PARTITION=y
CONFIG_USING_KERNEL_DTB_V2=y
CONFIG_ROCKCHIP_FIT_IMAGE_PACK=y
CONFIG_ROCKCHIP_NEW_IDB=y
@ -40,7 +41,6 @@ CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION=y
CONFIG_SPL_SHA256_SUPPORT=y
CONFIG_SPL_HASH_SUPPORT=y
CONFIG_SPL_MTD_SUPPORT=y
CONFIG_SPI_FLASH_SFDP_SUPPORT=y
CONFIG_SPL_OPTEE=y
CONFIG_SPL_AB=y
# CONFIG_FASTBOOT is not set
@ -65,10 +65,9 @@ CONFIG_CMD_SCRIPT_UPDATE=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_TFTP_BOOTM=y
CONFIG_CMD_TFTP_FLASH=y
CONFIG_CMD_DHCP=y
# CONFIG_CMD_NFS is not set
CONFIG_CMD_PING=y
# CONFIG_CMD_MISC is not set
CONFIG_CMD_PMIC=y
CONFIG_CMD_MTD_BLK=y
# CONFIG_SPL_DOS_PARTITION is not set
CONFIG_EFI_PARTITION_ENTRIES_NUMBERS=64
@ -81,7 +80,6 @@ CONFIG_REGMAP=y
CONFIG_SPL_REGMAP=y
CONFIG_SYSCON=y
CONFIG_SPL_SYSCON=y
CONFIG_ROCKCHIP_VENDOR_PARTITION=y
# CONFIG_SARADC_ROCKCHIP is not set
CONFIG_SARADC_ROCKCHIP_V2=y
CONFIG_CLK=y
@ -110,22 +108,27 @@ CONFIG_MTD_SPI_NAND=y
CONFIG_SPI_FLASH=y
CONFIG_SF_DEFAULT_MODE=0x1
CONFIG_SF_DEFAULT_SPEED=50000000
CONFIG_SPI_FLASH_SFDP_SUPPORT=y
CONFIG_SPI_FLASH_GIGADEVICE=y
CONFIG_SPI_FLASH_MACRONIX=y
CONFIG_SPI_FLASH_WINBOND=y
CONFIG_SPI_FLASH_XMC=y
CONFIG_SPI_FLASH_MTD=y
CONFIG_PHY_ROCKCHIP_INNO_USB2=y
CONFIG_DM_ETH=y
CONFIG_DM_ETH_PHY=y
CONFIG_DWC_ETH_QOS=y
# CONFIG_DWC_ETH_QOS_FULL is not set
CONFIG_GMAC_ROCKCHIP=y
CONFIG_PHY_ROCKCHIP_INNO_USB2=y
CONFIG_PINCTRL=y
CONFIG_SPL_PINCTRL=y
CONFIG_DM_PMIC=y
# CONFIG_SPL_PMIC_CHILDREN is not set
CONFIG_PMIC_RK801=y
CONFIG_REGULATOR_PWM=y
CONFIG_DM_REGULATOR_FIXED=y
CONFIG_DM_REGULATOR_GPIO=y
CONFIG_REGULATOR_RK801=y
CONFIG_PWM_ROCKCHIP=y
CONFIG_RAM=y
CONFIG_SPL_RAM=y
@ -148,6 +151,7 @@ CONFIG_USB_GADGET_DOWNLOAD=y
CONFIG_DM_VIDEO=y
CONFIG_DISPLAY=y
CONFIG_DRM_ROCKCHIP=y
CONFIG_DRM_MEM_RESERVED_SIZE_MBYTES=8
CONFIG_DRM_ROCKCHIP_INNO_MIPI_PHY=y
CONFIG_DRM_ROCKCHIP_DW_MIPI_DSI=y
CONFIG_DRM_ROCKCHIP_RGB=y
@ -155,14 +159,14 @@ CONFIG_DRM_ROCKCHIP_RGB=y
CONFIG_USE_TINY_PRINTF=y
# CONFIG_REGEX is not set
CONFIG_SPL_TINY_MEMSET=y
CONFIG_LZ4=y
CONFIG_LZMA=y
CONFIG_SPL_LZMA=y
CONFIG_SPL_GZIP=y
CONFIG_RSA=y
CONFIG_SPL_RSA=y
CONFIG_RSA_N_SIZE=0x200
CONFIG_RSA_E_SIZE=0x10
CONFIG_RSA_C_SIZE=0x20
CONFIG_LZ4=y
CONFIG_LZMA=y
CONFIG_SPL_LZMA=y
CONFIG_SPL_GZIP=y
CONFIG_ERRNO_STR=y
# CONFIG_EFI_LOADER is not set

2
u-boot/configs/rk3506b-rt.config
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@ -0,0 +1,2 @@
CONFIG_BASE_DEFCONFIG="rk3506_defconfig"
CONFIG_LOADER_INI="RK3506BMINIALL_RT.ini"

1
u-boot/configs/rk3528-aarch32.config
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@ -2,7 +2,6 @@ CONFIG_ARM64_BOOT_AARCH32=y
# CONFIG_ARM64_SUPPORT_AARCH32 is not set
# CONFIG_ARMV7_LPAE is not set
CONFIG_BASE_DEFCONFIG="rk3528_defconfig"
CONFIG_LOADER_INI="RK3528MINIALL_BOOT_AARCH32.ini"
CONFIG_BOOTP_PXE_CLIENTARCH=0x15
CONFIG_BOOTP_VCI_STRING="U-Boot.armv7"
CONFIG_CPU_V7=y

1
u-boot/configs/rk3528_defconfig
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@ -199,3 +199,4 @@ CONFIG_AVB_LIBAVB_USER=y
CONFIG_RK_AVB_LIBAVB_USER=y
CONFIG_OPTEE_CLIENT=y
CONFIG_OPTEE_V2=y
CONFIG_OPTEE_ALWAYS_USE_SECURITY_PARTITION=y

24
u-boot/configs/rk3562-aarch32.config
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@ -0,0 +1,24 @@
CONFIG_ARM64_BOOT_AARCH32=y
# CONFIG_ARM64_SUPPORT_AARCH32 is not set
# CONFIG_ARMV7_LPAE is not set
CONFIG_BASE_DEFCONFIG="rk3562_defconfig"
CONFIG_BOOTP_PXE_CLIENTARCH=0x15
CONFIG_BOOTP_VCI_STRING="U-Boot.armv7"
CONFIG_CPU_V7=y
# CONFIG_DEBUG_LL is not set
CONFIG_HAS_THUMB2=y
CONFIG_HAS_VBAR=y
CONFIG_HAVE_PRIVATE_LIBGCC=y
# CONFIG_PHYS_64BIT is not set
# CONFIG_SPL_OF_LIBFDT is not set
CONFIG_SPL_SYS_THUMB_BUILD=y
CONFIG_SPL_USE_ARCH_MEMCPY=y
CONFIG_SPL_USE_ARCH_MEMSET=y
CONFIG_SYS_ARM_ARCH=7
CONFIG_SYS_CPU="armv7"
CONFIG_SYS_THUMB_BUILD=y
CONFIG_TPL_USE_ARCH_MEMCPY=y
CONFIG_TPL_USE_ARCH_MEMSET=y
CONFIG_USE_ARCH_MEMCPY=y
CONFIG_USE_ARCH_MEMSET=y
CONFIG_USE_PRIVATE_LIBGCC=y

1462
u-boot/configs/rk3568-pcie-ep_defconfig
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222
u-boot/configs/rk3576-ipc_defconfig
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@ -0,0 +1,222 @@
CONFIG_ARM=y
CONFIG_ARCH_ROCKCHIP=y
CONFIG_SPL_GPIO_SUPPORT=y
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_SYS_MALLOC_F_LEN=0x80000
CONFIG_SPL_FIT_GENERATOR="arch/arm/mach-rockchip/make_fit_atf.sh"
CONFIG_ROCKCHIP_RK3576=y
CONFIG_ROCKCHIP_FIT_IMAGE=y
CONFIG_USING_KERNEL_DTB_V2=y
CONFIG_ROCKCHIP_FIT_IMAGE_PACK=y
CONFIG_ROCKCHIP_NEW_IDB=y
CONFIG_SANITY_CPU_SWAP=y
CONFIG_SPL_SERIAL_SUPPORT=y
CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
CONFIG_TARGET_EVB_RK3576=y
CONFIG_SPL_LIBDISK_SUPPORT=y
CONFIG_SPL_SPI_FLASH_SUPPORT=y
CONFIG_SPL_SPI_SUPPORT=y
CONFIG_ARMV8_CRYPTO=y
CONFIG_DEFAULT_DEVICE_TREE="rk3576-evb"
CONFIG_DEBUG_UART=y
CONFIG_FIT=y
CONFIG_FIT_IMAGE_POST_PROCESS=y
CONFIG_SPL_LOAD_FIT=y
CONFIG_SPL_FIT_IMAGE_POST_PROCESS=y
CONFIG_SPL_FIT_HW_CRYPTO=y
# CONFIG_SPL_SYS_DCACHE_OFF is not set
CONFIG_SPL_FIT_IMAGE_MULTIPLE=1
CONFIG_BOOTDELAY=0
CONFIG_SYS_CONSOLE_INFO_QUIET=y
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_BOARD_RNG_SEED=y
CONFIG_SPL_BOARD_INIT=y
# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
# CONFIG_SPL_LEGACY_IMAGE_SUPPORT is not set
CONFIG_SPL_SEPARATE_BSS=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION=0x1
CONFIG_SPL_MTD_SUPPORT=y
CONFIG_SPL_UFS_SUPPORT=y
CONFIG_SPL_ATF=y
CONFIG_SPL_AB=y
# CONFIG_FASTBOOT is not set
CONFIG_CMD_BOOTZ=y
CONFIG_CMD_DTIMG=y
# CONFIG_CMD_ELF is not set
# CONFIG_CMD_IMI is not set
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_XIMG is not set
# CONFIG_CMD_LZMADEC is not set
# CONFIG_CMD_UNZIP is not set
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_FPGA is not set
CONFIG_CMD_GPIO=y
CONFIG_CMD_GPT=y
# CONFIG_CMD_LOADB is not set
# CONFIG_CMD_LOADS is not set
CONFIG_CMD_MMC=y
CONFIG_CMD_SF=y
CONFIG_CMD_SPI=y
CONFIG_CMD_UFS=y
CONFIG_CMD_USB=y
CONFIG_CMD_USB_MASS_STORAGE=y
# CONFIG_CMD_ITEST is not set
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_TFTPPUT=y
CONFIG_CMD_TFTP_BOOTM=y
CONFIG_CMD_TFTP_FLASH=y
# CONFIG_CMD_MISC is not set
CONFIG_CMD_MTD_BLK=y
# CONFIG_SPL_DOS_PARTITION is not set
# CONFIG_ISO_PARTITION is not set
CONFIG_EFI_PARTITION_ENTRIES_NUMBERS=64
# CONFIG_SPL_EFI_PARTITION is not set
CONFIG_SPL_OF_CONTROL=y
CONFIG_SPL_DTB_MINIMUM=y
CONFIG_OF_LIVE=y
CONFIG_OF_SPL_REMOVE_PROPS="interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
CONFIG_OF_U_BOOT_REMOVE_PROPS="interrupt-parent"
CONFIG_ENVF=y
# CONFIG_NET_TFTP_VARS is not set
CONFIG_REGMAP=y
CONFIG_SPL_REGMAP=y
CONFIG_SYSCON=y
CONFIG_SPL_SYSCON=y
# CONFIG_SARADC_ROCKCHIP is not set
CONFIG_SARADC_ROCKCHIP_V2=y
CONFIG_CLK=y
CONFIG_SPL_CLK=y
CONFIG_CLK_SCMI=y
CONFIG_DM_CRYPTO=y
CONFIG_SPL_DM_CRYPTO=y
CONFIG_ROCKCHIP_CRYPTO_V2=y
CONFIG_SPL_ROCKCHIP_CRYPTO_V2=y
CONFIG_DM_RNG=y
CONFIG_RNG_ROCKCHIP=y
CONFIG_SCMI_FIRMWARE=y
CONFIG_GPIO_HOG=y
CONFIG_ROCKCHIP_GPIO=y
CONFIG_ROCKCHIP_GPIO_V2=y
CONFIG_SYS_I2C_ROCKCHIP=y
CONFIG_I2C_MUX=y
CONFIG_DM_KEY=y
CONFIG_RK8XX_PWRKEY=y
CONFIG_ADC_KEY=y
CONFIG_MISC=y
CONFIG_SPL_MISC=y
CONFIG_MISC_DECOMPRESS=y
CONFIG_SPL_MISC_DECOMPRESS=y
CONFIG_ROCKCHIP_OTP=y
CONFIG_ROCKCHIP_HW_DECOMPRESS=y
CONFIG_SPL_ROCKCHIP_HW_DECOMPRESS=y
CONFIG_SPL_ROCKCHIP_SECURE_OTP=y
CONFIG_MMC_DW=y
CONFIG_MMC_DW_ROCKCHIP=y
CONFIG_MMC_SDHCI=y
CONFIG_MMC_SDHCI_SDMA=y
CONFIG_MMC_SDHCI_ROCKCHIP=y
CONFIG_MTD=y
CONFIG_MTD_BLK=y
CONFIG_MTD_DEVICE=y
CONFIG_MTD_SPI_NAND=y
CONFIG_SPI_FLASH=y
CONFIG_SF_DEFAULT_MODE=0x1
CONFIG_SF_DEFAULT_SPEED=50000000
CONFIG_SPI_FLASH_GIGADEVICE=y
CONFIG_SPI_FLASH_MACRONIX=y
CONFIG_SPI_FLASH_WINBOND=y
CONFIG_SPI_FLASH_MTD=y
CONFIG_DM_ETH=y
CONFIG_DM_ETH_PHY=y
CONFIG_DWC_ETH_QOS=y
CONFIG_GMAC_ROCKCHIP=y
CONFIG_PHY_ROCKCHIP_INNO_USB2=y
CONFIG_PHY_ROCKCHIP_NANENG_COMBOPHY=y
CONFIG_PHY_ROCKCHIP_SAMSUNG_HDPTX=y
CONFIG_PHY_ROCKCHIP_USBDP=y
CONFIG_PINCTRL=y
CONFIG_SPL_PINCTRL=y
CONFIG_DM_FUEL_GAUGE=y
CONFIG_POWER_FG_CW201X=y
CONFIG_POWER_FG_CW221X=y
CONFIG_DM_PMIC=y
CONFIG_PMIC_RK8XX=y
CONFIG_DM_POWER_DELIVERY=y
CONFIG_TYPEC_TCPM=y
CONFIG_TYPEC_TCPCI=y
CONFIG_TYPEC_HUSB311=y
CONFIG_TYPEC_FUSB302=y
CONFIG_REGULATOR_PWM=y
CONFIG_DM_REGULATOR_FIXED=y
CONFIG_DM_REGULATOR_GPIO=y
CONFIG_REGULATOR_RK8XX=y
CONFIG_CHARGER_BQ25700=y
CONFIG_CHARGER_BQ25890=y
CONFIG_CHARGER_SGM41542=y
CONFIG_DM_CHARGE_DISPLAY=y
CONFIG_CHARGE_ANIMATION=y
CONFIG_PWM_ROCKCHIP=y
CONFIG_RAM=y
CONFIG_SPL_RAM=y
CONFIG_TPL_RAM=y
CONFIG_DM_RESET=y
CONFIG_SPL_DM_RESET=y
CONFIG_SPL_RESET_ROCKCHIP=y
CONFIG_SCSI=y
CONFIG_DM_SCSI=y
CONFIG_BAUDRATE=1500000
CONFIG_DEBUG_UART_BASE=0x2ad40000
CONFIG_DEBUG_UART_CLOCK=24000000
CONFIG_DEBUG_UART_SHIFT=2
CONFIG_ROCKCHIP_SFC=y
CONFIG_SYSRESET=y
CONFIG_USB=y
CONFIG_USB_XHCI_HCD=y
CONFIG_USB_XHCI_DWC3=y
CONFIG_USB_EHCI_HCD=y
CONFIG_USB_EHCI_GENERIC=y
CONFIG_USB_OHCI_HCD=y
CONFIG_USB_OHCI_GENERIC=y
CONFIG_USB_DWC3=y
CONFIG_USB_DWC3_GADGET=y
CONFIG_USB_DWC3_GENERIC=y
CONFIG_USB_STORAGE=y
CONFIG_USB_GADGET=y
CONFIG_USB_GADGET_MANUFACTURER="Rockchip"
CONFIG_USB_GADGET_VENDOR_NUM=0x2207
CONFIG_USB_GADGET_PRODUCT_NUM=0x350e
CONFIG_USB_GADGET_DOWNLOAD=y
CONFIG_UFS=y
CONFIG_ROCKCHIP_UFS=y
CONFIG_DM_VIDEO=y
CONFIG_DISPLAY=y
CONFIG_DRM_ROCKCHIP=y
CONFIG_DRM_ROCKCHIP_DW_HDMI_QP=y
CONFIG_DRM_ROCKCHIP_DW_MIPI_DSI2=y
CONFIG_DRM_ROCKCHIP_DW_DP=y
CONFIG_DRM_ROCKCHIP_ANALOGIX_DP=y
CONFIG_DRM_ROCKCHIP_RGB=y
CONFIG_DRM_ROCKCHIP_SAMSUNG_MIPI_DCPHY=y
CONFIG_PHY_ROCKCHIP_SAMSUNG_HDPTX_HDMI=y
CONFIG_USE_TINY_PRINTF=y
CONFIG_LIB_RAND=y
CONFIG_SPL_TINY_MEMSET=y
CONFIG_RSA=y
CONFIG_SPL_RSA=y
CONFIG_RSA_N_SIZE=0x200
CONFIG_RSA_E_SIZE=0x10
CONFIG_RSA_C_SIZE=0x20
CONFIG_LZ4=y
CONFIG_SPL_GZIP=y
CONFIG_ERRNO_STR=y
# CONFIG_EFI_LOADER is not set
CONFIG_AVB_LIBAVB=y
CONFIG_AVB_LIBAVB_AB=y
CONFIG_AVB_LIBAVB_ATX=y
CONFIG_AVB_LIBAVB_USER=y
CONFIG_RK_AVB_LIBAVB_USER=y
CONFIG_OPTEE_CLIENT=y
CONFIG_OPTEE_V2=y
CONFIG_OPTEE_ALWAYS_USE_SECURITY_PARTITION=y

1
u-boot/configs/rv1103b_defconfig
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@ -99,6 +99,7 @@ CONFIG_ROCKCHIP_GPIO=y
# CONFIG_INPUT is not set
CONFIG_MISC=y
CONFIG_SPL_MISC=y
CONFIG_ROCKCHIP_OTP=y
CONFIG_MISC_DECOMPRESS=y
CONFIG_SPL_MISC_DECOMPRESS=y
CONFIG_ROCKCHIP_HW_DECOMPRESS=y

1
u-boot/configs/rv1106b-fastboot-emmc_defconfig
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@ -91,6 +91,7 @@ CONFIG_SPL_MISC_DECOMPRESS=y
CONFIG_SPL_ROCKCHIP_HW_DECOMPRESS=y
CONFIG_MMC_DW=y
CONFIG_MMC_DW_ROCKCHIP=y
CONFIG_MMC_USE_PRE_CONFIG=y
CONFIG_MTD=y
CONFIG_MTD_BLK=y
CONFIG_MTD_DEVICE=y

23
u-boot/configs/rv1126b-aarch32.config
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@ -0,0 +1,23 @@
CONFIG_ARM64_BOOT_AARCH32=y
# CONFIG_ARM64_SUPPORT_AARCH32 is not set
# CONFIG_ARMV7_LPAE is not set
CONFIG_BOOTP_PXE_CLIENTARCH=0x15
CONFIG_BOOTP_VCI_STRING="U-Boot.armv7"
CONFIG_CPU_V7=y
# CONFIG_DEBUG_LL is not set
CONFIG_HAS_THUMB2=y
CONFIG_HAS_VBAR=y
CONFIG_HAVE_PRIVATE_LIBGCC=y
# CONFIG_PHYS_64BIT is not set
# CONFIG_SPL_OF_LIBFDT is not set
CONFIG_SPL_SYS_THUMB_BUILD=y
CONFIG_SPL_USE_ARCH_MEMCPY=y
CONFIG_SPL_USE_ARCH_MEMSET=y
CONFIG_SYS_ARM_ARCH=7
CONFIG_SYS_CPU="armv7"
CONFIG_SYS_THUMB_BUILD=y
CONFIG_TPL_USE_ARCH_MEMCPY=y
CONFIG_TPL_USE_ARCH_MEMSET=y
CONFIG_USE_ARCH_MEMCPY=y
CONFIG_USE_ARCH_MEMSET=y
CONFIG_USE_PRIVATE_LIBGCC=y

21
u-boot/configs/rv1126b-ipc.config
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@ -0,0 +1,21 @@
CONFIG_BASE_DEFCONFIG="rv1126b_defconfig"
# CONFIG_CMD_GPT is not set
CONFIG_CMD_SCRIPT_UPDATE=y
# CONFIG_EFI_PARTITION is not set
CONFIG_ENVF_LIST="blkdevparts mtdparts sys_bootargs app reserved ipaddr serverip netmask gatewayip ethaddr"
CONFIG_ENVF=y
CONFIG_ENV_NAND_OFFSET=0x0
CONFIG_ENV_NAND_OFFSET_REDUND=0x0
CONFIG_ENV_NAND_SIZE=0x40000
CONFIG_ENV_NOR_OFFSET=0x0
CONFIG_ENV_NOR_OFFSET_REDUND=0x0
CONFIG_ENV_NOR_SIZE=0x10000
CONFIG_ENV_OFFSET=0x0
CONFIG_ENV_OFFSET_REDUND=0x0
CONFIG_ENV_PARTITION=y
CONFIG_LOADER_INI="RV1126BMINIALL_IPC.ini"
# CONFIG_SPL_EFI_PARTITION is not set
CONFIG_SPL_ENVF=y
CONFIG_SPL_ENV_PARTITION=y
CONFIG_SPL_FIT_IMAGE_KB=512
CONFIG_SPL_FIT_IMAGE_MULTIPLE=1

166
u-boot/configs/rv1126b-spi-nor_defconfig
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@ -0,0 +1,166 @@
CONFIG_ARM=y
CONFIG_ARCH_ROCKCHIP=y
CONFIG_SPL_GPIO_SUPPORT=y
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_SYS_MALLOC_F_LEN=0x80000
CONFIG_SPL_FIT_GENERATOR="arch/arm/mach-rockchip/make_fit_atf.sh"
CONFIG_ROCKCHIP_RV1126B=y
CONFIG_ROCKCHIP_FIT_IMAGE=y
CONFIG_ROCKCHIP_VENDOR_PARTITION=y
CONFIG_USING_KERNEL_DTB_V2=y
CONFIG_ROCKCHIP_FIT_IMAGE_PACK=y
CONFIG_ROCKCHIP_NEW_IDB=y
CONFIG_SPL_SERIAL_SUPPORT=y
CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
CONFIG_TARGET_EVB_RV1126B=y
CONFIG_SPL_LIBDISK_SUPPORT=y
CONFIG_SPL_SPI_FLASH_SUPPORT=y
CONFIG_SPL_SPI_SUPPORT=y
CONFIG_ARMV8_CRYPTO=y
CONFIG_DEFAULT_DEVICE_TREE="rv1126b-evb"
CONFIG_DEBUG_UART=y
CONFIG_FIT=y
CONFIG_FIT_IMAGE_POST_PROCESS=y
CONFIG_SPL_LOAD_FIT=y
CONFIG_SPL_FIT_IMAGE_POST_PROCESS=y
# CONFIG_SPL_SYS_DCACHE_OFF is not set
CONFIG_SPL_FIT_IMAGE_KB=896
CONFIG_SPL_FIT_IMAGE_MULTIPLE=1
CONFIG_BOOTDELAY=0
CONFIG_SYS_CONSOLE_INFO_QUIET=y
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_ANDROID_BOOTLOADER=y
CONFIG_ANDROID_AVB=y
CONFIG_ANDROID_BOOT_IMAGE_HASH=y
CONFIG_BOARD_RNG_SEED=y
CONFIG_SPL_BOARD_INIT=y
# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
# CONFIG_SPL_LEGACY_IMAGE_SUPPORT is not set
CONFIG_SPL_SEPARATE_BSS=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION=0x1
CONFIG_SPL_MTD_SUPPORT=y
CONFIG_SPL_ATF=y
CONFIG_SPL_AB=y
CONFIG_FASTBOOT_BUF_ADDR=0x40c00800
CONFIG_FASTBOOT_BUF_SIZE=0x07000000
CONFIG_FASTBOOT_FLASH=y
CONFIG_FASTBOOT_FLASH_MMC_DEV=0
CONFIG_CMD_BOOTZ=y
CONFIG_CMD_DTIMG=y
# CONFIG_CMD_ELF is not set
# CONFIG_CMD_IMI is not set
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_XIMG is not set
# CONFIG_CMD_LZMADEC is not set
# CONFIG_CMD_UNZIP is not set
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_FPGA is not set
CONFIG_CMD_GPIO=y
CONFIG_RANDOM_UUID=y
# CONFIG_CMD_LOADB is not set
# CONFIG_CMD_LOADS is not set
CONFIG_CMD_BOOT_ANDROID=y
CONFIG_CMD_MMC=y
CONFIG_CMD_SF=y
CONFIG_CMD_SPI=y
CONFIG_CMD_USB=y
CONFIG_CMD_USB_MASS_STORAGE=y
# CONFIG_CMD_ITEST is not set
# CONFIG_CMD_SETEXPR is not set
# CONFIG_CMD_MISC is not set
CONFIG_CMD_MTD_BLK=y
# CONFIG_SPL_DOS_PARTITION is not set
# CONFIG_ISO_PARTITION is not set
# CONFIG_EFI_PARTITION is not set
CONFIG_SPL_OF_CONTROL=y
CONFIG_SPL_DTB_MINIMUM=y
CONFIG_OF_LIVE=y
CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
CONFIG_OF_U_BOOT_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
# CONFIG_NET_TFTP_VARS is not set
CONFIG_REGMAP=y
CONFIG_SPL_REGMAP=y
CONFIG_SYSCON=y
CONFIG_SPL_SYSCON=y
# CONFIG_SARADC_ROCKCHIP is not set
CONFIG_SARADC_ROCKCHIP_V2=y
CONFIG_CLK=y
CONFIG_SPL_CLK=y
CONFIG_DM_RNG=y
CONFIG_RNG_ROCKCHIP=y
CONFIG_GPIO_HOG=y
CONFIG_ROCKCHIP_GPIO=y
CONFIG_ROCKCHIP_GPIO_V2=y
CONFIG_SYS_I2C_ROCKCHIP=y
CONFIG_I2C_MUX=y
CONFIG_DM_KEY=y
CONFIG_ADC_KEY=y
CONFIG_MISC=y
CONFIG_SPL_MISC=y
CONFIG_MISC_DECOMPRESS=y
CONFIG_SPL_MISC_DECOMPRESS=y
CONFIG_MMC_DW=y
CONFIG_MMC_DW_ROCKCHIP=y
CONFIG_MTD=y
CONFIG_MTD_BLK=y
CONFIG_MTD_DEVICE=y
CONFIG_SPI_FLASH=y
CONFIG_SF_DEFAULT_MODE=0x1
CONFIG_SF_DEFAULT_SPEED=50000000
CONFIG_SPI_FLASH_GIGADEVICE=y
CONFIG_SPI_FLASH_MACRONIX=y
CONFIG_SPI_FLASH_WINBOND=y
CONFIG_SPI_FLASH_MTD=y
CONFIG_PHY_ROCKCHIP_INNO_USB2=y
CONFIG_PHY_ROCKCHIP_NANENG_COMBOPHY=y
CONFIG_PINCTRL=y
CONFIG_SPL_PINCTRL=y
CONFIG_DM_PMIC=y
CONFIG_PMIC_RK801=y
CONFIG_REGULATOR_PWM=y
CONFIG_DM_REGULATOR_FIXED=y
CONFIG_DM_REGULATOR_GPIO=y
CONFIG_REGULATOR_RK801=y
CONFIG_RAM=y
CONFIG_SPL_RAM=y
CONFIG_TPL_RAM=y
CONFIG_DM_RESET=y
CONFIG_SPL_DM_RESET=y
CONFIG_SPL_RESET_ROCKCHIP=y
CONFIG_BAUDRATE=1500000
CONFIG_DEBUG_UART_BASE=0x20810000
CONFIG_DEBUG_UART_CLOCK=24000000
CONFIG_DEBUG_UART_SHIFT=2
CONFIG_ROCKCHIP_SFC=y
CONFIG_SYSRESET=y
CONFIG_USB=y
CONFIG_USB_XHCI_HCD=y
CONFIG_USB_XHCI_DWC3=y
CONFIG_USB_EHCI_HCD=y
CONFIG_USB_EHCI_GENERIC=y
CONFIG_USB_OHCI_HCD=y
CONFIG_USB_OHCI_GENERIC=y
CONFIG_USB_DWC3=y
CONFIG_USB_DWC3_GADGET=y
CONFIG_USB_DWC3_GENERIC=y
CONFIG_USB_STORAGE=y
CONFIG_USB_GADGET=y
CONFIG_USB_GADGET_MANUFACTURER="Rockchip"
CONFIG_USB_GADGET_VENDOR_NUM=0x2207
CONFIG_USB_GADGET_PRODUCT_NUM=0x110f
CONFIG_USB_GADGET_DOWNLOAD=y
CONFIG_USE_TINY_PRINTF=y
CONFIG_LIB_RAND=y
CONFIG_SPL_TINY_MEMSET=y
CONFIG_LZ4=y
CONFIG_SPL_LZMA=y
CONFIG_SPL_GZIP=y
CONFIG_ERRNO_STR=y
# CONFIG_EFI_LOADER is not set
CONFIG_AVB_LIBAVB=y
CONFIG_AVB_LIBAVB_AB=y
CONFIG_AVB_LIBAVB_ATX=y
CONFIG_AVB_LIBAVB_USER=y
CONFIG_RK_AVB_LIBAVB_USER=y

81
u-boot/configs/rv1126b-usbplug.config
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@ -0,0 +1,81 @@
CONFIG_ARM64=y
CONFIG_ARM_PSCI_FW=y
CONFIG_ARM_SMCCC=y
# CONFIG_ARMV8_CRYPTO is not set
# CONFIG_ARMV8_MULTIENTRY is not set
# CONFIG_ARMV8_PSCI is not set
# CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT is not set
# CONFIG_ARMV8_SET_SMPEN is not set
CONFIG_BASE_DEFCONFIG="rockchip-usbplug_defconfig"
CONFIG_CMD_BOOTI=y
CONFIG_DEBUG_UART_BASE=0x20810000
CONFIG_DEFAULT_DEVICE_TREE="rv1126b-evb"
CONFIG_DMA_ADDR_T_64BIT=y
CONFIG_DM_RESET=y
CONFIG_FIRMWARE=y
CONFIG_GICV2=y
CONFIG_IRQ=y
CONFIG_MTD_NAND_BBT_USING_FLASH=y
CONFIG_MTD_NAND_CORE=y
CONFIG_MTD_SPI_NAND=y
# CONFIG_NAND_ARASAN is not set
# CONFIG_NAND_ATMEL is not set
# CONFIG_NAND_BRCMNAND is not set
# CONFIG_NAND_DAVINCI is not set
# CONFIG_NAND_DENALI_DT is not set
# CONFIG_NAND_LPC32XX_SLC is not set
# CONFIG_NAND_PXA3XX is not set
# CONFIG_NAND_ROCKCHIP is not set
# CONFIG_NAND_ROCKCHIP_V9 is not set
# CONFIG_NAND_VF610_NFC is not set
CONFIG_NAND=y
# CONFIG_NAND_ZYNQ is not set
# CONFIG_NOP_PHY is not set
CONFIG_OF_LIVE=y
CONFIG_PHYS_64BIT=y
CONFIG_PHY=y
# CONFIG_POSITION_INDEPENDENT is not set
CONFIG_PSCI_RESET=y
CONFIG_RESET_ROCKCHIP=y
CONFIG_ROCKCHIP_BOOT_MODE_REG=0x20130220
CONFIG_ROCKCHIP_BROM_HELPER=y
# CONFIG_ROCKCHIP_DEBUGGER is not set
CONFIG_ROCKCHIP_IRAM_START_ADDR=0x3ffb0000
CONFIG_ROCKCHIP_NEW_IDB=y
CONFIG_ROCKCHIP_RV1126B=y
# CONFIG_ROCKCHIP_RV1126 is not set
CONFIG_ROCKCHIP_STIMER_BASE=0x20820000
# CONFIG_SCMI_FIRMWARE is not set
CONFIG_SPI_FLASH_SFDP_SUPPORT=y
CONFIG_SPI_FLASH_XMC=y
CONFIG_SPI_FLASH_XTX=y
CONFIG_SPI_NAND_BIWIN=y
CONFIG_SPI_NAND_DOSILICON=y
CONFIG_SPI_NAND_ESMT=y
CONFIG_SPI_NAND_ETRON=y
CONFIG_SPI_NAND_FMSH=y
CONFIG_SPI_NAND_FORESEE=y
CONFIG_SPI_NAND_GIGADEVICE=y
CONFIG_SPI_NAND_GSTO=y
CONFIG_SPI_NAND_HYF=y
CONFIG_SPI_NAND_JSC=y
CONFIG_SPI_NAND_MACRONIX=y
CONFIG_SPI_NAND_MICRON=y
CONFIG_SPI_NAND_SILICONGO=y
CONFIG_SPI_NAND_SKYHIGH=y
CONFIG_SPI_NAND_TOSHIBA=y
CONFIG_SPI_NAND_UNIM=y
CONFIG_SPI_NAND_WINBOND=y
CONFIG_SPI_NAND_XINCUN=y
CONFIG_SPI_NAND_XTX=y
# CONFIG_SPL_ARMV8_SEC_FIRMWARE_SUPPORT is not set
CONFIG_SPL_LDSCRIPT="arch/arm/cpu/armv8/u-boot-spl.lds"
# CONFIG_SPL_SCMI_FIRMWARE is not set
CONFIG_STATIC_RELA=y
CONFIG_SYS_ARM_ARCH=8
CONFIG_SYS_BOARD="evb_rv1126b"
CONFIG_SYS_CONFIG_NAME="evb_rv1126b"
CONFIG_SYS_CPU="armv8"
CONFIG_SYSRESET_PSCI=y
CONFIG_TARGET_EVB_RV1126B=y
CONFIG_OF_ADDR_SIZE_AUTO_NOPARENT=y

175
u-boot/configs/rv1126b_defconfig
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@ -0,0 +1,175 @@
CONFIG_ARM=y
CONFIG_ARCH_ROCKCHIP=y
CONFIG_SPL_GPIO_SUPPORT=y
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_SYS_MALLOC_F_LEN=0x80000
CONFIG_SPL_FIT_GENERATOR="arch/arm/mach-rockchip/make_fit_atf.sh"
CONFIG_ROCKCHIP_RV1126B=y
CONFIG_ROCKCHIP_FIT_IMAGE=y
CONFIG_ROCKCHIP_VENDOR_PARTITION=y
CONFIG_USING_KERNEL_DTB_V2=y
CONFIG_ROCKCHIP_FIT_IMAGE_PACK=y
CONFIG_ROCKCHIP_NEW_IDB=y
CONFIG_ROCKCHIP_EMMC_IOMUX=y
CONFIG_SPL_SERIAL_SUPPORT=y
CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
CONFIG_TARGET_EVB_RV1126B=y
CONFIG_SPL_LIBDISK_SUPPORT=y
CONFIG_SPL_SPI_FLASH_SUPPORT=y
CONFIG_SPL_SPI_SUPPORT=y
CONFIG_ARMV8_CRYPTO=y
CONFIG_DEFAULT_DEVICE_TREE="rv1126b-evb"
CONFIG_DEBUG_UART=y
# CONFIG_ANDROID_BOOT_IMAGE is not set
CONFIG_FIT=y
CONFIG_FIT_IMAGE_POST_PROCESS=y
CONFIG_SPL_LOAD_FIT=y
CONFIG_SPL_FIT_IMAGE_POST_PROCESS=y
# CONFIG_SPL_SYS_DCACHE_OFF is not set
CONFIG_BOOTDELAY=0
CONFIG_SYS_CONSOLE_INFO_QUIET=y
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_BOARD_RNG_SEED=y
CONFIG_SPL_BOARD_INIT=y
# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
# CONFIG_SPL_LEGACY_IMAGE_SUPPORT is not set
CONFIG_SPL_SEPARATE_BSS=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION=0x1
CONFIG_SPL_MTD_SUPPORT=y
CONFIG_SPL_ATF=y
CONFIG_SPL_AB=y
CONFIG_FASTBOOT_BUF_ADDR=0x40c00800
CONFIG_FASTBOOT_BUF_SIZE=0x07000000
CONFIG_FASTBOOT_FLASH=y
CONFIG_FASTBOOT_FLASH_MMC_DEV=0
CONFIG_CMD_BOOTZ=y
CONFIG_CMD_DTIMG=y
# CONFIG_CMD_ELF is not set
# CONFIG_CMD_IMI is not set
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_XIMG is not set
# CONFIG_CMD_LZMADEC is not set
# CONFIG_CMD_UNZIP is not set
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_FPGA is not set
CONFIG_CMD_GPIO=y
CONFIG_CMD_GPT=y
# CONFIG_CMD_LOADB is not set
# CONFIG_CMD_LOADS is not set
CONFIG_CMD_MMC=y
CONFIG_CMD_SF=y
CONFIG_CMD_SPI=y
CONFIG_CMD_USB=y
CONFIG_CMD_USB_MASS_STORAGE=y
# CONFIG_CMD_ITEST is not set
# CONFIG_CMD_SETEXPR is not set
# CONFIG_CMD_MISC is not set
CONFIG_CMD_MTD_BLK=y
# CONFIG_SPL_DOS_PARTITION is not set
# CONFIG_ISO_PARTITION is not set
CONFIG_EFI_PARTITION_ENTRIES_NUMBERS=64
CONFIG_OF_ADDR_SIZE_AUTO_NOPARENT=y
CONFIG_SPL_OF_CONTROL=y
CONFIG_SPL_DTB_MINIMUM=y
CONFIG_OF_LIVE=y
CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
CONFIG_OF_U_BOOT_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
# CONFIG_NET_TFTP_VARS is not set
CONFIG_REGMAP=y
CONFIG_SPL_REGMAP=y
CONFIG_SYSCON=y
CONFIG_SPL_SYSCON=y
# CONFIG_SARADC_ROCKCHIP is not set
CONFIG_SARADC_ROCKCHIP_V2=y
CONFIG_CLK=y
CONFIG_SPL_CLK=y
CONFIG_DM_CRYPTO=y
CONFIG_SPL_DM_CRYPTO=y
CONFIG_ROCKCHIP_EC=y
CONFIG_ROCKCHIP_CRYPTO_CE=y
CONFIG_SPL_ROCKCHIP_CRYPTO_CE=y
CONFIG_DM_RNG=y
CONFIG_RNG_ROCKCHIP=y
CONFIG_GPIO_HOG=y
CONFIG_ROCKCHIP_GPIO=y
CONFIG_ROCKCHIP_GPIO_V2=y
CONFIG_SYS_I2C_ROCKCHIP=y
CONFIG_I2C_MUX=y
CONFIG_DM_KEY=y
CONFIG_RK8XX_PWRKEY=y
CONFIG_ADC_KEY=y
CONFIG_MISC=y
CONFIG_SPL_MISC=y
CONFIG_MISC_DECOMPRESS=y
CONFIG_SPL_MISC_DECOMPRESS=y
CONFIG_ROCKCHIP_OTP=y
CONFIG_ROCKCHIP_HW_DECOMPRESS=y
CONFIG_SPL_ROCKCHIP_HW_DECOMPRESS=y
CONFIG_MMC_DW=y
CONFIG_MMC_DW_ROCKCHIP=y
CONFIG_MTD=y
CONFIG_MTD_BLK=y
CONFIG_MTD_DEVICE=y
CONFIG_MTD_SPI_NAND=y
CONFIG_SPI_FLASH=y
CONFIG_SF_DEFAULT_MODE=0x1
CONFIG_SF_DEFAULT_SPEED=50000000
CONFIG_SPI_FLASH_GIGADEVICE=y
CONFIG_SPI_FLASH_MACRONIX=y
CONFIG_SPI_FLASH_WINBOND=y
CONFIG_SPI_FLASH_MTD=y
CONFIG_PHY_ROCKCHIP_INNO_USB2=y
CONFIG_PHY_ROCKCHIP_NANENG_COMBOPHY=y
CONFIG_PINCTRL=y
CONFIG_SPL_PINCTRL=y
CONFIG_DM_PMIC=y
CONFIG_PMIC_RK801=y
CONFIG_PMIC_RK8XX=y
CONFIG_REGULATOR_PWM=y
CONFIG_DM_REGULATOR_FIXED=y
CONFIG_DM_REGULATOR_GPIO=y
CONFIG_REGULATOR_RK801=y
CONFIG_REGULATOR_RK8XX=y
CONFIG_RAM=y
CONFIG_SPL_RAM=y
CONFIG_TPL_RAM=y
CONFIG_DM_RESET=y
CONFIG_SPL_DM_RESET=y
CONFIG_SPL_RESET_ROCKCHIP=y
CONFIG_BAUDRATE=1500000
CONFIG_DEBUG_UART_BASE=0x20810000
CONFIG_DEBUG_UART_CLOCK=24000000
CONFIG_DEBUG_UART_SHIFT=2
CONFIG_ROCKCHIP_SFC=y
CONFIG_SYSRESET=y
CONFIG_USB=y
CONFIG_USB_XHCI_HCD=y
CONFIG_USB_XHCI_DWC3=y
CONFIG_USB_EHCI_HCD=y
CONFIG_USB_EHCI_GENERIC=y
CONFIG_USB_OHCI_HCD=y
CONFIG_USB_OHCI_GENERIC=y
CONFIG_USB_DWC3=y
CONFIG_USB_DWC3_GADGET=y
CONFIG_USB_DWC3_GENERIC=y
CONFIG_USB_STORAGE=y
CONFIG_USB_GADGET=y
CONFIG_USB_GADGET_MANUFACTURER="Rockchip"
CONFIG_USB_GADGET_VENDOR_NUM=0x2207
CONFIG_USB_GADGET_PRODUCT_NUM=0x110f
CONFIG_USB_GADGET_DOWNLOAD=y
CONFIG_USE_TINY_PRINTF=y
CONFIG_LIB_RAND=y
CONFIG_SPL_TINY_MEMSET=y
CONFIG_LZ4=y
CONFIG_SPL_LZMA=y
CONFIG_SPL_GZIP=y
CONFIG_ERRNO_STR=y
# CONFIG_EFI_LOADER is not set
CONFIG_AVB_LIBAVB=y
CONFIG_AVB_LIBAVB_AB=y
CONFIG_AVB_LIBAVB_ATX=y
CONFIG_AVB_LIBAVB_USER=y
CONFIG_RK_AVB_LIBAVB_USER=y

2
u-boot/drivers/Kconfig
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@ -40,6 +40,8 @@ source "drivers/i2c/Kconfig"
source "drivers/input/Kconfig"
source "drivers/keylad/Kconfig"
source "drivers/led/Kconfig"
source "drivers/mailbox/Kconfig"

3
u-boot/drivers/Makefile
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@ -5,6 +5,7 @@
obj-$(CONFIG_$(SPL_TPL_)CLK) += clk/
obj-$(CONFIG_$(SPL_TPL_)DM) += core/
obj-$(CONFIG_$(SPL_TPL_)DM_CRYPTO) += crypto/
obj-$(CONFIG_$(SPL_TPL_)DM_KEYLAD) += keylad/
obj-$(CONFIG_$(SPL_TPL_)DM_RNG) += rng/
obj-$(CONFIG_$(SPL_TPL_)DRIVERS_MISC_SUPPORT) += misc/ sysreset/ firmware/
obj-$(CONFIG_$(SPL_TPL_)I2C_SUPPORT) += i2c/
@ -27,6 +28,7 @@ ifdef CONFIG_SPL_BUILD
obj-$(CONFIG_SPL_ADC_SUPPORT) += adc/
obj-$(CONFIG_SPL_CPU_SUPPORT) += cpu/
obj-$(CONFIG_SPL_CRYPTO_SUPPORT) += crypto/
obj-$(CONFIG_SPL_KEYLAD_SUPPORT) += keylad/
obj-$(CONFIG_SPL_GPIO_SUPPORT) += gpio/
obj-$(CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT) += ddr/fsl/
obj-$(CONFIG_ARMADA_38X) += ddr/marvell/a38x/
@ -85,6 +87,7 @@ obj-y += block/
obj-$(CONFIG_BOOTCOUNT_LIMIT) += bootcount/
obj-$(CONFIG_CPU) += cpu/
obj-y += crypto/
obj-y += keylad/
obj-y += firmware/
obj-$(CONFIG_FPGA) += fpga/
obj-y += misc/

17
u-boot/drivers/adc/rockchip-saradc-v2.c
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@ -93,6 +93,7 @@ struct rockchip_saradc_data {
int num_bits;
int num_channels;
unsigned long clk_rate;
int das_soc_data;
};
struct rockchip_saradc_priv {
@ -146,7 +147,10 @@ static int rockchip_saradc_start_channel(struct udevice *dev, int channel)
reset_deassert(&priv->rst);
#endif
writel(0x20, &priv->regs->t_pd_soc);
writel(0xc, &priv->regs->t_das_soc);
if (priv->data->das_soc_data)
writel(priv->data->das_soc_data, &priv->regs->t_das_soc);
else
writel(0xc, &priv->regs->t_das_soc);
val = SARADC2_EN_END_INT << 16 | SARADC2_EN_END_INT;
writel(val, &priv->regs->end_int_en);
val = SARADC2_START | SARADC2_SINGLE_MODE | channel;
@ -250,6 +254,13 @@ static const struct rockchip_saradc_data rv1103b_saradc_data = {
.clk_rate = 1000000,
};
static const struct rockchip_saradc_data rv1126b_saradc_data = {
.num_bits = 13,
.num_channels = 8,
.clk_rate = 24000000,
.das_soc_data = 0x14,
};
static const struct udevice_id rockchip_saradc_ids[] = {
{
.compatible = "rockchip,rk3588-saradc",
@ -271,6 +282,10 @@ static const struct udevice_id rockchip_saradc_ids[] = {
.compatible = "rockchip,rv1103b-saradc",
.data = (ulong)&rv1103b_saradc_data
},
{
.compatible = "rockchip,rv1126b-saradc",
.data = (ulong)&rv1126b_saradc_data
},
{ }
};

25
u-boot/drivers/block/blk-uclass.c
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@ -342,6 +342,18 @@ ulong blk_write_devnum(enum if_type if_type, int devnum, lbaint_t start,
return blk_dwrite(desc, start, blkcnt, buffer);
}
ulong blk_write_zeroes_devnum(enum if_type if_type, int devnum, lbaint_t start,
lbaint_t blkcnt)
{
struct blk_desc *desc;
int ret;
ret = get_desc(if_type, devnum, &desc);
if (ret)
return ret;
return blk_dwrite_zeroes(desc, start, blkcnt);
}
ulong blk_erase_devnum(enum if_type if_type, int devnum, lbaint_t start,
lbaint_t blkcnt)
{
@ -480,6 +492,19 @@ unsigned long blk_dwrite(struct blk_desc *block_dev, lbaint_t start,
return ops->write(dev, start, blkcnt, buffer);
}
unsigned long blk_dwrite_zeroes(struct blk_desc *block_dev, lbaint_t start,
lbaint_t blkcnt)
{
struct udevice *dev = block_dev->bdev;
const struct blk_ops *ops = blk_get_ops(dev);
if (!ops->write_zeroes)
return -ENOSYS;
blkcache_invalidate(block_dev->if_type, block_dev->devnum);
return ops->write_zeroes(dev, start, blkcnt);
}
unsigned long blk_derase(struct blk_desc *block_dev, lbaint_t start,
lbaint_t blkcnt)
{

1
u-boot/drivers/clk/rockchip/Makefile
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@ -27,3 +27,4 @@ obj-$(CONFIG_ROCKCHIP_RV1103B) += clk_rv1103b.o
obj-$(CONFIG_ROCKCHIP_RV1106) += clk_rv1106.o
obj-$(CONFIG_ROCKCHIP_RV1108) += clk_rv1108.o
obj-$(CONFIG_ROCKCHIP_RV1126) += clk_rv1126.o
obj-$(CONFIG_ROCKCHIP_RV1126B) += clk_rv1126b.o

2
u-boot/drivers/clk/rockchip/clk_rk3506.c
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@ -981,6 +981,7 @@ static ulong rk3506_mac_get_rate(struct rk3506_clk_priv *priv, ulong clk_id)
case CLK_MAC_OUT:
con = readl(&cru->pmuclksel_con[0]);
div = (con & CLK_MAC_OUT_DIV_MASK) >> CLK_MAC_OUT_DIV_SHIFT;
break;
default:
return -ENOENT;
}
@ -1005,6 +1006,7 @@ static ulong rk3506_mac_set_rate(struct rk3506_clk_priv *priv, ulong clk_id,
div = DIV_ROUND_UP(priv->gpll_hz, rate);
rk_clrsetreg(&cru->pmuclksel_con[0], CLK_MAC_OUT_DIV_MASK,
((div - 1) << CLK_MAC_OUT_DIV_SHIFT));
break;
default:
return -ENOENT;
}

1826
u-boot/drivers/clk/rockchip/clk_rv1126b.c
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File diff suppressed because it is too large Load Diff

65
u-boot/drivers/crypto/crypto-uclass.c
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@ -4,6 +4,7 @@
*/
#include <crypto.h>
#include <keylad.h>
static const u8 null_hash_sha1_value[] = {
0xda, 0x39, 0xa3, 0xee, 0x5e, 0x6b, 0x4b, 0x0d,
@ -69,6 +70,14 @@ u32 crypto_algo_nbits(u32 algo)
return 3072;
case CRYPTO_RSA4096:
return 4096;
case CRYPTO_SM2:
return 256;
case CRYPTO_ECC_192R1:
return 192;
case CRYPTO_ECC_224R1:
return 224;
case CRYPTO_ECC_256R1:
return 256;
}
printf("Unknown crypto algorithm: 0x%x\n", algo);
@ -264,6 +273,19 @@ int crypto_rsa_verify(struct udevice *dev, rsa_key *ctx, u8 *sign, u8 *output)
return ops->rsa_verify(dev, ctx, sign, output);
}
int crypto_ec_verify(struct udevice *dev, ec_key *ctx, u8 *hash, u32 hash_len, u8 *sign)
{
const struct dm_crypto_ops *ops = device_get_ops(dev);
if (!ops || !ops->ec_verify)
return -ENOSYS;
if (!ctx || !ctx->x || !ctx->y || !ctx->y || !hash || hash_len == 0 || !sign)
return -EINVAL;
return ops->ec_verify(dev, ctx, hash, hash_len, sign);
}
int crypto_cipher(struct udevice *dev, cipher_context *ctx,
const u8 *in, u8 *out, u32 len, bool enc)
{
@ -272,6 +294,9 @@ int crypto_cipher(struct udevice *dev, cipher_context *ctx,
if (!ops || !ops->cipher_crypt)
return -ENOSYS;
if (!ctx || !ctx->key || ctx->key_len == 0)
return -EINVAL;
return ops->cipher_crypt(dev, ctx, in, out, len, enc);
}
@ -283,6 +308,9 @@ int crypto_mac(struct udevice *dev, cipher_context *ctx,
if (!ops || !ops->cipher_mac)
return -ENOSYS;
if (!ctx || !ctx->key || ctx->key_len == 0)
return -EINVAL;
return ops->cipher_mac(dev, ctx, in, len, tag);
}
@ -295,9 +323,46 @@ int crypto_ae(struct udevice *dev, cipher_context *ctx,
if (!ops || !ops->cipher_ae)
return -ENOSYS;
if (!ctx || !ctx->key || ctx->key_len == 0)
return -EINVAL;
return ops->cipher_ae(dev, ctx, in, len, aad, aad_len, out, tag);
}
int crypto_fw_cipher(struct udevice *dev, cipher_fw_context *ctx,
const u8 *in, u8 *out, u32 len, bool enc)
{
const struct dm_crypto_ops *ops = device_get_ops(dev);
struct udevice *keylad_dev;
if (!ops || !ops->cipher_fw_crypt)
return -ENOSYS;
keylad_dev = keylad_get_device();
if (!keylad_dev) {
printf("No keylad device found.\n");
return -ENOSYS;
}
if (keylad_transfer_fwkey(keylad_dev, crypto_keytable_addr(dev),
ctx->fw_keyid, ctx->key_len)) {
printf("Failed to transfer key from keylad.\n");
return -ENOSYS;
}
return ops->cipher_fw_crypt(dev, ctx, in, out, len, enc);
}
ulong crypto_keytable_addr(struct udevice *dev)
{
const struct dm_crypto_ops *ops = device_get_ops(dev);
if (!ops || !ops->keytable_addr)
return 0;
return ops->keytable_addr(dev);
}
UCLASS_DRIVER(crypto) = {
.id = UCLASS_CRYPTO,
.name = "crypto",

42
u-boot/drivers/crypto/rockchip/Kconfig
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@ -1,6 +1,6 @@
config ROCKCHIP_RSA
bool "Enable rockchip RSA support"
depends on ROCKCHIP_CRYPTO_V1 || ROCKCHIP_CRYPTO_V2
depends on ROCKCHIP_CRYPTO_V1 || ROCKCHIP_CRYPTO_V2 || ROCKCHIP_CRYPTO_CE
default y
help
This enable RSA512/RSA1024/RSA2048 algorithm support for
@ -8,15 +8,31 @@ config ROCKCHIP_RSA
config SPL_ROCKCHIP_RSA
bool "Enable rockchip RSA support in spl"
depends on SPL_ROCKCHIP_CRYPTO_V1 || SPL_ROCKCHIP_CRYPTO_V2
depends on SPL_ROCKCHIP_CRYPTO_V1 || SPL_ROCKCHIP_CRYPTO_V2 || SPL_ROCKCHIP_CRYPTO_CE
default y
help
This enable RSA512/RSA1024/RSA2048 algorithm support for
rockchip crypto module.
config ROCKCHIP_EC
bool "Enable rockchip ECC/SM2 support"
depends on ROCKCHIP_CRYPTO_V1 || ROCKCHIP_CRYPTO_V2 || ROCKCHIP_CRYPTO_CE
default n
help
This enable SM2/ECC192R1/ECC224R1/ECC256R1 algorithm support for
rockchip crypto module.
config SPL_ROCKCHIP_EC
bool "Enable rockchip ECC/SM2 support in spl"
depends on SPL_ROCKCHIP_CRYPTO_V1 || SPL_ROCKCHIP_CRYPTO_V2 || SPL_ROCKCHIP_CRYPTO_CE
default n
help
This enable SM2/ECC192R1/ECC224R1/ECC256R1 algorithm support for
rockchip crypto module.
config ROCKCHIP_CIPHER
bool "Enable rockchip cipher support"
depends on ROCKCHIP_CRYPTO_V1 || ROCKCHIP_CRYPTO_V2
depends on ROCKCHIP_CRYPTO_V1 || ROCKCHIP_CRYPTO_V2 || ROCKCHIP_CRYPTO_CE
default n
help
This enable DES/AES/SM4 algorithm support for
@ -24,7 +40,7 @@ config ROCKCHIP_CIPHER
config SPL_ROCKCHIP_CIPHER
bool "Enable rockchip cipher support in spl"
depends on SPL_ROCKCHIP_CRYPTO_V1 || SPL_ROCKCHIP_CRYPTO_V2
depends on SPL_ROCKCHIP_CRYPTO_V1 || SPL_ROCKCHIP_CRYPTO_V2 || SPL_ROCKCHIP_CRYPTO_CE
default n
help
This enable DES/AES/SM4 algorithm support for
@ -32,7 +48,7 @@ config SPL_ROCKCHIP_CIPHER
config ROCKCHIP_HMAC
bool "Enable rockchip hmac support"
depends on ROCKCHIP_CRYPTO_V1 || ROCKCHIP_CRYPTO_V2
depends on ROCKCHIP_CRYPTO_V1 || ROCKCHIP_CRYPTO_V2 || ROCKCHIP_CRYPTO_CE
default n
help
This enable HMAC algorithm support for
@ -40,7 +56,7 @@ config ROCKCHIP_HMAC
config SPL_ROCKCHIP_HMAC
bool "Enable rockchip hmac support in spl"
depends on SPL_ROCKCHIP_CRYPTO_V1 || SPL_ROCKCHIP_CRYPTO_V2
depends on SPL_ROCKCHIP_CRYPTO_V1 || SPL_ROCKCHIP_CRYPTO_V2 || SPL_ROCKCHIP_CRYPTO_CE
default n
help
This enable HMAC algorithm support for
@ -73,3 +89,17 @@ config SPL_ROCKCHIP_CRYPTO_V2
help
This enable MD5/SHA1/SHA256/RSA512/RSA1024/RSA2048 algorithm support for
rockchip crypto v2 on platforms: px30/rk3326/rk1808/rk3308.
config ROCKCHIP_CRYPTO_CE
bool "Enable rockchip crypto ce support"
depends on DM_CRYPTO
help
This enable MD5/SHA1/SHA256/RSA512/RSA1024/RSA2048/RSA3072/RSA4096 algorithm support for
rockchip crypto ce on platforms: rv1126b.
config SPL_ROCKCHIP_CRYPTO_CE
bool "Enable rockchip crypto ce support in spl"
depends on SPL_DM_CRYPTO
help
This enable MD5/SHA1/SHA256/RSA512/RSA1024/RSA2048/RSA3072/RSA4096 algorithm support for
rockchip crypto ce on platforms: rv1126b.

12
u-boot/drivers/crypto/rockchip/Makefile
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@ -4,9 +4,17 @@
# Copyright (c) 2019 Fuzhou Rockchip Electronics Co., Ltd
#
crypto_common_rsa := crypto_v2_pka.o crypto_v2_util.o crypto_mpa.o
crypto_common_ec := crypto_ecc.o crypto_v2_util.o crypto_mpa.o
obj-$(CONFIG_$(SPL_TPL_)ROCKCHIP_CRYPTO_V1) += crypto_v1.o crypto_hash_cache.o
obj-$(CONFIG_$(SPL_TPL_)ROCKCHIP_CRYPTO_V2) += crypto_v2.o crypto_hash_cache.o
obj-$(CONFIG_$(SPL_TPL_)ROCKCHIP_CRYPTO_CE) += crypto_ce.o rkce_core.o
ifneq ($(filter y,$(CONFIG_$(SPL_TPL_)ROCKCHIP_CRYPTO_V2) $(CONFIG_$(SPL_TPL_)ROCKCHIP_CRYPTO_CE))$(CONFIG_$(SPL_TPL_)ROCKCHIP_RSA),)
obj-y += $(crypto_common_rsa)
endif
ifeq ($(CONFIG_$(SPL_TPL_)ROCKCHIP_CRYPTO_V2)$(CONFIG_$(SPL_TPL_)ROCKCHIP_RSA), yy)
obj-y += crypto_v2_pka.o crypto_v2_util.o
ifneq ($(filter y,$(CONFIG_$(SPL_TPL_)ROCKCHIP_CRYPTO_V2) $(CONFIG_$(SPL_TPL_)ROCKCHIP_CRYPTO_CE))$(CONFIG_$(SPL_TPL_)ROCKCHIP_EC),)
obj-y += $(crypto_common_ec)
endif

1187
u-boot/drivers/crypto/rockchip/crypto_ce.c
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File diff suppressed because it is too large Load Diff

424
u-boot/drivers/crypto/rockchip/crypto_ecc.c
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@ -0,0 +1,424 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (c) 2024 Rockchip Electronics Co., Ltd
*/
#include <common.h>
#include <crypto.h>
#include <dm.h>
#include <linux/errno.h>
#include <rockchip/crypto_mpa.h>
#include <rockchip/crypto_v2.h>
#include <rockchip/crypto_ecc.h>
#define WORDS2BYTES(words) ((words) * 4)
#define RK_ECP_IS_BIGNUM_INVALID(b) (!b || !b->d || b->size > RK_ECP_MAX_WORDS)
#define RK_ECP_IS_POINT_INVALID(p) (RK_ECP_IS_BIGNUM_INVALID(p->x) && \
RK_ECP_IS_BIGNUM_INVALID(p->y))
/*************************************************************/
/* Macros for waiting EC machine ready states */
/*************************************************************/
#define RK_ECP_WRITE_REG(offset, val) crypto_write((val), (offset))
#define RK_ECP_READ_REG(offset) crypto_read((offset))
#define RK_ECP_RAM_FOR_ECC() \
RK_ECP_WRITE_REG(RK_ECC_RAM_CTL, RK_ECC_RAM_CTL_SEL_MASK | RK_ECC_RAM_CTL_ECC)
#define RK_ECP_RAM_FOR_CPU() \
RK_ECP_WRITE_REG(RK_ECC_RAM_CTL, RK_ECC_RAM_CTL_SEL_MASK | RK_ECC_RAM_CTL_CPU)
/* big endian to little endian */
#define RK_ECP_LOAD_DATA(dst, big_src) rk_ecp_load_data(dst, big_src)
/* little endian to littel endian */
#define RK_ECP_LOAD_DATA_EXT(dst, src, n_bytes) \
do { \
util_word_memset((void *)(dst), 0, RK_ECP_MAX_WORDS);\
util_word_memcpy((void *)(dst), (void *)(src), (n_bytes) / 4); \
} while (0)
#define RK_GET_GRPOUP_NBYTES(grp) ((grp)->p_len)
#define RK_LOAD_GROUP_A(G) do { \
grp->curve_name = #G; \
grp->wide = G ## _wide;\
grp->p = G ## _p; \
grp->p_len = sizeof(G ## _p); \
grp->a = G ## _a; \
grp->a_len = sizeof(G ## _a); \
grp->n = G ## _n; \
grp->n_len = sizeof(G ## _n); \
grp->gx = G ## _gx; \
grp->gx_len = sizeof(G ## _gx); \
grp->gy = G ## _gy; \
grp->gy_len = sizeof(G ## _gy); \
} while (0)
/* transform to big endian */
/*
* Domain parameters for secp192r1
*/
static const uint32_t secp192r1_wide = RK_ECC_CURVE_WIDE_192;
static const uint8_t secp192r1_p[] = {
0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
0xFE, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
};
static const uint8_t secp192r1_a[] = {
0xFC, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
0xFE, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
};
static const uint8_t secp192r1_gx[] = {
0x12, 0x10, 0xFF, 0x82, 0xFD, 0x0A, 0xFF, 0xF4,
0x00, 0x88, 0xA1, 0x43, 0xEB, 0x20, 0xBF, 0x7C,
0xF6, 0x90, 0x30, 0xB0, 0x0E, 0xA8, 0x8D, 0x18,
};
static const uint8_t secp192r1_gy[] = {
0x11, 0x48, 0x79, 0x1E, 0xA1, 0x77, 0xF9, 0x73,
0xD5, 0xCD, 0x24, 0x6B, 0xED, 0x11, 0x10, 0x63,
0x78, 0xDA, 0xC8, 0xFF, 0x95, 0x2B, 0x19, 0x07,
};
static const uint8_t secp192r1_n[] = {
0x31, 0x28, 0xD2, 0xB4, 0xB1, 0xC9, 0x6B, 0x14,
0x36, 0xF8, 0xDE, 0x99, 0xFF, 0xFF, 0xFF, 0xFF,
0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
};
/*
* Domain parameters for secp224r1
*/
static const uint32_t secp224r1_wide = RK_ECC_CURVE_WIDE_224;
static const uint8_t secp224r1_p[] = {
0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0xFF, 0xFF, 0xFF, 0xFF,
0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
0xFF, 0xFF, 0xFF, 0xFF, 0x00, 0x00, 0x00, 0x00,
};
static const uint8_t secp224r1_a[] = {
0xFE, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
0xFF, 0xFF, 0xFF, 0xFF, 0xFE, 0xFF, 0xFF, 0xFF,
0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
0xFF, 0xFF, 0xFF, 0xFF, 0x00, 0x00, 0x00, 0x00,
};
static const uint8_t secp224r1_gx[] = {
0x21, 0x1D, 0x5C, 0x11, 0xD6, 0x80, 0x32, 0x34,
0x22, 0x11, 0xC2, 0x56, 0xD3, 0xC1, 0x03, 0x4A,
0xB9, 0x90, 0x13, 0x32, 0x7F, 0xBF, 0xB4, 0x6B,
0xBD, 0x0C, 0x0E, 0xB7,
};
static const uint8_t secp224r1_gy[] = {
0x34, 0x7E, 0x00, 0x85, 0x99, 0x81, 0xD5, 0x44,
0x64, 0x47, 0x07, 0x5A, 0xA0, 0x75, 0x43, 0xCD,
0xE6, 0xDF, 0x22, 0x4C, 0xFB, 0x23, 0xF7, 0xB5,
0x88, 0x63, 0x37, 0xBD,
};
static const uint8_t secp224r1_n[] = {
0x3D, 0x2A, 0x5C, 0x5C, 0x45, 0x29, 0xDD, 0x13,
0x3E, 0xF0, 0xB8, 0xE0, 0xA2, 0x16, 0xFF, 0xFF,
0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
0xFF, 0xFF, 0xFF, 0xFF,
};
/*
* Domain parameters for secp256r1
*/
static const uint32_t secp256r1_wide = RK_ECC_CURVE_WIDE_256;
static const uint8_t secp256r1_p[] = {
0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
0xFF, 0xFF, 0xFF, 0xFF, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x01, 0x00, 0x00, 0x00, 0xFF, 0xFF, 0xFF, 0xFF,
};
static const uint8_t secp256r1_a[] = {
0xFC, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
0xFF, 0xFF, 0xFF, 0xFF, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x01, 0x00, 0x00, 0x00, 0xFF, 0xFF, 0xFF, 0xFF,
};
static const uint8_t secp256r1_gx[] = {
0x96, 0xC2, 0x98, 0xD8, 0x45, 0x39, 0xA1, 0xF4,
0xA0, 0x33, 0xEB, 0x2D, 0x81, 0x7D, 0x03, 0x77,
0xF2, 0x40, 0xA4, 0x63, 0xE5, 0xE6, 0xBC, 0xF8,
0x47, 0x42, 0x2C, 0xE1, 0xF2, 0xD1, 0x17, 0x6B,
};
static const uint8_t secp256r1_gy[] = {
0xF5, 0x51, 0xBF, 0x37, 0x68, 0x40, 0xB6, 0xCB,
0xCE, 0x5E, 0x31, 0x6B, 0x57, 0x33, 0xCE, 0x2B,
0x16, 0x9E, 0x0F, 0x7C, 0x4A, 0xEB, 0xE7, 0x8E,
0x9B, 0x7F, 0x1A, 0xFE, 0xE2, 0x42, 0xE3, 0x4F,
};
static const uint8_t secp256r1_n[] = {
0x51, 0x25, 0x63, 0xFC, 0xC2, 0xCA, 0xB9, 0xF3,
0x84, 0x9E, 0x17, 0xA7, 0xAD, 0xFA, 0xE6, 0xBC,
0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
0x00, 0x00, 0x00, 0x00, 0xFF, 0xFF, 0xFF, 0xFF,
};
/*
* Domain parameters for sm2p256v1_p
*/
static const uint32_t sm2p256v1_wide = RK_ECC_CURVE_WIDE_256;
static const uint8_t sm2p256v1_p[] = {
0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
0x00, 0x00, 0x00, 0x00, 0xFF, 0xFF, 0xFF, 0xFF,
0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
0xFF, 0xFF, 0xFF, 0xFF, 0xFE, 0xFF, 0xFF, 0xFF,
};
static const uint8_t sm2p256v1_a[] = {
0xFC, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
0x00, 0x00, 0x00, 0x00, 0xFF, 0xFF, 0xFF, 0xFF,
0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
0xFF, 0xFF, 0xFF, 0xFF, 0xFE, 0xFF, 0xFF, 0xFF,
};
static const uint8_t sm2p256v1_gx[] = {
0xC7, 0x74, 0x4C, 0x33, 0x89, 0x45, 0x5A, 0x71,
0xE1, 0x0B, 0x66, 0xF2, 0xBF, 0x0B, 0xE3, 0x8F,
0x94, 0xC9, 0x39, 0x6A, 0x46, 0x04, 0x99, 0x5F,
0x19, 0x81, 0x19, 0x1F, 0x2C, 0xAE, 0xC4, 0x32,
};
static const uint8_t sm2p256v1_gy[] = {
0xA0, 0xF0, 0x39, 0x21, 0xE5, 0x32, 0xDF, 0x02,
0x40, 0x47, 0x2A, 0xC6, 0x7C, 0x87, 0xA9, 0xD0,
0x53, 0x21, 0x69, 0x6B, 0xE3, 0xCE, 0xBD, 0x59,
0x9C, 0x77, 0xF6, 0xF4, 0xA2, 0x36, 0x37, 0xBC,
};
static const uint8_t sm2p256v1_n[] = {
0x23, 0x41, 0xD5, 0x39, 0x09, 0xF4, 0xBB, 0x53,
0x2B, 0x05, 0xC6, 0x21, 0x6B, 0xDF, 0x03, 0x72,
0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
0xFF, 0xFF, 0xFF, 0xFF, 0xFE, 0xFF, 0xFF, 0xFF,
};
static inline u32 word_reverse(u32 word)
{
u32 i;
u32 new_word = 0;
for (i = 0; i < sizeof(u32); i++) {
new_word |= (word & 0xff) << (8 * (sizeof(u32) - i - 1));
word >>= 8;
}
return new_word;
}
static inline bool is_ec_supported(void)
{
return !!RK_ECP_READ_REG(RK_ECC_MAX_CURVE_WIDE);
}
/* reverse endian word copy */
static int rk_ecp_load_data(u32 *dst, struct mpa_num *src)
{
u32 i;
u32 dst_pos, src_pos;
util_word_memset(dst, 0, RK_ECP_MAX_WORDS);
dst_pos = src->size - 1;
src_pos = 0;
for (i = 0; i < src->size; i++)
dst[dst_pos--] = word_reverse(src->d[src_pos++]);
return 0;
}
static int rk_word_cmp_zero(uint32_t *buf1, uint32_t n_words)
{
int ret = 0;
uint32_t i;
for (i = 0 ; i < n_words; i++) {
if (buf1[i] != 0)
ret = -EINVAL;
}
return ret;
}
/*
* Set a group using well-known domain parameters
*/
static int rk_ecp_group_load(struct rk_ecp_group *grp, enum rk_ecp_group_id id)
{
memset(grp, 0x00, sizeof(*grp));
grp->id = id;
switch (id) {
case RK_ECP_DP_SECP192R1:
RK_LOAD_GROUP_A(secp192r1);
return 0;
case RK_ECP_DP_SECP224R1:
RK_LOAD_GROUP_A(secp224r1);
return 0;
case RK_ECP_DP_SECP256R1:
RK_LOAD_GROUP_A(secp256r1);
return 0;
case RK_ECP_DP_SM2P256V1:
RK_LOAD_GROUP_A(sm2p256v1);
return 0;
default:
return -EINVAL;
}
}
static int rockchip_ecc_request_set(uint32_t ecc_ctl, uint32_t wide)
{
RK_ECP_WRITE_REG(RK_ECC_CURVE_WIDE, wide);
RK_ECP_WRITE_REG(RK_ECC_INT_EN, 0);
RK_ECP_WRITE_REG(RK_ECC_INT_ST, RK_ECP_READ_REG(RK_ECC_INT_ST));
RK_ECP_WRITE_REG(RK_ECC_CTL, ecc_ctl);
return 0;
}
static int rockchip_ecc_request_wait_done(void)
{
int ret = 0;
u32 reg_val = 0;
do {
reg_val = crypto_read(RK_ECC_INT_ST);
} while ((reg_val & 0x01) != RK_ECC_INT_ST_DONE);
if (RK_ECP_READ_REG(RK_ECC_ABN_ST)) {
ret = -EFAULT;
goto exit;
}
exit:
if (ret) {
printf("RK_ECC_CTL = %08x\n", RK_ECP_READ_REG(RK_ECC_CTL));
printf("RK_ECC_INT_EN = %08x\n", RK_ECP_READ_REG(RK_ECC_INT_EN));
printf("RK_ECC_CURVE_WIDE = %08x\n", RK_ECP_READ_REG(RK_ECC_CURVE_WIDE));
printf("RK_ECC_RAM_CTL = %08x\n", RK_ECP_READ_REG(RK_ECC_RAM_CTL));
printf("RK_ECC_INT_ST = %08x\n", RK_ECP_READ_REG(RK_ECC_INT_ST));
printf("RK_ECC_ABN_ST = %08x\n", RK_ECP_READ_REG(RK_ECC_ABN_ST));
}
RK_ECP_WRITE_REG(RK_ECC_CTL, 0);
RK_ECP_RAM_FOR_CPU();
return ret;
}
static int rockchip_ecc_request_trigger(void)
{
uint32_t ecc_ctl = RK_ECP_READ_REG(RK_ECC_CTL);
RK_ECP_RAM_FOR_ECC();
RK_ECP_WRITE_REG(RK_ECC_CTL, ecc_ctl | RK_ECC_CTL_REQ_ECC);
return rockchip_ecc_request_wait_done();
}
static uint32_t rockchip_ecc_get_group_id(uint32_t crypto_algo)
{
switch (crypto_algo) {
case CRYPTO_ECC_192R1:
return RK_ECP_DP_SECP192R1;
case CRYPTO_ECC_224R1:
return RK_ECP_DP_SECP224R1;
case CRYPTO_ECC_256R1:
return RK_ECP_DP_SECP256R1;
case CRYPTO_SM2:
return RK_ECP_DP_SM2P256V1;
default:
return RK_ECP_DP_NONE;
}
}
int rockchip_ecc_verify(uint32_t crypto_algo, uint8_t *hash, uint32_t hash_len,
struct rk_ecp_point *point_P, struct rk_ecp_point *point_sign)
{
int ret;
uint32_t curve_sel = 0;
struct mpa_num *bn_hash = NULL;
uint32_t group_id = rockchip_ecc_get_group_id(crypto_algo);
struct rk_ecp_group grp;
struct rk_ecc_verify *ecc_st = (struct rk_ecc_verify *)SM2_RAM_BASE;
if (!is_ec_supported())
return -ENOSYS;
if (!hash ||
hash_len == 0 ||
hash_len > RK_ECP_MAX_BYTES ||
RK_ECP_IS_POINT_INVALID(point_P) ||
RK_ECP_IS_POINT_INVALID(point_sign)) {
ret = -EINVAL;
goto exit;
}
ret = rk_ecp_group_load(&grp, group_id);
if (ret)
goto exit;
rk_mpa_alloc(&bn_hash, hash, BYTE2WORD(hash_len));
if (!bn_hash) {
ret = -ENOMEM;
goto exit;
}
RK_ECP_RAM_FOR_CPU();
curve_sel = group_id == RK_ECP_DP_SM2P256V1 ?
RK_ECC_CTL_FUNC_SM2_CURVER : RK_ECC_CTL_FUNC_ECC_CURVER;
RK_ECP_LOAD_DATA(ecc_st->e, bn_hash);
RK_ECP_LOAD_DATA(ecc_st->r_, point_sign->x);
RK_ECP_LOAD_DATA(ecc_st->s_, point_sign->y);
RK_ECP_LOAD_DATA(ecc_st->p_x, point_P->x);
RK_ECP_LOAD_DATA(ecc_st->p_y, point_P->y);
RK_ECP_LOAD_DATA_EXT(ecc_st->A, grp.a, grp.a_len);
RK_ECP_LOAD_DATA_EXT(ecc_st->P, grp.p, grp.p_len);
RK_ECP_LOAD_DATA_EXT(ecc_st->N, grp.n, grp.n_len);
RK_ECP_LOAD_DATA_EXT(ecc_st->G_x, grp.gx, grp.gx_len);
RK_ECP_LOAD_DATA_EXT(ecc_st->G_y, grp.gy, grp.gy_len);
rockchip_ecc_request_set(curve_sel | RK_ECC_CTL_FUNC_SEL_VERIFY, grp.wide);
ret = rockchip_ecc_request_trigger();
if (ret ||
rk_word_cmp_zero(ecc_st->v, RK_ECP_MAX_WORDS) ||
rk_word_cmp_zero(ecc_st->r_, RK_ECP_MAX_WORDS) == 0) {
ret = -EKEYREJECTED;
}
exit:
rk_mpa_free(&bn_hash);
return ret;
}

74
u-boot/drivers/crypto/rockchip/crypto_mpa.c
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@ -0,0 +1,74 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (c) 2024 Rockchip Electronics Co., Ltd
*/
#include <common.h>
#include <malloc.h>
#include <rockchip/crypto_mpa.h>
int rk_mpa_alloc(struct mpa_num **mpa, void *data, u32 word_size)
{
u32 alignment = sizeof(u32);
u32 byte_size = word_size * sizeof(u32);
struct mpa_num *tmp_mpa = NULL;
if (!mpa || word_size == 0)
return -EINVAL;
*mpa = NULL;
tmp_mpa = malloc(sizeof(*tmp_mpa));
if (!tmp_mpa)
return -ENOMEM;
memset(tmp_mpa, 0x00, sizeof(*tmp_mpa));
if (!data || (unsigned long)data % alignment) {
tmp_mpa->d = memalign(alignment, byte_size);
if (!tmp_mpa->d) {
free(tmp_mpa);
return -ENOMEM;
}
if (data)
memcpy(tmp_mpa->d, data, byte_size);
else
memset(tmp_mpa->d, 0x00, byte_size);
tmp_mpa->alloc = MPA_USE_ALLOC;
} else {
tmp_mpa->d = data;
}
tmp_mpa->size = word_size;
*mpa = tmp_mpa;
return 0;
}
void rk_mpa_free(struct mpa_num **mpa)
{
struct mpa_num *tmp_mpa = NULL;
if (mpa && (*mpa)) {
tmp_mpa = *mpa;
if (tmp_mpa->alloc == MPA_USE_ALLOC)
free(tmp_mpa->d);
free(tmp_mpa);
}
}
/*get bignum data length*/
int rk_check_size(u32 *data, u32 max_word_size)
{
for (int i = (max_word_size - 1); i >= 0; i--) {
if (data[i] == 0)
continue;
else
return (i + 1);
}
return 0;
}

114
u-boot/drivers/crypto/rockchip/crypto_v2.c
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@ -11,6 +11,7 @@
#include <clk-uclass.h>
#include <asm/arch/hardware.h>
#include <asm/arch/clock.h>
#include <rockchip/crypto_ecc.h>
#include <rockchip/crypto_hash_cache.h>
#include <rockchip/crypto_v2.h>
#include <rockchip/crypto_v2_pka.h>
@ -307,6 +308,13 @@ static u32 crypto_v3_dynamic_cap(void)
CRYPTO_RSA3072 |
CRYPTO_RSA4096;
#if CONFIG_IS_ENABLED(ROCKCHIP_EC)
capability |= (CRYPTO_SM2 |
CRYPTO_ECC_192R1 |
CRYPTO_ECC_224R1 |
CRYPTO_ECC_256R1);
#endif
for (i = 0; i < ARRAY_SIZE(cap_tbl); i++) {
ver_reg = crypto_read(cap_tbl[i].ver_offset);
@ -881,6 +889,10 @@ static int hw_cipher_init(u32 chn, const u8 *key, const u8 *twk_key,
u32 rk_mode = RK_GET_RK_MODE(mode);
u32 key_chn_sel = chn;
u32 reg_ctrl = 0;
bool use_otpkey = false;
if (!key && key_len)
use_otpkey = true;
IMSG("%s: key addr is %p, key_len is %d, iv addr is %p",
__func__, key, key_len, iv);
@ -925,7 +937,12 @@ static int hw_cipher_init(u32 chn, const u8 *key, const u8 *twk_key,
reg_ctrl |= CRYPTO_BC_DECRYPT;
/* write key data to reg */
write_key_reg(key_chn_sel, key, key_len);
if (!use_otpkey) {
write_key_reg(key_chn_sel, key, key_len);
crypto_write(CRYPTO_SEL_USER, CRYPTO_KEY_SEL);
} else {
crypto_write(CRYPTO_SEL_KEYTABLE, CRYPTO_KEY_SEL);
}
/* write twk key for xts mode */
if (rk_mode == RK_MODE_XTS)
@ -1290,6 +1307,36 @@ int rockchip_crypto_cipher(struct udevice *dev, cipher_context *ctx,
return ret;
}
int rockchip_crypto_fw_cipher(struct udevice *dev, cipher_fw_context *ctx,
const u8 *in, u8 *out, u32 len, bool enc)
{
int ret;
rk_crypto_enable_clk(dev);
switch (ctx->algo) {
case CRYPTO_DES:
ret = rk_crypto_des(dev, ctx->mode, NULL, ctx->key_len,
ctx->iv, in, out, len, enc);
break;
case CRYPTO_AES:
ret = rk_crypto_aes(dev, ctx->mode, NULL, NULL, ctx->key_len,
ctx->iv, ctx->iv_len, in, out, len, enc);
break;
case CRYPTO_SM4:
ret = rk_crypto_sm4(dev, ctx->mode, NULL, NULL, ctx->key_len,
ctx->iv, ctx->iv_len, in, out, len, enc);
break;
default:
ret = -EINVAL;
break;
}
rk_crypto_disable_clk(dev);
return ret;
}
int rk_crypto_mac(struct udevice *dev, u32 algo, u32 mode,
const u8 *key, u32 key_len,
const u8 *in, u32 len, u8 *tag)
@ -1383,6 +1430,11 @@ int rockchip_crypto_ae(struct udevice *dev, cipher_context *ctx,
return ret;
}
static ulong rockchip_crypto_keytable_addr(struct udevice *dev)
{
return CRYPTO_S_BY_KEYLAD_BASE + CRYPTO_CH0_KEY_0;
}
#endif
#if CONFIG_IS_ENABLED(ROCKCHIP_RSA)
@ -1446,6 +1498,55 @@ exit:
}
#endif
#if CONFIG_IS_ENABLED(ROCKCHIP_EC)
static int rockchip_crypto_ec_verify(struct udevice *dev, ec_key *ctx,
u8 *hash, u32 hash_len, u8 *sign)
{
struct mpa_num *bn_sign = NULL;
struct rk_ecp_point point_P, point_sign;
u32 n_bits, n_words;
int ret;
if (!ctx)
return -EINVAL;
if (ctx->algo != CRYPTO_SM2 &&
ctx->algo != CRYPTO_ECC_192R1 &&
ctx->algo != CRYPTO_ECC_224R1 &&
ctx->algo != CRYPTO_ECC_256R1)
return -EINVAL;
n_bits = crypto_algo_nbits(ctx->algo);
n_words = BITS2WORD(n_bits);
ret = rk_mpa_alloc(&bn_sign, sign, n_words);
if (ret)
goto exit;
ret = rk_mpa_alloc(&point_P.x, ctx->x, n_words);
ret |= rk_mpa_alloc(&point_P.y, ctx->y, n_words);
if (ret)
goto exit;
ret = rk_mpa_alloc(&point_sign.x, sign, n_words);
ret |= rk_mpa_alloc(&point_sign.y, sign + WORD2BYTE(n_words), n_words);
if (ret)
goto exit;
rk_crypto_enable_clk(dev);
ret = rockchip_ecc_verify(ctx->algo, hash, hash_len, &point_P, &point_sign);
rk_crypto_disable_clk(dev);
exit:
rk_mpa_free(&bn_sign);
rk_mpa_free(&point_P.x);
rk_mpa_free(&point_P.y);
rk_mpa_free(&point_sign.x);
rk_mpa_free(&point_sign.y);
return ret;
}
#endif
static const struct dm_crypto_ops rockchip_crypto_ops = {
.capability = rockchip_crypto_capability,
.sha_init = rockchip_crypto_sha_init,
@ -1454,15 +1555,20 @@ static const struct dm_crypto_ops rockchip_crypto_ops = {
#if CONFIG_IS_ENABLED(ROCKCHIP_RSA)
.rsa_verify = rockchip_crypto_rsa_verify,
#endif
#if CONFIG_IS_ENABLED(ROCKCHIP_EC)
.ec_verify = rockchip_crypto_ec_verify,
#endif
#if CONFIG_IS_ENABLED(ROCKCHIP_HMAC)
.hmac_init = rockchip_crypto_hmac_init,
.hmac_update = rockchip_crypto_hmac_update,
.hmac_final = rockchip_crypto_hmac_final,
#endif
#if CONFIG_IS_ENABLED(ROCKCHIP_CIPHER)
.cipher_crypt = rockchip_crypto_cipher,
.cipher_mac = rockchip_crypto_mac,
.cipher_ae = rockchip_crypto_ae,
.cipher_crypt = rockchip_crypto_cipher,
.cipher_mac = rockchip_crypto_mac,
.cipher_ae = rockchip_crypto_ae,
.cipher_fw_crypt = rockchip_crypto_fw_cipher,
.keytable_addr = rockchip_crypto_keytable_addr,
#endif
};

72
u-boot/drivers/crypto/rockchip/crypto_v2_pka.c
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@ -15,14 +15,12 @@
void rk_pka_ram_ctrl_enable(void)
{
crypto_write((CRYPTO_RAM_PKA_RDY << CRYPTO_WRITE_MASK_SHIFT) |
CRYPTO_RAM_PKA_RDY, CRYPTO_RAM_CTL);
crypto_write(CRYPTO_RAM_CTL_SEL_MASK | CRYPTO_RAM_CTL_PKA, CRYPTO_RAM_CTL);
}
void rk_pka_ram_ctrl_disable(void)
{
crypto_write((CRYPTO_RAM_PKA_RDY << CRYPTO_WRITE_MASK_SHIFT),
CRYPTO_RAM_CTL);
crypto_write(CRYPTO_RAM_CTL_SEL_MASK | CRYPTO_RAM_CTL_CPU, CRYPTO_RAM_CTL);
}
void rk_pka_wait_on_ram_ready(void)
@ -493,6 +491,7 @@ u32 rk_pka_init(u32 regs_sizes_ptr[RK_PKA_MAX_REGS_COUNT], u32 count_of_sizes,
void rk_pka_finish(void)
{
RK_PKA_Terminate(0);
rk_pka_ram_ctrl_disable();
PKA_CLK_DISABLE();
}
@ -802,71 +801,6 @@ static int mpa_highest_bit_index(const struct mpa_num *src)
return (int)(rk_mpanum_size(src) - 1) * RK_WORD_SIZE + b;
}
/*get bignum data length*/
static int rk_check_size(u32 *data, u32 max_word_size)
{
for (int i = (max_word_size - 1); i >= 0; i--) {
if (data[i] == 0)
continue;
else
return (i + 1);
}
return 0;
}
int rk_mpa_alloc(struct mpa_num **mpa, void *data, u32 word_size)
{
u32 alignment = sizeof(u32);
u32 byte_size = word_size * sizeof(u32);
struct mpa_num *tmp_mpa = NULL;
if (!mpa || word_size == 0)
return -EINVAL;
*mpa = NULL;
tmp_mpa = malloc(sizeof(*tmp_mpa));
if (!tmp_mpa)
return -ENOMEM;
memset(tmp_mpa, 0x00, sizeof(*tmp_mpa));
if (!data || (unsigned long)data % alignment) {
tmp_mpa->d = memalign(alignment, byte_size);
if (!tmp_mpa->d) {
free(tmp_mpa);
return -ENOMEM;
}
if (data)
memcpy(tmp_mpa->d, data, byte_size);
else
memset(tmp_mpa->d, 0x00, byte_size);
tmp_mpa->alloc = MPA_USE_ALLOC;
} else {
tmp_mpa->d = data;
}
tmp_mpa->size = word_size;
*mpa = tmp_mpa;
return 0;
}
void rk_mpa_free(struct mpa_num **mpa)
{
struct mpa_num *tmp_mpa = NULL;
if (mpa && (*mpa)) {
tmp_mpa = *mpa;
if (tmp_mpa->alloc == MPA_USE_ALLOC)
free(tmp_mpa->d);
free(tmp_mpa);
}
}
/* c = |a| + |b| */
int rk_abs_add(void *a, void *b, void *c)

623
u-boot/drivers/crypto/rockchip/rkce_core.c
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@ -0,0 +1,623 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Crypto acceleration support for Rockchip crypto engine
*
* Copyright (c) 2025 Rockchip Electronics Co., Ltd.
*
* Author: Lin Jinhan <troy.lin@rock-chips.com>
*
*/
#include <linux/bug.h>
#include <linux/delay.h>
#include <linux/string.h>
#include "rockchip/rkce_core.h"
#include "rockchip/rkce_debug.h"
#include "rockchip/rkce_error.h"
#include "rockchip/rkce_reg.h"
struct rkce_chn_info {
void *td_virt;
uint32_t int_st;
uint32_t td_id;
int result;
request_cb_func cb_func;
};
struct rkce_hardware {
struct RKCE_REG *rkce_reg;
struct rkce_chn_info chn[RKCE_TD_TYPE_MAX];
};
#define RST_TIMEOUT_MS 100
#define TD_PUSH_TIMEOUT_MS 3000
#define IP_VERSION_MASK (0xfU >> 28)
#define IP_VERSION_RKCE (0x1U >> 28)
#define GET_IP_VERSION(ver) ((ver) & IP_VERSION_MASK)
#define IS_SYMM_TD(td_type) ((td_type) == RKCE_TD_TYPE_SYMM || \
(td_type) == RKCE_TD_TYPE_SYMM_HASH_IN || \
(td_type) == RKCE_TD_TYPE_SYMM_HASH_OUT)
#define IS_HASH_TD(td_type) ((td_type) == RKCE_TD_TYPE_HASH)
#define GET_RKCE_REG(hardware) (((struct rkce_hardware *)(hardware))->rkce_reg)
#define CHECK_RKCE_INITED(hardware) WARN_ON_ONCE(!(hardware) || \
!(((struct rkce_hardware *)(hardware))->rkce_reg))
#define POLL_TIMEOUT(condition, timeout_ms) ({ \
int timeout = timeout_ms; \
while ((condition) && timeout--) { \
udelay(1000); \
} \
if (timeout < 0) \
rk_err("%s timeout!\n", #condition); \
(timeout < 0) ? -RKCE_TIMEOUT : 0; \
})
static const uint32_t cipher_mode2bit_mask[] = {
[RKCE_SYMM_MODE_ECB] = RKCE_AES_VER_ECB_FLAG_MASK,
[RKCE_SYMM_MODE_CBC] = RKCE_AES_VER_CBC_FLAG_MASK,
[RKCE_SYMM_MODE_CFB] = RKCE_AES_VER_CFB_FLAG_MASK,
[RKCE_SYMM_MODE_OFB] = RKCE_AES_VER_OFB_FLAG_MASK,
[RKCE_SYMM_MODE_CTR] = RKCE_AES_VER_CTR_FLAG_MASK,
[RKCE_SYMM_MODE_XTS] = RKCE_AES_VER_XTS_FLAG_MASK,
[RKCE_SYMM_MODE_CTS] = RKCE_AES_VER_CTS_FLAG_MASK,
[RKCE_SYMM_MODE_CCM] = RKCE_AES_VER_CCM_FLAG_MASK,
[RKCE_SYMM_MODE_GCM] = RKCE_AES_VER_GCM_FLAG_MASK,
[RKCE_SYMM_MODE_CMAC] = RKCE_AES_VER_CMAC_FLAG_MASK,
[RKCE_SYMM_MODE_CBC_MAC] = RKCE_AES_VER_CBC_MAC_FLAG_MASK,
};
static const uint32_t hash_algo2bit_mask[] = {
[RKCE_HASH_ALGO_SHA1] = RKCE_HASH_VER_SHA1_FLAG_MASK,
[RKCE_HASH_ALGO_SHA224] = RKCE_HASH_VER_SHA224_FLAG_MASK,
[RKCE_HASH_ALGO_SHA256] = RKCE_HASH_VER_SHA256_FLAG_MASK,
[RKCE_HASH_ALGO_SHA384] = RKCE_HASH_VER_SHA384_FLAG_MASK,
[RKCE_HASH_ALGO_SHA512] = RKCE_HASH_VER_SHA512_FLAG_MASK,
[RKCE_HASH_ALGO_SHA512_224] = RKCE_HASH_VER_SHA512_224_FLAG_MASK,
[RKCE_HASH_ALGO_SHA512_256] = RKCE_HASH_VER_SHA512_256_FLAG_MASK,
[RKCE_HASH_ALGO_MD5] = RKCE_HASH_VER_MD5_FLAG_MASK,
[RKCE_HASH_ALGO_SM3] = RKCE_HASH_VER_SM3_FLAG_MASK,
};
static const uint32_t hmac_algo2bit_mask[] = {
[RKCE_HASH_ALGO_SHA1] = RKCE_HMAC_VER_SHA1_FLAG_MASK,
[RKCE_HASH_ALGO_SHA256] = RKCE_HMAC_VER_SHA256_FLAG_MASK,
[RKCE_HASH_ALGO_SHA512] = RKCE_HMAC_VER_SHA512_FLAG_MASK,
[RKCE_HASH_ALGO_MD5] = RKCE_HMAC_VER_MD5_FLAG_MASK,
[RKCE_HASH_ALGO_SM3] = RKCE_HMAC_VER_SM3_FLAG_MASK,
};
static bool rk_is_cipher_support(struct RKCE_REG *rkce_reg,
uint32_t algo, uint32_t mode, uint32_t key_len)
{
uint32_t version = 0;
uint32_t mask = 0;
bool key_len_valid = true;
switch (algo) {
case RKCE_SYMM_ALGO_DES:
case RKCE_SYMM_ALGO_TDES:
version = rkce_reg->DES_VER;
if (key_len == RKCE_DES_BLOCK_SIZE)
key_len_valid = true;
else if (key_len == 2 * RKCE_DES_BLOCK_SIZE ||
key_len == 3 * RKCE_DES_BLOCK_SIZE)
key_len_valid = version & RKCE_DES_VER_TDES_FLAG_MASK;
else
key_len_valid = false;
break;
case RKCE_SYMM_ALGO_AES:
version = rkce_reg->AES_VER;
if (key_len == RKCE_AES_KEYSIZE_128)
key_len_valid = version & RKCE_AES_VER_AES128_FLAG_MASK;
else if (key_len == RKCE_AES_KEYSIZE_192)
key_len_valid = version & RKCE_AES_VER_AES192_FLAG_MASK;
else if (key_len == RKCE_KEY_AES_256)
key_len_valid = version & RKCE_AES_VER_AES256_FLAG_MASK;
else
key_len_valid = false;
break;
case RKCE_SYMM_ALGO_SM4:
version = rkce_reg->SM4_VER;
key_len_valid = (key_len == RKCE_SM4_KEYSIZE) ? true : false;
break;
default:
return false;
}
mask = cipher_mode2bit_mask[mode];
if (key_len == 0)
key_len_valid = true;
return (version & mask) && key_len_valid;
}
static bool rk_is_hash_support(struct RKCE_REG *rkce_reg, uint32_t algo, uint32_t type)
{
uint32_t version = 0;
uint32_t mask = 0;
if (type == RKCE_ALGO_TYPE_HMAC) {
version = rkce_reg->HMAC_VER;
mask = hmac_algo2bit_mask[algo];
} else if (type == RKCE_ALGO_TYPE_HASH) {
version = rkce_reg->HASH_VER;
mask = hash_algo2bit_mask[algo];
} else {
return false;
}
return version & mask;
}
static bool rk_is_asym_support(struct RKCE_REG *rkce_reg, uint32_t algo)
{
switch (algo) {
case RKCE_ASYM_ALGO_RSA:
return !!rkce_reg->PKA_VER;
case RKCE_ASYM_ALGO_ECC_P192:
case RKCE_ASYM_ALGO_ECC_P224:
case RKCE_ASYM_ALGO_ECC_P256:
case RKCE_ASYM_ALGO_SM2:
return !!rkce_reg->ECC_MAX_CURVE_WIDE;
default:
return false;
}
}
bool rkce_hw_algo_valid(void *rkce_hw, uint32_t type, uint32_t algo, uint32_t mode)
{
struct RKCE_REG *rkce_reg;
CHECK_RKCE_INITED(rkce_hw);
rkce_reg = GET_RKCE_REG(rkce_hw);
if (type == RKCE_ALGO_TYPE_CIPHER || type == RKCE_ALGO_TYPE_AEAD) {
rk_debug("CIPHER");
return rk_is_cipher_support(rkce_reg, algo, mode, 0);
} else if (type == RKCE_ALGO_TYPE_HASH || type == RKCE_ALGO_TYPE_HMAC) {
rk_debug("HASH/HMAC");
return rk_is_hash_support(rkce_reg, algo, type);
} else if (type == RKCE_ALGO_TYPE_ASYM) {
rk_debug("ASYM");
return rk_is_asym_support(rkce_reg, algo);
} else {
return false;
}
}
uint32_t rkce_get_td_type(void *td)
{
if (!td)
return ~((uint32_t)0);
return ((struct rkce_symm_td *)td)->ctrl.td_type;
}
int rkce_soft_reset(void *rkce_hw, uint32_t reset_sel)
{
struct RKCE_REG *rkce_reg;
uint32_t value = 0;
CHECK_RKCE_INITED(rkce_hw);
rkce_reg = GET_RKCE_REG(rkce_hw);
if (reset_sel & RKCE_RESET_SYMM)
value |= RKCE_RST_CTL_SW_SYMM_RESET_SHIFT;
if (reset_sel & RKCE_RESET_HASH)
value |= RKCE_RST_CTL_SW_HASH_RESET_SHIFT;
if (reset_sel & RKCE_RESET_PKA)
value |= RKCE_RST_CTL_SW_PKA_RESET_SHIFT;
rkce_reg->RST_CTL = value | RKCE_WRITE_MASK_ALL;
return POLL_TIMEOUT(rkce_reg->RST_CTL, RST_TIMEOUT_MS);
}
static int rkce_check_version(struct RKCE_REG *rkce_reg)
{
rk_debug("rkce_reg->CE_VER = %08x\n", rkce_reg->CE_VER);
if (GET_IP_VERSION(rkce_reg->CE_VER) != IP_VERSION_RKCE) {
rk_err("IP version is %08x not a RKCE module.\n", rkce_reg->CE_VER);
return -RKCE_FAULT;
}
return RKCE_SUCCESS;
}
static int rkce_init(void *rkce_hw)
{
struct RKCE_REG *rkce_reg = GET_RKCE_REG(rkce_hw);
uint32_t value = 0;
int ret;
ret = rkce_check_version(rkce_hw);
if (ret)
goto exit;
rkce_soft_reset(rkce_hw, RKCE_RESET_SYMM | RKCE_RESET_HASH | RKCE_RESET_PKA);
/* clear symm interrupt register */
rkce_reg->SYMM_INT_EN = 0;
value = rkce_reg->SYMM_INT_ST;
rkce_reg->SYMM_INT_ST = value;
ret = POLL_TIMEOUT(rkce_reg->SYMM_INT_ST, RST_TIMEOUT_MS);
if (ret)
goto exit;
/* clear hash interrupt register */
rkce_reg->HASH_INT_EN = 0;
value = rkce_reg->HASH_INT_ST;
rkce_reg->HASH_INT_ST = value;
ret = POLL_TIMEOUT(rkce_reg->HASH_INT_ST, RST_TIMEOUT_MS);
if (ret)
goto exit;
if (rkce_reg->SYMM_CONTEXT_SIZE != RKCE_TD_SYMM_CTX_SIZE) {
rk_err("rkce symm context size (%u) != %u\n",
rkce_reg->SYMM_CONTEXT_SIZE, RKCE_TD_SYMM_CTX_SIZE);
return -RKCE_INVAL;
}
if (rkce_reg->HASH_CONTEXT_SIZE != RKCE_TD_HASH_CTX_SIZE) {
rk_err("rkce hash context size (%u) != %u\n",
rkce_reg->HASH_CONTEXT_SIZE, RKCE_TD_HASH_CTX_SIZE);
return -RKCE_INVAL;
}
exit:
return ret;
}
void *rkce_hardware_alloc(void __iomem *reg_base)
{
struct rkce_hardware *hardware;
rk_debug("reg_base = %p", reg_base);
if (!reg_base)
return NULL;
hardware = malloc(sizeof(*hardware));
if (!hardware)
return NULL;
hardware->rkce_reg = reg_base;
if (rkce_init(hardware) != 0) {
free(hardware);
return NULL;
}
rk_debug("hardware = %p", hardware);
return hardware;
}
void rkce_hardware_free(void *rkce_hw)
{
if (!rkce_hw)
return;
free(rkce_hw);
}
void rkce_dump_reginfo(void *rkce_hw)
{
struct RKCE_REG *rkce_reg;
CHECK_RKCE_INITED(rkce_hw);
rkce_reg = GET_RKCE_REG(rkce_hw);
rk_info("\n============================== reg info ===========================\n");
rk_info("FIFO_ST = %08x\n", rkce_reg->FIFO_ST);
rk_info("\n");
rk_info("SYMM_INT_EN = %08x\n", rkce_reg->SYMM_INT_EN);
rk_info("SYMM_INT_ST = %08x\n", rkce_reg->SYMM_INT_ST);
rk_info("SYMM_TD_ST = %08x\n", rkce_reg->SYMM_TD_ST);
rk_info("SYMM_TD_ID = %08x\n", rkce_reg->SYMM_TD_ID);
rk_info("SYMM_ST_DBG = %08x\n", rkce_reg->SYMM_ST_DBG);
rk_info("SYMM_TD_ADDR_DBG = %08x\n", rkce_reg->SYMM_TD_ADDR_DBG);
rk_info("SYMM_TD_GRANT_DBG = %08x\n", rkce_reg->SYMM_TD_GRANT_DBG);
rk_info("\n");
rk_info("HASH_INT_EN = %08x\n", rkce_reg->HASH_INT_EN);
rk_info("HASH_INT_ST = %08x\n", rkce_reg->HASH_INT_ST);
rk_info("HASH_TD_ST = %08x\n", rkce_reg->HASH_TD_ST);
rk_info("HASH_TD_ID = %08x\n", rkce_reg->HASH_TD_ID);
rk_info("HASH_ST_DBG = %08x\n", rkce_reg->HASH_ST_DBG);
rk_info("HASH_TD_ADDR_DBG = %08x\n", rkce_reg->HASH_TD_ADDR_DBG);
rk_info("HASH_TD_GRANT_DBG = %08x\n", rkce_reg->HASH_TD_GRANT_DBG);
rk_info("===================================================================\n");
}
int rkce_push_td(void *rkce_hw, void *td)
{
int ret = RKCE_SUCCESS;
struct RKCE_REG *rkce_reg;
uint32_t td_type;
struct rkce_hardware *hardware = rkce_hw;
CHECK_RKCE_INITED(rkce_hw);
if (!td)
return -RKCE_INVAL;
td_type = rkce_get_td_type(td);
rkce_reg = GET_RKCE_REG(rkce_hw);
rkce_dump_td(td);
if (IS_SYMM_TD(td_type)) {
rk_debug("rkce symm push td virt(%p), phys(%lx)\n",
td, rkce_cma_virt2phys(td));
WRITE_ONCE(rkce_reg->SYMM_INT_EN, 0x3f);
/* wait symm fifo valid */
ret = POLL_TIMEOUT(rkce_reg->TD_LOAD_CTRL & RKCE_TD_LOAD_CTRL_SYMM_TLR_MASK,
TD_PUSH_TIMEOUT_MS);
if (ret)
goto exit;
/* set task desc address */
rkce_reg->TD_ADDR = rkce_cma_virt2phys(td);
hardware->chn[RKCE_TD_TYPE_SYMM].td_virt = td;
/* tell rkce to load task desc address as symm td */
rkce_reg->TD_LOAD_CTRL = 0xffff0000 | RKCE_TD_LOAD_CTRL_SYMM_TLR_MASK;
} else if (IS_HASH_TD(td_type)) {
rk_debug("rkce hash push td virt(%p), phys(%lx)\n",
td, rkce_cma_virt2phys(td));
WRITE_ONCE(rkce_reg->HASH_INT_EN, 0x3f);
/* wait hash fifo valid */
ret = POLL_TIMEOUT(rkce_reg->TD_LOAD_CTRL & RKCE_TD_LOAD_CTRL_HASH_TLR_MASK,
TD_PUSH_TIMEOUT_MS);
if (ret)
goto exit;
/* set task desc address */
rkce_reg->TD_ADDR = rkce_cma_virt2phys(td);
hardware->chn[RKCE_TD_TYPE_HASH].td_virt = td;
/* tell rkce to load task desc address as hash td */
rkce_reg->TD_LOAD_CTRL = 0xffff0000 | RKCE_TD_LOAD_CTRL_HASH_TLR_MASK;
} else {
return -RKCE_INVAL;
}
exit:
return ret;
}
int rkce_push_td_sync(void *rkce_hw, void *td, uint32_t timeout_ms)
{
int ret = RKCE_SUCCESS;
struct RKCE_REG *rkce_reg;
uint32_t td_type;
uint32_t value, mask;
CHECK_RKCE_INITED(rkce_hw);
if (!td)
return -RKCE_INVAL;
td_type = rkce_get_td_type(td);
rkce_reg = GET_RKCE_REG(rkce_hw);
rkce_dump_td(td);
if (IS_SYMM_TD(td_type)) {
rk_debug("rkce symm push td virt(%p), phys(%lx)\n",
td, rkce_cma_virt2phys(td));
WRITE_ONCE(rkce_reg->SYMM_INT_EN, 0x00);
/* wait symm fifo valid */
ret = POLL_TIMEOUT(rkce_reg->TD_LOAD_CTRL & RKCE_TD_LOAD_CTRL_SYMM_TLR_MASK,
timeout_ms);
if (ret)
goto exit;
/* set task desc address */
rkce_reg->TD_ADDR = rkce_cma_virt2phys(td);
/* tell rkce to load task desc address as symm td */
rkce_reg->TD_LOAD_CTRL = 0xffff0000 | RKCE_TD_LOAD_CTRL_SYMM_TLR_MASK;
/* wait symm done */
ret = POLL_TIMEOUT(!(rkce_reg->SYMM_INT_ST), timeout_ms);
mask = RKCE_SYMM_INT_ST_TD_DONE_MASK;
value = READ_ONCE(rkce_reg->SYMM_INT_ST);
WRITE_ONCE(rkce_reg->SYMM_INT_ST, value);
rk_debug("symm ret = %d, value = %08x, IN_ST = %08x\n",
ret, value, READ_ONCE(rkce_reg->SYMM_INT_ST));
} else if (IS_HASH_TD(td_type)) {
rk_debug("rkce hash push td virt(%p), phys(%lx)\n",
td, rkce_cma_virt2phys(td));
WRITE_ONCE(rkce_reg->HASH_INT_EN, 0x00);
/* wait hash fifo valid */
ret = POLL_TIMEOUT(rkce_reg->TD_LOAD_CTRL & RKCE_TD_LOAD_CTRL_HASH_TLR_MASK,
timeout_ms);
if (ret)
goto exit;
/* set task desc address */
rkce_reg->TD_ADDR = rkce_cma_virt2phys(td);
/* tell rkce to load task desc address as hash td */
rkce_reg->TD_LOAD_CTRL = 0xffff0000 | RKCE_TD_LOAD_CTRL_HASH_TLR_MASK;
/* wait hash done */
ret = POLL_TIMEOUT(!(rkce_reg->HASH_INT_ST), timeout_ms);
mask = RKCE_HASH_INT_ST_TD_DONE_MASK;
value = READ_ONCE(rkce_reg->HASH_INT_ST);
WRITE_ONCE(rkce_reg->HASH_INT_ST, value);
rk_debug("hash ret = %d, value = %08x, INT_ST = %08x\n",
ret, value, READ_ONCE(rkce_reg->HASH_INT_ST));
} else {
rk_debug("unknown td_type = %u\n", td_type);
return -RKCE_INVAL;
}
if (ret)
goto exit;
ret = (value == mask) ? 0 : -RKCE_FAULT;
exit:
return ret;
}
int rkce_init_symm_td(struct rkce_symm_td *td, struct rkce_symm_td_buf *buf)
{
if (!td ||
!buf ||
!rkce_cma_virt2phys(td) ||
!rkce_cma_virt2phys(buf)) {
rk_debug("td = %p buf = %p", td, buf);
return -RKCE_INVAL;
}
memset(td, 0x00, sizeof(*td));
td->ctrl.td_type = RKCE_TD_TYPE_SYMM;
td->task_id = rkce_cma_virt2phys(buf);
td->key_addr = rkce_cma_virt2phys(buf->key1);
td->iv_addr = rkce_cma_virt2phys(buf->iv);
td->gcm_len_addr = rkce_cma_virt2phys(&buf->gcm_len);
td->tag_addr = rkce_cma_virt2phys(buf->tag);
td->symm_ctx_addr = rkce_cma_virt2phys(buf->ctx);
return RKCE_SUCCESS;
}
int rkce_init_hash_td(struct rkce_hash_td *td, struct rkce_hash_td_buf *buf)
{
if (!td ||
!buf ||
!rkce_cma_virt2phys(td) ||
!rkce_cma_virt2phys(buf)) {
rk_debug("td = %p buf = %p", td, buf);
return -RKCE_INVAL;
}
memset(td, 0x00, sizeof(*td));
td->ctrl.td_type = RKCE_TD_TYPE_HASH;
td->task_id = rkce_cma_virt2phys(buf);
td->key_addr = rkce_cma_virt2phys(buf->key);
td->hash_addr = rkce_cma_virt2phys(buf->hash);
td->hash_ctx_addr = rkce_cma_virt2phys(buf->ctx);
return RKCE_SUCCESS;
}
int rkce_irq_callback_set(void *rkce_hw, enum rkce_td_type td_type, request_cb_func cb_func)
{
struct rkce_hardware *hardware = rkce_hw;
CHECK_RKCE_INITED(rkce_hw);
if (!cb_func)
return -RKCE_INVAL;
if (td_type == RKCE_TD_TYPE_SYMM)
hardware->chn[RKCE_TD_TYPE_SYMM].cb_func = cb_func;
else if (td_type == RKCE_TD_TYPE_HASH)
hardware->chn[RKCE_TD_TYPE_HASH].cb_func = cb_func;
else
return -RKCE_INVAL;
return RKCE_SUCCESS;
}
void rkce_irq_handler(void *rkce_hw)
{
struct rkce_chn_info *cur_chn;
struct RKCE_REG *rkce_reg;
struct rkce_hardware *hardware = rkce_hw;
CHECK_RKCE_INITED(rkce_hw);
rkce_reg = GET_RKCE_REG(rkce_hw);
if (rkce_reg->SYMM_INT_ST) {
cur_chn = &hardware->chn[RKCE_TD_TYPE_SYMM];
cur_chn->int_st = READ_ONCE(rkce_reg->SYMM_INT_ST);
cur_chn->td_id = rkce_reg->SYMM_TD_ID;
/* clear symm int */
WRITE_ONCE(rkce_reg->SYMM_INT_ST, cur_chn->int_st);
cur_chn->result = (cur_chn->int_st == RKCE_SYMM_INT_ST_TD_DONE_MASK) ?
RKCE_SUCCESS : cur_chn->int_st;
}
if (rkce_reg->HASH_INT_ST) {
cur_chn = &hardware->chn[RKCE_TD_TYPE_HASH];
cur_chn->int_st = READ_ONCE(rkce_reg->HASH_INT_ST);
cur_chn->td_id = rkce_reg->HASH_TD_ID;
/* clear hash int */
WRITE_ONCE(rkce_reg->HASH_INT_ST, cur_chn->int_st);
cur_chn->result = (cur_chn->int_st == RKCE_HASH_INT_ST_TD_DONE_MASK) ?
RKCE_SUCCESS : cur_chn->int_st;
}
}
void rkce_irq_thread(void *rkce_hw)
{
uint32_t i;
bool is_fault = false;
struct rkce_hardware *hardware = rkce_hw;
CHECK_RKCE_INITED(rkce_hw);
for (i = 0; i < ARRAY_SIZE(hardware->chn); i++) {
struct rkce_chn_info *cur_chn = &hardware->chn[i];
if (cur_chn->result) {
is_fault = true;
rk_err("td_type = %u, wrong SISR = %08x, td_id = %08x, td_virt = %p\n",
i, cur_chn->int_st, cur_chn->td_id, cur_chn->td_virt);
}
if (cur_chn->int_st == 0 || !(cur_chn->cb_func))
continue;
rk_debug("##################### finalize td %p, result = %d\n",
cur_chn->td_virt, cur_chn->result);
if (cur_chn->cb_func && cur_chn->td_virt)
cur_chn->cb_func(cur_chn->result, cur_chn->td_id, cur_chn->td_virt);
cur_chn->result = 0;
cur_chn->int_st = 0;
cur_chn->td_id = 0;
cur_chn->td_virt = NULL;
}
if (is_fault)
rkce_dump_reginfo(hardware);
}

9
u-boot/drivers/keylad/Kconfig
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menu "Keylad devices"
config SPL_DM_KEYLAD
bool "Enable Driver Model for KEYLAD drivers in spl"
depends on SPL_DM
---help---
This config enables the dm keylad support.
endmenu

6
u-boot/drivers/keylad/Makefile
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#
# Copyright (c) 2025 Rockchip Electronics Co., Ltd
#
# SPDX-License-Identifier: GPL-2.0+
obj-$(CONFIG_$(SPL_TPL_)DM_KEYLAD) += keylad-uclass.o rk_keylad.o

49
u-boot/drivers/keylad/keylad-uclass.c
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// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (c) 2025 Rockchip Electronics Co., Ltd
*/
#include <keylad.h>
struct udevice *keylad_get_device(void)
{
const struct dm_keylad_ops *ops;
struct udevice *dev;
struct uclass *uc;
int ret;
ret = uclass_get(UCLASS_KEYLAD, &uc);
if (ret)
return NULL;
for (uclass_first_device(UCLASS_KEYLAD, &dev);
dev;
uclass_next_device(&dev)) {
ops = device_get_ops(dev);
if (!ops || !ops->transfer_fwkey)
continue;
return dev;
}
return NULL;
}
int keylad_transfer_fwkey(struct udevice *dev, ulong dst,
enum RK_FW_KEYID fw_keyid, u32 keylen)
{
const struct dm_keylad_ops *ops = device_get_ops(dev);
if (!ops || !ops->transfer_fwkey)
return -ENOSYS;
if (dst == 0)
return -EINVAL;
return ops->transfer_fwkey(dev, dst, fw_keyid, keylen);
}
UCLASS_DRIVER(keylad) = {
.id = UCLASS_KEYLAD,
.name = "keylad",
};

221
u-boot/drivers/keylad/rk_keylad.c
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// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (c) 2025 Rockchip Electronics Co., Ltd
*/
#include <common.h>
#include <clk.h>
#include <keylad.h>
#include <dm.h>
#include <asm/io.h>
#include <clk-uclass.h>
#include <asm/arch/hardware.h>
#include <asm/arch/clock.h>
#define KEYLAD_APB_CMD 0x0450
#define REG_APB_CMD_EN BIT(0)
#define VALUE_APB_CMD_DISABLE 0
#define VALUE_APB_CMD_ENABLE BIT(0)
#define KEYLAD_APB_PADDR 0x0454
#define KEYLAD_APB_PWDATA 0x0458
#define KEYLAD_APB_PWRITE 0x045C
#define KEYLAD_DATA_CTL 0x0460
#define VALUE_DATA_CTL_EN BIT(15)
#define KEYLAD_KEY_SEL 0x0610
#define VALUE_KEY_SEL_OUTER_KEY 0x00000000
#define KEYLAD_LOCKSTEP_FLAG 0x0618
#define KEYLAD_LOCKSTEP_EN 0x061C
#define KEY_LADDER_OTP_KEY_REQ 0x0640
#define KL_OTP_KEY_REQ_DST_ADDR(addr) ((addr) & 0x3) // 256bit algin address
#define KL_OTP_KEY_REQ_BYTE_SWAP BIT(4)
#define KL_OTP_KEY_REQ_WORD_SWAP BIT(5)
#define KL_OTP_KEY_REQ_EN BIT(8)
#define KL_OTP_KEY_ECC_ST BIT(12)
#define KL_OTP_KEY_REQ_SRC_ADDR(addr) (((addr) & 0xffff) << 16)// byte address, dword align
#define KEY_LADDER_KEY_LEN 0x0648
#define KL_KEY_LEN(len) ((len) & 0x3f)
#define KEYLAD_KEY_REG_SIZE_BYTES 4
#define KEYLAD_KEY_REG_NUM 32
#define KEYLAD_AREA_NUM 2
#define RK_KEYLAD_TIME_OUT 10000 /* max 10ms */
#define KEYLAD_POLL_TIMEOUT(condition, timeout, ret) do { \
u32 time_out = timeout; \
while (condition) { \
if (time_out-- == 0) { \
printf("[%s] %d: time out!\n", __func__, __LINE__); \
ret = -ETIMEDOUT; \
break; \
} \
udelay(1); \
} \
} while (0)
struct rockchip_keylad_priv {
fdt_addr_t reg;
};
fdt_addr_t keylad_base;
static inline u32 keylad_read(u32 offset)
{
return readl(keylad_base + offset);
}
static inline void keylad_write(u32 offset, u32 val)
{
writel(val, keylad_base + offset);
}
static int rk_get_fwkey_param(u32 keyid, u32 *offset, u32 *max_len)
{
switch (keyid) {
case RK_FW_KEY0:
*offset = OEM_CIPHER_KEY_FW_ADDR;
*max_len = OEM_CIPHER_KEY_FW_LEN;
break;
default:
return -EINVAL;
}
return 0;
}
static int rk_keylad_send_key(u32 key_reg, u32 n_words, ulong dst_addr)
{
int ret = 0;
/* key_reg of 32bits can be 0-31 */
if ((key_reg + n_words) > KEYLAD_KEY_REG_NUM)
return -EINVAL;
for (u32 i = 0; i < n_words; i++) {
/* set destination addr */
keylad_write(KEYLAD_APB_PADDR,
(dst_addr & 0xffffffff) + (i * KEYLAD_KEY_REG_SIZE_BYTES));
/* select which word of key table to be sent */
keylad_write(KEYLAD_APB_PWDATA, key_reg + i);
keylad_write(KEYLAD_APB_CMD, VALUE_APB_CMD_ENABLE);
KEYLAD_POLL_TIMEOUT((keylad_read(KEYLAD_APB_CMD) & REG_APB_CMD_EN) ==
VALUE_APB_CMD_ENABLE, RK_KEYLAD_TIME_OUT, ret);
}
return ret;
}
static int rk_keylad_read_otp_key(u32 otp_offset, u32 keylad_area, u32 keylen)
{
int ret = 0;
u32 val = 0;
u32 nbytes = keylen;
/* keylad_area of 256bits can be 0-1 */
if (keylad_area >= KEYLAD_AREA_NUM)
return -EINVAL;
// rk_otp_keylad_read_init();
/* src use byte address, dst use keytable block address */
val = KL_OTP_KEY_REQ_SRC_ADDR(otp_offset / 2) |
KL_OTP_KEY_REQ_DST_ADDR(keylad_area) |
KL_OTP_KEY_REQ_BYTE_SWAP |
KL_OTP_KEY_REQ_EN;
keylad_write(KEYLAD_KEY_SEL, VALUE_KEY_SEL_OUTER_KEY);
keylad_write(KEY_LADDER_KEY_LEN, KL_KEY_LEN(nbytes));
keylad_write(KEY_LADDER_OTP_KEY_REQ, val);
KEYLAD_POLL_TIMEOUT(keylad_read(KEY_LADDER_OTP_KEY_REQ) & KL_OTP_KEY_REQ_EN,
RK_KEYLAD_TIME_OUT, ret);
val = keylad_read(KEY_LADDER_OTP_KEY_REQ);
if (val & KL_OTP_KEY_ECC_ST) {
printf("KEYLAD transfer OTP key ECC check error!");
ret = -EIO;
}
// rk_otp_keylad_read_deinit();
return ret;
}
static int rockchip_keylad_transfer_fwkey(struct udevice *dev, ulong dst,
u32 fw_keyid, u32 keylen)
{
int res = 0;
u32 fw_key_offset;
u32 max_key_len = 0;
if (keylen % 4) {
printf("key_len(%u) must be multiple of 4 error.", keylen);
return -EINVAL;
}
res = rk_get_fwkey_param(fw_keyid, &fw_key_offset, &max_key_len);
if (res)
return res;
if (keylen > max_key_len) {
printf("key_len(%u) > %u error.", keylen, max_key_len);
return -EINVAL;
}
res = rk_keylad_read_otp_key(fw_key_offset, 0, keylen);
if (res) {
printf("Keyladder read otp key err: 0x%x.", res);
return res;
}
/// TODO: enable clock
res = rk_keylad_send_key(0, keylen / 4, dst);
if (res) {
printf("Keyladder transfer key err: 0x%x.", res);
return res;
}
return res;
}
static const struct dm_keylad_ops rockchip_keylad_ops = {
.transfer_fwkey = rockchip_keylad_transfer_fwkey,
};
static int rockchip_keylad_ofdata_to_platdata(struct udevice *dev)
{
struct rockchip_keylad_priv *priv = dev_get_priv(dev);
memset(priv, 0x00, sizeof(*priv));
priv->reg = (fdt_addr_t)dev_read_addr_ptr(dev);
if (priv->reg == FDT_ADDR_T_NONE)
return -EINVAL;
keylad_base = priv->reg;
return 0;
}
static const struct udevice_id rockchip_keylad_ids[] = {
{
.compatible = "rockchip,keylad",
},
};
U_BOOT_DRIVER(rockchip_keylad) = {
.name = "rockchip_keylad",
.id = UCLASS_KEYLAD,
.of_match = rockchip_keylad_ids,
.ops = &rockchip_keylad_ops,
.ofdata_to_platdata = rockchip_keylad_ofdata_to_platdata,
.priv_auto_alloc_size = sizeof(struct rockchip_keylad_priv),
};

8
u-boot/drivers/misc/rockchip-otp.c
Unescape View File

@ -506,6 +506,14 @@ static const struct udevice_id rockchip_otp_ids[] = {
.compatible = "rockchip,rv1126-otp",
.data = (ulong)&rv1126_data,
},
{
.compatible = "rockchip,rv1126b-otp",
.data = (ulong)&rk3568_data,
},
{
.compatible = "rockchip,rv1103b-otp",
.data = (ulong)&rk3568_data,
},
{}
};

32
u-boot/drivers/mmc/dw_mmc.c
Unescape View File

@ -163,43 +163,19 @@ static void dwmci_prepare_data(struct dwmci_host *host,
dwmci_writel(host, DWMCI_BYTCNT, data->blocksize * data->blocks);
}
#ifdef CONFIG_SPL_BUILD
static unsigned int dwmci_get_drto(struct dwmci_host *host,
const unsigned int size)
{
unsigned int drto_clks;
unsigned int drto_div;
unsigned int drto_ms;
drto_clks = dwmci_readl(host, DWMCI_TMOUT) >> 8;
drto_div = (dwmci_readl(host, DWMCI_CLKDIV) & 0xff) * 2;
if (drto_div == 0)
drto_div = 1;
drto_ms = DIV_ROUND_UP_ULL((u64)MSEC_PER_SEC * drto_clks * drto_div,
host->mmc->clock);
/* add a bit spare time */
drto_ms += 50;
return drto_ms;
}
#else
static unsigned int dwmci_get_drto(struct dwmci_host *host,
const unsigned int size)
{
unsigned int timeout;
timeout = size * 8; /* counting in bits */
timeout *= 10; /* wait 10 times as long */
timeout /= host->mmc->clock;
timeout /= host->mmc->bus_width;
timeout *= 1000; /* counting in msec */
timeout = (timeout < 10000) ? 10000 : timeout;
timeout *= 10; /* wait 10 times as long */
timeout /= (host->mmc->clock / 1000); /* counting in msec */
timeout = (timeout < 1000) ? 1000 : timeout;
return timeout;
}
#endif
static unsigned int dwmci_get_cto(struct dwmci_host *host)
{
@ -310,7 +286,6 @@ read_again:
dwmci_writel(host, DWMCI_RINTSTS,
mask & (DWMCI_INTMSK_RXDR | DWMCI_INTMSK_DTO));
start = get_timer(0);
} else if (data->flags == MMC_DATA_WRITE &&
(mask & DWMCI_INTMSK_TXDR)) {
while (size) {
@ -340,7 +315,6 @@ write_again:
}
dwmci_writel(host, DWMCI_RINTSTS,
DWMCI_INTMSK_TXDR);
start = get_timer(0);
}
}

8
u-boot/drivers/mmc/mmc.c
Unescape View File

@ -2214,11 +2214,17 @@ static int mmc_select_card(struct mmc *mmc, int n)
int mmc_start_init(struct mmc *mmc)
{
int bus_width = 1;
/*
* We use the MMC config set by the bootrom.
* So it is no need to reset the eMMC device.
*/
mmc_set_bus_width(mmc, 8);
if (mmc->cfg->host_caps & MMC_MODE_8BIT)
bus_width = 8;
else if (mmc->cfg->host_caps & MMC_MODE_4BIT)
bus_width = 4;
mmc_set_bus_width(mmc, bus_width);
mmc_set_clock(mmc, 1);
mmc_set_timing(mmc, MMC_TIMING_LEGACY);
/* Send cmd7 to return stand-by state*/

4
u-boot/drivers/mmc/rockchip_dw_mmc.c
Unescape View File

@ -243,7 +243,7 @@ static int rockchip_mmc_set_phase(struct dwmci_host *host, bool sample, int degr
if (sample)
dwmci_writel(host, SDMMC_TIMING_CON1, HIWORD_UPDATE(raw_value, 0x07ff, 1));
else
dwmci_writel(host, SDMMC_TIMING_CON1, HIWORD_UPDATE(raw_value, 0x07ff, 1));
dwmci_writel(host, SDMMC_TIMING_CON0, HIWORD_UPDATE(raw_value, 0x07ff, 1));
debug("set %s_phase(%d) delay_nums=%u actual_degrees=%d\n",
sample ? "sample" : "drv", degrees, delay_num,
@ -272,7 +272,7 @@ static int rockchip_dwmmc_execute_tuning(struct dwmci_host *host, u32 opcode)
int middle_phase, real_middle_phase;
ulong ts;
if (!(priv->sample_clk.dev))
if (!(priv->sample_clk.dev) && priv->usrid != USRID_INTER_PHASE)
return -EIO;
ts = get_timer(0);

2
u-boot/drivers/mmc/rockchip_sdhci.c
Unescape View File

@ -672,7 +672,7 @@ static const struct sdhci_data rk3576_data = {
.hs200_tx_tap = 16,
.hs400_tx_tap = 7,
.hs400_cmd_tap = 7,
.hs400_strbin_tap = 5,
.hs400_strbin_tap = 7,
.ddr50_strbin_delay_num = 16,
};

5
u-boot/drivers/mtd/mtd_blk.c
Unescape View File

@ -31,6 +31,8 @@
#define MTD_BLK_TABLE_BLOCK_UNKNOWN (-2)
#define MTD_BLK_TABLE_BLOCK_SHIFT (-1)
#define FACTORY_UNKNOWN_LBA (0xffffffff - 34)
static int *mtd_map_blk_table;
#if CONFIG_IS_ENABLED(SUPPORT_USBPLUG)
@ -432,7 +434,8 @@ char *mtd_part_parse(struct blk_desc *dev_desc)
strcat(mtd_part_info, ",");
if (part_get_info(dev_desc, p + 1, &info)) {
/* Partition with grow tag in parameter will be resized */
if ((info.size + info.start + 64) >= dev_desc->lba) {
if ((info.size + info.start + 64) >= dev_desc->lba ||
(info.size + info.start - 1) == FACTORY_UNKNOWN_LBA) {
if (dev_desc->devnum == BLK_MTD_SPI_NOR) {
/* Nor is 64KB erase block(kernel) and gpt table just
* resserve 33 sectors for the last partition. This

11
u-boot/drivers/mtd/nand/spi/core.c
Unescape View File

@ -289,8 +289,6 @@ static int spinand_read_from_cache_op(struct spinand_device *spinand,
if (ret)
return ret;
if (spinand->support_cont_read)
op.addr.nbytes = 3;
ret = spi_mem_exec_op(spinand->slave, &op);
if (ret)
return ret;
@ -593,6 +591,7 @@ static int spinand_mtd_read(struct mtd_info *mtd, loff_t from,
bool enable_ecc = false;
bool ecc_failed = false;
int ret = 0;
bool cont_real = spinand->support_cont_read;
if (ops->mode != MTD_OPS_RAW && spinand->eccinfo.ooblayout)
enable_ecc = true;
@ -610,6 +609,12 @@ static int spinand_mtd_read(struct mtd_info *mtd, loff_t from,
if (ret)
break;
/* For misaligned situations, temporarily disable the cont read capability */
if (iter.req.dataoffs)
spinand->support_cont_read = false;
else
spinand->support_cont_read = cont_real;
if (spinand->support_cont_read) {
iter.req.datalen = ops->len;
iter.req.ooblen = 0;
@ -643,6 +648,8 @@ static int spinand_mtd_read(struct mtd_info *mtd, loff_t from,
if (ecc_failed && !ret)
ret = -EBADMSG;
spinand->support_cont_read = cont_real;
return ret ? ret : max_bitflips;
}

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