diff --git a/u-boot/arch/arm/Kconfig b/u-boot/arch/arm/Kconfig index c8dcb8ffe96..a29690a6466 100644 --- a/u-boot/arch/arm/Kconfig +++ b/u-boot/arch/arm/Kconfig @@ -98,6 +98,9 @@ config ARM_ERRATA_798870 config ARM_ERRATA_801819 bool +config ARM_ERRATA_814220 + bool + config ARM_ERRATA_826974 bool diff --git a/u-boot/arch/arm/cpu/armv7/cache_v7_asm.S b/u-boot/arch/arm/cpu/armv7/cache_v7_asm.S index bd27ab219c6..2747081d98f 100644 --- a/u-boot/arch/arm/cpu/armv7/cache_v7_asm.S +++ b/u-boot/arch/arm/cpu/armv7/cache_v7_asm.S @@ -65,6 +65,9 @@ loop2: skip: add r10, r10, #2 @ increment cache number cmp r3, r10 +#ifdef CONFIG_ARM_ERRATA_814220 + dsb +#endif bgt flush_levels finished: mov r10, #0 @ swith back to cache level 0 diff --git a/u-boot/arch/arm/cpu/armv7/psci.S b/u-boot/arch/arm/cpu/armv7/psci.S index 95b962dadf0..7b74becc3a2 100644 --- a/u-boot/arch/arm/cpu/armv7/psci.S +++ b/u-boot/arch/arm/cpu/armv7/psci.S @@ -226,6 +226,9 @@ loop2: skip: add r10, r10, #2 @ increment cache number cmp r3, r10 +#ifdef CONFIG_ARM_ERRATA_814220 + dsb +#endif bgt flush_levels finished: mov r10, #0 @ swith back to cache level 0 diff --git a/u-boot/arch/arm/dts/rk1808-u-boot.dtsi b/u-boot/arch/arm/dts/rk1808-u-boot.dtsi index 7fedf6047d7..1749b52476e 100644 --- a/u-boot/arch/arm/dts/rk1808-u-boot.dtsi +++ b/u-boot/arch/arm/dts/rk1808-u-boot.dtsi @@ -148,23 +148,3 @@ u-boot,dm-pre-reloc; status = "okay"; }; - -&usb_host0_ehci { - u-boot,dm-pre-reloc; - status = "okay"; -}; - -&usb_host0_ohci { - u-boot,dm-pre-reloc; - status = "okay"; -}; - -&usbdrd3 { - u-boot,dm-pre-reloc; - status = "okay"; -}; - -&usbdrd_dwc3 { - u-boot,dm-pre-reloc; - status = "okay"; -}; diff --git a/u-boot/arch/arm/dts/rk3568-u-boot.dtsi b/u-boot/arch/arm/dts/rk3568-u-boot.dtsi index d2a1b0c2150..93402878efe 100644 --- a/u-boot/arch/arm/dts/rk3568-u-boot.dtsi +++ b/u-boot/arch/arm/dts/rk3568-u-boot.dtsi @@ -73,26 +73,6 @@ status = "okay"; }; -&usbdrd30 { - u-boot,dm-pre-reloc; - status = "okay"; -}; - -&usbdrd_dwc3 { - u-boot,dm-pre-reloc; - status = "okay"; -}; - -&usbhost30 { - u-boot,dm-pre-reloc; - status = "okay"; -}; - -&usbhost_dwc3 { - u-boot,dm-pre-reloc; - status = "okay"; -}; - &usb2phy0 { u-boot,dm-pre-reloc; status = "okay"; diff --git a/u-boot/arch/arm/dts/rv1103b-u-boot.dtsi b/u-boot/arch/arm/dts/rv1103b-u-boot.dtsi index a31355a9f3f..8305835877b 100644 --- a/u-boot/arch/arm/dts/rv1103b-u-boot.dtsi +++ b/u-boot/arch/arm/dts/rv1103b-u-boot.dtsi @@ -127,12 +127,3 @@ status = "okay"; }; -&usbdrd { - u-boot,dm-pre-reloc; - status = "okay"; -}; - -&usbdrd_dwc3 { - u-boot,dm-pre-reloc; - status = "okay"; -}; diff --git a/u-boot/arch/arm/dts/rv1106-u-boot.dtsi b/u-boot/arch/arm/dts/rv1106-u-boot.dtsi index 8821862dbbf..cdd69f8122e 100644 --- a/u-boot/arch/arm/dts/rv1106-u-boot.dtsi +++ b/u-boot/arch/arm/dts/rv1106-u-boot.dtsi @@ -202,13 +202,3 @@ u-boot,dm-pre-reloc; status = "okay"; }; - -&usbdrd { - u-boot,dm-pre-reloc; - status = "okay"; -}; - -&usbdrd_dwc3 { - u-boot,dm-pre-reloc; - status = "okay"; -}; diff --git a/u-boot/arch/arm/dts/rv1106b-evb2.dts b/u-boot/arch/arm/dts/rv1106b-evb2.dts index beb2547ac60..f1a4cd137ef 100644 --- a/u-boot/arch/arm/dts/rv1106b-evb2.dts +++ b/u-boot/arch/arm/dts/rv1106b-evb2.dts @@ -33,6 +33,11 @@ }; }; +&emmc { + bus-width = <4>; + mmc-hs200-1_8v; +}; + /delete-node/ &gmac; &pinctrl { diff --git a/u-boot/arch/arm/dts/rv1126-u-boot.dtsi b/u-boot/arch/arm/dts/rv1126-u-boot.dtsi index 5ba9f0963ad..36660aa7637 100644 --- a/u-boot/arch/arm/dts/rv1126-u-boot.dtsi +++ b/u-boot/arch/arm/dts/rv1126-u-boot.dtsi @@ -184,16 +184,6 @@ status = "okay"; }; -&usbdrd { - u-boot,dm-pre-reloc; - status = "okay"; -}; - -&usbdrd_dwc3 { - u-boot,dm-pre-reloc; - status = "okay"; -}; - &pinctrl { u-boot,dm-spl; status = "okay"; diff --git a/u-boot/arch/arm/dts/rv1126b-evb.dts b/u-boot/arch/arm/dts/rv1126b-evb.dts new file mode 100644 index 00000000000..306d868e965 --- /dev/null +++ b/u-boot/arch/arm/dts/rv1126b-evb.dts @@ -0,0 +1,30 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2025 Rockchip Electronics Co., Ltd. + */ + +/dts-v1/; +#include "rv1126b.dtsi" +#include "rv1126b-u-boot.dtsi" +#include + +/ { + model = "Rockchip RV1126B Evaluation board"; + compatible = "rockchip,rv1126b-evb", "rockchip,rv1126b"; + + adc-keys { + compatible = "adc-keys"; + io-channels = <&saradc0 0>; + io-channel-names = "buttons"; + keyup-threshold-microvolt = <1800000>; + u-boot,dm-pre-reloc; + status = "okay"; + + volumeup-key { + u-boot,dm-pre-reloc; + linux,code = ; + label = "volume up"; + press-threshold-microvolt = <1750>; + }; + }; +}; diff --git a/u-boot/arch/arm/dts/rv1126b-pinctrl.dtsi b/u-boot/arch/arm/dts/rv1126b-pinctrl.dtsi new file mode 100644 index 00000000000..be3bbc1731b --- /dev/null +++ b/u-boot/arch/arm/dts/rv1126b-pinctrl.dtsi @@ -0,0 +1,2940 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2024 Rockchip Electronics Co., Ltd. + */ + +#include +#include "rockchip-pinconf.dtsi" + +/* + * This file is auto generated by pin2dts tool, please keep these code + * by adding changes at end of this file. + */ +&pinctrl { + cam_clk0 { + cam_clk0_pins: cam-clk0-pins { + rockchip,pins = + /* cam_clk0_out */ + <4 RK_PB1 3 &pcfg_pull_none>; + }; + }; + + cam_clk1 { + cam_clk1_pins: cam-clk1-pins { + rockchip,pins = + /* cam_clk1_out */ + <4 RK_PB0 3 &pcfg_pull_none>; + }; + }; + + cam_clk2 { + cam_clk2_pins: cam-clk2-pins { + rockchip,pins = + /* cam_clk2_out */ + <4 RK_PA1 3 &pcfg_pull_none>; + }; + }; + + cam_clk3 { + cam_clk3_pins: cam-clk3-pins { + rockchip,pins = + /* cam_clk3_out */ + <4 RK_PA0 3 &pcfg_pull_none>; + }; + }; + + can0 { + can0m0_pins: can0m0-pins { + rockchip,pins = + /* can0_rxd_m0 */ + <5 RK_PD4 3 &pcfg_pull_none>, + /* can0_txd_m0 */ + <5 RK_PD5 3 &pcfg_pull_none>; + }; + + can0m1_pins: can0m1-pins { + rockchip,pins = + /* can0_rxd_m1 */ + <6 RK_PA0 4 &pcfg_pull_none>, + /* can0_txd_m1 */ + <6 RK_PA1 4 &pcfg_pull_none>; + }; + }; + + can1 { + can1m0_pins: can1m0-pins { + rockchip,pins = + /* can1_rxd_m0 */ + <5 RK_PD6 3 &pcfg_pull_none>, + /* can1_txd_m0 */ + <5 RK_PD7 3 &pcfg_pull_none>; + }; + + can1m1_pins: can1m1-pins { + rockchip,pins = + /* can1_rxd_m1 */ + <6 RK_PA2 4 &pcfg_pull_none>, + /* can1_txd_m1 */ + <6 RK_PA3 4 &pcfg_pull_none>; + }; + }; + + clk { + clk_pins: clk-pins { + rockchip,pins = + /* clk_32k */ + <0 RK_PA2 2 &pcfg_pull_none>; + }; + }; + + dsm_aud { + dsm_aud_ln_pins: dsm-aud-ln-pins { + rockchip,pins = + /* dsm_aud_ln */ + <7 RK_PA3 4 &pcfg_pull_none>; + }; + + dsm_aud_lp_pins: dsm-aud-lp-pins { + rockchip,pins = + /* dsm_aud_lp */ + <7 RK_PA5 4 &pcfg_pull_none>; + }; + + dsm_aud_rn_pins: dsm-aud-rn-pins { + rockchip,pins = + /* dsm_aud_rn */ + <7 RK_PB0 4 &pcfg_pull_none>; + }; + + dsm_aud_rp_pins: dsm-aud-rp-pins { + rockchip,pins = + /* dsm_aud_rp */ + <7 RK_PB1 4 &pcfg_pull_none>; + }; + }; + + dsmc { + dsmc_int_pins: dsmc-int-pins { + rockchip,pins = + /* dsmc_int0 */ + <5 RK_PB6 5 &pcfg_pull_down>, + /* dsmc_int1 */ + <5 RK_PB2 5 &pcfg_pull_down>; + }; + + dsmc_clk_pins: dsmc-clk-pins { + rockchip,pins = + /* dsmc_clkn */ + <5 RK_PB6 4 &pcfg_pull_up>, + /* dsmc_resetn */ + <5 RK_PB2 4 &pcfg_pull_up>; + }; + + dsmc_csn_pins: dsmc-csn-pins { + rockchip,pins = + /* dsmc_csn0 */ + <5 RK_PB4 4 &pcfg_pull_up>, + /* dsmc_csn1 */ + <5 RK_PA0 4 &pcfg_pull_up>, + /* dsmc_csn2 */ + <5 RK_PD1 4 &pcfg_pull_up>, + /* dsmc_csn3 */ + <5 RK_PD0 4 &pcfg_pull_up>; + }; + + dsmc_bus16_pins: dsmc-bus16-pins { + rockchip,pins = + /* dsmc_clkp */ + <5 RK_PB7 4 &pcfg_pull_down>, + /* dsmc_d0 */ + <5 RK_PC7 4 &pcfg_pull_down>, + /* dsmc_d1 */ + <5 RK_PC6 4 &pcfg_pull_down>, + /* dsmc_d2 */ + <5 RK_PC5 4 &pcfg_pull_down>, + /* dsmc_d3 */ + <5 RK_PC4 4 &pcfg_pull_down>, + /* dsmc_d4 */ + <5 RK_PC3 4 &pcfg_pull_down>, + /* dsmc_d5 */ + <5 RK_PC2 4 &pcfg_pull_down>, + /* dsmc_d6 */ + <5 RK_PC1 4 &pcfg_pull_down>, + /* dsmc_d7 */ + <5 RK_PC0 4 &pcfg_pull_down>, + /* dsmc_d8 */ + <5 RK_PB1 4 &pcfg_pull_down>, + /* dsmc_d9 */ + <5 RK_PB0 4 &pcfg_pull_down>, + /* dsmc_d10 */ + <5 RK_PA7 4 &pcfg_pull_down>, + /* dsmc_d11 */ + <5 RK_PA6 4 &pcfg_pull_down>, + /* dsmc_d12 */ + <5 RK_PA5 4 &pcfg_pull_down>, + /* dsmc_d13 */ + <5 RK_PA4 4 &pcfg_pull_down>, + /* dsmc_d14 */ + <5 RK_PA3 4 &pcfg_pull_down>, + /* dsmc_d15 */ + <5 RK_PA2 4 &pcfg_pull_down>, + /* dsmc_dqs0 */ + <5 RK_PB5 4 &pcfg_pull_down>, + /* dsmc_dqs1 */ + <5 RK_PA1 4 &pcfg_pull_down>, + /* dsmc_int2 */ + <5 RK_PD3 4 &pcfg_pull_down>, + /* dsmc_int3 */ + <5 RK_PD2 4 &pcfg_pull_down>, + /* dsmc_rdyn */ + <5 RK_PB3 4 &pcfg_pull_down>; + }; + }; + + emmc { + emmc_pins: emmc-pins { + rockchip,pins = + /* emmc_clk */ + <1 RK_PB3 1 &pcfg_pull_none>, + /* emmc_cmd */ + <1 RK_PB1 1 &pcfg_pull_none>, + /* emmc_d0 */ + <1 RK_PA0 1 &pcfg_pull_none>, + /* emmc_d1 */ + <1 RK_PA1 1 &pcfg_pull_none>, + /* emmc_d2 */ + <1 RK_PA2 1 &pcfg_pull_none>, + /* emmc_d3 */ + <1 RK_PA3 1 &pcfg_pull_none>, + /* emmc_d4 */ + <1 RK_PA4 1 &pcfg_pull_none>, + /* emmc_d5 */ + <1 RK_PA5 1 &pcfg_pull_none>, + /* emmc_d6 */ + <1 RK_PA6 1 &pcfg_pull_none>, + /* emmc_d7 */ + <1 RK_PA7 1 &pcfg_pull_none>; + }; + }; + + emmc_testclk { + emmc_testclk_pins: emmc-testclk-pins { + rockchip,pins = + /* emmc_testclk_out */ + <2 RK_PA2 4 &pcfg_pull_none>; + }; + }; + + emmc_testdata { + emmc_testdata_pins: emmc-testdata-pins { + rockchip,pins = + /* emmc_testdata_out */ + <2 RK_PA3 4 &pcfg_pull_none>; + }; + }; + + eth { + ethm0_pins: ethm0-pins { + rockchip,pins = + /* eth_mclk_m0 */ + <6 RK_PB4 3 &pcfg_pull_none>, + /* eth_mdc_m0 */ + <6 RK_PC0 3 &pcfg_pull_none>, + /* eth_mdio_m0 */ + <6 RK_PB7 3 &pcfg_pull_none>, + /* eth_ppsclk_m0 */ + <6 RK_PA2 3 &pcfg_pull_none>, + /* eth_ppstrig_m0 */ + <6 RK_PA0 3 &pcfg_pull_none>, + /* eth_rxclk_m0 */ + <6 RK_PC3 3 &pcfg_pull_none>, + /* eth_rxctl_m0 */ + <6 RK_PB5 3 &pcfg_pull_none>, + /* eth_rxd0_m0 */ + <6 RK_PB2 3 &pcfg_pull_none>, + /* eth_rxd1_m0 */ + <6 RK_PB3 3 &pcfg_pull_none>, + /* eth_rxd2_m0 */ + <6 RK_PA3 3 &pcfg_pull_none>, + /* eth_rxd3_m0 */ + <6 RK_PA4 3 &pcfg_pull_none>, + /* eth_rxer_m0 */ + <6 RK_PB6 3 &pcfg_pull_none>, + /* eth_txclk_m0 */ + <6 RK_PC2 3 &pcfg_pull_none>, + /* eth_txctl_m0 */ + <6 RK_PB1 3 &pcfg_pull_none>, + /* eth_txd0_m0 */ + <6 RK_PA7 3 &pcfg_pull_none>, + /* eth_txd1_m0 */ + <6 RK_PB0 3 &pcfg_pull_none>, + /* eth_txd2_m0 */ + <6 RK_PA5 3 &pcfg_pull_none>, + /* eth_txd3_m0 */ + <6 RK_PA6 3 &pcfg_pull_none>; + }; + + ethm1_pins: ethm1-pins { + rockchip,pins = + /* eth_mclk_m1 */ + <5 RK_PB3 2 &pcfg_pull_none>, + /* eth_mdc_m1 */ + <5 RK_PB6 2 &pcfg_pull_none>, + /* eth_mdio_m1 */ + <5 RK_PB5 2 &pcfg_pull_none>, + /* eth_ppsclk_m1 */ + <5 RK_PA2 2 &pcfg_pull_none>, + /* eth_ppstrig_m1 */ + <5 RK_PD1 3 &pcfg_pull_none>, + /* eth_rxclk_m1 */ + <5 RK_PC7 2 &pcfg_pull_none>, + /* eth_rxctl_m1 */ + <5 RK_PB0 2 &pcfg_pull_none>, + /* eth_rxd0_m1 */ + <5 RK_PB1 2 &pcfg_pull_none>, + /* eth_rxd1_m1 */ + <5 RK_PB2 2 &pcfg_pull_none>, + /* eth_rxd2_m1 */ + <5 RK_PC3 2 &pcfg_pull_none>, + /* eth_rxd3_m1 */ + <5 RK_PC4 2 &pcfg_pull_none>, + /* eth_rxer_m1 */ + <5 RK_PB4 2 &pcfg_pull_none>, + /* eth_txclk_m1 */ + <5 RK_PC6 2 &pcfg_pull_none>, + /* eth_txctl_m1 */ + <5 RK_PC2 2 &pcfg_pull_none>, + /* eth_txd0_m1 */ + <5 RK_PB7 2 &pcfg_pull_none>, + /* eth_txd1_m1 */ + <5 RK_PC0 2 &pcfg_pull_none>, + /* eth_txd2_m1 */ + <5 RK_PC5 2 &pcfg_pull_none>, + /* eth_txd3_m1 */ + <5 RK_PA0 2 &pcfg_pull_none>; + }; + }; + + eth_clk_25m { + eth_clk_25mm0_out_pins: eth-clk-25mm0-out-pins { + rockchip,pins = + /* eth_clk_25m_out_m0 */ + <6 RK_PC1 3 &pcfg_pull_none>; + }; + + eth_clk_25mm1_out_pins: eth-clk-25mm1-out-pins { + rockchip,pins = + /* eth_clk_25m_out_m1 */ + <5 RK_PC1 2 &pcfg_pull_none>; + }; + }; + + eth_ptp { + eth_ptpm0_pins: eth-ptpm0-pins { + rockchip,pins = + /* eth_ptp_refclk_m0 */ + <6 RK_PA1 3 &pcfg_pull_none>; + }; + + eth_ptpm1_pins: eth-ptpm1-pins { + rockchip,pins = + /* eth_ptp_refclk_m1 */ + <5 RK_PD0 3 &pcfg_pull_none>; + }; + }; + + eth_testrxclk { + eth_testrxclkm0_pins: eth-testrxclkm0-pins { + rockchip,pins = + /* eth_testrxclk_out_m0 */ + <5 RK_PB6 6 &pcfg_pull_none>; + }; + + eth_testrxclkm1_pins: eth-testrxclkm1-pins { + rockchip,pins = + /* eth_testrxclk_out_m1 */ + <6 RK_PC0 4 &pcfg_pull_none>; + }; + }; + + eth_testrxd { + eth_testrxdm0_pins: eth-testrxdm0-pins { + rockchip,pins = + /* eth_testrxd_out_m0 */ + <5 RK_PB5 6 &pcfg_pull_none>; + }; + + eth_testrxdm1_pins: eth-testrxdm1-pins { + rockchip,pins = + /* eth_testrxd_out_m1 */ + <6 RK_PB7 4 &pcfg_pull_none>; + }; + }; + + fephy { + fephym0_pins: fephym0-pins { + rockchip,pins = + /* fephy_ledlink_m0 */ + <3 RK_PB4 6 &pcfg_pull_none>, + /* fephy_ledspd_m0 */ + <3 RK_PB5 6 &pcfg_pull_none>; + }; + + fephym1_pins: fephym1-pins { + rockchip,pins = + /* fephy_ledlink_m1 */ + <5 RK_PD4 1 &pcfg_pull_none>, + /* fephy_ledspd_m1 */ + <5 RK_PD5 1 &pcfg_pull_none>; + }; + + fephym2_pins: fephym2-pins { + rockchip,pins = + /* fephy_ledlink_m2 */ + <6 RK_PC2 4 &pcfg_pull_none>, + /* fephy_ledspd_m2 */ + <6 RK_PC3 4 &pcfg_pull_none>; + }; + }; + + flash_trig { + flash_trig_pins: flash-trig-pins { + rockchip,pins = + /* flash_trig_out */ + <3 RK_PB2 6 &pcfg_pull_none>; + }; + }; + + fspi0 { + fspi0_bus4_pins: fspi0-bus4-pins { + rockchip,pins = + /* fspi0_d0 */ + <1 RK_PB4 1 &pcfg_pull_none>, + /* fspi0_d1 */ + <1 RK_PB5 1 &pcfg_pull_none>, + /* fspi0_d2 */ + <1 RK_PB2 1 &pcfg_pull_none>, + /* fspi0_d3 */ + <1 RK_PB6 1 &pcfg_pull_none>; + }; + + fspi0_clk_pins: fspi0-clk-pins { + rockchip,pins = + /* fspi0_clk */ + <1 RK_PB7 1 &pcfg_pull_none>; + }; + fspi0_csn0_pins: fspi0-csn0-pins { + rockchip,pins = + /* fspi0_csn0 */ + <1 RK_PB0 1 &pcfg_pull_none>; + }; + fspi0_csn1_pins: fspi0-csn1-pins { + rockchip,pins = + /* fspi0_csn1 */ + <1 RK_PA5 2 &pcfg_pull_none>; + }; + }; + + fspi1 { + fspi1m0_bus4_pins: fspi1m0-bus4-pins { + rockchip,pins = + /* fspi1_d0_m0 */ + <0 RK_PB0 1 &pcfg_pull_none>, + /* fspi1_d1_m0 */ + <0 RK_PB1 1 &pcfg_pull_none>, + /* fspi1_d2_m0 */ + <0 RK_PA6 1 &pcfg_pull_none>, + /* fspi1_d3_m0 */ + <0 RK_PA1 1 &pcfg_pull_none>; + }; + + fspi1m0_clk_pins: fspi1m0-clk-pins { + rockchip,pins = + /* fspi1m0_clk */ + <0 RK_PB2 1 &pcfg_pull_none>; + }; + fspi1m0_csn0_pins: fspi1m0-csn0-pins { + rockchip,pins = + /* fspi1m0_csn0 */ + <0 RK_PA7 1 &pcfg_pull_none>; + }; + + fspi1m1_bus4_pins: fspi1m1-bus4-pins { + rockchip,pins = + /* fspi1_d0_m1 */ + <1 RK_PA0 2 &pcfg_pull_none>, + /* fspi1_d1_m1 */ + <1 RK_PA1 2 &pcfg_pull_none>, + /* fspi1_d2_m1 */ + <1 RK_PA2 2 &pcfg_pull_none>, + /* fspi1_d3_m1 */ + <1 RK_PA3 2 &pcfg_pull_none>; + }; + + fspi1m1_clk_pins: fspi1m1-clk-pins { + rockchip,pins = + /* fspi1m1_clk */ + <1 RK_PB3 2 &pcfg_pull_none>; + }; + fspi1m1_csn0_pins: fspi1m1-csn0-pins { + rockchip,pins = + /* fspi1m1_csn0 */ + <1 RK_PB1 2 &pcfg_pull_none>; + }; + }; + + i2c0 { + i2c0m0_pins: i2c0m0-pins { + rockchip,pins = + /* i2c0_scl_m0 */ + <0 RK_PC2 5 &pcfg_pull_none>, + /* i2c0_sda_m0 */ + <0 RK_PC3 5 &pcfg_pull_none>; + }; + + i2c0m1_pins: i2c0m1-pins { + rockchip,pins = + /* i2c0_scl_m1 */ + <2 RK_PA1 3 &pcfg_pull_none>, + /* i2c0_sda_m1 */ + <2 RK_PA0 3 &pcfg_pull_none>; + }; + }; + + i2c1 { + i2c1m0_pins: i2c1m0-pins { + rockchip,pins = + /* i2c1_scl_m0 */ + <0 RK_PB3 3 &pcfg_pull_none>, + /* i2c1_sda_m0 */ + <0 RK_PB4 3 &pcfg_pull_none>; + }; + + i2c1m1_pins: i2c1m1-pins { + rockchip,pins = + /* i2c1_scl_m1 */ + <3 RK_PA2 2 &pcfg_pull_none>, + /* i2c1_sda_m1 */ + <3 RK_PA3 2 &pcfg_pull_none>; + }; + + i2c1m2_pins: i2c1m2-pins { + rockchip,pins = + /* i2c1_scl_m2 */ + <4 RK_PA1 6 &pcfg_pull_none>, + /* i2c1_sda_m2 */ + <4 RK_PA0 6 &pcfg_pull_none>; + }; + + i2c1m3_pins: i2c1m3-pins { + rockchip,pins = + /* i2c1_scl_m3 */ + <7 RK_PB0 5 &pcfg_pull_none>, + /* i2c1_sda_m3 */ + <7 RK_PB1 5 &pcfg_pull_none>; + }; + }; + + i2c2 { + i2c2m0_pins: i2c2m0-pins { + rockchip,pins = + /* i2c2_scl_m0 */ + <0 RK_PD0 1 &pcfg_pull_none>, + /* i2c2_sda_m0 */ + <0 RK_PD1 1 &pcfg_pull_none>; + }; + + i2c2m1_pins: i2c2m1-pins { + rockchip,pins = + /* i2c2_scl_m1 */ + <5 RK_PD4 6 &pcfg_pull_none>, + /* i2c2_sda_m1 */ + <5 RK_PD5 6 &pcfg_pull_none>; + }; + + i2c2m2_pins: i2c2m2-pins { + rockchip,pins = + /* i2c2_scl_m2 */ + <6 RK_PC0 8 &pcfg_pull_none>, + /* i2c2_sda_m2 */ + <6 RK_PC3 8 &pcfg_pull_none>; + }; + }; + + i2c3 { + i2c3m0_pins: i2c3m0-pins { + rockchip,pins = + /* i2c3_scl_m0 */ + <0 RK_PC0 1 &pcfg_pull_none>, + /* i2c3_sda_m0 */ + <0 RK_PC1 1 &pcfg_pull_none>; + }; + + i2c3m1_pins: i2c3m1-pins { + rockchip,pins = + /* i2c3_scl_m1 */ + <4 RK_PA4 6 &pcfg_pull_none>, + /* i2c3_sda_m1 */ + <4 RK_PA5 6 &pcfg_pull_none>; + }; + + i2c3m2_pins: i2c3m2-pins { + rockchip,pins = + /* i2c3_scl_m2 */ + <5 RK_PD0 6 &pcfg_pull_none>, + /* i2c3_sda_m2 */ + <5 RK_PD1 6 &pcfg_pull_none>; + }; + + i2c3m3_pins: i2c3m3-pins { + rockchip,pins = + /* i2c3_scl_m3 */ + <6 RK_PA0 8 &pcfg_pull_none>, + /* i2c3_sda_m3 */ + <6 RK_PA1 8 &pcfg_pull_none>; + }; + }; + + i2c4 { + i2c4m0_pins: i2c4m0-pins { + rockchip,pins = + /* i2c4_scl_m0 */ + <3 RK_PB4 5 &pcfg_pull_none>, + /* i2c4_sda_m0 */ + <3 RK_PB5 5 &pcfg_pull_none>; + }; + + i2c4m1_pins: i2c4m1-pins { + rockchip,pins = + /* i2c4_scl_m1 */ + <6 RK_PA2 8 &pcfg_pull_none>, + /* i2c4_sda_m1 */ + <6 RK_PA3 8 &pcfg_pull_none>; + }; + + i2c4m2_pins: i2c4m2-pins { + rockchip,pins = + /* i2c4_scl_m2 */ + <4 RK_PA7 6 &pcfg_pull_none>, + /* i2c4_sda_m2 */ + <4 RK_PA6 6 &pcfg_pull_none>; + }; + }; + + i2c5 { + i2c5m0_pins: i2c5m0-pins { + rockchip,pins = + /* i2c5_scl_m0 */ + <0 RK_PC4 5 &pcfg_pull_none>, + /* i2c5_sda_m0 */ + <0 RK_PC5 5 &pcfg_pull_none>; + }; + + i2c5m1_pins: i2c5m1-pins { + rockchip,pins = + /* i2c5_scl_m1 */ + <3 RK_PB6 5 &pcfg_pull_none>, + /* i2c5_sda_m1 */ + <3 RK_PB7 5 &pcfg_pull_none>; + }; + + i2c5m2_pins: i2c5m2-pins { + rockchip,pins = + /* i2c5_scl_m2 */ + <5 RK_PA1 2 &pcfg_pull_none>, + /* i2c5_sda_m2 */ + <5 RK_PA7 6 &pcfg_pull_none>; + }; + }; + + ir_fpa { + ir_fpa_pins: ir-fpa-pins { + rockchip,pins = + /* ir_fpa_d0 */ + <6 RK_PA2 2 &pcfg_pull_none>, + /* ir_fpa_d1 */ + <6 RK_PA3 2 &pcfg_pull_none>, + /* ir_fpa_d2 */ + <6 RK_PA4 2 &pcfg_pull_none>, + /* ir_fpa_d3 */ + <6 RK_PA5 2 &pcfg_pull_none>, + /* ir_fpa_d4 */ + <6 RK_PA6 2 &pcfg_pull_none>, + /* ir_fpa_d5 */ + <6 RK_PA7 2 &pcfg_pull_none>, + /* ir_fpa_d6 */ + <6 RK_PB0 2 &pcfg_pull_none>, + /* ir_fpa_d7 */ + <6 RK_PB1 2 &pcfg_pull_none>, + /* ir_fpa_d8 */ + <6 RK_PB2 2 &pcfg_pull_none>, + /* ir_fpa_d9 */ + <6 RK_PB3 2 &pcfg_pull_none>, + /* ir_fpa_d10 */ + <6 RK_PB4 2 &pcfg_pull_none>, + /* ir_fpa_d11 */ + <6 RK_PB5 2 &pcfg_pull_none>, + /* ir_fpa_d12 */ + <6 RK_PB6 2 &pcfg_pull_none>, + /* ir_fpa_d13 */ + <6 RK_PB7 2 &pcfg_pull_none>, + /* ir_fpa_fsync */ + <5 RK_PD4 5 &pcfg_pull_none>, + /* ir_fpa_hsync */ + <6 RK_PC3 2 &pcfg_pull_none>, + /* ir_fpa_mclk */ + <6 RK_PC2 2 &pcfg_pull_none>, + /* ir_fpa_sda0 */ + <5 RK_PA0 6 &pcfg_pull_none>, + /* ir_fpa_sda1 */ + <5 RK_PA1 6 &pcfg_pull_none>, + /* ir_fpa_sda2 */ + <5 RK_PB0 6 &pcfg_pull_none>, + /* ir_fpa_sda3 */ + <5 RK_PB1 6 &pcfg_pull_none>, + /* ir_fpa_sda4 */ + <5 RK_PC0 6 &pcfg_pull_none>, + /* ir_fpa_sda5 */ + <5 RK_PC1 6 &pcfg_pull_none>, + /* ir_fpa_sda6 */ + <5 RK_PC2 6 &pcfg_pull_none>, + /* ir_fpa_vsync */ + <6 RK_PC0 2 &pcfg_pull_none>; + }; + }; + + ir_fpa_clk { + ir_fpa_clk_pins: ir-fpa-clk-pins { + rockchip,pins = + /* ir_fpa_clk_adout */ + <6 RK_PC1 2 &pcfg_pull_none>; + }; + }; + + jtag { + jtagm0_pins: jtagm0-pins { + rockchip,pins = + /* jtag_tck_m0 */ + <0 RK_PB3 4 &pcfg_pull_none>, + /* jtag_tms_m0 */ + <0 RK_PB4 4 &pcfg_pull_none>; + }; + + jtagm1_pins: jtagm1-pins { + rockchip,pins = + /* jtag_tck_m1 */ + <2 RK_PA1 4 &pcfg_pull_none>, + /* jtag_tms_m1 */ + <2 RK_PA0 4 &pcfg_pull_none>; + }; + + jtagm2_pins: jtagm2-pins { + rockchip,pins = + /* jtag_tck_m2 */ + <5 RK_PD6 2 &pcfg_pull_none>, + /* jtag_tms_m2 */ + <5 RK_PD7 2 &pcfg_pull_none>; + }; + }; + + pdm { + pdmm0_clk0_pins: pdmm0-clk0-pins { + rockchip,pins = + /* pdm_clk0_m0 */ + <7 RK_PA4 3 &pcfg_pull_none>; + }; + + pdmm0_clk1_pins: pdmm0-clk1-pins { + rockchip,pins = + /* pdm_clk1_m0 */ + <7 RK_PA1 3 &pcfg_pull_none>; + }; + + pdmm0_sdi0_pins: pdmm0-sdi0-pins { + rockchip,pins = + /* pdm_sdi0_m0 */ + <7 RK_PA6 3 &pcfg_pull_none>; + }; + + pdmm0_sdi1_pins: pdmm0-sdi1-pins { + rockchip,pins = + /* pdm_sdi1_m0 */ + <7 RK_PB1 3 &pcfg_pull_none>; + }; + + pdmm0_sdi2_pins: pdmm0-sdi2-pins { + rockchip,pins = + /* pdm_sdi2_m0 */ + <7 RK_PB0 3 &pcfg_pull_none>; + }; + + pdmm0_sdi3_pins: pdmm0-sdi3-pins { + rockchip,pins = + /* pdm_sdi3_m0 */ + <7 RK_PA7 3 &pcfg_pull_none>; + }; + + pdmm1_clk0_pins: pdmm1-clk0-pins { + rockchip,pins = + /* pdm_clk0_m1 */ + <6 RK_PB4 6 &pcfg_pull_none>; + }; + + pdmm1_clk1_pins: pdmm1-clk1-pins { + rockchip,pins = + /* pdm_clk1_m1 */ + <6 RK_PB7 6 &pcfg_pull_none>; + }; + + pdmm1_sdi0_pins: pdmm1-sdi0-pins { + rockchip,pins = + /* pdm_sdi0_m1 */ + <6 RK_PB5 6 &pcfg_pull_none>; + }; + + pdmm1_sdi1_pins: pdmm1-sdi1-pins { + rockchip,pins = + /* pdm_sdi1_m1 */ + <6 RK_PB6 6 &pcfg_pull_none>; + }; + + pdmm1_sdi2_pins: pdmm1-sdi2-pins { + rockchip,pins = + /* pdm_sdi2_m1 */ + <6 RK_PB2 6 &pcfg_pull_none>; + }; + + pdmm1_sdi3_pins: pdmm1-sdi3-pins { + rockchip,pins = + /* pdm_sdi3_m1 */ + <6 RK_PB3 6 &pcfg_pull_none>; + }; + }; + + pmu { + pmu_pins: pmu-pins { + rockchip,pins = + /* pmu_dbg */ + <0 RK_PA2 3 &pcfg_pull_none>; + }; + }; + + prelight_trig { + prelight_trig_pins: prelight-trig-pins { + rockchip,pins = + /* prelight_trig_out */ + <3 RK_PB3 6 &pcfg_pull_none>; + }; + }; + + preroll { + preroll_pins: preroll-pins { + rockchip,pins = + /* preroll_dbg */ + <0 RK_PB3 5 &pcfg_pull_none>; + }; + }; + + pwm0 { + pwm0m0_ch0_pins: pwm0m0-ch0-pins { + rockchip,pins = + /* pwm0m0_ch0 */ + <0 RK_PC4 3 &pcfg_pull_none>; + }; + pwm0m0_ch1_pins: pwm0m0-ch1-pins { + rockchip,pins = + /* pwm0m0_ch1 */ + <0 RK_PC5 3 &pcfg_pull_none>; + }; + pwm0m0_ch2_pins: pwm0m0-ch2-pins { + rockchip,pins = + /* pwm0m0_ch2 */ + <0 RK_PC6 3 &pcfg_pull_none>; + }; + pwm0m0_ch3_pins: pwm0m0-ch3-pins { + rockchip,pins = + /* pwm0m0_ch3 */ + <0 RK_PC7 3 &pcfg_pull_none>; + }; + pwm0m0_ch4_pins: pwm0m0-ch4-pins { + rockchip,pins = + /* pwm0m0_ch4 */ + <0 RK_PD0 3 &pcfg_pull_none>; + }; + pwm0m0_ch5_pins: pwm0m0-ch5-pins { + rockchip,pins = + /* pwm0m0_ch5 */ + <0 RK_PD1 3 &pcfg_pull_none>; + }; + pwm0m0_ch6_pins: pwm0m0-ch6-pins { + rockchip,pins = + /* pwm0m0_ch6 */ + <0 RK_PC1 3 &pcfg_pull_none>; + }; + pwm0m0_ch7_pins: pwm0m0-ch7-pins { + rockchip,pins = + /* pwm0m0_ch7 */ + <0 RK_PC0 3 &pcfg_pull_none>; + }; + + pwm0m1_ch0_pins: pwm0m1-ch0-pins { + rockchip,pins = + /* pwm0m1_ch0 */ + <5 RK_PA7 7 &pcfg_pull_none>; + }; + pwm0m1_ch1_pins: pwm0m1-ch1-pins { + rockchip,pins = + /* pwm0m1_ch1 */ + <5 RK_PA6 7 &pcfg_pull_none>; + }; + pwm0m1_ch2_pins: pwm0m1-ch2-pins { + rockchip,pins = + /* pwm0m1_ch2 */ + <5 RK_PA5 7 &pcfg_pull_none>; + }; + pwm0m1_ch3_pins: pwm0m1-ch3-pins { + rockchip,pins = + /* pwm0m1_ch3 */ + <5 RK_PA4 7 &pcfg_pull_none>; + }; + pwm0m1_ch4_pins: pwm0m1-ch4-pins { + rockchip,pins = + /* pwm0m1_ch4 */ + <4 RK_PA2 4 &pcfg_pull_none>; + }; + pwm0m1_ch5_pins: pwm0m1-ch5-pins { + rockchip,pins = + /* pwm0m1_ch5 */ + <4 RK_PA3 4 &pcfg_pull_none>; + }; + pwm0m1_ch6_pins: pwm0m1-ch6-pins { + rockchip,pins = + /* pwm0m1_ch6 */ + <4 RK_PA6 4 &pcfg_pull_none>; + }; + pwm0m1_ch7_pins: pwm0m1-ch7-pins { + rockchip,pins = + /* pwm0m1_ch7 */ + <4 RK_PA7 4 &pcfg_pull_none>; + }; + + pwm0m2_ch0_pins: pwm0m2-ch0-pins { + rockchip,pins = + /* pwm0m2_ch0 */ + <6 RK_PC0 6 &pcfg_pull_none>; + }; + pwm0m2_ch1_pins: pwm0m2-ch1-pins { + rockchip,pins = + /* pwm0m2_ch1 */ + <6 RK_PC1 6 &pcfg_pull_none>; + }; + pwm0m2_ch2_pins: pwm0m2-ch2-pins { + rockchip,pins = + /* pwm0m2_ch2 */ + <6 RK_PC2 6 &pcfg_pull_none>; + }; + pwm0m2_ch3_pins: pwm0m2-ch3-pins { + rockchip,pins = + /* pwm0m2_ch3 */ + <6 RK_PC3 6 &pcfg_pull_none>; + }; + pwm0m2_ch4_pins: pwm0m2-ch4-pins { + rockchip,pins = + /* pwm0m2_ch4 */ + <5 RK_PA3 7 &pcfg_pull_none>; + }; + pwm0m2_ch5_pins: pwm0m2-ch5-pins { + rockchip,pins = + /* pwm0m2_ch5 */ + <5 RK_PA2 7 &pcfg_pull_none>; + }; + pwm0m2_ch6_pins: pwm0m2-ch6-pins { + rockchip,pins = + /* pwm0m2_ch6 */ + <5 RK_PD0 7 &pcfg_pull_none>; + }; + pwm0m2_ch7_pins: pwm0m2-ch7-pins { + rockchip,pins = + /* pwm0m2_ch7 */ + <5 RK_PD4 7 &pcfg_pull_none>; + }; + }; + + pwm1 { + pwm1m0_ch0_pins: pwm1m0-ch0-pins { + rockchip,pins = + /* pwm1m0_ch0 */ + <0 RK_PA5 2 &pcfg_pull_none>; + }; + pwm1m0_ch1_pins: pwm1m0-ch1-pins { + rockchip,pins = + /* pwm1m0_ch1 */ + <0 RK_PA1 2 &pcfg_pull_none>; + }; + pwm1m0_ch2_pins: pwm1m0-ch2-pins { + rockchip,pins = + /* pwm1m0_ch2 */ + <0 RK_PB3 2 &pcfg_pull_none>; + }; + pwm1m0_ch3_pins: pwm1m0-ch3-pins { + rockchip,pins = + /* pwm1m0_ch3 */ + <0 RK_PB4 2 &pcfg_pull_none>; + }; + + pwm1m1_ch0_pins: pwm1m1-ch0-pins { + rockchip,pins = + /* pwm1m1_ch0 */ + <5 RK_PD3 7 &pcfg_pull_none>; + }; + pwm1m1_ch1_pins: pwm1m1-ch1-pins { + rockchip,pins = + /* pwm1m1_ch1 */ + <5 RK_PD2 7 &pcfg_pull_none>; + }; + pwm1m1_ch2_pins: pwm1m1-ch2-pins { + rockchip,pins = + /* pwm1m1_ch2 */ + <5 RK_PD1 7 &pcfg_pull_none>; + }; + pwm1m1_ch3_pins: pwm1m1-ch3-pins { + rockchip,pins = + /* pwm1m1_ch3 */ + <5 RK_PD5 7 &pcfg_pull_none>; + }; + + pwm1m2_ch0_pins: pwm1m2-ch0-pins { + rockchip,pins = + /* pwm1m2_ch0 */ + <6 RK_PA0 6 &pcfg_pull_none>; + }; + pwm1m2_ch1_pins: pwm1m2-ch1-pins { + rockchip,pins = + /* pwm1m2_ch1 */ + <6 RK_PA1 6 &pcfg_pull_none>; + }; + pwm1m2_ch2_pins: pwm1m2-ch2-pins { + rockchip,pins = + /* pwm1m2_ch2 */ + <6 RK_PA2 6 &pcfg_pull_none>; + }; + pwm1m2_ch3_pins: pwm1m2-ch3-pins { + rockchip,pins = + /* pwm1m2_ch3 */ + <6 RK_PA3 6 &pcfg_pull_none>; + }; + }; + + pwm2 { + pwm2m0_ch0_pins: pwm2m0-ch0-pins { + rockchip,pins = + /* pwm2m0_ch0 */ + <3 RK_PB2 3 &pcfg_pull_none>; + }; + pwm2m0_ch1_pins: pwm2m0-ch1-pins { + rockchip,pins = + /* pwm2m0_ch1 */ + <3 RK_PB3 3 &pcfg_pull_none>; + }; + pwm2m0_ch2_pins: pwm2m0-ch2-pins { + rockchip,pins = + /* pwm2m0_ch2 */ + <3 RK_PB4 3 &pcfg_pull_none>; + }; + pwm2m0_ch3_pins: pwm2m0-ch3-pins { + rockchip,pins = + /* pwm2m0_ch3 */ + <3 RK_PB5 3 &pcfg_pull_none>; + }; + pwm2m0_ch4_pins: pwm2m0-ch4-pins { + rockchip,pins = + /* pwm2m0_ch4 */ + <5 RK_PA0 7 &pcfg_pull_none>; + }; + pwm2m0_ch5_pins: pwm2m0-ch5-pins { + rockchip,pins = + /* pwm2m0_ch5 */ + <5 RK_PA1 7 &pcfg_pull_none>; + }; + pwm2m0_ch6_pins: pwm2m0-ch6-pins { + rockchip,pins = + /* pwm2m0_ch6 */ + <5 RK_PD6 7 &pcfg_pull_none>; + }; + pwm2m0_ch7_pins: pwm2m0-ch7-pins { + rockchip,pins = + /* pwm2m0_ch7 */ + <5 RK_PD7 7 &pcfg_pull_none>; + }; + + pwm2m1_ch0_pins: pwm2m1-ch0-pins { + rockchip,pins = + /* pwm2m1_ch0 */ + <5 RK_PB2 7 &pcfg_pull_none>; + }; + pwm2m1_ch1_pins: pwm2m1-ch1-pins { + rockchip,pins = + /* pwm2m1_ch1 */ + <5 RK_PB3 7 &pcfg_pull_none>; + }; + pwm2m1_ch2_pins: pwm2m1-ch2-pins { + rockchip,pins = + /* pwm2m1_ch2 */ + <5 RK_PB6 7 &pcfg_pull_none>; + }; + pwm2m1_ch3_pins: pwm2m1-ch3-pins { + rockchip,pins = + /* pwm2m1_ch3 */ + <5 RK_PB7 7 &pcfg_pull_none>; + }; + pwm2m1_ch4_pins: pwm2m1-ch4-pins { + rockchip,pins = + /* pwm2m1_ch4 */ + <7 RK_PA0 5 &pcfg_pull_none>; + }; + pwm2m1_ch5_pins: pwm2m1-ch5-pins { + rockchip,pins = + /* pwm2m1_ch5 */ + <7 RK_PA1 5 &pcfg_pull_none>; + }; + pwm2m1_ch6_pins: pwm2m1-ch6-pins { + rockchip,pins = + /* pwm2m1_ch6 */ + <7 RK_PA2 5 &pcfg_pull_none>; + }; + pwm2m1_ch7_pins: pwm2m1-ch7-pins { + rockchip,pins = + /* pwm2m1_ch7 */ + <7 RK_PA3 5 &pcfg_pull_none>; + }; + + pwm2m2_ch0_pins: pwm2m2-ch0-pins { + rockchip,pins = + /* pwm2m2_ch0 */ + <6 RK_PA4 6 &pcfg_pull_none>; + }; + pwm2m2_ch1_pins: pwm2m2-ch1-pins { + rockchip,pins = + /* pwm2m2_ch1 */ + <6 RK_PA5 6 &pcfg_pull_none>; + }; + pwm2m2_ch2_pins: pwm2m2-ch2-pins { + rockchip,pins = + /* pwm2m2_ch2 */ + <6 RK_PA6 6 &pcfg_pull_none>; + }; + pwm2m2_ch3_pins: pwm2m2-ch3-pins { + rockchip,pins = + /* pwm2m2_ch3 */ + <6 RK_PA7 4 &pcfg_pull_none>; + }; + }; + + pwm3 { + pwm3m0_ch0_pins: pwm3m0-ch0-pins { + rockchip,pins = + /* pwm3m0_ch0 */ + <1 RK_PA0 3 &pcfg_pull_none>; + }; + pwm3m0_ch1_pins: pwm3m0-ch1-pins { + rockchip,pins = + /* pwm3m0_ch1 */ + <1 RK_PA1 3 &pcfg_pull_none>; + }; + pwm3m0_ch2_pins: pwm3m0-ch2-pins { + rockchip,pins = + /* pwm3m0_ch2 */ + <1 RK_PA2 3 &pcfg_pull_none>; + }; + pwm3m0_ch3_pins: pwm3m0-ch3-pins { + rockchip,pins = + /* pwm3m0_ch3 */ + <1 RK_PA3 3 &pcfg_pull_none>; + }; + pwm3m0_ch4_pins: pwm3m0-ch4-pins { + rockchip,pins = + /* pwm3m0_ch4 */ + <1 RK_PA4 3 &pcfg_pull_none>; + }; + pwm3m0_ch5_pins: pwm3m0-ch5-pins { + rockchip,pins = + /* pwm3m0_ch5 */ + <1 RK_PA5 3 &pcfg_pull_none>; + }; + pwm3m0_ch6_pins: pwm3m0-ch6-pins { + rockchip,pins = + /* pwm3m0_ch6 */ + <1 RK_PA6 3 &pcfg_pull_none>; + }; + pwm3m0_ch7_pins: pwm3m0-ch7-pins { + rockchip,pins = + /* pwm3m0_ch7 */ + <1 RK_PA7 3 &pcfg_pull_none>; + }; + + pwm3m1_ch0_pins: pwm3m1-ch0-pins { + rockchip,pins = + /* pwm3m1_ch0 */ + <5 RK_PC0 7 &pcfg_pull_none>; + }; + pwm3m1_ch1_pins: pwm3m1-ch1-pins { + rockchip,pins = + /* pwm3m1_ch1 */ + <5 RK_PC1 7 &pcfg_pull_none>; + }; + pwm3m1_ch2_pins: pwm3m1-ch2-pins { + rockchip,pins = + /* pwm3m1_ch2 */ + <5 RK_PC2 7 &pcfg_pull_none>; + }; + pwm3m1_ch3_pins: pwm3m1-ch3-pins { + rockchip,pins = + /* pwm3m1_ch3 */ + <5 RK_PC3 7 &pcfg_pull_none>; + }; + pwm3m1_ch4_pins: pwm3m1-ch4-pins { + rockchip,pins = + /* pwm3m1_ch4 */ + <5 RK_PC4 7 &pcfg_pull_none>; + }; + pwm3m1_ch5_pins: pwm3m1-ch5-pins { + rockchip,pins = + /* pwm3m1_ch5 */ + <5 RK_PC5 7 &pcfg_pull_none>; + }; + pwm3m1_ch6_pins: pwm3m1-ch6-pins { + rockchip,pins = + /* pwm3m1_ch6 */ + <5 RK_PC6 7 &pcfg_pull_none>; + }; + pwm3m1_ch7_pins: pwm3m1-ch7-pins { + rockchip,pins = + /* pwm3m1_ch7 */ + <5 RK_PC7 7 &pcfg_pull_none>; + }; + }; + + pwr { + pwr_pins: pwr-pins { + rockchip,pins = + /* pwr_ctrl0 */ + <0 RK_PA3 1 &pcfg_pull_none>, + /* pwr_ctrl1 */ + <0 RK_PA4 1 &pcfg_pull_none>, + /* pwr_ctrl2 */ + <0 RK_PC2 2 &pcfg_pull_none>; + }; + }; + + ref_clk0 { + ref_clk0_pins: ref-clk0-pins { + rockchip,pins = + /* ref_clk0_out */ + <0 RK_PA0 1 &pcfg_pull_none>; + }; + }; + + rtc_32k { + rtc_32k_pins: rtc-32k-pins { + rockchip,pins = + /* rtc_32k_out */ + <0 RK_PA2 1 &pcfg_pull_none>; + }; + }; + + sai0 { + sai0m0_lrck_pins: sai0m0-lrck-pins { + rockchip,pins = + /* sai0_lrck_m0 */ + <7 RK_PA3 1 &pcfg_pull_none>; + }; + + sai0m0_mclk_pins: sai0m0-mclk-pins { + rockchip,pins = + /* sai0_mclk_m0 */ + <7 RK_PA2 1 &pcfg_pull_none>; + }; + + sai0m0_sclk_pins: sai0m0-sclk-pins { + rockchip,pins = + /* sai0_sclk_m0 */ + <7 RK_PA0 1 &pcfg_pull_none>; + }; + + sai0m0_sdi0_pins: sai0m0-sdi0-pins { + rockchip,pins = + /* sai0_sdi0_m0 */ + <7 RK_PA6 1 &pcfg_pull_none>; + }; + + sai0m0_sdi1_pins: sai0m0-sdi1-pins { + rockchip,pins = + /* sai0_sdi1_m0 */ + <7 RK_PB1 1 &pcfg_pull_none>; + }; + + sai0m0_sdi2_pins: sai0m0-sdi2-pins { + rockchip,pins = + /* sai0_sdi2_m0 */ + <7 RK_PB0 1 &pcfg_pull_none>; + }; + + sai0m0_sdi3_pins: sai0m0-sdi3-pins { + rockchip,pins = + /* sai0_sdi3_m0 */ + <7 RK_PA7 1 &pcfg_pull_none>; + }; + + sai0m0_sdo0_pins: sai0m0-sdo0-pins { + rockchip,pins = + /* sai0_sdo0_m0 */ + <7 RK_PA5 1 &pcfg_pull_none>; + }; + + sai0m0_sdo1_pins: sai0m0-sdo1-pins { + rockchip,pins = + /* sai0_sdo1_m0 */ + <7 RK_PA7 2 &pcfg_pull_none>; + }; + + sai0m0_sdo2_pins: sai0m0-sdo2-pins { + rockchip,pins = + /* sai0_sdo2_m0 */ + <7 RK_PB0 2 &pcfg_pull_none>; + }; + + sai0m0_sdo3_pins: sai0m0-sdo3-pins { + rockchip,pins = + /* sai0_sdo3_m0 */ + <7 RK_PB1 2 &pcfg_pull_none>; + }; + + sai0m1_lrck_pins: sai0m1-lrck-pins { + rockchip,pins = + /* sai0_lrck_m1 */ + <6 RK_PA1 5 &pcfg_pull_none>; + }; + + sai0m1_mclk_pins: sai0m1-mclk-pins { + rockchip,pins = + /* sai0_mclk_m1 */ + <6 RK_PA4 5 &pcfg_pull_none>; + }; + + sai0m1_sclk_pins: sai0m1-sclk-pins { + rockchip,pins = + /* sai0_sclk_m1 */ + <6 RK_PA0 5 &pcfg_pull_none>; + }; + + sai0m1_sdi0_pins: sai0m1-sdi0-pins { + rockchip,pins = + /* sai0_sdi0_m1 */ + <6 RK_PA3 5 &pcfg_pull_none>; + }; + + sai0m1_sdi1_pins: sai0m1-sdi1-pins { + rockchip,pins = + /* sai0_sdi1_m1 */ + <6 RK_PB1 5 &pcfg_pull_none>; + }; + + sai0m1_sdi2_pins: sai0m1-sdi2-pins { + rockchip,pins = + /* sai0_sdi2_m1 */ + <6 RK_PB0 5 &pcfg_pull_none>; + }; + + sai0m1_sdi3_pins: sai0m1-sdi3-pins { + rockchip,pins = + /* sai0_sdi3_m1 */ + <6 RK_PA7 5 &pcfg_pull_none>; + }; + + sai0m1_sdo0_pins: sai0m1-sdo0-pins { + rockchip,pins = + /* sai0_sdo0_m1 */ + <6 RK_PA2 5 &pcfg_pull_none>; + }; + + sai0m1_sdo1_pins: sai0m1-sdo1-pins { + rockchip,pins = + /* sai0_sdo1_m1 */ + <6 RK_PA7 6 &pcfg_pull_none>; + }; + + sai0m1_sdo2_pins: sai0m1-sdo2-pins { + rockchip,pins = + /* sai0_sdo2_m1 */ + <6 RK_PB0 6 &pcfg_pull_none>; + }; + + sai0m1_sdo3_pins: sai0m1-sdo3-pins { + rockchip,pins = + /* sai0_sdo3_m1 */ + <6 RK_PB1 6 &pcfg_pull_none>; + }; + }; + + sai1 { + sai1m0_lrck_pins: sai1m0-lrck-pins { + rockchip,pins = + /* sai1_lrck_m0 */ + <1 RK_PB4 2 &pcfg_pull_none>; + }; + + sai1m0_mclk_pins: sai1m0-mclk-pins { + rockchip,pins = + /* sai1_mclk_m0 */ + <1 RK_PB0 2 &pcfg_pull_none>; + }; + + sai1m0_sclk_pins: sai1m0-sclk-pins { + rockchip,pins = + /* sai1_sclk_m0 */ + <1 RK_PB5 2 &pcfg_pull_none>; + }; + + sai1m0_sdi_pins: sai1m0-sdi-pins { + rockchip,pins = + /* sai1m0_sdi */ + <1 RK_PB6 2 &pcfg_pull_none>; + }; + sai1m0_sdo_pins: sai1m0-sdo-pins { + rockchip,pins = + /* sai1m0_sdo */ + <1 RK_PB2 2 &pcfg_pull_none>; + }; + + sai1m1_lrck_pins: sai1m1-lrck-pins { + rockchip,pins = + /* sai1_lrck_m1 */ + <4 RK_PA5 2 &pcfg_pull_none>; + }; + + sai1m1_mclk_pins: sai1m1-mclk-pins { + rockchip,pins = + /* sai1_mclk_m1 */ + <4 RK_PA3 2 &pcfg_pull_none>; + }; + + sai1m1_sclk_pins: sai1m1-sclk-pins { + rockchip,pins = + /* sai1_sclk_m1 */ + <4 RK_PA4 2 &pcfg_pull_none>; + }; + + sai1m1_sdi_pins: sai1m1-sdi-pins { + rockchip,pins = + /* sai1m1_sdi */ + <4 RK_PA6 2 &pcfg_pull_none>; + }; + sai1m1_sdo_pins: sai1m1-sdo-pins { + rockchip,pins = + /* sai1m1_sdo */ + <4 RK_PA7 2 &pcfg_pull_none>; + }; + + sai1m2_lrck_pins: sai1m2-lrck-pins { + rockchip,pins = + /* sai1_lrck_m2 */ + <5 RK_PC6 5 &pcfg_pull_none>; + }; + + sai1m2_mclk_pins: sai1m2-mclk-pins { + rockchip,pins = + /* sai1_mclk_m2 */ + <5 RK_PC3 5 &pcfg_pull_none>; + }; + + sai1m2_sclk_pins: sai1m2-sclk-pins { + rockchip,pins = + /* sai1_sclk_m2 */ + <5 RK_PC5 5 &pcfg_pull_none>; + }; + + sai1m2_sdi_pins: sai1m2-sdi-pins { + rockchip,pins = + /* sai1m2_sdi */ + <5 RK_PC7 5 &pcfg_pull_none>; + }; + sai1m2_sdo_pins: sai1m2-sdo-pins { + rockchip,pins = + /* sai1m2_sdo */ + <5 RK_PC4 5 &pcfg_pull_none>; + }; + }; + + sai2 { + sai2m0_lrck_pins: sai2m0-lrck-pins { + rockchip,pins = + /* sai2_lrck_m0 */ + <3 RK_PB5 2 &pcfg_pull_none>; + }; + + sai2m0_mclk_pins: sai2m0-mclk-pins { + rockchip,pins = + /* sai2_mclk_m0 */ + <3 RK_PB6 2 &pcfg_pull_none>; + }; + + sai2m0_sclk_pins: sai2m0-sclk-pins { + rockchip,pins = + /* sai2_sclk_m0 */ + <3 RK_PB4 2 &pcfg_pull_none>; + }; + + sai2m0_sdi0_pins: sai2m0-sdi0-pins { + rockchip,pins = + /* sai2_sdi0_m0 */ + <3 RK_PB3 2 &pcfg_pull_none>; + }; + + sai2m0_sdi1_pins: sai2m0-sdi1-pins { + rockchip,pins = + /* sai2_sdi1_m0 */ + <3 RK_PB7 2 &pcfg_pull_none>; + }; + + sai2m0_sdi2_pins: sai2m0-sdi2-pins { + rockchip,pins = + /* sai2_sdi2_m0 */ + <3 RK_PB1 2 &pcfg_pull_none>; + }; + + sai2m0_sdo_pins: sai2m0-sdo-pins { + rockchip,pins = + /* sai2m0_sdo */ + <3 RK_PB2 2 &pcfg_pull_none>; + }; + + sai2m1_lrck_pins: sai2m1-lrck-pins { + rockchip,pins = + /* sai2_lrck_m1 */ + <5 RK_PA7 5 &pcfg_pull_none>; + }; + + sai2m1_mclk_pins: sai2m1-mclk-pins { + rockchip,pins = + /* sai2_mclk_m1 */ + <5 RK_PA3 5 &pcfg_pull_none>; + }; + + sai2m1_sclk_pins: sai2m1-sclk-pins { + rockchip,pins = + /* sai2_sclk_m1 */ + <5 RK_PA5 5 &pcfg_pull_none>; + }; + + sai2m1_sdi0_pins: sai2m1-sdi0-pins { + rockchip,pins = + /* sai2_sdi0_m1 */ + <5 RK_PA6 5 &pcfg_pull_none>; + }; + + sai2m1_sdi1_pins: sai2m1-sdi1-pins { + rockchip,pins = + /* sai2_sdi1_m1 */ + <5 RK_PA2 5 &pcfg_pull_none>; + }; + + sai2m1_sdi2_pins: sai2m1-sdi2-pins { + rockchip,pins = + /* sai2_sdi2_m1 */ + <5 RK_PA1 5 &pcfg_pull_none>; + }; + + sai2m1_sdo_pins: sai2m1-sdo-pins { + rockchip,pins = + /* sai2m1_sdo */ + <5 RK_PA4 5 &pcfg_pull_none>; + }; + }; + + sdmmc0_pins: sdmmc0 { + sdmmc0_bus4_pins: sdmmc0-bus4-pins { + rockchip,pins = + /* sdmmc0_d0 */ + <2 RK_PA0 1 &pcfg_pull_up>, + /* sdmmc0_d1 */ + <2 RK_PA1 1 &pcfg_pull_up>, + /* sdmmc0_d2 */ + <2 RK_PA2 1 &pcfg_pull_up>, + /* sdmmc0_d3 */ + <2 RK_PA3 1 &pcfg_pull_up>; + }; + + sdmmc0_cmd_pins: sdmmc0-cmd-pins { + rockchip,pins = + /* sdmmc0_cmd */ + <2 RK_PA5 1 &pcfg_pull_up>; + }; + + sdmmc0_clk_pins: sdmmc0-clk-pins { + rockchip,pins = + /* sdmmc0_clk */ + <2 RK_PA4 1 &pcfg_pull_none>; + }; + sdmmc0_detn_pins: sdmmc0-detn-pins { + rockchip,pins = + /* sdmmc0_detn */ + <0 RK_PA5 1 &pcfg_pull_none>; + }; + }; + + sdmmc1 { + sdmmc1_bus4_pins: sdmmc1-bus4-pins { + rockchip,pins = + /* sdmmc1_d0 */ + <3 RK_PA2 1 &pcfg_pull_up>, + /* sdmmc1_d1 */ + <3 RK_PA3 1 &pcfg_pull_up>, + /* sdmmc1_d2 */ + <3 RK_PA4 1 &pcfg_pull_up>, + /* sdmmc1_d3 */ + <3 RK_PA5 1 &pcfg_pull_up>; + }; + + sdmmc1_cmd_pins: sdmmc1-cmd-pins { + rockchip,pins = + /* sdmmc1_cmd */ + <3 RK_PA1 1 &pcfg_pull_up>; + }; + + sdmmc1_clk_pins: sdmmc1-clk-pins { + rockchip,pins = + /* sdmmc1_clk */ + <3 RK_PA0 1 &pcfg_pull_none>; + }; + sdmmc1_detn_pins: sdmmc1-detn-pins { + rockchip,pins = + /* sdmmc1_detn */ + <3 RK_PB6 3 &pcfg_pull_none>; + }; + }; + + sdmmc0_testclk { + sdmmc0_testclk_out_pins: sdmmc0-testclk-out-pins { + rockchip,pins = + /* sdmmc0_testclk_out */ + <1 RK_PB7 3 &pcfg_pull_none>; + }; + }; + + sdmmc0_testdata { + sdmmc0_testdata_out_pins: sdmmc0-testdata-out-pins { + rockchip,pins = + /* sdmmc0_testdata_out */ + <1 RK_PB0 3 &pcfg_pull_none>; + }; + }; + + sdmmc1_testclk { + sdmmc1_testclk_out_pins: sdmmc1-testclk-out-pins { + rockchip,pins = + /* sdmmc1_testclk_out */ + <3 RK_PA6 6 &pcfg_pull_none>; + }; + }; + + sdmmc1_testdata { + sdmmc1_testdata_out_pins: sdmmc1-testdata-out-pins { + rockchip,pins = + /* sdmmc1_testdata_out */ + <3 RK_PA7 6 &pcfg_pull_none>; + }; + }; + + spi0 { + spi0m0_clk_pins: spi0m0-clk-pins { + rockchip,pins = + /* spi0_clk_m0 */ + <0 RK_PB2 2 &pcfg_pull_none_drv_level_3>, + /* spi0_miso_m0 */ + <0 RK_PB1 2 &pcfg_pull_none_drv_level_3>, + /* spi0_mosi_m0 */ + <0 RK_PB0 2 &pcfg_pull_none_drv_level_3>; + }; + + spi0m0_csn0_pins: spi0m0-csn0-pins { + rockchip,pins = + /* spi0m0_csn0 */ + <0 RK_PA7 2 &pcfg_pull_none_drv_level_3>; + }; + spi0m0_csn1_pins: spi0m0-csn1-pins { + rockchip,pins = + /* spi0m0_csn1 */ + <0 RK_PA6 2 &pcfg_pull_none_drv_level_3>; + }; + + spi0m1_clk_pins: spi0m1-clk-pins { + rockchip,pins = + /* spi0_clk_m1 */ + <4 RK_PA7 1 &pcfg_pull_none_drv_level_3>, + /* spi0_miso_m1 */ + <4 RK_PA5 1 &pcfg_pull_none_drv_level_3>, + /* spi0_mosi_m1 */ + <4 RK_PA4 1 &pcfg_pull_none_drv_level_3>; + }; + + spi0m1_csn0_pins: spi0m1-csn0-pins { + rockchip,pins = + /* spi0m1_csn0 */ + <4 RK_PA6 1 &pcfg_pull_none_drv_level_3>; + }; + spi0m1_csn1_pins: spi0m1-csn1-pins { + rockchip,pins = + /* spi0m1_csn1 */ + <4 RK_PA3 1 &pcfg_pull_none_drv_level_3>; + }; + + spi0m2_clk_pins: spi0m2-clk-pins { + rockchip,pins = + /* spi0_clk_m2 */ + <5 RK_PA6 2 &pcfg_pull_none_drv_level_3>, + /* spi0_miso_m2 */ + <5 RK_PA5 2 &pcfg_pull_none_drv_level_3>, + /* spi0_mosi_m2 */ + <5 RK_PA4 2 &pcfg_pull_none_drv_level_3>; + }; + + spi0m2_csn0_pins: spi0m2-csn0-pins { + rockchip,pins = + /* spi0m2_csn0 */ + <5 RK_PA3 2 &pcfg_pull_none_drv_level_3>; + }; + spi0m2_csn1_pins: spi0m2-csn1-pins { + rockchip,pins = + /* spi0m2_csn1 */ + <5 RK_PA7 2 &pcfg_pull_none_drv_level_3>; + }; + }; + + spi1 { + spi1m0_clk_pins: spi1m0-clk-pins { + rockchip,pins = + /* spi1_clk_m0 */ + <6 RK_PB4 4 &pcfg_pull_none_drv_level_3>, + /* spi1_miso_m0 */ + <6 RK_PB3 4 &pcfg_pull_none_drv_level_3>, + /* spi1_mosi_m0 */ + <6 RK_PB2 4 &pcfg_pull_none_drv_level_3>; + }; + + spi1m0_csn0_pins: spi1m0-csn0-pins { + rockchip,pins = + /* spi1m0_csn0 */ + <6 RK_PB1 4 &pcfg_pull_none_drv_level_3>; + }; + spi1m0_csn1_pins: spi1m0-csn1-pins { + rockchip,pins = + /* spi1m0_csn1 */ + <6 RK_PB0 4 &pcfg_pull_none_drv_level_3>; + }; + + spi1m1_clk_pins: spi1m1-clk-pins { + rockchip,pins = + /* spi1_clk_m1 */ + <3 RK_PB4 1 &pcfg_pull_none_drv_level_3>, + /* spi1_miso_m1 */ + <3 RK_PB3 1 &pcfg_pull_none_drv_level_3>, + /* spi1_mosi_m1 */ + <3 RK_PB2 1 &pcfg_pull_none_drv_level_3>; + }; + + spi1m1_csn0_pins: spi1m1-csn0-pins { + rockchip,pins = + /* spi1m1_csn0 */ + <3 RK_PB5 1 &pcfg_pull_none_drv_level_3>; + }; + spi1m1_csn1_pins: spi1m1-csn1-pins { + rockchip,pins = + /* spi1m1_csn1 */ + <3 RK_PB6 1 &pcfg_pull_none_drv_level_3>; + }; + + spi1m2_clk_pins: spi1m2-clk-pins { + rockchip,pins = + /* spi1_clk_m2 */ + <5 RK_PD1 2 &pcfg_pull_none_drv_level_3>, + /* spi1_miso_m2 */ + <5 RK_PD3 2 &pcfg_pull_none_drv_level_3>, + /* spi1_mosi_m2 */ + <5 RK_PD2 2 &pcfg_pull_none_drv_level_3>; + }; + + spi1m2_csn0_pins: spi1m2-csn0-pins { + rockchip,pins = + /* spi1m2_csn0 */ + <5 RK_PD0 2 &pcfg_pull_none_drv_level_3>; + }; + spi1m2_csn1_pins: spi1m2-csn1-pins { + rockchip,pins = + /* spi1m2_csn1 */ + <5 RK_PD4 2 &pcfg_pull_none_drv_level_3>; + }; + }; + + spi2ahb { + spi2ahb_clk_pins: spi2ahb-clk-pins { + rockchip,pins = + /* spi2ahb_clk */ + <0 RK_PC3 1 &pcfg_pull_none>; + }; + + spi2ahb_csn0_pins: spi2ahb-csn0-pins { + rockchip,pins = + /* spi2ahb_csn0 */ + <0 RK_PC2 1 &pcfg_pull_none>; + }; + spi2ahb_d0_pins: spi2ahb-d0-pins { + rockchip,pins = + /* spi2ahb_d0 */ + <0 RK_PC7 1 &pcfg_pull_none>; + }; + spi2ahb_d1_pins: spi2ahb-d1-pins { + rockchip,pins = + /* spi2ahb_d1 */ + <0 RK_PC6 1 &pcfg_pull_none>; + }; + spi2ahb_d2_pins: spi2ahb-d2-pins { + rockchip,pins = + /* spi2ahb_d2 */ + <0 RK_PC5 1 &pcfg_pull_none>; + }; + spi2ahb_d3_pins: spi2ahb-d3-pins { + rockchip,pins = + /* spi2ahb_d3 */ + <0 RK_PC4 1 &pcfg_pull_none>; + }; + }; + + test_clk0 { + test_clk0_pins: test-clk0-pins { + rockchip,pins = + /* test_clk0_out */ + <0 RK_PA0 2 &pcfg_pull_none>; + }; + }; + + test_clk1 { + test_clk1_pins: test-clk1-pins { + rockchip,pins = + /* test_clk1_out */ + <2 RK_PA2 5 &pcfg_pull_none>; + }; + }; + + tsadc { + tsadc_pins: tsadc-pins { + rockchip,pins = + /* tsadc_shut */ + <0 RK_PA1 3 &pcfg_pull_none>, + /* tsadc_shutorg */ + <0 RK_PA1 4 &pcfg_pull_none>; + }; + }; + + uart0 { + uart0m0_xfer_pins: uart0m0-xfer-pins { + rockchip,pins = + /* uart0_rx_m0 */ + <2 RK_PA0 2 &pcfg_pull_up>, + /* uart0_tx_m0 */ + <2 RK_PA1 2 &pcfg_pull_up>; + }; + + uart0m1_xfer_pins: uart0m1-xfer-pins { + rockchip,pins = + /* uart0_rx_m1 */ + <5 RK_PD7 1 &pcfg_pull_up>, + /* uart0_tx_m1 */ + <5 RK_PD6 1 &pcfg_pull_up>; + }; + + uart0m2_xfer_pins: uart0m2-xfer-pins { + rockchip,pins = + /* uart0_rx_m2 */ + <0 RK_PB4 1 &pcfg_pull_up>, + /* uart0_tx_m2 */ + <0 RK_PB3 1 &pcfg_pull_up>; + }; + }; + + uart1 { + uart1m0_xfer_pins: uart1m0-xfer-pins { + rockchip,pins = + /* uart1_rx_m0 */ + <0 RK_PC5 4 &pcfg_pull_up>, + /* uart1_tx_m0 */ + <0 RK_PC4 4 &pcfg_pull_up>; + }; + + uart1m0_ctsn_pins: uart1m0-ctsn-pins { + rockchip,pins = + /* uart1m0_ctsn */ + <0 RK_PC7 4 &pcfg_pull_none>; + }; + uart1m0_rtsn_pins: uart1m0-rtsn-pins { + rockchip,pins = + /* uart1m0_rtsn */ + <0 RK_PC6 4 &pcfg_pull_none>; + }; + + uart1m1_xfer_pins: uart1m1-xfer-pins { + rockchip,pins = + /* uart1_rx_m1 */ + <3 RK_PB7 4 &pcfg_pull_up>, + /* uart1_tx_m1 */ + <3 RK_PB6 4 &pcfg_pull_up>; + }; + + uart1m1_ctsn_pins: uart1m1-ctsn-pins { + rockchip,pins = + /* uart1m1_ctsn */ + <3 RK_PB5 4 &pcfg_pull_none>; + }; + uart1m1_rtsn_pins: uart1m1-rtsn-pins { + rockchip,pins = + /* uart1m1_rtsn */ + <3 RK_PB4 4 &pcfg_pull_none>; + }; + }; + + uart2 { + uart2m0_xfer_pins: uart2m0-xfer-pins { + rockchip,pins = + /* uart2_rx_m0 */ + <3 RK_PB0 4 &pcfg_pull_up>, + /* uart2_tx_m0 */ + <3 RK_PB1 4 &pcfg_pull_up>; + }; + + uart2m0_ctsn_pins: uart2m0-ctsn-pins { + rockchip,pins = + /* uart2m0_ctsn */ + <3 RK_PA7 4 &pcfg_pull_none>; + }; + uart2m0_rtsn_pins: uart2m0-rtsn-pins { + rockchip,pins = + /* uart2m0_rtsn */ + <3 RK_PA6 4 &pcfg_pull_none>; + }; + + uart2m1_xfer_pins: uart2m1-xfer-pins { + rockchip,pins = + /* uart2_rx_m1 */ + <7 RK_PB0 6 &pcfg_pull_up>, + /* uart2_tx_m1 */ + <7 RK_PB1 6 &pcfg_pull_up>; + }; + + uart2m1_ctsn_pins: uart2m1-ctsn-pins { + rockchip,pins = + /* uart2m1_ctsn */ + <7 RK_PA4 6 &pcfg_pull_none>; + }; + uart2m1_rtsn_pins: uart2m1-rtsn-pins { + rockchip,pins = + /* uart2m1_rtsn */ + <7 RK_PA7 6 &pcfg_pull_none>; + }; + }; + + uart3 { + uart3m0_xfer_pins: uart3m0-xfer-pins { + rockchip,pins = + /* uart3_rx_m0 */ + <2 RK_PA2 2 &pcfg_pull_up>, + /* uart3_tx_m0 */ + <2 RK_PA3 2 &pcfg_pull_up>; + }; + + uart3m0_ctsn_pins: uart3m0-ctsn-pins { + rockchip,pins = + /* uart3m0_ctsn */ + <2 RK_PA5 2 &pcfg_pull_none>; + }; + uart3m0_rtsn_pins: uart3m0-rtsn-pins { + rockchip,pins = + /* uart3m0_rtsn */ + <2 RK_PA4 2 &pcfg_pull_none>; + }; + + uart3m1_xfer_pins: uart3m1-xfer-pins { + rockchip,pins = + /* uart3_rx_m1 */ + <5 RK_PD5 8 &pcfg_pull_up>, + /* uart3_tx_m1 */ + <5 RK_PD4 8 &pcfg_pull_up>; + }; + + uart3m1_ctsn_pins: uart3m1-ctsn-pins { + rockchip,pins = + /* uart3m1_ctsn */ + <5 RK_PD3 8 &pcfg_pull_none>; + }; + uart3m1_rtsn_pins: uart3m1-rtsn-pins { + rockchip,pins = + /* uart3m1_rtsn */ + <5 RK_PD2 8 &pcfg_pull_none>; + }; + + uart3m2_xfer_pins: uart3m2-xfer-pins { + rockchip,pins = + /* uart3_rx_m2 */ + <6 RK_PC3 7 &pcfg_pull_up>, + /* uart3_tx_m2 */ + <6 RK_PC2 7 &pcfg_pull_up>; + }; + + uart3m2_ctsn_pins: uart3m2-ctsn-pins { + rockchip,pins = + /* uart3m2_ctsn */ + <6 RK_PC1 7 &pcfg_pull_none>; + }; + uart3m2_rtsn_pins: uart3m2-rtsn-pins { + rockchip,pins = + /* uart3m2_rtsn */ + <6 RK_PC0 7 &pcfg_pull_none>; + }; + }; + + uart4 { + uart4m0_xfer_pins: uart4m0-xfer-pins { + rockchip,pins = + /* uart4_rx_m0 */ + <4 RK_PA2 5 &pcfg_pull_up>, + /* uart4_tx_m0 */ + <4 RK_PA3 5 &pcfg_pull_up>; + }; + + uart4m0_ctsn_pins: uart4m0-ctsn-pins { + rockchip,pins = + /* uart4m0_ctsn */ + <4 RK_PA1 5 &pcfg_pull_none>; + }; + uart4m0_rtsn_pins: uart4m0-rtsn-pins { + rockchip,pins = + /* uart4m0_rtsn */ + <4 RK_PA0 5 &pcfg_pull_none>; + }; + + uart4m1_xfer_pins: uart4m1-xfer-pins { + rockchip,pins = + /* uart4_rx_m1 */ + <5 RK_PA3 8 &pcfg_pull_up>, + /* uart4_tx_m1 */ + <5 RK_PA2 8 &pcfg_pull_up>; + }; + + uart4m1_ctsn_pins: uart4m1-ctsn-pins { + rockchip,pins = + /* uart4m1_ctsn */ + <5 RK_PA1 8 &pcfg_pull_none>; + }; + uart4m1_rtsn_pins: uart4m1-rtsn-pins { + rockchip,pins = + /* uart4m1_rtsn */ + <5 RK_PA0 8 &pcfg_pull_none>; + }; + + uart4m2_xfer_pins: uart4m2-xfer-pins { + rockchip,pins = + /* uart4_rx_m2 */ + <6 RK_PA1 7 &pcfg_pull_up>, + /* uart4_tx_m2 */ + <6 RK_PA0 7 &pcfg_pull_up>; + }; + + uart4m2_ctsn_pins: uart4m2-ctsn-pins { + rockchip,pins = + /* uart4m2_ctsn */ + <6 RK_PA7 7 &pcfg_pull_none>; + }; + uart4m2_rtsn_pins: uart4m2-rtsn-pins { + rockchip,pins = + /* uart4m2_rtsn */ + <6 RK_PA6 7 &pcfg_pull_none>; + }; + + uart4m3_xfer_pins: uart4m3-xfer-pins { + rockchip,pins = + /* uart4_rx_m3 */ + <2 RK_PA4 3 &pcfg_pull_up>, + /* uart4_tx_m3 */ + <2 RK_PA5 3 &pcfg_pull_up>; + }; + + uart4m3_ctsn_pins: uart4m3-ctsn-pins { + rockchip,pins = + /* uart4m3_ctsn */ + <2 RK_PA3 3 &pcfg_pull_none>; + }; + uart4m3_rtsn_pins: uart4m3-rtsn-pins { + rockchip,pins = + /* uart4m3_rtsn */ + <2 RK_PA2 3 &pcfg_pull_none>; + }; + }; + + uart5 { + uart5m0_xfer_pins: uart5m0-xfer-pins { + rockchip,pins = + /* uart5_rx_m0 */ + <4 RK_PA7 5 &pcfg_pull_up>, + /* uart5_tx_m0 */ + <4 RK_PA6 5 &pcfg_pull_up>; + }; + + uart5m0_ctsn_pins: uart5m0-ctsn-pins { + rockchip,pins = + /* uart5m0_ctsn */ + <4 RK_PB1 5 &pcfg_pull_none>; + }; + uart5m0_rtsn_pins: uart5m0-rtsn-pins { + rockchip,pins = + /* uart5m0_rtsn */ + <4 RK_PB0 5 &pcfg_pull_none>; + }; + + uart5m1_xfer_pins: uart5m1-xfer-pins { + rockchip,pins = + /* uart5_rx_m1 */ + <5 RK_PA5 8 &pcfg_pull_up>, + /* uart5_tx_m1 */ + <5 RK_PA4 8 &pcfg_pull_up>; + }; + + uart5m1_ctsn_pins: uart5m1-ctsn-pins { + rockchip,pins = + /* uart5m1_ctsn */ + <5 RK_PA7 8 &pcfg_pull_none>; + }; + uart5m1_rtsn_pins: uart5m1-rtsn-pins { + rockchip,pins = + /* uart5m1_rtsn */ + <5 RK_PA6 8 &pcfg_pull_none>; + }; + + uart5m2_xfer_pins: uart5m2-xfer-pins { + rockchip,pins = + /* uart5_rx_m2 */ + <6 RK_PA3 7 &pcfg_pull_up>, + /* uart5_tx_m2 */ + <6 RK_PA2 7 &pcfg_pull_up>; + }; + + uart5m2_ctsn_pins: uart5m2-ctsn-pins { + rockchip,pins = + /* uart5m2_ctsn */ + <6 RK_PA5 7 &pcfg_pull_none>; + }; + uart5m2_rtsn_pins: uart5m2-rtsn-pins { + rockchip,pins = + /* uart5m2_rtsn */ + <6 RK_PA4 7 &pcfg_pull_none>; + }; + }; + + uart6 { + uart6m0_xfer_pins: uart6m0-xfer-pins { + rockchip,pins = + /* uart6_rx_m0 */ + <5 RK_PB1 8 &pcfg_pull_up>, + /* uart6_tx_m0 */ + <5 RK_PB0 8 &pcfg_pull_up>; + }; + + uart6m0_ctsn_pins: uart6m0-ctsn-pins { + rockchip,pins = + /* uart6m0_ctsn */ + <5 RK_PB3 8 &pcfg_pull_none>; + }; + uart6m0_rtsn_pins: uart6m0-rtsn-pins { + rockchip,pins = + /* uart6m0_rtsn */ + <5 RK_PB2 8 &pcfg_pull_none>; + }; + + uart6m1_xfer_pins: uart6m1-xfer-pins { + rockchip,pins = + /* uart6_rx_m1 */ + <6 RK_PB1 7 &pcfg_pull_up>, + /* uart6_tx_m1 */ + <6 RK_PB0 7 &pcfg_pull_up>; + }; + + uart6m1_ctsn_pins: uart6m1-ctsn-pins { + rockchip,pins = + /* uart6m1_ctsn */ + <6 RK_PB3 7 &pcfg_pull_none>; + }; + uart6m1_rtsn_pins: uart6m1-rtsn-pins { + rockchip,pins = + /* uart6m1_rtsn */ + <6 RK_PB2 7 &pcfg_pull_none>; + }; + }; + + uart7 { + uart7m0_xfer_pins: uart7m0-xfer-pins { + rockchip,pins = + /* uart7_rx_m0 */ + <5 RK_PB5 8 &pcfg_pull_up>, + /* uart7_tx_m0 */ + <5 RK_PB4 8 &pcfg_pull_up>; + }; + + uart7m0_ctsn_pins: uart7m0-ctsn-pins { + rockchip,pins = + /* uart7m0_ctsn */ + <5 RK_PB7 8 &pcfg_pull_none>; + }; + uart7m0_rtsn_pins: uart7m0-rtsn-pins { + rockchip,pins = + /* uart7m0_rtsn */ + <5 RK_PB6 8 &pcfg_pull_none>; + }; + + uart7m1_xfer_pins: uart7m1-xfer-pins { + rockchip,pins = + /* uart7_rx_m1 */ + <6 RK_PB5 7 &pcfg_pull_up>, + /* uart7_tx_m1 */ + <6 RK_PB4 7 &pcfg_pull_up>; + }; + + uart7m1_ctsn_pins: uart7m1-ctsn-pins { + rockchip,pins = + /* uart7m1_ctsn */ + <6 RK_PB7 7 &pcfg_pull_none>; + }; + uart7m1_rtsn_pins: uart7m1-rtsn-pins { + rockchip,pins = + /* uart7m1_rtsn */ + <6 RK_PB6 7 &pcfg_pull_none>; + }; + }; + + vi_cif { + vi_cifm0_pins: vi-cifm0-pins { + rockchip,pins = + /* vi_cif_clkin_m0 */ + <6 RK_PC1 1 &pcfg_pull_none>, + /* vi_cif_clkout_m0 */ + <6 RK_PC2 1 &pcfg_pull_none>, + /* vi_cif_d0_m0 */ + <6 RK_PA0 1 &pcfg_pull_none>, + /* vi_cif_d10_m0 */ + <6 RK_PB2 1 &pcfg_pull_none>, + /* vi_cif_d11_m0 */ + <6 RK_PB3 1 &pcfg_pull_none>, + /* vi_cif_d12_m0 */ + <6 RK_PB4 1 &pcfg_pull_none>, + /* vi_cif_d13_m0 */ + <6 RK_PB5 1 &pcfg_pull_none>, + /* vi_cif_d14_m0 */ + <6 RK_PB6 1 &pcfg_pull_none>, + /* vi_cif_d15_m0 */ + <6 RK_PB7 1 &pcfg_pull_none>, + /* vi_cif_d1_m0 */ + <6 RK_PA1 1 &pcfg_pull_none>, + /* vi_cif_d2_m0 */ + <6 RK_PA2 1 &pcfg_pull_none>, + /* vi_cif_d3_m0 */ + <6 RK_PA3 1 &pcfg_pull_none>, + /* vi_cif_d4_m0 */ + <6 RK_PA4 1 &pcfg_pull_none>, + /* vi_cif_d5_m0 */ + <6 RK_PA5 1 &pcfg_pull_none>, + /* vi_cif_d6_m0 */ + <6 RK_PA6 1 &pcfg_pull_none>, + /* vi_cif_d7_m0 */ + <6 RK_PA7 1 &pcfg_pull_none>, + /* vi_cif_d8_m0 */ + <6 RK_PB0 1 &pcfg_pull_none>, + /* vi_cif_d9_m0 */ + <6 RK_PB1 1 &pcfg_pull_none>, + /* vi_cif_hsync_m0 */ + <6 RK_PC3 1 &pcfg_pull_none>, + /* vi_cif_vsync_m0 */ + <6 RK_PC0 1 &pcfg_pull_none>; + }; + + vi_cifm1_pins: vi-cifm1-pins { + rockchip,pins = + /* vi_cif_clkin_m1 */ + <5 RK_PC6 3 &pcfg_pull_none>, + /* vi_cif_clkout_m1 */ + <5 RK_PC5 3 &pcfg_pull_none>, + /* vi_cif_d0_m1 */ + <5 RK_PA0 3 &pcfg_pull_none>, + /* vi_cif_d10_m1 */ + <5 RK_PB6 3 &pcfg_pull_none>, + /* vi_cif_d11_m1 */ + <5 RK_PB7 3 &pcfg_pull_none>, + /* vi_cif_d12_m1 */ + <5 RK_PC0 3 &pcfg_pull_none>, + /* vi_cif_d13_m1 */ + <5 RK_PC1 3 &pcfg_pull_none>, + /* vi_cif_d14_m1 */ + <5 RK_PC2 3 &pcfg_pull_none>, + /* vi_cif_d15_m1 */ + <5 RK_PC3 3 &pcfg_pull_none>, + /* vi_cif_d1_m1 */ + <5 RK_PA1 3 &pcfg_pull_none>, + /* vi_cif_d2_m1 */ + <5 RK_PA2 3 &pcfg_pull_none>, + /* vi_cif_d3_m1 */ + <5 RK_PA7 3 &pcfg_pull_none>, + /* vi_cif_d4_m1 */ + <5 RK_PB0 3 &pcfg_pull_none>, + /* vi_cif_d5_m1 */ + <5 RK_PB1 3 &pcfg_pull_none>, + /* vi_cif_d6_m1 */ + <5 RK_PB2 3 &pcfg_pull_none>, + /* vi_cif_d7_m1 */ + <5 RK_PB3 3 &pcfg_pull_none>, + /* vi_cif_d8_m1 */ + <5 RK_PB4 3 &pcfg_pull_none>, + /* vi_cif_d9_m1 */ + <5 RK_PB5 3 &pcfg_pull_none>, + /* vi_cif_hsync_m1 */ + <5 RK_PC7 3 &pcfg_pull_none>, + /* vi_cif_vsync_m1 */ + <5 RK_PC4 3 &pcfg_pull_none>; + }; + }; + + vo_lcdc { + vo_lcdc_pins: vo-lcdc-pins { + rockchip,pins = + /* vo_lcdc_clk */ + <5 RK_PD3 1 &pcfg_pull_none>, + /* vo_lcdc_d0 */ + <5 RK_PA0 1 &pcfg_pull_none>, + /* vo_lcdc_d1 */ + <5 RK_PA1 1 &pcfg_pull_none>, + /* vo_lcdc_d2 */ + <5 RK_PA2 1 &pcfg_pull_none>, + /* vo_lcdc_d3 */ + <5 RK_PA3 1 &pcfg_pull_none>, + /* vo_lcdc_d4 */ + <5 RK_PA4 1 &pcfg_pull_none>, + /* vo_lcdc_d5 */ + <5 RK_PA5 1 &pcfg_pull_none>, + /* vo_lcdc_d6 */ + <5 RK_PA6 1 &pcfg_pull_none>, + /* vo_lcdc_d7 */ + <5 RK_PA7 1 &pcfg_pull_none>, + /* vo_lcdc_d8 */ + <5 RK_PB0 1 &pcfg_pull_none>, + /* vo_lcdc_d9 */ + <5 RK_PB1 1 &pcfg_pull_none>, + /* vo_lcdc_d10 */ + <5 RK_PB2 1 &pcfg_pull_none>, + /* vo_lcdc_d11 */ + <5 RK_PB3 1 &pcfg_pull_none>, + /* vo_lcdc_d12 */ + <5 RK_PB4 1 &pcfg_pull_none>, + /* vo_lcdc_d13 */ + <5 RK_PB5 1 &pcfg_pull_none>, + /* vo_lcdc_d14 */ + <5 RK_PB6 1 &pcfg_pull_none>, + /* vo_lcdc_d15 */ + <5 RK_PB7 1 &pcfg_pull_none>, + /* vo_lcdc_d16 */ + <5 RK_PC0 1 &pcfg_pull_none>, + /* vo_lcdc_d17 */ + <5 RK_PC1 1 &pcfg_pull_none>, + /* vo_lcdc_d18 */ + <5 RK_PC2 1 &pcfg_pull_none>, + /* vo_lcdc_d19 */ + <5 RK_PC3 1 &pcfg_pull_none>, + /* vo_lcdc_d20 */ + <5 RK_PC4 1 &pcfg_pull_none>, + /* vo_lcdc_d21 */ + <5 RK_PC5 1 &pcfg_pull_none>, + /* vo_lcdc_d22 */ + <5 RK_PC6 1 &pcfg_pull_none>, + /* vo_lcdc_d23 */ + <5 RK_PC7 1 &pcfg_pull_none>, + /* vo_lcdc_den */ + <5 RK_PD0 1 &pcfg_pull_none>, + /* vo_lcdc_hsync */ + <5 RK_PD1 1 &pcfg_pull_none>, + /* vo_lcdc_vsync */ + <5 RK_PD2 1 &pcfg_pull_none>; + }; + }; +}; + +/* + * This part is edited handly. + */ +&pinctrl { + dsmc { + dsmc_csn_idle: dsmc-csn-idle { + rockchip,pins = + /* dsmc_csn0 */ + <5 RK_PB4 RK_FUNC_GPIO &pcfg_pull_up>, + /* dsmc_csn1 */ + <5 RK_PA0 RK_FUNC_GPIO &pcfg_pull_up>, + /* dsmc_csn2 */ + <5 RK_PD1 RK_FUNC_GPIO &pcfg_pull_up>, + /* dsmc_csn3 */ + <5 RK_PD0 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + pdm { + pdmm0_clk0_idle: pdmm0-clk0-idle { + rockchip,pins = + /* pdm_clk0_m0 */ + <7 RK_PA4 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + pdmm0_clk1_idle: pdmm0-clk1-idle { + rockchip,pins = + /* pdm_clk1_m0 */ + <7 RK_PA1 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + pdmm1_clk0_idle: pdmm1-clk0-idle { + rockchip,pins = + /* pdm_clk0_m1 */ + <6 RK_PB4 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + pdmm1_clk1_idle: pdmm1-clk1-idle { + rockchip,pins = + /* pdm_clk1_m1 */ + <6 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + sdmmc0 { + sdmmc0_idle_pins: sdmmc0-idle-pins { + rockchip,pins = + <2 RK_PA0 RK_FUNC_GPIO &pcfg_pull_down>, + <2 RK_PA1 RK_FUNC_GPIO &pcfg_pull_down>, + <2 RK_PA2 RK_FUNC_GPIO &pcfg_pull_down>, + <2 RK_PA3 RK_FUNC_GPIO &pcfg_pull_down>, + <2 RK_PA4 RK_FUNC_GPIO &pcfg_pull_down>, + <2 RK_PA5 RK_FUNC_GPIO &pcfg_pull_down>; + }; + }; + + sdmmc1 { + sdmmc1_idle_pins: sdmmc1-idle-pins { + rockchip,pins = + <3 RK_PA0 RK_FUNC_GPIO &pcfg_pull_down>, + <3 RK_PA1 RK_FUNC_GPIO &pcfg_pull_down>, + <3 RK_PA2 RK_FUNC_GPIO &pcfg_pull_down>, + <3 RK_PA3 RK_FUNC_GPIO &pcfg_pull_down>, + <3 RK_PA4 RK_FUNC_GPIO &pcfg_pull_down>, + <3 RK_PA5 RK_FUNC_GPIO &pcfg_pull_down>; + }; + }; + + vo_lcdc { + bt1120_pins: bt1120-pins { + rockchip,pins = + /* vo_lcdc_clk */ + <5 RK_PD3 1 &pcfg_pull_none>, + /* vo_lcdc_d3 */ + <5 RK_PA3 1 &pcfg_pull_none>, + /* vo_lcdc_d4 */ + <5 RK_PA4 1 &pcfg_pull_none>, + /* vo_lcdc_d5 */ + <5 RK_PA5 1 &pcfg_pull_none>, + /* vo_lcdc_d6 */ + <5 RK_PA6 1 &pcfg_pull_none>, + /* vo_lcdc_d7 */ + <5 RK_PA7 1 &pcfg_pull_none>, + /* vo_lcdc_d10 */ + <5 RK_PB2 1 &pcfg_pull_none>, + /* vo_lcdc_d11 */ + <5 RK_PB3 1 &pcfg_pull_none>, + /* vo_lcdc_d12 */ + <5 RK_PB4 1 &pcfg_pull_none>, + /* vo_lcdc_d13 */ + <5 RK_PB5 1 &pcfg_pull_none>, + /* vo_lcdc_d14 */ + <5 RK_PB6 1 &pcfg_pull_none>, + /* vo_lcdc_d15 */ + <5 RK_PB7 1 &pcfg_pull_none>, + /* vo_lcdc_d19 */ + <5 RK_PC3 1 &pcfg_pull_none>, + /* vo_lcdc_d20 */ + <5 RK_PC4 1 &pcfg_pull_none>, + /* vo_lcdc_d21 */ + <5 RK_PC5 1 &pcfg_pull_none>, + /* vo_lcdc_d22 */ + <5 RK_PC6 1 &pcfg_pull_none>, + /* vo_lcdc_d23 */ + <5 RK_PC7 1 &pcfg_pull_none>; + }; + + bt656_m0_pins: bt656-m0-pins { + rockchip,pins = + /* vo_lcdc_clk */ + <5 RK_PD3 1 &pcfg_pull_none>, + /* vo_lcdc_d3 */ + <5 RK_PA3 1 &pcfg_pull_none>, + /* vo_lcdc_d4 */ + <5 RK_PA4 1 &pcfg_pull_none>, + /* vo_lcdc_d5 */ + <5 RK_PA5 1 &pcfg_pull_none>, + /* vo_lcdc_d6 */ + <5 RK_PA6 1 &pcfg_pull_none>, + /* vo_lcdc_d7 */ + <5 RK_PA7 1 &pcfg_pull_none>, + /* vo_lcdc_d10 */ + <5 RK_PB2 1 &pcfg_pull_none>, + /* vo_lcdc_d11 */ + <5 RK_PB3 1 &pcfg_pull_none>, + /* vo_lcdc_d12 */ + <5 RK_PB4 1 &pcfg_pull_none>; + }; + + bt656_m1_pins: bt656-m1-pins { + rockchip,pins = + /* vo_lcdc_clk */ + <5 RK_PD3 1 &pcfg_pull_none>, + /* vo_lcdc_d13 */ + <5 RK_PB5 1 &pcfg_pull_none>, + /* vo_lcdc_d14 */ + <5 RK_PB6 1 &pcfg_pull_none>, + /* vo_lcdc_d15 */ + <5 RK_PB7 1 &pcfg_pull_none>, + /* vo_lcdc_d19 */ + <5 RK_PC3 1 &pcfg_pull_none>, + /* vo_lcdc_d20 */ + <5 RK_PC4 1 &pcfg_pull_none>, + /* vo_lcdc_d21 */ + <5 RK_PC5 1 &pcfg_pull_none>, + /* vo_lcdc_d22 */ + <5 RK_PC6 1 &pcfg_pull_none>, + /* vo_lcdc_d23 */ + <5 RK_PC7 1 &pcfg_pull_none>; + }; + + mcu_rgb3x8_rgb2x8_m0_pins: mcu-rgb3x8-rgb2x8-m0-pins { + rockchip,pins = + /* vo_lcdc_clk */ + <5 RK_PD3 1 &pcfg_pull_none>, + /* vo_lcdc_d3 */ + <5 RK_PA3 1 &pcfg_pull_none>, + /* vo_lcdc_d4 */ + <5 RK_PA4 1 &pcfg_pull_none>, + /* vo_lcdc_d5 */ + <5 RK_PA5 1 &pcfg_pull_none>, + /* vo_lcdc_d6 */ + <5 RK_PA6 1 &pcfg_pull_none>, + /* vo_lcdc_d7 */ + <5 RK_PA7 1 &pcfg_pull_none>, + /* vo_lcdc_d10 */ + <5 RK_PB2 1 &pcfg_pull_none>, + /* vo_lcdc_d11 */ + <5 RK_PB3 1 &pcfg_pull_none>, + /* vo_lcdc_d12 */ + <5 RK_PB4 1 &pcfg_pull_none>, + /* vo_lcdc_den */ + <5 RK_PD0 1 &pcfg_pull_none>, + /* vo_lcdc_hsync */ + <5 RK_PD1 1 &pcfg_pull_none>, + /* vo_lcdc_vsync */ + <5 RK_PD2 1 &pcfg_pull_none>; + }; + + mcu_rgb3x8_rgb2x8_m1_pins: mcu-rgb3x8-rgb2x8-m1-pins { + rockchip,pins = + /* vo_lcdc_clk */ + <5 RK_PD3 1 &pcfg_pull_none>, + /* vo_lcdc_d13 */ + <5 RK_PB5 1 &pcfg_pull_none>, + /* vo_lcdc_d14 */ + <5 RK_PB6 1 &pcfg_pull_none>, + /* vo_lcdc_d15 */ + <5 RK_PB7 1 &pcfg_pull_none>, + /* vo_lcdc_d19 */ + <5 RK_PC3 1 &pcfg_pull_none>, + /* vo_lcdc_d20 */ + <5 RK_PC4 1 &pcfg_pull_none>, + /* vo_lcdc_d21 */ + <5 RK_PC5 1 &pcfg_pull_none>, + /* vo_lcdc_d22 */ + <5 RK_PC6 1 &pcfg_pull_none>, + /* vo_lcdc_d23 */ + <5 RK_PC7 1 &pcfg_pull_none>, + /* vo_lcdc_den */ + <5 RK_PD0 1 &pcfg_pull_none>, + /* vo_lcdc_hsync */ + <5 RK_PD1 1 &pcfg_pull_none>, + /* vo_lcdc_vsync */ + <5 RK_PD2 1 &pcfg_pull_none>; + }; + + mcu_rgb565_pins: mcu-rgb565-pins { + rockchip,pins = + /* vo_lcdc_clk */ + <5 RK_PD3 1 &pcfg_pull_none>, + /* vo_lcdc_d3 */ + <5 RK_PA3 1 &pcfg_pull_none>, + /* vo_lcdc_d4 */ + <5 RK_PA4 1 &pcfg_pull_none>, + /* vo_lcdc_d5 */ + <5 RK_PA5 1 &pcfg_pull_none>, + /* vo_lcdc_d6 */ + <5 RK_PA6 1 &pcfg_pull_none>, + /* vo_lcdc_d7 */ + <5 RK_PA7 1 &pcfg_pull_none>, + /* vo_lcdc_d10 */ + <5 RK_PB2 1 &pcfg_pull_none>, + /* vo_lcdc_d11 */ + <5 RK_PB3 1 &pcfg_pull_none>, + /* vo_lcdc_d12 */ + <5 RK_PB4 1 &pcfg_pull_none>, + /* vo_lcdc_d13 */ + <5 RK_PB5 1 &pcfg_pull_none>, + /* vo_lcdc_d14 */ + <5 RK_PB6 1 &pcfg_pull_none>, + /* vo_lcdc_d15 */ + <5 RK_PB7 1 &pcfg_pull_none>, + /* vo_lcdc_d19 */ + <5 RK_PC3 1 &pcfg_pull_none>, + /* vo_lcdc_d20 */ + <5 RK_PC4 1 &pcfg_pull_none>, + /* vo_lcdc_d21 */ + <5 RK_PC5 1 &pcfg_pull_none>, + /* vo_lcdc_d22 */ + <5 RK_PC6 1 &pcfg_pull_none>, + /* vo_lcdc_d23 */ + <5 RK_PC7 1 &pcfg_pull_none>, + /* vo_lcdc_den */ + <5 RK_PD0 1 &pcfg_pull_none>, + /* vo_lcdc_hsync */ + <5 RK_PD1 1 &pcfg_pull_none>, + /* vo_lcdc_vsync */ + <5 RK_PD2 1 &pcfg_pull_none>; + }; + + mcu_rgb666_pins: mcu-rgb666-pins { + rockchip,pins = + /* vo_lcdc_clk */ + <5 RK_PD3 1 &pcfg_pull_none>, + /* vo_lcdc_d2 */ + <5 RK_PA2 1 &pcfg_pull_none>, + /* vo_lcdc_d3 */ + <5 RK_PA3 1 &pcfg_pull_none>, + /* vo_lcdc_d4 */ + <5 RK_PA4 1 &pcfg_pull_none>, + /* vo_lcdc_d5 */ + <5 RK_PA5 1 &pcfg_pull_none>, + /* vo_lcdc_d6 */ + <5 RK_PA6 1 &pcfg_pull_none>, + /* vo_lcdc_d7 */ + <5 RK_PA7 1 &pcfg_pull_none>, + /* vo_lcdc_d10 */ + <5 RK_PB2 1 &pcfg_pull_none>, + /* vo_lcdc_d11 */ + <5 RK_PB3 1 &pcfg_pull_none>, + /* vo_lcdc_d12 */ + <5 RK_PB4 1 &pcfg_pull_none>, + /* vo_lcdc_d13 */ + <5 RK_PB5 1 &pcfg_pull_none>, + /* vo_lcdc_d14 */ + <5 RK_PB6 1 &pcfg_pull_none>, + /* vo_lcdc_d15 */ + <5 RK_PB7 1 &pcfg_pull_none>, + /* vo_lcdc_d18 */ + <5 RK_PC2 1 &pcfg_pull_none>, + /* vo_lcdc_d19 */ + <5 RK_PC3 1 &pcfg_pull_none>, + /* vo_lcdc_d20 */ + <5 RK_PC4 1 &pcfg_pull_none>, + /* vo_lcdc_d21 */ + <5 RK_PC5 1 &pcfg_pull_none>, + /* vo_lcdc_d22 */ + <5 RK_PC6 1 &pcfg_pull_none>, + /* vo_lcdc_d23 */ + <5 RK_PC7 1 &pcfg_pull_none>, + /* vo_lcdc_den */ + <5 RK_PD0 1 &pcfg_pull_none>, + /* vo_lcdc_hsync */ + <5 RK_PD1 1 &pcfg_pull_none>, + /* vo_lcdc_vsync */ + <5 RK_PD2 1 &pcfg_pull_none>; + }; + + mcu_rgb888_pins: mcu-rgb888-pins { + rockchip,pins = + /* vo_lcdc_clk */ + <5 RK_PD3 1 &pcfg_pull_none>, + /* vo_lcdc_d0 */ + <5 RK_PA0 1 &pcfg_pull_none>, + /* vo_lcdc_d1 */ + <5 RK_PA1 1 &pcfg_pull_none>, + /* vo_lcdc_d2 */ + <5 RK_PA2 1 &pcfg_pull_none>, + /* vo_lcdc_d3 */ + <5 RK_PA3 1 &pcfg_pull_none>, + /* vo_lcdc_d4 */ + <5 RK_PA4 1 &pcfg_pull_none>, + /* vo_lcdc_d5 */ + <5 RK_PA5 1 &pcfg_pull_none>, + /* vo_lcdc_d6 */ + <5 RK_PA6 1 &pcfg_pull_none>, + /* vo_lcdc_d7 */ + <5 RK_PA7 1 &pcfg_pull_none>, + /* vo_lcdc_d8 */ + <5 RK_PB0 1 &pcfg_pull_none>, + /* vo_lcdc_d9 */ + <5 RK_PB1 1 &pcfg_pull_none>, + /* vo_lcdc_d10 */ + <5 RK_PB2 1 &pcfg_pull_none>, + /* vo_lcdc_d11 */ + <5 RK_PB3 1 &pcfg_pull_none>, + /* vo_lcdc_d12 */ + <5 RK_PB4 1 &pcfg_pull_none>, + /* vo_lcdc_d13 */ + <5 RK_PB5 1 &pcfg_pull_none>, + /* vo_lcdc_d14 */ + <5 RK_PB6 1 &pcfg_pull_none>, + /* vo_lcdc_d15 */ + <5 RK_PB7 1 &pcfg_pull_none>, + /* vo_lcdc_d16 */ + <5 RK_PC0 1 &pcfg_pull_none>, + /* vo_lcdc_d17 */ + <5 RK_PC1 1 &pcfg_pull_none>, + /* vo_lcdc_d18 */ + <5 RK_PC2 1 &pcfg_pull_none>, + /* vo_lcdc_d19 */ + <5 RK_PC3 1 &pcfg_pull_none>, + /* vo_lcdc_d20 */ + <5 RK_PC4 1 &pcfg_pull_none>, + /* vo_lcdc_d21 */ + <5 RK_PC5 1 &pcfg_pull_none>, + /* vo_lcdc_d22 */ + <5 RK_PC6 1 &pcfg_pull_none>, + /* vo_lcdc_d23 */ + <5 RK_PC7 1 &pcfg_pull_none>, + /* vo_lcdc_den */ + <5 RK_PD0 1 &pcfg_pull_none>, + /* vo_lcdc_hsync */ + <5 RK_PD1 1 &pcfg_pull_none>, + /* vo_lcdc_vsync */ + <5 RK_PD2 1 &pcfg_pull_none>; + }; + + rgb3x8_rgb2x8_m0_pins: rgb3x8-rgb2x8-m0-pins { + rockchip,pins = + /* vo_lcdc_clk */ + <5 RK_PD3 1 &pcfg_pull_none>, + /* vo_lcdc_d3 */ + <5 RK_PA3 1 &pcfg_pull_none>, + /* vo_lcdc_d4 */ + <5 RK_PA4 1 &pcfg_pull_none>, + /* vo_lcdc_d5 */ + <5 RK_PA5 1 &pcfg_pull_none>, + /* vo_lcdc_d6 */ + <5 RK_PA6 1 &pcfg_pull_none>, + /* vo_lcdc_d7 */ + <5 RK_PA7 1 &pcfg_pull_none>, + /* vo_lcdc_d10 */ + <5 RK_PB2 1 &pcfg_pull_none>, + /* vo_lcdc_d11 */ + <5 RK_PB3 1 &pcfg_pull_none>, + /* vo_lcdc_d12 */ + <5 RK_PB4 1 &pcfg_pull_none>, + /* vo_lcdc_den */ + <5 RK_PD0 1 &pcfg_pull_none>, + /* vo_lcdc_hsync */ + <5 RK_PD1 1 &pcfg_pull_none>, + /* vo_lcdc_vsync */ + <5 RK_PD2 1 &pcfg_pull_none>; + }; + + rgb3x8_rgb2x8_m1_pins: rgb3x8-rgb2x8-m1-pins { + rockchip,pins = + /* vo_lcdc_clk */ + <5 RK_PD3 1 &pcfg_pull_none>, + /* vo_lcdc_d13 */ + <5 RK_PB5 1 &pcfg_pull_none>, + /* vo_lcdc_d14 */ + <5 RK_PB6 1 &pcfg_pull_none>, + /* vo_lcdc_d15 */ + <5 RK_PB7 1 &pcfg_pull_none>, + /* vo_lcdc_d19 */ + <5 RK_PC3 1 &pcfg_pull_none>, + /* vo_lcdc_d20 */ + <5 RK_PC4 1 &pcfg_pull_none>, + /* vo_lcdc_d21 */ + <5 RK_PC5 1 &pcfg_pull_none>, + /* vo_lcdc_d22 */ + <5 RK_PC6 1 &pcfg_pull_none>, + /* vo_lcdc_d23 */ + <5 RK_PC7 1 &pcfg_pull_none>, + /* vo_lcdc_den */ + <5 RK_PD0 1 &pcfg_pull_none>, + /* vo_lcdc_hsync */ + <5 RK_PD1 1 &pcfg_pull_none>, + /* vo_lcdc_vsync */ + <5 RK_PD2 1 &pcfg_pull_none>; + }; + + rgb565_pins: rgb565-pins { + rockchip,pins = + /* vo_lcdc_clk */ + <5 RK_PD3 1 &pcfg_pull_none>, + /* vo_lcdc_d3 */ + <5 RK_PA3 1 &pcfg_pull_none>, + /* vo_lcdc_d4 */ + <5 RK_PA4 1 &pcfg_pull_none>, + /* vo_lcdc_d5 */ + <5 RK_PA5 1 &pcfg_pull_none>, + /* vo_lcdc_d6 */ + <5 RK_PA6 1 &pcfg_pull_none>, + /* vo_lcdc_d7 */ + <5 RK_PA7 1 &pcfg_pull_none>, + /* vo_lcdc_d10 */ + <5 RK_PB2 1 &pcfg_pull_none>, + /* vo_lcdc_d11 */ + <5 RK_PB3 1 &pcfg_pull_none>, + /* vo_lcdc_d12 */ + <5 RK_PB4 1 &pcfg_pull_none>, + /* vo_lcdc_d13 */ + <5 RK_PB5 1 &pcfg_pull_none>, + /* vo_lcdc_d14 */ + <5 RK_PB6 1 &pcfg_pull_none>, + /* vo_lcdc_d15 */ + <5 RK_PB7 1 &pcfg_pull_none>, + /* vo_lcdc_d19 */ + <5 RK_PC3 1 &pcfg_pull_none>, + /* vo_lcdc_d20 */ + <5 RK_PC4 1 &pcfg_pull_none>, + /* vo_lcdc_d21 */ + <5 RK_PC5 1 &pcfg_pull_none>, + /* vo_lcdc_d22 */ + <5 RK_PC6 1 &pcfg_pull_none>, + /* vo_lcdc_d23 */ + <5 RK_PC7 1 &pcfg_pull_none>, + /* vo_lcdc_den */ + <5 RK_PD0 1 &pcfg_pull_none>, + /* vo_lcdc_hsync */ + <5 RK_PD1 1 &pcfg_pull_none>, + /* vo_lcdc_vsync */ + <5 RK_PD2 1 &pcfg_pull_none>; + }; + + rgb666_pins: rgb666-pins { + rockchip,pins = + /* vo_lcdc_clk */ + <5 RK_PD3 1 &pcfg_pull_none>, + /* vo_lcdc_d2 */ + <5 RK_PA2 1 &pcfg_pull_none>, + /* vo_lcdc_d3 */ + <5 RK_PA3 1 &pcfg_pull_none>, + /* vo_lcdc_d4 */ + <5 RK_PA4 1 &pcfg_pull_none>, + /* vo_lcdc_d5 */ + <5 RK_PA5 1 &pcfg_pull_none>, + /* vo_lcdc_d6 */ + <5 RK_PA6 1 &pcfg_pull_none>, + /* vo_lcdc_d7 */ + <5 RK_PA7 1 &pcfg_pull_none>, + /* vo_lcdc_d10 */ + <5 RK_PB2 1 &pcfg_pull_none>, + /* vo_lcdc_d11 */ + <5 RK_PB3 1 &pcfg_pull_none>, + /* vo_lcdc_d12 */ + <5 RK_PB4 1 &pcfg_pull_none>, + /* vo_lcdc_d13 */ + <5 RK_PB5 1 &pcfg_pull_none>, + /* vo_lcdc_d14 */ + <5 RK_PB6 1 &pcfg_pull_none>, + /* vo_lcdc_d15 */ + <5 RK_PB7 1 &pcfg_pull_none>, + /* vo_lcdc_d18 */ + <5 RK_PC2 1 &pcfg_pull_none>, + /* vo_lcdc_d19 */ + <5 RK_PC3 1 &pcfg_pull_none>, + /* vo_lcdc_d20 */ + <5 RK_PC4 1 &pcfg_pull_none>, + /* vo_lcdc_d21 */ + <5 RK_PC5 1 &pcfg_pull_none>, + /* vo_lcdc_d22 */ + <5 RK_PC6 1 &pcfg_pull_none>, + /* vo_lcdc_d23 */ + <5 RK_PC7 1 &pcfg_pull_none>, + /* vo_lcdc_den */ + <5 RK_PD0 1 &pcfg_pull_none>, + /* vo_lcdc_hsync */ + <5 RK_PD1 1 &pcfg_pull_none>, + /* vo_lcdc_vsync */ + <5 RK_PD2 1 &pcfg_pull_none>; + }; + + rgb888_pins: rgb888-pins { + rockchip,pins = + /* vo_lcdc_clk */ + <5 RK_PD3 1 &pcfg_pull_none>, + /* vo_lcdc_d0 */ + <5 RK_PA0 1 &pcfg_pull_none>, + /* vo_lcdc_d1 */ + <5 RK_PA1 1 &pcfg_pull_none>, + /* vo_lcdc_d2 */ + <5 RK_PA2 1 &pcfg_pull_none>, + /* vo_lcdc_d3 */ + <5 RK_PA3 1 &pcfg_pull_none>, + /* vo_lcdc_d4 */ + <5 RK_PA4 1 &pcfg_pull_none>, + /* vo_lcdc_d5 */ + <5 RK_PA5 1 &pcfg_pull_none>, + /* vo_lcdc_d6 */ + <5 RK_PA6 1 &pcfg_pull_none>, + /* vo_lcdc_d7 */ + <5 RK_PA7 1 &pcfg_pull_none>, + /* vo_lcdc_d8 */ + <5 RK_PB0 1 &pcfg_pull_none>, + /* vo_lcdc_d9 */ + <5 RK_PB1 1 &pcfg_pull_none>, + /* vo_lcdc_d10 */ + <5 RK_PB2 1 &pcfg_pull_none>, + /* vo_lcdc_d11 */ + <5 RK_PB3 1 &pcfg_pull_none>, + /* vo_lcdc_d12 */ + <5 RK_PB4 1 &pcfg_pull_none>, + /* vo_lcdc_d13 */ + <5 RK_PB5 1 &pcfg_pull_none>, + /* vo_lcdc_d14 */ + <5 RK_PB6 1 &pcfg_pull_none>, + /* vo_lcdc_d15 */ + <5 RK_PB7 1 &pcfg_pull_none>, + /* vo_lcdc_d16 */ + <5 RK_PC0 1 &pcfg_pull_none>, + /* vo_lcdc_d17 */ + <5 RK_PC1 1 &pcfg_pull_none>, + /* vo_lcdc_d18 */ + <5 RK_PC2 1 &pcfg_pull_none>, + /* vo_lcdc_d19 */ + <5 RK_PC3 1 &pcfg_pull_none>, + /* vo_lcdc_d20 */ + <5 RK_PC4 1 &pcfg_pull_none>, + /* vo_lcdc_d21 */ + <5 RK_PC5 1 &pcfg_pull_none>, + /* vo_lcdc_d22 */ + <5 RK_PC6 1 &pcfg_pull_none>, + /* vo_lcdc_d23 */ + <5 RK_PC7 1 &pcfg_pull_none>, + /* vo_lcdc_den */ + <5 RK_PD0 1 &pcfg_pull_none>, + /* vo_lcdc_hsync */ + <5 RK_PD1 1 &pcfg_pull_none>, + /* vo_lcdc_vsync */ + <5 RK_PD2 1 &pcfg_pull_none>; + }; + }; +}; diff --git a/u-boot/arch/arm/dts/rv1126b-u-boot.dtsi b/u-boot/arch/arm/dts/rv1126b-u-boot.dtsi new file mode 100644 index 00000000000..07b479dc176 --- /dev/null +++ b/u-boot/arch/arm/dts/rv1126b-u-boot.dtsi @@ -0,0 +1,173 @@ +/* + * (C) Copyright 2025 Rockchip Electronics Co., Ltd + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include + +/ { + aliases { + mmc0 = &emmc; + mmc1 = &sdmmc0; + }; + + chosen { + stdout-path = &uart0; + u-boot,spl-boot-order = &sdmmc0, &spi_nand, &spi_nor, &emmc; + }; +}; + +&gpio0 { + u-boot,dm-spl; + status = "okay"; +}; + +&gpio1 { + u-boot,dm-pre-reloc; + status = "okay"; +}; + +&gpio2 { + u-boot,dm-spl; + status = "okay"; +}; + +&gpio3 { + u-boot,dm-pre-reloc; + status = "okay"; +}; + +&gpio4 { + u-boot,dm-pre-reloc; + status = "okay"; +}; + +&grf { + u-boot,dm-spl; + status = "okay"; +}; + +&ioc_grf { + u-boot,dm-spl; + status = "okay"; +}; + +&cru { + u-boot,dm-spl; + status = "okay"; +}; + +&crypto { + u-boot,dm-spl; + status = "okay"; +}; + +&psci { + u-boot,dm-pre-reloc; + status = "okay"; +}; + +&uart0 { + u-boot,dm-spl; + status = "okay"; +}; + +&hw_decompress { + u-boot,dm-spl; + status = "okay"; +}; + +&rng { + u-boot,dm-pre-reloc; + status = "okay"; +}; + +&fspi0 { + u-boot,dm-spl; + status = "okay"; + + #address-cells = <1>; + #size-cells = <0>; + spi_nand: flash@0 { + u-boot,dm-spl; + compatible = "spi-nand"; + reg = <0>; + spi-tx-bus-width = <1>; + spi-rx-bus-width = <4>; + spi-max-frequency = <80000000>; + }; + + spi_nor: flash@1 { + u-boot,dm-spl; + compatible = "jedec,spi-nor"; + label = "sfc_nor"; + reg = <0>; + spi-tx-bus-width = <1>; + spi-rx-bus-width = <4>; + spi-max-frequency = <80000000>; + }; +}; + +&saradc0 { + u-boot,dm-pre-reloc; + status = "okay"; +}; + +&sdmmc0 { + bus-width = <4>; + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc0_bus4_pins &sdmmc0_cmd_pins &sdmmc0_clk_pins &sdmmc0_detn_pins>; + u-boot,dm-spl; + status = "okay"; +}; + +&emmc { + bus-width = <8>; + mmc-hs200-1_8v; + u-boot,dm-spl; + status = "okay"; +}; + +&sdmmc0_pins { + u-boot,dm-spl; +}; + +&sdmmc0_bus4_pins { + u-boot,dm-spl; +}; + +&sdmmc0_cmd_pins { + u-boot,dm-spl; +}; + +&sdmmc0_clk_pins { + u-boot,dm-spl; +}; + +&sdmmc0_detn_pins { + u-boot,dm-spl; +}; + +&pinctrl { + u-boot,dm-spl; + status = "okay"; +}; + +&pcfg_pull_up { + u-boot,dm-spl; +}; + +&pcfg_pull_none { + u-boot,dm-spl; +}; + +&usb2phy { + u-boot,dm-pre-reloc; + status = "okay"; +}; + +&usb2phy_otg { + u-boot,dm-pre-reloc; + status = "okay"; +}; diff --git a/u-boot/arch/arm/dts/rv1126b.dtsi b/u-boot/arch/arm/dts/rv1126b.dtsi new file mode 100644 index 00000000000..1da7346ccc8 --- /dev/null +++ b/u-boot/arch/arm/dts/rv1126b.dtsi @@ -0,0 +1,3313 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2024 Rockchip Electronics Co., Ltd. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/ { + compatible = "rockchip,rv1126b"; + + interrupt-parent = <&gic>; + #address-cells = <1>; + #size-cells = <1>; + + aliases { + csi2dphy0 = &csi2_dphy0; + csi2dphy1 = &csi2_dphy1; + csi2dphy2 = &csi2_dphy2; + csi2dphy3 = &csi2_dphy3; + csi2dphy4 = &csi2_dphy4; + csi2dphy5 = &csi2_dphy5; + ethernet0 = &gmac; + gpio0 = &gpio0; + gpio1 = &gpio1; + gpio2 = &gpio2; + gpio3 = &gpio3; + gpio4 = &gpio4; + gpio5 = &gpio5; + gpio6 = &gpio6; + gpio7 = &gpio7; + i2c0 = &i2c0; + i2c1 = &i2c1; + i2c2 = &i2c2; + i2c3 = &i2c3; + i2c4 = &i2c4; + i2c5 = &i2c5; + mmc0 = &emmc; + mmc1 = &sdmmc0; + mmc2 = &sdmmc1; + rkcif_mipi_lvds0= &rkcif_mipi_lvds; + rkcif_mipi_lvds1= &rkcif_mipi_lvds1; + rkcif_mipi_lvds2= &rkcif_mipi_lvds2; + rkcif_mipi_lvds3= &rkcif_mipi_lvds3; + serial0 = &uart0; + serial1 = &uart1; + serial2 = &uart2; + serial3 = &uart3; + serial4 = &uart4; + serial5 = &uart5; + serial6 = &uart6; + serial7 = &uart7; + spi0 = &spi0; + spi1 = &spi1; + spi2 = &fspi0; + spi3 = &fspi1; + }; + + clocks { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + mclkin_sai0: mclkin-sai0 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <0>; + clock-output-names = "mclk_sai0_from_io"; + status = "disabled"; + }; + + mclkin_sai1: mclkin-sai1 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <0>; + clock-output-names = "mclk_sai1_from_io"; + status = "disabled"; + }; + + mclkin_sai2: mclkin-sai2 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <0>; + clock-output-names = "mclk_sai2_from_io"; + status = "disabled"; + }; + + sclkin_sai0: sclkin-sai0 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <0>; + clock-output-names = "sclk_sai0_from_io"; + status = "disabled"; + }; + + sclkin_sai1: sclkin-sai1 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <0>; + clock-output-names = "sclk_sai1_from_io"; + status = "disabled"; + }; + + sclkin_sai2: sclkin-sai2 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <0>; + clock-output-names = "sclk_sai2_from_io"; + status = "disabled"; + }; + + xin32k: xin32k { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <32768>; + clock-output-names = "xin32k"; + }; + + xin24m: xin24m { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <24000000>; + clock-output-names = "xin24m"; + }; + + clk_rcosc: clk_rcosc { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <96000000>; + clock-output-names = "clk_rcosc"; + }; + + mclkout_sai0: mclkout-sai0@20100048 { + compatible = "rockchip,clk-out"; + reg = <0x20100048 0x4>; + clocks = <&cru MCLK_SAI0_OUT2IO>; + #clock-cells = <0>; + clock-output-names = "mclk_sai0_to_io"; + rockchip,bit-shift = <0>; + rockchip,bit-set-to-disable; + status = "disabled"; + }; + + mclkout_sai1: mclkout-sai1@20100048 { + compatible = "rockchip,clk-out"; + reg = <0x20100048 0x4>; + clocks = <&cru MCLK_SAI1_OUT2IO>; + #clock-cells = <0>; + clock-output-names = "mclk_sai1_to_io"; + rockchip,bit-shift = <1>; + rockchip,bit-set-to-disable; + status = "disabled"; + }; + + mclkout_sai2: mclkout-sai2@20100048 { + compatible = "rockchip,clk-out"; + reg = <0x20100048 0x4>; + clocks = <&cru MCLK_SAI2_OUT2IO>; + #clock-cells = <0>; + clock-output-names = "mclk_sai2_to_io"; + rockchip,bit-shift = <2>; + rockchip,bit-set-to-disable; + status = "disabled"; + }; + + pvtpll_core: pvtpll-core@20480000 { + compatible = "rockchip,rv1126b-core-pvtpll", "syscon"; + reg = <0x20480000 0x100>; + clocks = <&cru ARMCLK>; + #clock-cells = <0>; + clock-output-names = "clk_core_pvtpll"; + assigned-clocks = <&pvtpll_core>; + assigned-clock-rates = <1200000000>; + }; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu0: cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + reg = <0x0>; + enable-method = "psci"; + clocks = <&cru ARMCLK>; + operating-points-v2 = <&cpu_opp_table>; + }; + cpu1: cpu@1 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + reg = <0x1>; + enable-method = "psci"; + clocks = <&cru ARMCLK>; + operating-points-v2 = <&cpu_opp_table>; + }; + cpu2: cpu@2 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + reg = <0x2>; + enable-method = "psci"; + clocks = <&cru ARMCLK>; + operating-points-v2 = <&cpu_opp_table>; + }; + cpu3: cpu@3 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + reg = <0x3>; + enable-method = "psci"; + clocks = <&cru ARMCLK>; + operating-points-v2 = <&cpu_opp_table>; + }; + }; + + cpu_opp_table: cpu0-opp-table { + compatible = "operating-points-v2"; + opp-shared; + + nvmem-cells = <&cpu_leakage>; + nvmem-cell-names = "leakage"; + + opp-594000000 { + opp-hz = /bits/ 64 <594000000>; + opp-microvolt = <850000 850000 1100000>; + clock-latency-ns = <40000>; + opp-suspend; + }; + + opp-816000000 { + opp-hz = /bits/ 64 <816000000>; + opp-microvolt = <850000 850000 1100000>; + clock-latency-ns = <40000>; + }; + opp-1008000000 { + opp-hz = /bits/ 64 <1008000000>; + opp-microvolt = <850000 850000 1100000>; + clock-latency-ns = <40000>; + }; + opp-1200000000 { + opp-hz = /bits/ 64 <1200000000>; + opp-microvolt = <862500 862500 1100000>; + clock-latency-ns = <40000>; + }; + opp-1296000000 { + opp-hz = /bits/ 64 <1296000000>; + opp-microvolt = <912500 912500 1100000>; + clock-latency-ns = <40000>; + }; + opp-1416000000 { + opp-hz = /bits/ 64 <1416000000>; + opp-microvolt = <937500 937500 1100000>; + clock-latency-ns = <40000>; + }; + opp-1512000000 { + opp-hz = /bits/ 64 <1512000000>; + opp-microvolt = <962500 962500 1100000>; + clock-latency-ns = <40000>; + }; + opp-1608000000 { + opp-hz = /bits/ 64 <1608000000>; + opp-microvolt = <1012500 1012500 1100000>; + clock-latency-ns = <40000>; + }; + }; + + cpuinfo { + compatible = "rockchip,cpuinfo"; + nvmem-cells = <&otp_id>, <&cpu_version>, <&cpu_code>; + nvmem-cell-names = "id", "cpu-version", "cpu-code"; + }; + + /* dphy0 full mode */ + csi2_dphy0: csi2-dphy0 { + compatible = "rockchip,rv1126b-csi2-dphy"; + rockchip,hw = <&csi2_dphy0_hw>, <&csi2_dphy1_hw>; + status = "disabled"; + }; + + /* dphy0 split mode 01 */ + csi2_dphy1: csi2-dphy1 { + compatible = "rockchip,rv1126b-csi2-dphy"; + rockchip,hw = <&csi2_dphy0_hw>, <&csi2_dphy1_hw>; + status = "disabled"; + }; + + /* dphy0 split mode 23 */ + csi2_dphy2: csi2-dphy2 { + compatible = "rockchip,rv1126b-csi2-dphy"; + rockchip,hw = <&csi2_dphy0_hw>, <&csi2_dphy1_hw>; + status = "disabled"; + }; + + /* dphy1 full mode */ + csi2_dphy3: csi2-dphy3 { + compatible = "rockchip,rv1126b-csi2-dphy"; + rockchip,hw = <&csi2_dphy0_hw>, <&csi2_dphy1_hw>; + status = "disabled"; + }; + + /* dphy1 split mode 01 */ + csi2_dphy4: csi2-dphy4 { + compatible = "rockchip,rv1126b-csi2-dphy"; + rockchip,hw = <&csi2_dphy0_hw>, <&csi2_dphy1_hw>; + status = "disabled"; + }; + + /* dphy1 split mode 23 */ + csi2_dphy5: csi2-dphy5 { + compatible = "rockchip,rv1126b-csi2-dphy"; + rockchip,hw = <&csi2_dphy0_hw>, <&csi2_dphy1_hw>; + status = "disabled"; + }; + + display_subsystem: display-subsystem { + compatible = "rockchip,display-subsystem"; + ports = <&vop_out>; + status = "disabled"; + logo-memory-region = <&drm_logo>; + + route { + route_dsi: route-dsi { + status = "disabled"; + logo,uboot = "logo.bmp"; + logo,kernel = "logo_kernel.bmp"; + logo,mode = "center"; + charge_logo,mode = "center"; + connect = <&vop_out_dsi>; + }; + + route_rgb: route-rgb { + status = "disabled"; + logo,uboot = "logo.bmp"; + logo,kernel = "logo_kernel.bmp"; + logo,mode = "center"; + charge_logo,mode = "center"; + connect = <&vop_out_rgb>; + }; + }; + }; + + fiq_debugger: fiq-debugger { + compatible = "rockchip,fiq-debugger"; + rockchip,serial-id = <0>; + rockchip,wake-irq = <0>; + rockchip,irq-mode-enable = <0>; + rockchip,baudrate = <1500000>; /* Only 115200 and 1500000 */ + interrupts = ; + status = "disabled"; + }; + + mipi0_csi2: mipi0-csi2 { + compatible = "rockchip,rv1126b-mipi-csi2"; + rockchip,hw = <&mipi0_csi2_hw>, <&mipi1_csi2_hw>, + <&mipi2_csi2_hw>, <&mipi3_csi2_hw>; + status = "disabled"; + }; + + mipi1_csi2: mipi1-csi2 { + compatible = "rockchip,rv1126b-mipi-csi2"; + rockchip,hw = <&mipi0_csi2_hw>, <&mipi1_csi2_hw>, + <&mipi2_csi2_hw>, <&mipi3_csi2_hw>; + status = "disabled"; + }; + + mipi2_csi2: mipi2-csi2 { + compatible = "rockchip,rv1126b-mipi-csi2"; + rockchip,hw = <&mipi0_csi2_hw>, <&mipi1_csi2_hw>, + <&mipi2_csi2_hw>, <&mipi3_csi2_hw>; + status = "disabled"; + }; + + mipi3_csi2: mipi3-csi2 { + compatible = "rockchip,rv1126b-mipi-csi2"; + rockchip,hw = <&mipi0_csi2_hw>, <&mipi1_csi2_hw>, + <&mipi2_csi2_hw>, <&mipi3_csi2_hw>; + status = "disabled"; + }; + + mpp_srv: mpp-srv { + compatible = "rockchip,mpp-service"; + rockchip,taskqueue-count = <3>; + rockchip,resetgroup-count = <3>; + status = "disabled"; + }; + + mpp_vcodec: mpp-vcodec { + compatible = "rockchip,vcodec"; + status = "disabled"; + }; + + pmu_a53: pmu-a53 { + compatible = "arm,cortex-a53-pmu"; + interrupts = , + , + , + ; + interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>; + }; + + psci: psci { + compatible = "arm,psci-1.0"; + method = "smc"; + }; + + reserved-memory { + #address-cells = <1>; + #size-cells = <1>; + ranges; + + drm_logo: drm-logo@0 { + compatible = "rockchip,drm-logo"; + reg = <0x0 0x0>; + }; + }; + + rkaiisp_vir0: rkaiisp-vir0 { + compatible = "rockchip,rkaiisp-vir"; + rockchip,hw = <&rkaiisp>; + status = "disabled"; + }; + + rkaiisp_vir1: rkaiisp-vir1 { + compatible = "rockchip,rkaiisp-vir"; + rockchip,hw = <&rkaiisp>; + status = "disabled"; + }; + + rkaiisp_vir2: rkaiisp-vir2 { + compatible = "rockchip,rkaiisp-vir"; + rockchip,hw = <&rkaiisp>; + status = "disabled"; + }; + + rkaiisp_vir3: rkaiisp-vir3 { + compatible = "rockchip,rkaiisp-vir"; + rockchip,hw = <&rkaiisp>; + status = "disabled"; + }; + + rkcif_mipi_lvds: rkcif-mipi-lvds { + compatible = "rockchip,rkcif-mipi-lvds"; + rockchip,hw = <&rkcif>; + status = "disabled"; + }; + + rkcif_mipi_lvds_sditf: rkcif-mipi-lvds-sditf { + compatible = "rockchip,rkcif-sditf"; + rockchip,cif = <&rkcif_mipi_lvds>; + status = "disabled"; + }; + + rkcif_mipi_lvds_sditf_vir1: rkcif-mipi-lvds-sditf-vir1 { + compatible = "rockchip,rkcif-sditf"; + rockchip,cif = <&rkcif_mipi_lvds>; + status = "disabled"; + }; + + rkcif_mipi_lvds_sditf_vir2: rkcif-mipi-lvds-sditf-vir2 { + compatible = "rockchip,rkcif-sditf"; + rockchip,cif = <&rkcif_mipi_lvds>; + status = "disabled"; + }; + + rkcif_mipi_lvds_sditf_vir3: rkcif-mipi-lvds-sditf-vir3 { + compatible = "rockchip,rkcif-sditf"; + rockchip,cif = <&rkcif_mipi_lvds>; + status = "disabled"; + }; + + rkcif_mipi_lvds1: rkcif-mipi-lvds1 { + compatible = "rockchip,rkcif-mipi-lvds"; + rockchip,hw = <&rkcif>; + status = "disabled"; + }; + + rkcif_mipi_lvds1_sditf: rkcif-mipi-lvds1-sditf { + compatible = "rockchip,rkcif-sditf"; + rockchip,cif = <&rkcif_mipi_lvds1>; + status = "disabled"; + }; + + rkcif_mipi_lvds1_sditf_vir1: rkcif-mipi-lvds1-sditf-vir1 { + compatible = "rockchip,rkcif-sditf"; + rockchip,cif = <&rkcif_mipi_lvds1>; + status = "disabled"; + }; + + rkcif_mipi_lvds1_sditf_vir2: rkcif-mipi-lvds1-sditf-vir2 { + compatible = "rockchip,rkcif-sditf"; + rockchip,cif = <&rkcif_mipi_lvds1>; + status = "disabled"; + }; + + rkcif_mipi_lvds1_sditf_vir3: rkcif-mipi-lvds1-sditf-vir3 { + compatible = "rockchip,rkcif-sditf"; + rockchip,cif = <&rkcif_mipi_lvds1>; + status = "disabled"; + }; + + rkcif_mipi_lvds2: rkcif-mipi-lvds2 { + compatible = "rockchip,rkcif-mipi-lvds"; + rockchip,hw = <&rkcif>; + status = "disabled"; + }; + + rkcif_mipi_lvds2_sditf: rkcif-mipi-lvds2-sditf { + compatible = "rockchip,rkcif-sditf"; + rockchip,cif = <&rkcif_mipi_lvds2>; + status = "disabled"; + }; + + rkcif_mipi_lvds2_sditf_vir1: rkcif-mipi-lvds2-sditf-vir1 { + compatible = "rockchip,rkcif-sditf"; + rockchip,cif = <&rkcif_mipi_lvds2>; + status = "disabled"; + }; + + rkcif_mipi_lvds2_sditf_vir2: rkcif-mipi-lvds2-sditf-vir2 { + compatible = "rockchip,rkcif-sditf"; + rockchip,cif = <&rkcif_mipi_lvds2>; + status = "disabled"; + }; + + rkcif_mipi_lvds2_sditf_vir3: rkcif-mipi-lvds2-sditf-vir3 { + compatible = "rockchip,rkcif-sditf"; + rockchip,cif = <&rkcif_mipi_lvds2>; + status = "disabled"; + }; + + rkcif_mipi_lvds3: rkcif-mipi-lvds3 { + compatible = "rockchip,rkcif-mipi-lvds"; + rockchip,hw = <&rkcif>; + status = "disabled"; + }; + + rkcif_mipi_lvds3_sditf: rkcif-mipi-lvds3-sditf { + compatible = "rockchip,rkcif-sditf"; + rockchip,cif = <&rkcif_mipi_lvds3>; + status = "disabled"; + }; + + rkcif_mipi_lvds3_sditf_vir1: rkcif-mipi-lvds3-sditf-vir1 { + compatible = "rockchip,rkcif-sditf"; + rockchip,cif = <&rkcif_mipi_lvds3>; + status = "disabled"; + }; + + rkcif_mipi_lvds3_sditf_vir2: rkcif-mipi-lvds3-sditf-vir2 { + compatible = "rockchip,rkcif-sditf"; + rockchip,cif = <&rkcif_mipi_lvds3>; + status = "disabled"; + }; + + rkcif_mipi_lvds3_sditf_vir3: rkcif-mipi-lvds3-sditf-vir3 { + compatible = "rockchip,rkcif-sditf"; + rockchip,cif = <&rkcif_mipi_lvds3>; + status = "disabled"; + }; + + rkdvbm: rkdvbm { + compatible = "rockchip,rk-dvbm"; + status = "disabled"; + }; + + rkisp_vir0: rkisp-vir0 { + compatible = "rockchip,rkisp-vir"; + rockchip,hw = <&rkisp>; + dvbm = <&rkdvbm>; + status = "disabled"; + }; + + rkisp_vir1: rkisp-vir1 { + compatible = "rockchip,rkisp-vir"; + rockchip,hw = <&rkisp>; + dvbm = <&rkdvbm>; + status = "disabled"; + }; + + rkisp_vir2: rkisp-vir2 { + compatible = "rockchip,rkisp-vir"; + rockchip,hw = <&rkisp>; + dvbm = <&rkdvbm>; + status = "disabled"; + }; + + rkisp_vir3: rkisp-vir3 { + compatible = "rockchip,rkisp-vir"; + rockchip,hw = <&rkisp>; + dvbm = <&rkdvbm>; + status = "disabled"; + }; + + rkisp_vir0_sditf: rkisp-vir0-sditf { + compatible = "rockchip,rkisp-sditf"; + rockchip,isp = <&rkisp_vir0>; + status = "disabled"; + + port { + isp_sditf0: endpoint { + remote-endpoint = <&vpss0_in>; + }; + }; + }; + + rkisp_vir1_sditf: rkisp-vir1-sditf { + compatible = "rockchip,rkisp-sditf"; + rockchip,isp = <&rkisp_vir1>; + status = "disabled"; + + port { + isp_sditf1: endpoint { + remote-endpoint = <&vpss1_in>; + }; + }; + }; + + rkisp_vir2_sditf: rkisp-vir2-sditf { + compatible = "rockchip,rkisp-sditf"; + rockchip,isp = <&rkisp_vir2>; + status = "disabled"; + + port { + isp_sditf2: endpoint { + remote-endpoint = <&vpss2_in>; + }; + }; + }; + + rkisp_vir3_sditf: rkisp-vir3-sditf { + compatible = "rockchip,rkisp-sditf"; + rockchip,isp = <&rkisp_vir3>; + status = "disabled"; + + port { + isp_sditf3: endpoint { + remote-endpoint = <&vpss3_in>; + }; + }; + }; + + rkvpss_vir0: rkvpss-vir0 { + compatible = "rockchip,rkvpss-vir"; + rockchip,hw = <&rkvpss>; + status = "disabled"; + + port { + vpss0_in: endpoint { + remote-endpoint = <&isp_sditf0>; + }; + }; + }; + + rkvpss_vir1: rkvpss-vir1 { + compatible = "rockchip,rkvpss-vir"; + rockchip,hw = <&rkvpss>; + status = "disabled"; + + port { + vpss1_in: endpoint { + remote-endpoint = <&isp_sditf1>; + }; + }; + }; + + rkvpss_vir2: rkvpss-vir2 { + compatible = "rockchip,rkvpss-vir"; + rockchip,hw = <&rkvpss>; + status = "disabled"; + + port { + vpss2_in: endpoint { + remote-endpoint = <&isp_sditf2>; + }; + }; + }; + + rkvpss_vir3: rkvpss-vir3 { + compatible = "rockchip,rkvpss-vir"; + rockchip,hw = <&rkvpss>; + status = "disabled"; + + port { + vpss3_in: endpoint { + remote-endpoint = <&isp_sditf3>; + }; + }; + }; + + rockchip_system_monitor: rockchip-system-monitor { + compatible = "rockchip,system-monitor"; + }; + + thermal_zones: thermal-zones { + cpu_thermal: cpu-thermal { + polling-delay-passive = <20>; /* milliseconds */ + polling-delay = <1000>; /* milliseconds */ + thermal-sensors = <&tsadc 0>; + trips { + soc_crit: soc-crit { + /* millicelsius */ + temperature = <115000>; + /* millicelsius */ + hysteresis = <2000>; + type = "critical"; + }; + }; + }; + npu_thermal: npu-thermal { + polling-delay-passive = <20>; /* milliseconds */ + polling-delay = <1000>; /* milliseconds */ + thermal-sensors = <&tsadc 1>; + trips { + bigcore_crit: bigcore-crit { + /* millicelsius */ + temperature = <115000>; + /* millicelsius */ + hysteresis = <2000>; + type = "critical"; + }; + }; + }; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupts = , + , + , + ; + }; + + cru: clock-controller@20000000 { + compatible = "rockchip,rv1126b-cru"; + reg = <0x20000000 0xc0000>; + #clock-cells = <1>; + #reset-cells = <1>; + + assigned-clocks = + <&cru PLL_GPLL>, <&cru PLL_CPLL>, + <&cru PLL_AUPLL>, <&cru CLK_AUDIO_FRAC0_SRC>, + <&cru CLK_AUDIO_FRAC1_SRC>, <&cru CLK_UART_FRAC0_SRC>, + <&cru CLK_UART_FRAC1_SRC>, <&cru CLK_CM_FRAC0_SRC>, + <&cru CLK_CM_FRAC1_SRC>, <&cru CLK_CM_FRAC2_SRC>, + <&cru CLK_UART_FRAC0>, <&cru CLK_UART_FRAC1>, + <&cru CLK_CM_FRAC0>, <&cru CLK_CM_FRAC1>, + <&cru CLK_CM_FRAC2>, <&cru CLK_AUDIO_FRAC0>, + <&cru CLK_AUDIO_FRAC1>; + assigned-clock-rates = + <1188000000>, <1000000000>, + <786432000>, <786432000>, + <786432000>, <1188000000>, + <1188000000>, <1188000000>, + <1188000000>, <786432000>, + <96000000>, <128000000>, + <18432000>, <500000000>, + <32768000>, <45158400>, + <49152000>; + }; + + grf: syscon@20100000 { + compatible = "rockchip,rv1126b-grf", "syscon", "simple-mfd"; + reg = <0x20100000 0x91000>; + + reboot_mode: reboot-mode { + compatible = "syscon-reboot-mode"; + offset = <0x30200>; + mode-bootloader = ; + mode-charge = ; + mode-fastboot = ; + mode-loader = ; + mode-normal = ; + mode-recovery = ; + mode-ums = ; + mode-panic = ; + mode-watchdog = ; + }; + }; + + ioc_grf: syscon@201a0000 { + compatible = "rockchip,rv1126b-ioc-grf", "syscon", "simple-mfd"; + reg = <0x201a0000 0x50000>; + + rgb: rgb { + compatible = "rockchip,rv1126b-rgb"; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + rgb_in_vop: endpoint@0 { + reg = <0>; + remote-endpoint = <&vop_out_rgb>; + }; + }; + + }; + }; + }; + + qos_cpu: qos@20310000 { + compatible = "syscon"; + reg = <0x20310000 0x20>; + }; + + shaping_cpu: shaping@20310088 { + compatible = "syscon"; + reg = <0x20310088 0x4>; + }; + + qos_emmc: qos@20320000 { + compatible = "syscon"; + reg = <0x20320000 0x20>; + }; + + shaping_emmc: shaping@20320088 { + compatible = "syscon"; + reg = <0x20320088 0x4>; + }; + + qos_fspi0: qos@20320100 { + compatible = "syscon"; + reg = <0x20320100 0x20>; + }; + + shaping_fspi0: shaping@20320188 { + compatible = "syscon"; + reg = <0x20320188 0x4>; + }; + + qos_usb2host: qos@20320200 { + compatible = "syscon"; + reg = <0x20320200 0x20>; + }; + + shaping_usb2host: shaping@20320288 { + compatible = "syscon"; + reg = <0x20320288 0x4>; + }; + + qos_usb3otg: qos@20320300 { + compatible = "syscon"; + reg = <0x20320300 0x20>; + }; + + shaping_usb3otg: shaping@20320388 { + compatible = "syscon"; + reg = <0x20320388 0x4>; + }; + + qos_gmac: qos@20330000 { + compatible = "syscon"; + reg = <0x20330000 0x20>; + }; + + shaping_gmac: shaping@20330088 { + compatible = "syscon"; + reg = <0x20330088 0x4>; + }; + + qos_isp: qos@20330100 { + compatible = "syscon"; + reg = <0x20330100 0x20>; + }; + + shaping_isp: shaping@20330188 { + compatible = "syscon"; + reg = <0x20330188 0x4>; + }; + + qos_rkcan0: qos@20330200 { + compatible = "syscon"; + reg = <0x20330200 0x20>; + }; + + shaping_rkcan0: shaping@20330288 { + compatible = "syscon"; + reg = <0x20330288 0x4>; + }; + + qos_rkcan1: qos@20330300 { + compatible = "syscon"; + reg = <0x20330300 0x20>; + }; + + shaping_rkcan1: shaping@20330388 { + compatible = "syscon"; + reg = <0x20330388 0x4>; + }; + + qos_sdmmc0: qos@20330400 { + compatible = "syscon"; + reg = <0x20330400 0x20>; + }; + + shaping_sdmmc0: shaping@20330488 { + compatible = "syscon"; + reg = <0x20330488 0x4>; + }; + + qos_vicap: qos@20330500 { + compatible = "syscon"; + reg = <0x20330500 0x20>; + }; + + shaping_vicap: shaping@20330588 { + compatible = "syscon"; + reg = <0x20330588 0x4>; + }; + + qos_vpsl: qos@20330600 { + compatible = "syscon"; + reg = <0x20330600 0x20>; + }; + + shaping_vpsl: shaping@20330688 { + compatible = "syscon"; + reg = <0x20330688 0x4>; + }; + + qos_vpss: qos@20330700 { + compatible = "syscon"; + reg = <0x20330700 0x20>; + }; + + shaping_vpss: shaping@20330788 { + compatible = "syscon"; + reg = <0x20330788 0x4>; + }; + + qos_saradc1: qos@20330800 { + compatible = "syscon"; + reg = <0x20330800 0x20>; + }; + + shaping_saradc1: shaping@20330888 { + compatible = "syscon"; + reg = <0x20330888 0x4>; + }; + + qos_saradc2: qos@20330900 { + compatible = "syscon"; + reg = <0x20330900 0x20>; + }; + + shaping_saradc2: shaping@20330988 { + compatible = "syscon"; + reg = <0x20330988 0x4>; + }; + + qos_npu: qos@20340000 { + compatible = "syscon"; + reg = <0x20340000 0x20>; + }; + + shaping_npu: shaping@20340088 { + compatible = "syscon"; + reg = <0x20340088 0x4>; + }; + + qos_rkvenc: qos@20350000 { + compatible = "syscon"; + reg = <0x20350000 0x20>; + }; + + shaping_rkvenc: shaping@20350088 { + compatible = "syscon"; + reg = <0x20350088 0x4>; + }; + + qos_saradc0: qos@20350100 { + compatible = "syscon"; + reg = <0x20350100 0x20>; + }; + + shaping_saradc0: shaping@20350188 { + compatible = "syscon"; + reg = <0x20350188 0x4>; + }; + + qos_sdmmc1: qos@20350200 { + compatible = "syscon"; + reg = <0x20350200 0x20>; + }; + + shaping_sdmmc1: shaping@20350288 { + compatible = "syscon"; + reg = <0x20350288 0x4>; + }; + + qos_lpmcu: qos@20360000 { + compatible = "syscon"; + reg = <0x20360000 0x20>; + }; + + shaping_lpmcu: shaping@20360088 { + compatible = "syscon"; + reg = <0x20360088 0x4>; + }; + + qos_mcu: qos@20370100 { + compatible = "syscon"; + reg = <0x20370100 0x20>; + }; + + shaping_mcu: shaping@20370188 { + compatible = "syscon"; + reg = <0x20370188 0x4>; + }; + + qos_rga: qos@20370200 { + compatible = "syscon"; + reg = <0x20370200 0x20>; + }; + + shaping_rga: shaping@20370288 { + compatible = "syscon"; + reg = <0x20370288 0x4>; + }; + + qos_rkce: qos@20370400 { + compatible = "syscon"; + reg = <0x20370400 0x20>; + }; + + shaping_rkce: shaping@20370488 { + compatible = "syscon"; + reg = <0x20370488 0x4>; + }; + + qos_rkdma: qos@20370500 { + compatible = "syscon"; + reg = <0x20370500 0x20>; + }; + + shaping_rkdma: shaping@20370588 { + compatible = "syscon"; + reg = <0x20370588 0x4>; + }; + + qos_decom: qos@20380000 { + compatible = "syscon"; + reg = <0x20380000 0x20>; + }; + + shaping_decom: shaping@20380088 { + compatible = "syscon"; + reg = <0x20380088 0x4>; + }; + + qos_ooc: qos@20380100 { + compatible = "syscon"; + reg = <0x20380100 0x20>; + }; + + shaping_ooc: shaping@20380188 { + compatible = "syscon"; + reg = <0x20380188 0x4>; + }; + + qos_rkjpeg: qos@20380200 { + compatible = "syscon"; + reg = <0x20380200 0x20>; + }; + + shaping_rkjpeg: shaping@20380288 { + compatible = "syscon"; + reg = <0x20380288 0x4>; + }; + + qos_rkvdec: qos@20380300 { + compatible = "syscon"; + reg = <0x20380300 0x20>; + }; + + shaping_rkvdec: shaping@20380388 { + compatible = "syscon"; + reg = <0x20380388 0x4>; + }; + + qos_vop: qos@20380400 { + compatible = "syscon"; + reg = <0x20380400 0x20>; + }; + + shaping_vop: shaping@20380488 { + compatible = "syscon"; + reg = <0x20380488 0x4>; + }; + + qos_avsp_ro: qos@20390000 { + compatible = "syscon"; + reg = <0x20390000 0x20>; + }; + + shaping_avsp_ro: shaping@20390088 { + compatible = "syscon"; + reg = <0x20390088 0x4>; + }; + + qos_avsp_wo: qos@20390100 { + compatible = "syscon"; + reg = <0x20390100 0x20>; + }; + + shaping_avsp_wo: shaping@20390188 { + compatible = "syscon"; + reg = <0x20390188 0x4>; + }; + + qos_fec_ro: qos@20390200 { + compatible = "syscon"; + reg = <0x20390200 0x20>; + }; + + shaping_fec_ro: shaping@20390288 { + compatible = "syscon"; + reg = <0x20390288 0x4>; + }; + + qos_fec_wo: qos@20390300 { + compatible = "syscon"; + reg = <0x20390300 0x20>; + }; + + shaping_fec_wo: shaping@20390388 { + compatible = "syscon"; + reg = <0x20390388 0x4>; + }; + + qos_aad: qos@203a0000 { + compatible = "syscon"; + reg = <0x203a0000 0x20>; + }; + + shaping_aad: shaping@203a0088 { + compatible = "syscon"; + reg = <0x203a0088 0x4>; + }; + + qos_afe: qos@203a0100 { + compatible = "syscon"; + reg = <0x203a0100 0x20>; + }; + + shaping_afe: shaping@203a0188 { + compatible = "syscon"; + reg = <0x203a0188 0x4>; + }; + + qos_atdd: qos@203a0200 { + compatible = "syscon"; + reg = <0x203a0200 0x20>; + }; + + shaping_atdd: shaping@203a0288 { + compatible = "syscon"; + reg = <0x203a0288 0x4>; + }; + + qos_fspi1: qos@203a0300 { + compatible = "syscon"; + reg = <0x203a0300 0x20>; + }; + + shaping_fspi1: shaping@203a0388 { + compatible = "syscon"; + reg = <0x203a0388 0x4>; + }; + + qos_lpdma: qos@203a0400 { + compatible = "syscon"; + reg = <0x203a0400 0x20>; + }; + + shaping_lpdma: shaping@203a0488 { + compatible = "syscon"; + reg = <0x203a0488 0x4>; + }; + + qos_spi2ahb: qos@203a0500 { + compatible = "syscon"; + reg = <0x203a0500 0x20>; + }; + + shaping_spi2ahb: shaping@203a0588 { + compatible = "syscon"; + reg = <0x203a0588 0x4>; + }; + + qos_aisp: qos@203b0000 { + compatible = "syscon"; + reg = <0x203b0000 0x20>; + }; + + lpmcu_mbox0: mailbox@20500000 { + compatible = "rockchip,rv1126b-mailbox", "rockchip,rk3576-mailbox"; + reg = <0x20500000 0x20>; + interrupts = ; + clocks = <&cru PCLK_LPMCU_MAILBOX>; + clock-names = "pclk_mailbox"; + #mbox-cells = <1>; + status = "disabled"; + }; + + lpmcu_mbox1: mailbox@20510000 { + compatible = "rockchip,rv1126b-mailbox", "rockchip,rk3576-mailbox"; + reg = <0x20510000 0x20>; + interrupts = ; + clocks = <&cru PCLK_LPMCU_MAILBOX>; + clock-names = "pclk_mailbox"; + #mbox-cells = <1>; + status = "disabled"; + }; + + lpmcu_mbox2: mailbox@20520000 { + compatible = "rockchip,rv1126b-mailbox", "rockchip,rk3576-mailbox"; + reg = <0x20520000 0x20>; + interrupts = ; + clocks = <&cru PCLK_LPMCU_MAILBOX>; + clock-names = "pclk_mailbox"; + #mbox-cells = <1>; + status = "disabled"; + }; + + lpmcu_mbox3: mailbox@20530000 { + compatible = "rockchip,rv1126b-mailbox", "rockchip,rk3576-mailbox"; + reg = <0x20530000 0x20>; + interrupts = ; + clocks = <&cru PCLK_LPMCU_MAILBOX>; + clock-names = "pclk_mailbox"; + #mbox-cells = <1>; + status = "disabled"; + }; + + pwm1_4ch_0: pwm@20700000 { + compatible = "rockchip,rv1126b-pwm", "rockchip,rk3576-pwm"; + reg = <0x20700000 0x1000>; + interrupts = ; + clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>; + clock-names = "pwm", "pclk"; + pinctrl-names = "active"; + pinctrl-0 = <&pwm1m0_ch0_pins>; + #pwm-cells = <3>; + status = "disabled"; + }; + + pwm1_4ch_1: pwm@20710000 { + compatible = "rockchip,rv1126b-pwm", "rockchip,rk3576-pwm"; + reg = <0x20710000 0x1000>; + interrupts = ; + clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>; + clock-names = "pwm", "pclk"; + pinctrl-names = "active"; + pinctrl-0 = <&pwm1m0_ch1_pins>; + #pwm-cells = <3>; + status = "disabled"; + }; + + pwm1_4ch_2: pwm@20720000 { + compatible = "rockchip,rv1126b-pwm", "rockchip,rk3576-pwm"; + reg = <0x20720000 0x1000>; + interrupts = ; + clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>; + clock-names = "pwm", "pclk"; + pinctrl-names = "active"; + pinctrl-0 = <&pwm1m0_ch2_pins>; + #pwm-cells = <3>; + status = "disabled"; + }; + + pwm1_4ch_3: pwm@20730000 { + compatible = "rockchip,rv1126b-pwm", "rockchip,rk3576-pwm"; + reg = <0x20730000 0x1000>; + interrupts = ; + clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>; + clock-names = "pwm", "pclk"; + pinctrl-names = "active"; + pinctrl-0 = <&pwm1m0_ch3_pins>; + #pwm-cells = <3>; + status = "disabled"; + }; + + i2c2: i2c@20800000 { + compatible = "rockchip,rv1126b-i2c", "rockchip,rk3399-i2c"; + reg = <0x20800000 0x1000>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&cru CLK_I2C2>, <&cru PCLK_I2C2>; + clock-names = "i2c", "pclk"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c2m0_pins>; + status = "disabled"; + }; + + uart0: serial@20810000 { + compatible = "rockchip,rv1126b-uart", "snps,dw-apb-uart"; + reg = <0x20810000 0x100>; + interrupts = ; + clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>; + clock-names = "baudclk", "apb_pclk"; + reg-shift = <2>; + reg-io-width = <4>; + dmas = <&dmac 1>, <&dmac 0>; + pinctrl-names = "default"; + pinctrl-0 = <&uart0m0_xfer_pins>; + status = "disabled"; + }; + + pmu: power-management@20838000 { + compatible = "rockchip,rv1126b-pmu", "syscon", "simple-mfd"; + reg = <0x20838000 0x400>; + + power: power-controller { + compatible = "rockchip,rv1126b-power-controller"; + #power-domain-cells = <1>; + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + /* These power domains are grouped by VD_NPU */ + power-domain@RV1126B_PD_NPU { + reg = ; + pm_qos = <&qos_npu>; + pm_shaping = <&shaping_npu>; + }; + /* These power domains are grouped by VD_LOGIC */ + power-domain@RV1126B_PD_VDO { + reg = ; + pm_qos = <&qos_vop>, + <&qos_rkvdec>, + <&qos_rkjpeg>, + <&qos_decom>; + pm_shaping = <&shaping_vop>, + <&shaping_rkvdec>, + <&shaping_rkjpeg>, + <&shaping_decom>; + }; + power-domain@RV1126B_PD_AISP { + reg = ; + pm_qos = <&qos_aisp>; + }; + }; + }; + + audio_codec_pmu: audio-codec@20890000 { + compatible = "rockchip,rv1126b-codec", "rockchip,rk3506-codec"; + reg = <0x20890000 0x1000>; + #sound-dai-cells = <0>; + sound-name-prefix = "ACodec_LP"; + clocks = <&cru PCLK_AUDIO_ADC_PMU>, <&cru MCLK_AUDIO_ADC_PMU>; + clock-names = "pclk", "mclk"; + resets = <&cru SRST_MRESETN_AUDIO_ADC_PMU>; + reset-names = "rst"; + rockchip,grf = <&grf>; + status = "disabled"; + }; + + fspi1: spi@208c0000 { + compatible = "rockchip,rv1126b-fspi", "rockchip,fspi"; + reg = <0x208c0000 0x4000>; + interrupts = ; + clocks = <&cru SCLK_1X_FSPI1>, <&cru HCLK_FSPI1>; + clock-names = "clk_sfc", "hclk_sfc"; + rockchip,grf = <&grf>; + rockchip,max-dll = <0x7F>; + rockchip,sclk-x2-bypass; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + crypto: crypto@20940000 { + compatible = "rockchip,crypto-ce"; + reg = <0x20940000 0x2000>; + interrupts = ; + clocks = <&cru ACLK_NSRKCE>, <&cru HCLK_NS_RKCE>, + <&cru CLK_PKA_NSRKCE>; + clock-names = "aclk", "hclk", "pka"; + resets = <&cru SRST_HRESETN_NS_RKCE>; + reset-names = "crypto-rst"; + status = "disabled"; + }; + + rng: rng@20950000 { + compatible = "rockchip,rkrng"; + reg = <0x20950000 0x200>; + interrupts = ; + resets = <&cru SRST_HRESETN_RKRNG_NS>; + reset-names = "reset"; + status = "disabled"; + }; + + sai0: sai@20960000 { + compatible = "rockchip,rv1126b-sai", "rockchip,sai-v1"; + reg = <0x20960000 0x1000>; + interrupts = ; + clocks = <&cru MCLK_SAI0>, <&cru HCLK_SAI0>; + clock-names = "mclk", "hclk"; + dmas = <&dmac 17>, <&dmac 16>; + dma-names = "tx", "rx"; + resets = <&cru SRST_MRESETN_SAI0>, <&cru SRST_HRESETN_SAI0>; + reset-names = "m", "h"; + #sound-dai-cells = <0>; + sound-name-prefix = "SAI0"; + pinctrl-names = "default"; + pinctrl-0 = <&sai0m0_lrck_pins + &sai0m0_sclk_pins + &sai0m0_sdi0_pins + &sai0m0_sdi1_pins + &sai0m0_sdi2_pins + &sai0m0_sdi3_pins + &sai0m0_sdo0_pins>; + status = "disabled"; + }; + + sai1: sai@20970000 { + compatible = "rockchip,rv1126b-sai", "rockchip,sai-v1"; + reg = <0x20970000 0x1000>; + interrupts = ; + clocks = <&cru MCLK_SAI1>, <&cru HCLK_SAI1>; + clock-names = "mclk", "hclk"; + dmas = <&dmac 19>, <&dmac 18>; + dma-names = "tx", "rx"; + resets = <&cru SRST_MRESETN_SAI1>, <&cru SRST_HRESETN_SAI1>; + reset-names = "m", "h"; + #sound-dai-cells = <0>; + sound-name-prefix = "SAI1"; + pinctrl-names = "default"; + pinctrl-0 = <&sai1m0_lrck_pins + &sai1m0_sclk_pins + &sai1m0_sdi_pins + &sai1m0_sdo_pins>; + status = "disabled"; + }; + + sai2: sai@20980000 { + compatible = "rockchip,rv1126b-sai", "rockchip,sai-v1"; + reg = <0x20980000 0x1000>; + interrupts = ; + clocks = <&cru MCLK_SAI2>, <&cru HCLK_SAI2>; + clock-names = "mclk", "hclk"; + dmas = <&dmac 21>, <&dmac 20>; + dma-names = "tx", "rx"; + resets = <&cru SRST_MRESETN_SAI2>, <&cru SRST_HRESETN_SAI2>; + reset-names = "m", "h"; + #sound-dai-cells = <0>; + sound-name-prefix = "SAI2"; + pinctrl-names = "default"; + pinctrl-0 = <&sai2m0_lrck_pins + &sai2m0_sclk_pins + &sai2m0_sdi0_pins + &sai2m0_sdi1_pins + &sai2m0_sdi2_pins + &sai2m0_sdo_pins>; + status = "disabled"; + }; + + pdm: pdm@20990000 { + compatible = "rockchip,rv1126b-pdm", "rockchip,rk3576-pdm"; + reg = <0x20990000 0x1000>; + interrupts = ; + clocks = <&cru MCLK_PDM>, <&cru HCLK_PDM>, <&cru CLKOUT_PDM>; + clock-names = "pdm_clk", "pdm_hclk", "pdm_clk_out"; + dmas = <&dmac 26>; + dma-names = "rx"; + rockchip,pdm-data-shift = <5 5 5 5 5 5 5 5>; + pinctrl-names = "default", "idle", "clk"; + pinctrl-0 = <&pdmm0_sdi0_pins + &pdmm0_sdi1_pins + &pdmm0_sdi2_pins + &pdmm0_sdi3_pins>; + pinctrl-1 = <&pdmm0_clk0_idle + &pdmm0_clk1_idle>; + pinctrl-2 = <&pdmm0_clk0_pins + &pdmm0_clk1_pins>; + #sound-dai-cells = <0>; + sound-name-prefix = "PDM0"; + status = "disabled"; + }; + + acdcdig_dsm: acdcdig-dsm@209a0000 { + compatible = "rockchip,rv1126b-dsm"; + reg = <0x209a0000 0x1000>; + clocks = <&cru MCLK_RKDSM>, <&cru HCLK_RKDSM>; + clock-names = "dac", "pclk"; + resets = <&cru SRST_MRESETN_RKDSM>; + reset-names = "reset" ; + rockchip,grf = <&grf>; + rockchip,ioc-grf = <&ioc_grf>; + pinctrl-names = "default"; + pinctrl-0 = <&dsm_aud_ln_pins + &dsm_aud_lp_pins + &dsm_aud_rn_pins + &dsm_aud_rp_pins>; + #sound-dai-cells = <0>; + status = "disabled"; + }; + + asrc0: asrc@209b0000 { + compatible = "rockchip,rv1126b-asrc", "rockchip,rk3506-asrc"; + reg = <0x209b0000 0x1000>; + interrupts = ; + clocks = <&cru CLK_ASRC0>, <&cru HCLK_ASRC0>, + <&cru LRCK_SRC_ASRC0>, <&cru LRCK_DST_ASRC0>; + clock-names = "mclk", "hclk", + "src_lrck", "dst_lrck"; + dmas = <&dmac 22>, <&dmac 23>; + dma-names = "rx", "tx"; + resets = <&cru SRST_RESETN_ASRC0>, <&cru SRST_HRESETN_ASRC0>; + reset-names = "m", "h"; + #sound-dai-cells = <0>; + sound-name-prefix = "ASRC0"; + status = "disabled"; + }; + + asrc1: asrc@209c0000 { + compatible = "rockchip,rv1126b-asrc", "rockchip,rk3506-asrc"; + reg = <0x209c0000 0x1000>; + interrupts = ; + clocks = <&cru CLK_ASRC1>, <&cru HCLK_ASRC1>, + <&cru LRCK_SRC_ASRC1>, <&cru LRCK_DST_ASRC1>; + clock-names = "mclk", "hclk", + "src_lrck", "dst_lrck"; + dmas = <&dmac 24>, <&dmac 25>; + dma-names = "rx", "tx"; + resets = <&cru SRST_RESETN_ASRC1>, <&cru SRST_HRESETN_ASRC1>; + reset-names = "m", "h"; + #sound-dai-cells = <0>; + sound-name-prefix = "ASRC1"; + status = "disabled"; + }; + + rga2_core0: rga@209f0000 { + compatible = "rockchip,rga2"; + reg = <0x209f0000 0x1000>; + interrupts = ; + interrupt-names = "rga2_core0_irq"; + clocks = <&cru ACLK_RGA>, <&cru HCLK_RGA>, <&cru CLK_CORE_RGA>; + clock-names = "aclk_rga", "hclk_rga", "clk_rga"; + iommus = <&rga2_core0_mmu>; + status = "disabled"; + }; + + rga2_core0_mmu: iommu@209f0f00 { + compatible = "rockchip,iommu-v2"; + reg = <0x209f0f00 0x100>; + interrupts = ; + interrupt-names = "rga2_0_mmu"; + clocks = <&cru ACLK_RGA>, <&cru HCLK_RGA>; + clock-names = "aclk", "iface"; + #iommu-cells = <0>; + status = "disabled"; + }; + + wdt: watchdog@20b60000 { + compatible = "snps,dw-wdt"; + reg = <0x20b60000 0x100>; + clocks = <&cru TCLK_WDT_NS>, <&cru PCLK_WDT_NS>; + clock-names = "tclk", "pclk"; + interrupts = ; + status = "disabled"; + }; + + dmac: dma-controller@20b80000 { + compatible = "rockchip,rv1126b-dma", "rockchip,dma"; + reg = <0x20b80000 0x2000>; + interrupts = ; + clocks = <&cru ACLK_RKDMA>; + clock-names = "aclk"; + #dma-cells = <1>; + }; + + otp: otp@20b90000 { + compatible = "rockchip,rv1126b-otp"; + reg = <0x20b90000 0x4000>; + #address-cells = <1>; + #size-cells = <1>; + clocks = <&cru CLK_USER_OTPC_NS>, <&cru CLK_SBPI_OTPC_NS>, + <&cru PCLK_OTPC_NS>, <&cru PCLK_OTP_MASK>; + clock-names = "usr", "sbpi", "apb", "phy"; + resets = <&cru SRST_RESETN_USER_OTPC_NS>, <&cru SRST_RESETN_SBPI_OTPC_NS>, + <&cru SRST_PRESETN_OTPC_NS>, <&cru SRST_PRESETN_OTP_MASK>; + reset-names = "usr", "sbpi", "apb", "phy"; + + /* Data cells */ + cpu_code: cpu-code@2 { + reg = <0x02 0x2>; + }; + cpu_version: cpu-version@21 { + reg = <0x21 0x1>; + bits = <3 3>; + }; + otp_id: otp-id@22 { + reg = <0x22 0x10>; + }; + cpu_leakage: cpu-leakage@32 { + reg = <0x32 0x1>; + }; + log_leakage: log-leakage@33 { + reg = <0x33 0x1>; + }; + npu_leakage: npu-leakage@34 { + reg = <0x34 0x1>; + }; + }; + + tsadc: tsadc@20bb0000 { + compatible = "rockchip,rv1126b-tsadc"; + reg = <0x20bb0000 0x400>; + interrupts = ; + clocks = <&cru CLK_TSADC>, <&cru PCLK_TSADC>, + <&cru CLK_TSADC_PHYCTRL>; + clock-names = "tsadc", "apb_pclk", "tsadc_phyctrl"; + resets = <&cru SRST_RESETN_TSADC>, <&cru SRST_PRESETN_TSADC>, + <&cru SRST_RESETN_TSADC_PHYCTRL>; + reset-names = "tsadc", "tsadc-apb", "tsadc-phy"; + #thermal-sensor-cells = <1>; + rockchip,grf = <&grf>; + rockchip,hw-tshut-temp = <120000>; + rockchip,hw-tshut-mode = <0>; /* tshut mode 0:CRU 1:GPIO */ + rockchip,hw-tshut-polarity = <0>; /* tshut polarity 0:LOW 1:HIGH */ + status = "disabled"; + }; + + audio_codec: audio-codec@20bf0000 { + compatible = "rockchip,rv1126b-codec", "rockchip,rk3506-codec"; + reg = <0x20bf0000 0x1000>; + #sound-dai-cells = <0>; + sound-name-prefix = "ACodec"; + clocks = <&cru PCLK_AUDIO_ADC_BUS>, <&cru MCLK_AUDIO_ADC_BUS>; + clock-names = "pclk", "mclk"; + resets = <&cru SRST_MRESETN_AUDIO_ADC_BUS>; + reset-names = "rst"; + rockchip,grf = <&grf>; + status = "disabled"; + }; + + rktimer: timer@20c00000 { + compatible = "rockchip,rv1126b-timer", "rockchip,rk3288-timer"; + reg = <0x20c00000 0x20>; + interrupts = ; + clocks = <&cru PCLK_TIMER>, <&cru CLK_TIMER0>; + clock-names = "pclk", "timer"; + }; + + hpmcu_mbox0: mailbox@20d00000 { + compatible = "rockchip,rv1126b-mailbox", "rockchip,rk3576-mailbox"; + reg = <0x20d00000 0x20>; + interrupts = ; + clocks = <&cru PCLK_HPMCU_MAILBOX>; + clock-names = "pclk_mailbox"; + #mbox-cells = <1>; + status = "disabled"; + }; + + hpmcu_mbox1: mailbox@20d10000 { + compatible = "rockchip,rv1126b-mailbox", "rockchip,rk3576-mailbox"; + reg = <0x20d10000 0x20>; + interrupts = ; + clocks = <&cru PCLK_HPMCU_MAILBOX>; + clock-names = "pclk_mailbox"; + #mbox-cells = <1>; + status = "disabled"; + }; + + hpmcu_mbox2: mailbox@20d20000 { + compatible = "rockchip,rv1126b-mailbox", "rockchip,rk3576-mailbox"; + reg = <0x20d20000 0x20>; + interrupts = ; + clocks = <&cru PCLK_HPMCU_MAILBOX>; + clock-names = "pclk_mailbox"; + #mbox-cells = <1>; + status = "disabled"; + }; + + hpmcu_mbox3: mailbox@20d30000 { + compatible = "rockchip,rv1126b-mailbox", "rockchip,rk3576-mailbox"; + reg = <0x20d30000 0x20>; + interrupts = ; + clocks = <&cru PCLK_HPMCU_MAILBOX>; + clock-names = "pclk_mailbox"; + #mbox-cells = <1>; + status = "disabled"; + }; + + pwm0_8ch_0: pwm@20e00000 { + compatible = "rockchip,rv1126b-pwm", "rockchip,rk3576-pwm"; + reg = <0x20e00000 0x1000>; + interrupts = ; + clocks = <&cru CLK_PWM0>, <&cru PCLK_PWM0>; + clock-names = "pwm", "pclk"; + pinctrl-names = "active"; + pinctrl-0 = <&pwm0m0_ch0_pins>; + #pwm-cells = <3>; + status = "disabled"; + }; + + pwm0_8ch_1: pwm@20e10000 { + compatible = "rockchip,rv1126b-pwm", "rockchip,rk3576-pwm"; + reg = <0x20e10000 0x1000>; + interrupts = ; + clocks = <&cru CLK_PWM0>, <&cru PCLK_PWM0>; + clock-names = "pwm", "pclk"; + pinctrl-names = "active"; + pinctrl-0 = <&pwm0m0_ch1_pins>; + #pwm-cells = <3>; + status = "disabled"; + }; + + pwm0_8ch_2: pwm@20e20000 { + compatible = "rockchip,rv1126b-pwm", "rockchip,rk3576-pwm"; + reg = <0x20e20000 0x1000>; + interrupts = ; + clocks = <&cru CLK_PWM0>, <&cru PCLK_PWM0>; + clock-names = "pwm", "pclk"; + pinctrl-names = "active"; + pinctrl-0 = <&pwm0m0_ch2_pins>; + #pwm-cells = <3>; + status = "disabled"; + }; + + pwm0_8ch_3: pwm@20e30000 { + compatible = "rockchip,rv1126b-pwm", "rockchip,rk3576-pwm"; + reg = <0x20e30000 0x1000>; + interrupts = ; + clocks = <&cru CLK_PWM0>, <&cru PCLK_PWM0>; + clock-names = "pwm", "pclk"; + pinctrl-names = "active"; + pinctrl-0 = <&pwm0m0_ch3_pins>; + #pwm-cells = <3>; + status = "disabled"; + }; + + pwm0_8ch_4: pwm@20e40000 { + compatible = "rockchip,rv1126b-pwm", "rockchip,rk3576-pwm"; + reg = <0x20e40000 0x1000>; + interrupts = ; + clocks = <&cru CLK_PWM0>, <&cru PCLK_PWM0>; + clock-names = "pwm", "pclk"; + pinctrl-names = "active"; + pinctrl-0 = <&pwm0m0_ch4_pins>; + #pwm-cells = <3>; + status = "disabled"; + }; + + pwm0_8ch_5: pwm@20e50000 { + compatible = "rockchip,rv1126b-pwm", "rockchip,rk3576-pwm"; + reg = <0x20e50000 0x1000>; + interrupts = ; + clocks = <&cru CLK_PWM0>, <&cru PCLK_PWM0>; + clock-names = "pwm", "pclk"; + pinctrl-names = "active"; + pinctrl-0 = <&pwm0m0_ch5_pins>; + #pwm-cells = <3>; + status = "disabled"; + }; + + pwm0_8ch_6: pwm@20e60000 { + compatible = "rockchip,rv1126b-pwm", "rockchip,rk3576-pwm"; + reg = <0x20e60000 0x1000>; + interrupts = ; + clocks = <&cru CLK_PWM0>, <&cru PCLK_PWM0>; + clock-names = "pwm", "pclk"; + pinctrl-names = "active"; + pinctrl-0 = <&pwm0m0_ch6_pins>; + #pwm-cells = <3>; + status = "disabled"; + }; + + pwm0_8ch_7: pwm@20e70000 { + compatible = "rockchip,rv1126b-pwm", "rockchip,rk3576-pwm"; + reg = <0x20e70000 0x1000>; + interrupts = ; + clocks = <&cru CLK_PWM0>, <&cru PCLK_PWM0>; + clock-names = "pwm", "pclk"; + pinctrl-names = "active"; + pinctrl-0 = <&pwm0m0_ch7_pins>; + #pwm-cells = <3>; + status = "disabled"; + }; + + pwm2_8ch_0: pwm@20f00000 { + compatible = "rockchip,rv1126b-pwm", "rockchip,rk3576-pwm"; + reg = <0x20f00000 0x1000>; + interrupts = ; + clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>, <&cru CLK_OSC_PWM2>; + clock-names = "pwm", "pclk", "osc"; + pinctrl-names = "active"; + pinctrl-0 = <&pwm2m0_ch0_pins>; + #pwm-cells = <3>; + status = "disabled"; + }; + + pwm2_8ch_1: pwm@20f10000 { + compatible = "rockchip,rv1126b-pwm", "rockchip,rk3576-pwm"; + reg = <0x20f10000 0x1000>; + interrupts = ; + clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>, <&cru CLK_OSC_PWM2>; + clock-names = "pwm", "pclk", "osc"; + pinctrl-names = "active"; + pinctrl-0 = <&pwm2m0_ch1_pins>; + #pwm-cells = <3>; + status = "disabled"; + }; + + pwm2_8ch_2: pwm@20f20000 { + compatible = "rockchip,rv1126b-pwm", "rockchip,rk3576-pwm"; + reg = <0x20f20000 0x1000>; + interrupts = ; + clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>, <&cru CLK_OSC_PWM2>; + clock-names = "pwm", "pclk", "osc"; + pinctrl-names = "active"; + pinctrl-0 = <&pwm2m0_ch2_pins>; + #pwm-cells = <3>; + status = "disabled"; + }; + + pwm2_8ch_3: pwm@20f30000 { + compatible = "rockchip,rv1126b-pwm", "rockchip,rk3576-pwm"; + reg = <0x20f30000 0x1000>; + interrupts = ; + clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>, <&cru CLK_OSC_PWM2>; + clock-names = "pwm", "pclk", "osc"; + pinctrl-names = "active"; + pinctrl-0 = <&pwm2m0_ch3_pins>; + #pwm-cells = <3>; + status = "disabled"; + }; + + pwm2_8ch_4: pwm@20f40000 { + compatible = "rockchip,rv1126b-pwm", "rockchip,rk3576-pwm"; + reg = <0x20f40000 0x1000>; + interrupts = ; + clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>, <&cru CLK_OSC_PWM2>; + clock-names = "pwm", "pclk", "osc"; + pinctrl-names = "active"; + pinctrl-0 = <&pwm2m0_ch4_pins>; + #pwm-cells = <3>; + status = "disabled"; + }; + + pwm2_8ch_5: pwm@20f50000 { + compatible = "rockchip,rv1126b-pwm", "rockchip,rk3576-pwm"; + reg = <0x20f50000 0x1000>; + interrupts = ; + clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>, <&cru CLK_OSC_PWM2>; + clock-names = "pwm", "pclk", "osc"; + pinctrl-names = "active"; + pinctrl-0 = <&pwm2m0_ch5_pins>; + #pwm-cells = <3>; + status = "disabled"; + }; + + pwm2_8ch_6: pwm@20f60000 { + compatible = "rockchip,rv1126b-pwm", "rockchip,rk3576-pwm"; + reg = <0x20f60000 0x1000>; + interrupts = ; + clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>, <&cru CLK_OSC_PWM2>; + clock-names = "pwm", "pclk", "osc"; + pinctrl-names = "active"; + pinctrl-0 = <&pwm2m0_ch6_pins>; + #pwm-cells = <3>; + status = "disabled"; + }; + + pwm2_8ch_7: pwm@20f70000 { + compatible = "rockchip,rv1126b-pwm", "rockchip,rk3576-pwm"; + reg = <0x20f70000 0x1000>; + interrupts = ; + clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>, <&cru CLK_OSC_PWM2>; + clock-names = "pwm", "pclk", "osc"; + pinctrl-names = "active"; + pinctrl-0 = <&pwm2m0_ch7_pins>; + #pwm-cells = <3>; + status = "disabled"; + }; + + pwm3_8ch_0: pwm@21000000 { + compatible = "rockchip,rv1126b-pwm", "rockchip,rk3576-pwm"; + reg = <0x21000000 0x1000>; + interrupts = ; + clocks = <&cru CLK_PWM3>, <&cru PCLK_PWM3>; + clock-names = "pwm", "pclk"; + pinctrl-names = "active"; + pinctrl-0 = <&pwm3m0_ch0_pins>; + #pwm-cells = <3>; + status = "disabled"; + }; + + pwm3_8ch_1: pwm@21010000 { + compatible = "rockchip,rv1126b-pwm", "rockchip,rk3576-pwm"; + reg = <0x21010000 0x1000>; + interrupts = ; + clocks = <&cru CLK_PWM3>, <&cru PCLK_PWM3>; + clock-names = "pwm", "pclk"; + pinctrl-names = "active"; + pinctrl-0 = <&pwm3m0_ch1_pins>; + #pwm-cells = <3>; + status = "disabled"; + }; + + pwm3_8ch_2: pwm@21020000 { + compatible = "rockchip,rv1126b-pwm", "rockchip,rk3576-pwm"; + reg = <0x21020000 0x1000>; + interrupts = ; + clocks = <&cru CLK_PWM3>, <&cru PCLK_PWM3>; + clock-names = "pwm", "pclk"; + pinctrl-names = "active"; + pinctrl-0 = <&pwm3m0_ch2_pins>; + #pwm-cells = <3>; + status = "disabled"; + }; + + pwm3_8ch_3: pwm@21030000 { + compatible = "rockchip,rv1126b-pwm", "rockchip,rk3576-pwm"; + reg = <0x21030000 0x1000>; + interrupts = ; + clocks = <&cru CLK_PWM3>, <&cru PCLK_PWM3>; + clock-names = "pwm", "pclk"; + pinctrl-names = "active"; + pinctrl-0 = <&pwm3m0_ch3_pins>; + #pwm-cells = <3>; + status = "disabled"; + }; + + pwm3_8ch_4: pwm@21040000 { + compatible = "rockchip,rv1126b-pwm", "rockchip,rk3576-pwm"; + reg = <0x21040000 0x1000>; + interrupts = ; + clocks = <&cru CLK_PWM3>, <&cru PCLK_PWM3>; + clock-names = "pwm", "pclk"; + pinctrl-names = "active"; + pinctrl-0 = <&pwm3m0_ch4_pins>; + #pwm-cells = <3>; + status = "disabled"; + }; + + pwm3_8ch_5: pwm@21050000 { + compatible = "rockchip,rv1126b-pwm", "rockchip,rk3576-pwm"; + reg = <0x21050000 0x1000>; + interrupts = ; + clocks = <&cru CLK_PWM3>, <&cru PCLK_PWM3>; + clock-names = "pwm", "pclk"; + pinctrl-names = "active"; + pinctrl-0 = <&pwm3m0_ch5_pins>; + #pwm-cells = <3>; + status = "disabled"; + }; + + pwm3_8ch_6: pwm@21060000 { + compatible = "rockchip,rv1126b-pwm", "rockchip,rk3576-pwm"; + reg = <0x21060000 0x1000>; + interrupts = ; + clocks = <&cru CLK_PWM3>, <&cru PCLK_PWM3>; + clock-names = "pwm", "pclk"; + pinctrl-names = "active"; + pinctrl-0 = <&pwm3m0_ch6_pins>; + #pwm-cells = <3>; + status = "disabled"; + }; + + pwm3_8ch_7: pwm@21070000 { + compatible = "rockchip,rv1126b-pwm", "rockchip,rk3576-pwm"; + reg = <0x21070000 0x1000>; + interrupts = ; + clocks = <&cru CLK_PWM3>, <&cru PCLK_PWM3>; + clock-names = "pwm", "pclk"; + pinctrl-names = "active"; + pinctrl-0 = <&pwm3m0_ch7_pins>; + #pwm-cells = <3>; + status = "disabled"; + }; + + i2c0: i2c@21100000 { + compatible = "rockchip,rv1126b-i2c", "rockchip,rk3399-i2c"; + reg = <0x21100000 0x1000>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&cru CLK_I2C0>, <&cru PCLK_I2C0>; + clock-names = "i2c", "pclk"; + dmas = <&dmac 29>, <&dmac 28>; + dma-names = "tx", "rx"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c0m0_pins>; + status = "disabled"; + }; + + i2c1: i2c@21110000 { + compatible = "rockchip,rv1126b-i2c", "rockchip,rk3399-i2c"; + reg = <0x21110000 0x1000>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&cru CLK_I2C1>, <&cru PCLK_I2C1>; + clock-names = "i2c", "pclk"; + dmas = <&dmac 31>, <&dmac 30>; + dma-names = "tx", "rx"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c1m0_pins>; + status = "disabled"; + }; + + i2c3: i2c@21120000 { + compatible = "rockchip,rv1126b-i2c", "rockchip,rk3399-i2c"; + reg = <0x21120000 0x1000>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&cru CLK_I2C3>, <&cru PCLK_I2C3>; + clock-names = "i2c", "pclk"; + dmas = <&dmac 35>, <&dmac 34>; + dma-names = "tx", "rx"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c3m0_pins>; + status = "disabled"; + }; + + i2c4: i2c@21130000 { + compatible = "rockchip,rv1126b-i2c", "rockchip,rk3399-i2c"; + reg = <0x21130000 0x1000>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&cru CLK_I2C4>, <&cru PCLK_I2C4>; + clock-names = "i2c", "pclk"; + dmas = <&dmac 37>, <&dmac 36>; + dma-names = "tx", "rx"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c4m0_pins>; + status = "disabled"; + }; + + i2c5: i2c@21140000 { + compatible = "rockchip,rv1126b-i2c", "rockchip,rk3399-i2c"; + reg = <0x21140000 0x1000>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&cru CLK_I2C5>, <&cru PCLK_I2C5>; + clock-names = "i2c", "pclk"; + dmas = <&dmac 39>, <&dmac 38>; + dma-names = "tx", "rx"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c5m0_pins>; + status = "disabled"; + }; + + uart1: serial@21160000 { + compatible = "rockchip,rv1126b-uart", "snps,dw-apb-uart"; + reg = <0x21160000 0x100>; + interrupts = ; + clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>; + clock-names = "baudclk", "apb_pclk"; + reg-shift = <2>; + reg-io-width = <4>; + dmas = <&dmac 3>, <&dmac 2>; + pinctrl-names = "default"; + pinctrl-0 = <&uart1m0_xfer_pins &uart1m0_ctsn_pins &uart1m0_rtsn_pins>; + status = "disabled"; + }; + + uart2: serial@21170000 { + compatible = "rockchip,rv1126b-uart", "snps,dw-apb-uart"; + reg = <0x21170000 0x100>; + interrupts = ; + clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>; + clock-names = "baudclk", "apb_pclk"; + reg-shift = <2>; + reg-io-width = <4>; + dmas = <&dmac 5>, <&dmac 4>; + pinctrl-names = "default"; + pinctrl-0 = <&uart2m0_xfer_pins &uart2m0_ctsn_pins &uart2m0_rtsn_pins>; + status = "disabled"; + }; + + uart3: serial@21180000 { + compatible = "rockchip,rv1126b-uart", "snps,dw-apb-uart"; + reg = <0x21180000 0x100>; + interrupts = ; + clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>; + clock-names = "baudclk", "apb_pclk"; + reg-shift = <2>; + reg-io-width = <4>; + dmas = <&dmac 7>, <&dmac 6>; + pinctrl-names = "default"; + pinctrl-0 = <&uart3m0_xfer_pins &uart3m0_ctsn_pins &uart3m0_rtsn_pins>; + status = "disabled"; + }; + + uart4: serial@21190000 { + compatible = "rockchip,rv1126b-uart", "snps,dw-apb-uart"; + reg = <0x21190000 0x100>; + interrupts = ; + clocks = <&cru SCLK_UART4>, <&cru PCLK_UART4>; + clock-names = "baudclk", "apb_pclk"; + reg-shift = <2>; + reg-io-width = <4>; + dmas = <&dmac 9>, <&dmac 8>; + pinctrl-names = "default"; + pinctrl-0 = <&uart4m0_xfer_pins &uart4m0_ctsn_pins &uart4m0_rtsn_pins>; + status = "disabled"; + }; + + uart5: serial@211a0000 { + compatible = "rockchip,rv1126b-uart", "snps,dw-apb-uart"; + reg = <0x211a0000 0x100>; + interrupts = ; + clocks = <&cru SCLK_UART5>, <&cru PCLK_UART5>; + clock-names = "baudclk", "apb_pclk"; + reg-shift = <2>; + reg-io-width = <4>; + dmas = <&dmac 11>, <&dmac 10>; + pinctrl-names = "default"; + pinctrl-0 = <&uart5m0_xfer_pins &uart5m0_ctsn_pins &uart5m0_rtsn_pins>; + status = "disabled"; + }; + + uart6: serial@211b0000 { + compatible = "rockchip,rv1126b-uart", "snps,dw-apb-uart"; + reg = <0x211b0000 0x100>; + interrupts = ; + clocks = <&cru SCLK_UART6>, <&cru PCLK_UART6>; + clock-names = "baudclk", "apb_pclk"; + reg-shift = <2>; + reg-io-width = <4>; + dmas = <&dmac 13>, <&dmac 12>; + pinctrl-names = "default"; + pinctrl-0 = <&uart6m0_xfer_pins &uart6m0_ctsn_pins &uart6m0_rtsn_pins>; + status = "disabled"; + }; + + uart7: serial@211c0000 { + compatible = "rockchip,rv1126b-uart", "snps,dw-apb-uart"; + reg = <0x211c0000 0x100>; + interrupts = ; + clocks = <&cru SCLK_UART7>, <&cru PCLK_UART7>; + clock-names = "baudclk", "apb_pclk"; + reg-shift = <2>; + reg-io-width = <4>; + dmas = <&dmac 15>, <&dmac 14>; + pinctrl-names = "default"; + pinctrl-0 = <&uart7m0_xfer_pins &uart7m0_ctsn_pins &uart7m0_rtsn_pins>; + status = "disabled"; + }; + + spi0: spi@211e0000 { + compatible = "rockchip,rv1126b-spi", "rockchip,rk3066-spi"; + reg = <0x211e0000 0x1000>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&cru CLK_SPI0>, <&cru PCLK_SPI0>; + clock-names = "spiclk", "apb_pclk"; + dmas = <&dmac 40>, <&dmac 41>; + dma-names = "rx", "tx"; + pinctrl-names = "default"; + pinctrl-0 = <&spi0m0_clk_pins &spi0m0_csn0_pins &spi0m0_csn1_pins>; + status = "disabled"; + }; + + spi1: spi@211f0000 { + compatible = "rockchip,rv1126b-spi", "rockchip,rk3066-spi"; + reg = <0x211f0000 0x1000>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&cru CLK_SPI1>, <&cru PCLK_SPI1>; + clock-names = "spiclk", "apb_pclk"; + dmas = <&dmac 42>, <&dmac 43>; + dma-names = "rx", "tx"; + pinctrl-names = "default"; + pinctrl-0 = <&spi1m0_clk_pins &spi1m0_csn0_pins &spi1m0_csn1_pins>; + status = "disabled"; + }; + + gic: interrupt-controller@21201000 { + compatible = "arm,gic-400"; + #interrupt-cells = <3>; + #address-cells = <0>; + interrupt-controller; + reg = <0x21201000 0x1000>, + <0x21202000 0x2000>, + <0x21204000 0x2000>, + <0x21206000 0x2000>; + interrupts = ; + }; + + hwlock: hwspinlock@21210000 { + compatible = "rockchip,hwspinlock"; + reg = <0x21210000 0x100>; + #hwlock-cells = <1>; + rockchip,hwlock-num-locks = <64>; + status = "disabled"; + }; + + rtc: rtc@21280000 { + compatible = "rockchip,rv1126b-rtc"; + reg = <0x21280000 0x1000>; + rockchip,grf = <&grf>; + interrupts = ; + clocks = <&cru PCLK_RTC_ROOT>; + clock-names = "pclk_phy"; + assigned-clocks = <&cru PCLK_RTC_ROOT>; + assigned-clock-rates = <50000000>; + status = "disabled"; + }; + + usb2phy: usb2-phy@21400000 { + compatible = "rockchip,rv1126b-usb2phy"; + reg = <0x21400000 0x10000>; + clocks = <&cru PCLK_USB2PHY>; + clock-names = "pclk"; + clock-output-names = "usb480m_phy"; + #clock-cells = <0>; + rockchip,usbctrl-grf = <&grf>; + rockchip,usbgrf = <&grf>; + status = "disabled"; + + usb2phy_host: host-port { + #phy-cells = <0>; + interrupts = ; + interrupt-names = "linestate"; + status = "disabled"; + }; + + usb2phy_otg: otg-port { + #phy-cells = <0>; + interrupts = , + , + ; + interrupt-names = "otg-id", "otg-bvalid", "linestate"; + status = "disabled"; + }; + }; + + usb3phy: usb3-phy@21410000 { + compatible = "rockchip,rv1126b-usb3-phy"; + reg = <0x21410000 0x10000>; + clocks = <&cru CLK_REF_PIPEPHY>, <&cru PCLK_PIPEPHY>; + clock-names = "refclk", "apbclk"; + assigned-clocks = <&cru CLK_REF_PIPEPHY>; + assigned-clock-rates = <100000000>; + #phy-cells = <1>; + resets = <&cru SRST_PRESETN_PIPEPHY>, <&cru SRST_RESETN_REF_PIPEPHY>; + reset-names = "combphy-apb", "combphy"; + rockchip,pipe-grf = <&grf>; + rockchip,pipe-phy-grf = <&grf>; + status = "disabled"; + }; + + fspi0: spi@21460000 { + compatible = "rockchip,rv1126b-fspi", "rockchip,fspi"; + reg = <0x21460000 0x4000>; + interrupts = ; + clocks = <&cru SCLK_2X_FSPI0>, <&cru HCLK_FSPI0>; + clock-names = "clk_sfc", "hclk_sfc"; + rockchip,grf = <&grf>; + rockchip,max-dll = <0xFF>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + emmc: mmc@21470000 { + compatible = "rockchip,rv1126b-dw-mshc", "rockchip,rk3288-dw-mshc"; + reg = <0x21470000 0x4000>; + interrupts = ; + clocks = <&cru HCLK_EMMC>, <&cru CCLK_EMMC>; + clock-names = "biu", "ciu"; + fifo-depth = <0x100>; + max-frequency = <200000000>; + status = "disabled"; + }; + + usb_host_ehci: usb@21480000 { + compatible = "generic-ehci"; + reg = <0x21480000 0x40000>; + interrupts = ; + clocks = <&cru HCLK_USB2HOST>, <&cru HCLK_ARB_USB2HOST>, <&usb2phy>; + clock-names = "usbhost", "arbiter", "utmi"; + phys = <&usb2phy_host>; + phy-names = "usb2-phy"; + status = "disabled"; + }; + + usb_host_ohci: usb@214c0000 { + compatible = "generic-ohci"; + reg = <0x214c0000 0x40000>; + interrupts = ; + clocks = <&cru HCLK_USB2HOST>, <&cru HCLK_ARB_USB2HOST>, <&usb2phy>; + clock-names = "usbhost", "arbiter", "utmi"; + phys = <&usb2phy_host>; + phy-names = "usb2-phy"; + status = "disabled"; + }; + + usb_drd_dwc3: usb@21500000 { + compatible = "rockchip,rv1126b-dwc3", "rockchip,rk3576-dwc3", "snps,dwc3"; + reg = <0x21500000 0x100000>; + clocks = <&cru CLK_REF_USB3OTG>, + <&cru CLK_SUSPEND_USB3OTG>, + <&cru ACLK_USB3OTG>; + clock-names = "ref", "suspend", "bus_clk"; + interrupts = ; + resets = <&cru SRST_ARESETN_USB3OTG>; + reset-names = "usb3-otg"; + dr_mode = "otg"; + phys = <&usb2phy_otg>, <&usb3phy PHY_TYPE_USB3>; + phy-names = "usb2-phy", "usb3-phy"; + phy_type = "utmi_wide"; + snps,dis_enblslpm_quirk; + snps,dis-u1-entry-quirk; + snps,dis-u2-entry-quirk; + snps,dis-u2-freeclk-exists-quirk; + snps,dis-del-phy-power-chg-quirk; + snps,dis-tx-ipgap-linecheck-quirk; + snps,dis_rxdet_inp3_quirk; + snps,parkmode-disable-hs-quirk; + snps,parkmode-disable-ss-quirk; + status = "disabled"; + }; + + dfi: dfi@21620000 { + compatible = "rockchip,rv1126b-dfi"; + reg = <0x21620000 0x10000>; + rockchip,pmugrf = <&grf>; + status = "disabled"; + }; + + mipi0_csi2_hw: mipi0-csi2-hw@21c00000 { + compatible = "rockchip,rv1126b-mipi-csi2-hw"; + reg = <0x21c00000 0x10000>; + reg-names = "csihost_regs"; + interrupts = , + ; + interrupt-names = "csi-intr1", "csi-intr2"; + clocks = <&cru PCLK_CSI2HOST0>, <&cru DCLK_CSI2HOST0>; + clock-names = "pclk_csi2host", "dclk_csi2host"; + resets = <&cru SRST_PRESETN_CSI2HOST0>; + reset-names = "srst_csihost_p"; + status = "okay"; + }; + + mipi1_csi2_hw: mipi1-csi2-hw@21c10000 { + compatible = "rockchip,rv1126b-mipi-csi2-hw"; + reg = <0x21c10000 0x10000>; + reg-names = "csihost_regs"; + interrupts = , + ; + interrupt-names = "csi-intr1", "csi-intr2"; + clocks = <&cru PCLK_CSI2HOST1>, <&cru DCLK_CSI2HOST1>; + clock-names = "pclk_csi2host", "dclk_csi2host"; + resets = <&cru SRST_PRESETN_CSI2HOST1>; + reset-names = "srst_csihost_p"; + status = "okay"; + }; + + mipi2_csi2_hw: mipi2-csi2-hw@21c20000 { + compatible = "rockchip,rv1126b-mipi-csi2-hw"; + reg = <0x21c20000 0x10000>; + reg-names = "csihost_regs"; + interrupts = , + ; + interrupt-names = "csi-intr1", "csi-intr2"; + clocks = <&cru PCLK_CSI2HOST2>, <&cru DCLK_CSI2HOST2>; + clock-names = "pclk_csi2host", "dclk_csi2host"; + resets = <&cru SRST_PRESETN_CSI2HOST2>; + reset-names = "srst_csihost_p"; + status = "okay"; + }; + + mipi3_csi2_hw: mipi3-csi2-hw@21c30000 { + compatible = "rockchip,rv1126b-mipi-csi2-hw"; + reg = <0x21c30000 0x10000>; + reg-names = "csihost_regs"; + interrupts = , + ; + interrupt-names = "csi-intr1", "csi-intr2"; + clocks = <&cru PCLK_CSI2HOST3>, <&cru DCLK_CSI2HOST3>; + clock-names = "pclk_csi2host", "dclk_csi2host"; + resets = <&cru SRST_PRESETN_CSI2HOST3>; + reset-names = "srst_csihost_p"; + status = "okay"; + }; + + csi2_dphy0_hw: csi2-dphy0-hw@21c40000 { + compatible = "rockchip,rv1126b-csi2-dphy-hw"; + reg = <0x21c40000 0x10000>; + clocks = <&cru PCLK_CSIPHY0>; + clock-names = "pclk"; + resets = <&cru SRST_PRESETN_CSIPHY0>; + reset-names = "srst_p_csiphy0"; + rockchip,grf = <&grf>; + status = "okay"; + }; + + csi2_dphy1_hw: csi2-dphy1-hw@21c50000 { + compatible = "rockchip,rv1126b-csi2-dphy-hw"; + reg = <0x21c50000 0x10000>; + clocks = <&cru PCLK_CSIPHY1>; + clock-names = "pclk"; + resets = <&cru SRST_PRESETN_CSIPHY1>; + reset-names = "srst_p_csiphy1"; + rockchip,grf = <&grf>; + status = "okay"; + }; + + gmac: ethernet@21c70000 { + compatible = "rockchip,rv1126b-gmac", "snps,dwmac-4.20a"; + reg = <0x21c70000 0x10000>; + interrupts = , + ; + interrupt-names = "macirq", "eth_wake_irq"; + rockchip,grf = <&grf>; + rockchip,php_grf = <&ioc_grf>; + clocks = <&cru CLK_GMAC_125M>, <&cru CLK_50M_GMAC_IOBUF_VI>, + <&cru PCLK_GMAC>, <&cru ACLK_GMAC>, + <&cru CLK_GMAC_PTP_REF>; + clock-names = "stmmaceth", "clk_mac_ref", + "pclk_mac", "aclk_mac", + "ptp_ref"; + resets = <&cru SRST_ARESETN_GMAC>; + reset-names = "stmmaceth"; + + snps,mixed-burst; + snps,tso; + + snps,axi-config = <&gmac0_stmmac_axi_setup>; + snps,mtl-rx-config = <&gmac0_mtl_rx_setup>; + snps,mtl-tx-config = <&gmac0_mtl_tx_setup>; + status = "disabled"; + + mdio: mdio { + compatible = "snps,dwmac-mdio"; + #address-cells = <0x1>; + #size-cells = <0x0>; + }; + + gmac0_stmmac_axi_setup: stmmac-axi-config { + snps,wr_osr_lmt = <4>; + snps,rd_osr_lmt = <8>; + snps,blen = <0 0 0 0 16 8 4>; + }; + + gmac0_mtl_rx_setup: rx-queues-config { + snps,rx-queues-to-use = <1>; + queue0 { + status = "okay"; + }; + }; + + gmac0_mtl_tx_setup: tx-queues-config { + snps,tx-queues-to-use = <1>; + queue0 { + status = "okay"; + }; + }; + }; + + dsmc: dsmc@21ca0000 { + compatible = "rockchip,rv1126b-dsmc", "rockchip,rk3506-dsmc"; + reg = <0x21ca0000 0x10000>; + rockchip,grf = <&grf>; + interrupts = ; + resets = <&cru SRST_ARESETN_DSMC>, <&cru SRST_PRESETN_DSMC>; + reset-names = "dsmc", "apb"; + clocks = <&cru CLK_SYS_DSMC_ROOT>, + <&cru ACLK_DSMC>, + <&cru PCLK_DSMC>, + <&cru CLK_SYS_DSMC_ROOT>; + clock-names = "clk_sys", "aclk_dsmc", "pclk", "aclk_root"; + clock-frequency = <100000000>; + dmas = <&dmac 46>, <&dmac 47>; + dma-names = "req0", "req1"; + pinctrl-names = "default", "active", "lb-slave"; + pinctrl-0 = <&dsmc_csn_idle + &dsmc_bus16_pins + &dsmc_clk_pins>; + pinctrl-1 = <&dsmc_csn_pins>; + pinctrl-2 = <&dsmc_int_pins>; + status = "disabled"; + slave { + rockchip,dqs-dll = <0x20 0x20 + 0x20 0x20 + 0x20 0x20 + 0x20 0x20>; + rockchip,ranges = <0x0 0x10000000 0x0 0x2000000>; + rockchip,slave-dev = <&dsmc_slave>; + }; + }; + + dsmc_slave: dsmc-slave { + compatible = "rockchip,dsmc-slave"; + rockchip,clk-mode = <0>; + status = "disabled"; + psram { + dsmc_psram0: psram0 { + status = "disabled"; + }; + dsmc_psram1: psram1 { + status = "disabled"; + }; + dsmc_psram2: psram2 { + status = "disabled"; + }; + dsmc_psram3: psram3 { + status = "disabled"; + }; + }; + + lb-slave { + dsmc_lb_slave0: lb-slave0 { + rockchip,mtr-timing = <1 0 0 0 0 0 2 2>; + rockchip,int-en = <0x0>; + status = "disabled"; + dsmc_p0_region: region { + dsmc_p0_region0: region0 { + rockchip,attribute = "Merged FIFO"; + rockchip,ca-addr-width = <0>; + rockchip,dummy-clk-num = <1>; + rockchip,cs0-be-ctrled = <0>; + rockchip,cs0-ctrl = <0>; + status = "disabled"; + }; + dsmc_p0_region1: region1 { + rockchip,attribute = "No-Merge FIFO"; + rockchip,ca-addr-width = <0>; + rockchip,dummy-clk-num = <1>; + rockchip,cs0-be-ctrled = <0>; + rockchip,cs0-ctrl = <0>; + status = "disabled"; + }; + dsmc_p0_region2: region2 { + rockchip,attribute = "DPRA"; + rockchip,ca-addr-width = <0>; + rockchip,dummy-clk-num = <1>; + rockchip,cs0-be-ctrled = <0>; + rockchip,cs0-ctrl = <0>; + status = "disabled"; + }; + dsmc_p0_region3: region3 { + rockchip,attribute = "Register"; + rockchip,ca-addr-width = <0>; + rockchip,dummy-clk-num = <1>; + rockchip,cs0-be-ctrled = <0>; + rockchip,cs0-ctrl = <0>; + status = "disabled"; + }; + }; + }; + dsmc_lb_slave1: lb-slave1 { + rockchip,mtr-timing = <1 0 0 0 0 0 2 2>; + rockchip,int-en = <0x1>; + status = "disabled"; + dsmc_p1_region: region { + dsmc_p1_region0: region0 { + rockchip,attribute = "Merged FIFO"; + rockchip,ca-addr-width = <0>; + rockchip,dummy-clk-num = <1>; + rockchip,cs0-be-ctrled = <0>; + rockchip,cs0-ctrl = <0>; + status = "disabled"; + }; + dsmc_p1_region1: region1 { + rockchip,attribute = "No-Merge FIFO"; + rockchip,ca-addr-width = <0>; + rockchip,dummy-clk-num = <1>; + rockchip,cs0-be-ctrled = <0>; + rockchip,cs0-ctrl = <0>; + status = "disabled"; + }; + dsmc_p1_region2: region2 { + rockchip,attribute = "DPRA"; + rockchip,ca-addr-width = <0>; + rockchip,dummy-clk-num = <1>; + rockchip,cs0-be-ctrled = <0>; + rockchip,cs0-ctrl = <0>; + status = "disabled"; + }; + dsmc_p1_region3: region3 { + rockchip,attribute = "Register"; + rockchip,ca-addr-width = <0>; + rockchip,dummy-clk-num = <1>; + rockchip,cs0-be-ctrled = <0>; + rockchip,cs0-ctrl = <0>; + status = "disabled"; + }; + }; + }; + dsmc_lb_slave2: lb-slave2 { + rockchip,mtr-timing = <1 0 0 0 0 0 2 2>; + rockchip,int-en = <0x2>; + status = "disabled"; + dsmc_p2_region: region { + dsmc_p2_region0: region0 { + rockchip,attribute = "Merged FIFO"; + rockchip,ca-addr-width = <0>; + rockchip,dummy-clk-num = <1>; + rockchip,cs0-be-ctrled = <0>; + rockchip,cs0-ctrl = <0>; + status = "disabled"; + }; + dsmc_p2_region1: region1 { + rockchip,attribute = "No-Merge FIFO"; + rockchip,ca-addr-width = <0>; + rockchip,dummy-clk-num = <1>; + rockchip,cs0-be-ctrled = <0>; + rockchip,cs0-ctrl = <0>; + status = "disabled"; + }; + dsmc_p2_region2: region2 { + rockchip,attribute = "DPRA"; + rockchip,ca-addr-width = <0>; + rockchip,dummy-clk-num = <1>; + rockchip,cs0-be-ctrled = <0>; + rockchip,cs0-ctrl = <0>; + status = "disabled"; + }; + dsmc_p2_region3: region3 { + rockchip,attribute = "Register"; + rockchip,ca-addr-width = <0>; + rockchip,dummy-clk-num = <1>; + rockchip,cs0-be-ctrled = <0>; + rockchip,cs0-ctrl = <0>; + status = "disabled"; + }; + }; + }; + dsmc_lb_slave3: lb-slave3 { + rockchip,mtr-timing = <1 0 0 0 0 0 2 2>; + rockchip,int-en = <0x3>; + status = "disabled"; + dsmc_p3_region: region { + dsmc_p3_region0: region0 { + rockchip,attribute = "Merged FIFO"; + rockchip,ca-addr-width = <0>; + rockchip,dummy-clk-num = <1>; + rockchip,cs0-be-ctrled = <0>; + rockchip,cs0-ctrl = <0>; + status = "disabled"; + }; + dsmc_p3_region1: region1 { + rockchip,attribute = "No-Merge FIFO"; + rockchip,ca-addr-width = <0>; + rockchip,dummy-clk-num = <1>; + rockchip,cs0-be-ctrled = <0>; + rockchip,cs0-ctrl = <0>; + status = "disabled"; + }; + dsmc_p3_region2: region2 { + rockchip,attribute = "DPRA"; + rockchip,ca-addr-width = <0>; + rockchip,dummy-clk-num = <1>; + rockchip,cs0-be-ctrled = <0>; + rockchip,cs0-ctrl = <0>; + status = "disabled"; + }; + dsmc_p3_region3: region3 { + rockchip,attribute = "Register"; + rockchip,ca-addr-width = <0>; + rockchip,dummy-clk-num = <1>; + rockchip,cs0-be-ctrled = <0>; + rockchip,cs0-ctrl = <0>; + status = "disabled"; + }; + }; + }; + }; + }; + + saradc1: saradc@21cb0000 { + compatible = "rockchip,rv1126b-saradc"; + reg = <0x21cb0000 0x10000>; + interrupts = ; + #io-channel-cells = <1>; + clocks = <&cru CLK_SARADC1>, <&cru PCLK_SARADC1>; + clock-names = "saradc", "apb_pclk"; + resets = <&cru SRST_PRESETN_SARADC1>; + reset-names = "saradc-apb"; + status = "disabled"; + }; + + saradc2: saradc@21cc0000 { + compatible = "rockchip,rv1126b-saradc"; + reg = <0x21cc0000 0x10000>; + interrupts = ; + #io-channel-cells = <1>; + clocks = <&cru CLK_SARADC2>, <&cru PCLK_SARADC2>; + clock-names = "saradc", "apb_pclk"; + resets = <&cru SRST_PRESETN_SARADC2>; + reset-names = "saradc-apb"; + status = "disabled"; + }; + + rkisp: isp@21d00000 { + compatible = "rockchip,rv1126b-rkisp"; + reg = <0x21d00000 0x7f00>, <0x21d30000 0x2f00>; + interrupts = , + , + , + , + ; + interrupt-names = "isp_mipi_irq", "isp_mi_irq", "isp_irq", + "vpsl_mi_irq", "vpsl_irq"; + clocks = <&cru HCLK_ISP>, <&cru ACLK_ISP>, + <&cru CLK_CORE_ISP>, <&cru ISP0CLK_VICAP>, + <&cru HCLK_VPSL>, <&cru ACLK_VPSL>, <&cru CLK_CORE_VPSL>; + clock-names = "hclk_isp", "aclk_isp", + "clk_isp_core", "clk_isp_vicap", + "hclk_vpsl", "aclk_vpsl", "clk_core_vpsl"; + iommus = <&rkisp_mmu>; + status = "disabled"; + }; + + rkisp_mmu: iommu@21d07f00 { + compatible = "rockchip,iommu-v2"; + reg = <0x21d07f00 0x100>, <0x21d32f00 0x100>; + interrupts = , ; + interrupt-names = "isp_mmu", "vpsl_mmu"; + clocks = <&cru ACLK_ISP>, <&cru HCLK_ISP>, + <&cru ACLK_VPSL>, <&cru HCLK_VPSL>; + clock-names = "aclk0", "iface0", "aclk1", "iface1"; + #iommu-cells = <0>; + rockchip,disable-mmu-reset; + status = "disabled"; + }; + + rkcif: rkcif@21d10000 { + compatible = "rockchip,rv1126b-cif"; + reg = <0x21d10000 0x1000>; + reg-names = "cif_regs"; + interrupts = ; + interrupt-names = "cif-intr"; + clocks = <&cru ACLK_VICAP>, <&cru HCLK_VICAP>, + <&cru DCLK_VICAP>, <&cru ISP0CLK_VICAP>; + clock-names = "aclk_cif", "hclk_cif", + "dclk_cif", "isp0clk_cif"; + resets = <&cru SRST_ARESETN_VICAP>, <&cru SRST_HRESETN_VICAP>, + <&cru SRST_DRESETN_VICAP>, <&cru SRST_ISP0RESETN_VICAP>; + reset-names = "rst_cif_a", "rst_cif_h", + "rst_cif_d", "rst_cif_isp0"; + rockchip,grf = <&grf>; + iommus = <&rkcif_mmu>; + status = "disabled"; + }; + + rkcif_mmu: iommu@21d10f00 { + compatible = "rockchip,iommu-v2"; + reg = <0x21d10f00 0x100>; + interrupts = ; + interrupt-names = "cif_mmu"; + clocks = <&cru ACLK_VICAP>, <&cru HCLK_VICAP>; + clock-names = "aclk", "iface"; + rockchip,disable-mmu-reset; + #iommu-cells = <0>; + status = "disabled"; + }; + + rkvpss: vpss@21d20000 { + compatible = "rockchip,rv1126b-rkvpss"; + reg = <0x21d20000 0x3f00>; + interrupts = , + ; + interrupt-names = "mi_irq", "vpss_irq"; + clocks = <&cru ACLK_VPSS>, <&cru HCLK_VPSS>, + <&cru CLK_CORE_VPSS>; + clock-names = "aclk_vpss", "hclk_vpss", "clk_vpss"; + iommus = <&rkvpss_mmu>; + status = "disabled"; + }; + + rkvpss_mmu: iommu@21d23f00 { + compatible = "rockchip,iommu-v2"; + reg = <0x21d23f00 0x100>; + interrupts = ; + interrupt-names = "vpss_mmu"; + clocks = <&cru ACLK_VPSS>, <&cru HCLK_VPSS>; + clock-names = "aclk", "iface"; + #iommu-cells = <0>; + rockchip,disable-mmu-reset; + status = "disabled"; + }; + + can0: can@21d40000 { + compatible = "rockchip,rv1126b-canfd"; + reg = <0x21d40000 0x1000>; + interrupts = ; + clocks = <&cru CLK_CAN0>, <&cru HCLK_CAN0>; + clock-names = "baudclk", "apb_pclk"; + resets = <&cru SRST_RESETN_CAN0>, <&cru SRST_HRESETN_CAN0>; + reset-names = "can", "can-apb"; + dmas = <&dmac 44>; + dma-names = "rx"; + status = "disabled"; + }; + + can1: can@21d50000 { + compatible = "rockchip,rv1126b-canfd"; + reg = <0x21d50000 0x1000>; + interrupts = ; + clocks = <&cru CLK_CAN1>, <&cru HCLK_CAN1>; + clock-names = "baudclk", "apb_pclk"; + resets = <&cru SRST_RESETN_CAN1>, <&cru SRST_HRESETN_CAN1>; + reset-names = "can", "can-apb"; + dmas = <&dmac 45>; + dma-names = "rx"; + status = "disabled"; + }; + + sdmmc0: mmc@21d60000 { + compatible = "rockchip,rv1126b-dw-mshc", "rockchip,rk3288-dw-mshc"; + reg = <0x21d60000 0x4000>; + interrupts = ; + clocks = <&cru HCLK_SDMMC0>, <&cru CCLK_SDMMC0>; + clock-names = "biu", "ciu"; + fifo-depth = <0x100>; + max-frequency = <200000000>; + pinctrl-names = "normal", "idle"; + pinctrl-0 = <&sdmmc0_clk_pins &sdmmc0_cmd_pins &sdmmc0_detn_pins &sdmmc0_bus4_pins>; + pinctrl-1 = <&sdmmc0_idle_pins &sdmmc0_detn_pins>; + status = "disabled"; + }; + + saradc0: saradc@21f10000 { + compatible = "rockchip,rv1126b-saradc"; + reg = <0x21f10000 0x10000>; + interrupts = ; + #io-channel-cells = <1>; + clocks = <&cru CLK_SARADC0>, <&cru PCLK_SARADC0>; + clock-names = "saradc", "apb_pclk"; + resets = <&cru SRST_PRESETN_SARADC0>; + reset-names = "saradc-apb"; + status = "disabled"; + }; + + rkvenc: rkvenc@21f40000 { + compatible = "rockchip,rkv-encoder-rv1126b", "rockchip,rkv-encoder-v2"; + reg = <0x21f40000 0x6000>; + interrupts = ; + interrupt-names = "irq_rkvenc"; + clocks = <&cru ACLK_VEPU>, <&cru HCLK_VEPU>, <&cru CLK_CORE_VEPU>; + clock-names = "aclk_vcodec", "hclk_vcodec", "clk_core"; + rockchip,normal-rates = <396000000>, <0>, <396000000>; + resets = <&cru SRST_ARESETN_VEPU>, <&cru SRST_HRESETN_VEPU>, + <&cru SRST_RESETN_CORE_VEPU>; + reset-names = "video_a", "video_h", "video_core"; + assigned-clocks = <&cru ACLK_VEPU>, <&cru CLK_CORE_VEPU>; + assigned-clock-rates = <396000000>, <396000000>; + iommus = <&rkvenc_mmu>; + rockchip,srv = <&mpp_srv>; + rockchip,taskqueue-node = <0>; + rockchip,resetgroup-node = <0>; + rockchip,skip-pmu-idle-request; + dvbm = <&rkdvbm>; + power-domains = <&power RV1126B_PD_VDO>; + status = "disabled"; + }; + + rkvenc_mmu: iommu@21f4f000 { + compatible = "rockchip,iommu-v2"; + reg = <0x21f4f000 0x100>; + interrupts = ; + interrupt-names = "rkvenc_mmu"; + clocks = <&cru ACLK_VEPU>, <&cru HCLK_VEPU>; + clock-names = "aclk", "iface"; + #iommu-cells = <0>; + rockchip,shootdown-entire; + rockchip,enable-cmd-retry; + power-domains = <&power RV1126B_PD_VDO>; + status = "disabled"; + }; + + sdmmc1: mmc@21f60000 { + compatible = "rockchip,rv1126b-dw-mshc", "rockchip,rk3288-dw-mshc"; + reg = <0x21f60000 0x4000>; + interrupts = ; + clocks = <&cru HCLK_SDMMC1>, <&cru CCLK_SDMMC1>; + clock-names = "biu", "ciu"; + fifo-depth = <0x100>; + max-frequency = <200000000>; + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc1_clk_pins &sdmmc1_cmd_pins &sdmmc1_detn_pins &sdmmc1_bus4_pins>; + status = "disabled"; + }; + + rkfec: rkfec@21f80000 { + compatible = "rockchip,rv1126b-rkfec"; + reg = <0x21f80000 0xf00>; + interrupts = ; + interrupt-names = "fec_irq"; + clocks = <&cru ACLK_FEC>, <&cru HCLK_FEC>, <&cru CLK_CORE_FEC>; + clock-names = "aclk_fec", "hclk_fec", "clk_fec"; + iommus = <&rkfec_mmu>; + status = "disabled"; + }; + + rkfec_mmu: iommu@21f80f00 { + compatible = "rockchip,iommu-v2"; + reg = <0x21f80f00 0x100>; + interrupts = ; + interrupt-names = "fec_mmu"; + clocks = <&cru ACLK_FEC>, <&cru HCLK_FEC>; + clock-names = "aclk", "iface"; + #iommu-cells = <0>; + rockchip,disable-mmu-reset; + status = "disabled"; + }; + + rkavsp: rkavsp@21f90000 { + compatible = "rockchip,rv1126b-rkavsp"; + reg = <0x21f90000 0xf00>; + interrupts = , ; + interrupt-names = "dcp_irq", "rcs_irq"; + clocks = <&cru ACLK_AVSP>, <&cru HCLK_AVSP>; + clock-names = "aclk_avsp", "hclk_avsp"; + iommus = <&rkavsp_mmu>; + status = "disabled"; + }; + + rkavsp_mmu: iommu@21f90f00 { + compatible = "rockchip,iommu-v2"; + reg = <0x21f90f00 0x100>; + interrupts = ; + interrupt-names = "avsp_mmu"; + clocks = <&cru ACLK_AVSP>, <&cru HCLK_AVSP>; + clock-names = "aclk", "iface"; + #iommu-cells = <0>; + rockchip,disable-mmu-reset; + status = "disabled"; + }; + + rkaiisp: rkaiisp@21fa0000 { + compatible = "rockchip,rv1126b-rkaiisp"; + reg = <0x21fa0000 0x3f00>; + interrupts = ; + interrupt-names = "irq"; + clocks = <&cru ACLK_AISP>, <&cru HCLK_AISP>, + <&cru CLK_CORE_AISP>; + clock-names = "aclk_aiisp", "hclk_aiisp", "clk_aiisp_core"; + iommus = <&rkaiisp_mmu>; + power-domains = <&power RV1126B_PD_AISP>; + status = "disabled"; + }; + + rkaiisp_mmu: iommu@21fa3f00 { + compatible = "rockchip,iommu-v2"; + reg = <0x21fa3f00 0x100>; + interrupts = ; + interrupt-names = "aiisp_mmu"; + clocks = <&cru ACLK_AISP>, <&cru HCLK_AISP>; + clock-names = "aclk", "iface"; + power-domains = <&power RV1126B_PD_AISP>; + rockchip,disable-mmu-reset; + #iommu-cells = <0>; + status = "disabled"; + }; + + rknpu: npu@22000000 { + compatible = "rockchip,rv1126b-rknpu"; + reg = <0x22000000 0x8000>; + interrupts = ; + interrupt-names = "npu_irq"; + clocks = <&cru ACLK_RKNN>, <&cru HCLK_RKNN>; + clock-names = "aclk", "hclk"; + assigned-clocks = <&cru ACLK_RKNN>; + assigned-clock-rates = <800000000>; + operating-points-v2 = <&npu_opp_table>; + resets = <&cru SRST_ARESETN_RKNN>, <&cru SRST_HRESETN_RKNN>; + reset-names = "srst_a", "srst_h"; + power-domains = <&power RV1126B_PD_NPU>; + iommus = <&rknpu_mmu>; + status = "disabled"; + }; + + npu_opp_table: npu-opp-table { + compatible = "operating-points-v2"; + + nvmem-cells = <&npu_leakage>; + nvmem-cell-names = "leakage"; + + opp-396000000 { + opp-hz = /bits/ 64 <396000000>; + opp-microvolt = <900000 900000 1000000>; + }; + opp-594000000 { + opp-hz = /bits/ 64 <594000000>; + opp-microvolt = <900000 900000 1000000>; + }; + }; + + rknpu_mmu: iommu@22002000 { + compatible = "rockchip,iommu-v2"; + reg = <0x22002000 0x100>; + interrupts = ; + interrupt-names = "rknpu_mmu"; + clocks = <&cru ACLK_RKNN>, <&cru HCLK_RKNN>; + clock-names = "aclk", "hclk"; + power-domains = <&power RV1126B_PD_NPU>; + #iommu-cells = <0>; + status = "disabled"; + }; + + hw_decompress: decompress@22100000 { + compatible = "rockchip,hw-decompress"; + reg = <0x22100000 0x1000>; + interrupts = ; + clocks = <&cru ACLK_DECOM>, <&cru DCLK_DECOM>, <&cru PCLK_DECOM>; + clock-names = "aclk", "dclk", "pclk"; + resets = <&cru SRST_DRESETN_DECOM>; + reset-names = "dresetn"; + status = "disabled"; + }; + + mipi_dphy: mipi-dphy@22110000 { + compatible = "rockchip,rv1126b-dsi-dphy", "rockchip,rv1126-dsi-dphy"; + reg = <0x22110000 0x500>, <0x22120000 0x500>; + reg-names = "phy", "host"; + assigned-clock-rates = <24000000>; + clocks = <&xin24m>, <&cru PCLK_DSIPHY>, <&cru PCLK_MIPI_DSI>; + clock-names = "ref", "pclk", "pclk_host"; + #clock-cells = <0>; + resets = <&cru SRST_PRESETN_DSIPHY>; + reset-names = "apb"; + #phy-cells = <0>; + rockchip,grf = <&grf>; + status = "disabled"; + }; + + dsi: dsi@22120000 { + compatible = "rockchip,rv1126b-mipi-dsi"; + reg = <0x22120000 0x500>; + interrupts = ; + clocks = <&cru PCLK_MIPI_DSI>; + clock-names = "pclk"; + resets = <&cru SRST_PRESETN_MIPI_DSI>; + reset-names = "apb"; + phys = <&mipi_dphy>; + phy-names = "dphy"; + rockchip,grf = <&grf>; + #address-cells = <1>; + #size-cells = <0>; + power-domains = <&power RV1126B_PD_VDO>; + status = "disabled"; + + ports { + port { + dsi_in_vop: endpoint { + remote-endpoint = <&vop_out_dsi>; + }; + }; + }; + }; + + rkvdec: rkvdec@22140100 { + compatible = "rockchip,rkv-decoder-rv1126b", "rockchip,rkv-decoder-v384a"; + reg = <0x22140100 0x600>, <0x22140000 0x100>; + reg-names = "regs", "link"; + interrupts = ; + interrupt-names = "irq_rkvdec"; + clocks = <&cru ACLK_RKVDEC>, <&cru HCLK_RKVDEC>, <&cru CLK_HEVC_CA_RKVDEC>; + clock-names = "aclk_vcodec", "hclk_vcodec", "clk_hevc_cabac"; + resets = <&cru SRST_ARESETN_VDO_BIU >, <&cru SRST_HRESETN_VDO_BIU>, + <&cru SRST_RESETN_HEVC_CA_RKVDEC>; + reset-names = "video_a","video_h", "video_hevc_cabac"; + rockchip,normal-rates = <300000000>, <0>, <300000000>; + assigned-clocks = <&cru ACLK_RKVDEC>, <&cru HCLK_RKVDEC>, <&cru CLK_HEVC_CA_RKVDEC>; + assigned-clock-rates = <300000000>, <0>, <300000000>; + iommus = <&rkvdec_mmu>; + rockchip,srv = <&mpp_srv>; + rockchip,task-capacity = <8>; + rockchip,taskqueue-node = <1>; + rockchip,resetgroup-node = <1>; + rockchip,skip-pmu-idle-request; + power-domains = <&power RV1126B_PD_VDO>; + status = "disabled"; + }; + + rkvdec_mmu: iommu@22140800 { + compatible = "rockchip,iommu-v2"; + reg = <0x22140800 0x40>, <0x22140900 0x40>; + interrupts = ; + interrupt-names = "irq_rkvdec_mmu"; + clocks = <&cru ACLK_RKVDEC>, <&cru HCLK_RKVDEC>, <&cru CLK_HEVC_CA_RKVDEC>; + clock-names = "aclk", "iface", "iface_c"; + rockchip,enable-cmd-retry; + rockchip,shootdown-entire; + #iommu-cells = <0>; + power-domains = <&power RV1126B_PD_VDO>; + status = "disabled"; + }; + + vop: vop@22150000 { + compatible = "rockchip,rv1126b-vop"; + reg = <0x22150000 0x200>, <0x22150a00 0x400>; + reg-names = "regs", "gamma_lut"; + rockchip,grf = <&ioc_grf>; + interrupts = ; + clocks = <&cru ACLK_VOP>, <&cru DCLK_VOP>, <&cru HCLK_VOP>; + clock-names = "aclk_vop", "dclk_vop", "hclk_vop"; + iommus = <&vop_mmu>; + status = "disabled"; + + vop_out: port { + #address-cells = <1>; + #size-cells = <0>; + + vop_out_rgb: endpoint@0 { + reg = <0>; + remote-endpoint = <&rgb_in_vop>; + }; + + vop_out_dsi: endpoint@1 { + reg = <1>; + remote-endpoint = <&dsi_in_vop>; + }; + }; + }; + + vop_mmu: iommu@22150f00 { + compatible = "rockchip,iommu-v2"; + reg = <0x22150f00 0x100>; + interrupts = ; + interrupt-names = "vop_mmu"; + clocks = <&cru ACLK_VOP>, <&cru HCLK_VOP>; + clock-names = "aclk", "iface"; + #iommu-cells = <0>; + rockchip,disable-device-link-resume; + status = "disabled"; + }; + + jpegd: jpegd@22170000 { + compatible = "rockchip,rkv-jpeg-decoder-v1"; + reg = <0x22170000 0x330>; + interrupts = ; + interrupt-names = "irq_jpegd"; + clocks = <&cru ACLK_RKJPEG>, <&cru HCLK_RKJPEG>; + clock-names = "aclk_vcodec", "hclk_vcodec"; + rockchip,normal-rates = <400000000>, <0>; + assigned-clocks = <&cru ACLK_RKJPEG>; + assigned-clock-rates = <400000000>; + resets = <&cru SRST_ARESETN_RKJPEG>, <&cru SRST_HRESETN_RKJPEG>; + reset-names = "video_a", "video_h"; + rockchip,skip-pmu-idle-request; + iommus = <&jpeg_mmu>; + rockchip,srv = <&mpp_srv>; + rockchip,taskqueue-node = <2>; + rockchip,resetgroup-node = <2>; + power-domains = <&power RV1126B_PD_VDO>; + status = "disabled"; + }; + + jpeg_mmu: iommu@22170f00 { + compatible = "rockchip,iommu-v2"; + reg = <0x22170f00 0x28>; + interrupts = ; + interrupt-names = "irq_jpeg_mmu"; + clocks = <&cru ACLK_RKJPEG>, <&cru HCLK_RKJPEG>; + clock-name = "aclk", "iface"; + #iommu-cells = <0>; + rockchip,shootdown-entire; + power-domains = <&power RV1126B_PD_VDO>; + status = "disabled"; + }; + + decom_mmu: iommu@22180000 { + compatible = "rockchip,iommu-v2"; + reg = <0x22180000 0x100>; + interrupts = ; + interrupt-names = "decom_mmu"; + clocks = <&cru ACLK_RKMMU_DECOM>, <&cru HCLK_RKMMU_DECOM>; + clock-names = "aclk", "iface"; + #iommu-cells = <0>; + status = "disabled"; + }; + + system_sram: sram@3ffb0000 { + compatible = "mmio-sram"; + reg = <0x3ffb0000 0x10000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x3ffb0000 0x10000>; + }; + + pinctrl: pinctrl { + compatible = "rockchip,rv1126b-pinctrl"; + rockchip,grf = <&ioc_grf>; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + gpio0: gpio@20600000 { + compatible = "rockchip,gpio-bank"; + reg = <0x20600000 0x200>; + interrupts = ; + clocks = <&cru PCLK_PMU_GPIO0>, <&cru DBCLK_PMU_GPIO0>; + + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&pinctrl 0 0 32>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio1: gpio@21300000 { + compatible = "rockchip,gpio-bank"; + reg = <0x21300000 0x200>; + interrupts = ; + clocks = <&cru PCLK_GPIO1>, <&cru DBCLK_GPIO1>; + + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&pinctrl 0 32 32>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio2: gpio@21700000 { + compatible = "rockchip,gpio-bank"; + reg = <0x21700000 0x200>; + interrupts = ; + clocks = <&cru PCLK_GPIO2>, <&cru DBCLK_GPIO2>; + + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&pinctrl 0 64 32>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio3: gpio@21e00000 { + compatible = "rockchip,gpio-bank"; + reg = <0x21e00000 0x200>; + interrupts = ; + clocks = <&cru PCLK_GPIO3>, <&cru DBCLK_GPIO3>; + + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&pinctrl 0 96 32>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio4: gpio@21800000 { + compatible = "rockchip,gpio-bank"; + reg = <0x21800000 0x200>; + interrupts = ; + clocks = <&cru PCLK_GPIO4>, <&cru DBCLK_GPIO4>; + + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&pinctrl 0 128 32>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio5: gpio@21900000 { + compatible = "rockchip,gpio-bank"; + reg = <0x21900000 0x200>; + interrupts = ; + clocks = <&cru PCLK_GPIO5>, <&cru DBCLK_GPIO5>; + + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&pinctrl 0 160 32>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio6: gpio@21a00000 { + compatible = "rockchip,gpio-bank"; + reg = <0x21a00000 0x200>; + interrupts = ; + clocks = <&cru PCLK_GPIO6>, <&cru DBCLK_GPIO6>; + + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&pinctrl 0 192 32>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio7: gpio@21b00000 { + compatible = "rockchip,gpio-bank"; + reg = <0x21b00000 0x200>; + interrupts = ; + clocks = <&cru PCLK_GPIO7>, <&cru DBCLK_GPIO7>; + + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&pinctrl 0 224 32>; + interrupt-controller; + #interrupt-cells = <2>; + }; + }; +}; + +#include "rv1126b-pinctrl.dtsi" diff --git a/u-boot/arch/arm/include/asm/arch-rockchip/cru_rv1126b.h b/u-boot/arch/arm/include/asm/arch-rockchip/cru_rv1126b.h new file mode 100644 index 00000000000..31ef3e2c7b8 --- /dev/null +++ b/u-boot/arch/arm/include/asm/arch-rockchip/cru_rv1126b.h @@ -0,0 +1,387 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (c) 2025 Rockchip Electronics Co. Ltd. + * Author: Elaine Zhang + */ + +#ifndef _ASM_ARCH_CRU_RV1126B_H +#define _ASM_ARCH_CRU_RV1126B_H + +#include + +#define MHz 1000000 +#define KHz 1000 +#define OSC_HZ (24 * MHz) +#define RC_OSC_HZ (125 * MHz) + +#define GPLL_HZ (1188 * MHz) +#define AUPLL_HZ (983040000) +#define CPLL_HZ (1000 * MHz) + +/* RV1126B pll id */ +enum rv1126b_pll_id { + GPLL, + AUPLL, + CPLL, + PLL_COUNT, +}; + +struct rv1126b_clk_info { + unsigned long id; + char *name; + bool is_cru; +}; + +struct rv1126b_clk_priv { + struct rv1126b_cru *cru; + struct rv1126b_grf *grf; + ulong gpll_hz; + ulong aupll_hz; + ulong cpll_hz; + ulong armclk_hz; + ulong armclk_enter_hz; + ulong armclk_init_hz; + bool sync_kernel; + bool set_armclk_rate; +}; + +struct rv1126b_grf_clk_priv { + struct rv1126b_grf *grf; +}; + +struct rv1126b_pll { + unsigned int con0; + unsigned int con1; + unsigned int con2; + unsigned int con3; + unsigned int con4; + unsigned int reserved0[3]; +}; + +struct rv1126b_cru { + struct rv1126b_pll pll[2]; + unsigned int reserved0[176]; + unsigned int clksel_con[71]; + unsigned int reserved1[249]; + unsigned int clkgate_con[16]; + unsigned int reserved2[112]; + unsigned int softrst_con[16]; + unsigned int reserved3[112]; + unsigned int glb_cnt_th; + unsigned int glb_rst_st; + unsigned int glb_srst_fst; + unsigned int glb_srst_snd; + unsigned int glb_rst_con[3]; + unsigned int reserved4[41]; + unsigned int clk_cm_frac0_div_h; + unsigned int clk_cm_frac1_div_h; + unsigned int clk_cm_frac2_div_h; + unsigned int clk_uart_frac0_div_h; + unsigned int clk_uart_frac1_div_h; + unsigned int clk_audio_frac0_div_h; + unsigned int clk_audio_frac1_div_h; + unsigned int reserved5[15753]; + unsigned int bus_clksel_con[4]; + unsigned int reserved6[316]; + unsigned int bus_clkgate_con[7]; + unsigned int reserved7[121]; + unsigned int bus_softrst_con[8]; + unsigned int reserved8[15928]; + unsigned int peri_clksel_con[2]; + unsigned int reserved9[318]; + unsigned int peri_clkgate_con[2]; + unsigned int reserved10[126]; + unsigned int peri_softrst_con[2]; + unsigned int reserved11[15934]; + unsigned int core_clksel_con[3]; + unsigned int reserved12[317]; + unsigned int core_clkgate_con[2]; + unsigned int reserved13[126]; + unsigned int core_softrst_con[2]; + unsigned int reserved14[15934]; + unsigned int pmu_clksel_con[9]; + unsigned int reserved15[311]; + unsigned int pmu_clkgate_con[4]; + unsigned int reserved16[124]; + unsigned int pmu_softrst_con[4]; + unsigned int reserved17[15932]; + unsigned int pmu1_clksel_con[2]; + unsigned int reserved18[318]; + unsigned int pmu1_clkgate_con[2]; + unsigned int reserved19[126]; + unsigned int pmu1_softrst_con[2]; + unsigned int reserved20[32318]; + unsigned int vi_clksel_con[1]; + unsigned int reserved21[319]; + unsigned int vi_clkgate_con[5]; + unsigned int reserved22[123]; + unsigned int vi_softrst_con[4]; +}; + +check_member(rv1126b_cru, clksel_con[0], 0x300); +check_member(rv1126b_cru, clkgate_con[0], 0x800); +check_member(rv1126b_cru, softrst_con[0], 0xa00); +check_member(rv1126b_cru, clk_cm_frac0_div_h, 0xcc0); +check_member(rv1126b_cru, bus_clksel_con[0], 0x10300); +check_member(rv1126b_cru, bus_clkgate_con[0], 0x10800); +check_member(rv1126b_cru, bus_softrst_con[0], 0x10a00); +check_member(rv1126b_cru, peri_clksel_con[0], 0x20300); +check_member(rv1126b_cru, peri_clkgate_con[0], 0x20800); +check_member(rv1126b_cru, peri_softrst_con[0], 0x20a00); +check_member(rv1126b_cru, core_clksel_con[0], 0x30300); +check_member(rv1126b_cru, core_clkgate_con[0], 0x30800); +check_member(rv1126b_cru, core_softrst_con[0], 0x30a00); +check_member(rv1126b_cru, pmu_clksel_con[0], 0x40300); +check_member(rv1126b_cru, pmu_clkgate_con[0], 0x40800); +check_member(rv1126b_cru, pmu_softrst_con[0], 0x40a00); +check_member(rv1126b_cru, pmu1_clksel_con[0], 0x50300); +check_member(rv1126b_cru, pmu1_clkgate_con[0], 0x50800); +check_member(rv1126b_cru, pmu1_softrst_con[0], 0x50a00); +check_member(rv1126b_cru, vi_clksel_con[0], 0x70300); +check_member(rv1126b_cru, vi_clkgate_con[0], 0x70800); +check_member(rv1126b_cru, vi_softrst_con[0], 0x70a00); + +struct pll_rate_table { + unsigned long rate; + unsigned int fbdiv; + unsigned int postdiv1; + unsigned int refdiv; + unsigned int postdiv2; + unsigned int dsmpd; + unsigned int frac; +}; + +#define RV1126B_CRU_BASE 0x20000000 +#define RV1126B_TOPCRU_BASE 0x0 +#define RV1126B_BUSCRU_BASE 0x10000 +#define RV1126B_PERICRU_BASE 0x20000 +#define RV1126B_CORECRU_BASE 0x30000 +#define RV1126B_PMUCRU_BASE 0x40000 +#define RV1126B_PMU1CRU_BASE 0x50000 +#define RV1126B_DDRCRU_BASE 0x60000 +#define RV1126B_SUBDDRCRU_BASE 0x68000 +#define RV1126B_VICRU_BASE 0x70000 +#define RV1126B_VEPUCRU_BASE 0x80000 +#define RV1126B_NPUCRU_BASE 0x90000 +#define RV1126B_VDOCRU_BASE 0xA0000 +#define RV1126B_VCPCRU_BASE 0xB0000 + +#define RV1126B_PLL_CON(x) ((x) * 0x4 + RV1126B_TOPCRU_BASE) +#define RV1126B_MODE_CON (0x280 + RV1126B_TOPCRU_BASE) +#define RV1126B_CLKSEL_CON(x) ((x) * 0x4 + 0x300 + RV1126B_TOPCRU_BASE) +#define RV1126B_PERIPLL_CON(x) ((x) * 0x4 + RV1126B_PERICRU_BASE) +#define RV1126B_SUBDDRPLL_CON(x) ((x) * 0x4 + RV1126B_SUBDDRCRU_BASE) + +enum { + /* CRU_CLK_SEL10_CON */ + CLK_AUDIO_FRAC1_SRC_SEL_SHIFT = 12, + CLK_AUDIO_FRAC1_SRC_SEL_MASK = 0x3 << CLK_AUDIO_FRAC1_SRC_SEL_SHIFT, + CLK_AUDIO_FRAC0_SRC_SEL_SHIFT = 10, + CLK_AUDIO_FRAC0_SRC_SEL_MASK = 0x3 << CLK_AUDIO_FRAC0_SRC_SEL_SHIFT, + CLK_UART_FRAC1_SRC_SEL_SHIFT = 8, + CLK_UART_FRAC1_SRC_SEL_MASK = 0x3 << CLK_UART_FRAC1_SRC_SEL_SHIFT, + CLK_UART_FRAC0_SRC_SEL_SHIFT = 6, + CLK_UART_FRAC0_SRC_SEL_MASK = 0x3 << CLK_UART_FRAC0_SRC_SEL_SHIFT, + CLK_CM_FRAC2_SRC_SEL_SHIFT = 4, + CLK_CM_FRAC2_SRC_SEL_MASK = 0x3 << CLK_CM_FRAC2_SRC_SEL_SHIFT, + CLK_CM_FRAC1_SRC_SEL_SHIFT = 2, + CLK_CM_FRAC1_SRC_SEL_MASK = 0x3 << CLK_CM_FRAC1_SRC_SEL_SHIFT, + CLK_CM_FRAC0_SRC_SEL_SHIFT = 0, + CLK_CM_FRAC0_SRC_SEL_MASK = 0x3 << CLK_CM_FRAC0_SRC_SEL_SHIFT, + CLK_FRAC_SRC_SEL_24M = 0, + CLK_FRAC_SRC_SEL_GPLL, + CLK_FRAC_SRC_SEL_AUPLL, + CLK_FRAC_SRC_SEL_CPLL, + + /* CRU_CLK_SEL12_CON */ + SCLK_UART1_SEL_SHIFT = 13, + SCLK_UART1_SEL_MASK = 0x7 << SCLK_UART1_SEL_SHIFT, + SCLK_UART1_DIV_SHIFT = 8, + SCLK_UART1_DIV_MASK = 0x1f << SCLK_UART1_DIV_SHIFT, + SCLK_UART0_SRC_SEL_SHIFT = 5, + SCLK_UART0_SRC_SEL_MASK = 0x7 << SCLK_UART0_SRC_SEL_SHIFT, + SCLK_UART_SEL_OSC = 0, + SCLK_UART_SEL_CM_FRAC0, + SCLK_UART_SEL_CM_FRAC1, + SCLK_UART_SEL_CM_FRAC2, + SCLK_UART_SEL_UART_FRAC0, + SCLK_UART_SEL_UART_FRAC1, + SCLK_UART0_SRC_DIV_SHIFT = 0, + SCLK_UART0_SRC_DIV_MASK = 0x1f << SCLK_UART0_SRC_DIV_SHIFT, + + /* CRU_CLK_SEL13_CON */ + SCLK_UART3_SEL_SHIFT = 13, + SCLK_UART3_SEL_MASK = 0x7 << SCLK_UART3_SEL_SHIFT, + SCLK_UART3_DIV_SHIFT = 8, + SCLK_UART3_DIV_MASK = 0x1f << SCLK_UART3_DIV_SHIFT, + SCLK_UART2_SEL_SHIFT = 5, + SCLK_UART2_SEL_MASK = 0x7 << SCLK_UART2_SEL_SHIFT, + SCLK_UART2_DIV_SHIFT = 0, + SCLK_UART2_DIV_MASK = 0x1f << SCLK_UART2_DIV_SHIFT, + + /* CRU_CLK_SEL14_CON */ + SCLK_UART5_SEL_SHIFT = 13, + SCLK_UART5_SEL_MASK = 0x7 << SCLK_UART5_SEL_SHIFT, + SCLK_UART5_DIV_SHIFT = 8, + SCLK_UART5_DIV_MASK = 0x1f << SCLK_UART5_DIV_SHIFT, + SCLK_UART4_SEL_SHIFT = 5, + SCLK_UART4_SEL_MASK = 0x7 << SCLK_UART4_SEL_SHIFT, + SCLK_UART4_DIV_SHIFT = 0, + SCLK_UART4_DIV_MASK = 0x1f << SCLK_UART4_DIV_SHIFT, + + /* CRU_CLK_SEL15_CON */ + SCLK_UART7_SEL_SHIFT = 13, + SCLK_UART7_SEL_MASK = 0x7 << SCLK_UART7_SEL_SHIFT, + SCLK_UART7_DIV_SHIFT = 8, + SCLK_UART7_DIV_MASK = 0x1f << SCLK_UART7_DIV_SHIFT, + SCLK_UART6_SEL_SHIFT = 5, + SCLK_UART6_SEL_MASK = 0x7 << SCLK_UART6_SEL_SHIFT, + SCLK_UART6_DIV_SHIFT = 0, + SCLK_UART6_DIV_MASK = 0x1f << SCLK_UART6_DIV_SHIFT, + + /* CRU_CLK_SEL25_CON */ + CLK_FRAC_NUMERATOR_SHIFT = 16, + CLK_FRAC_NUMERATOR_MASK = 0xffff << 16, + CLK_FRAC_DENOMINATOR_SHIFT = 0, + CLK_FRAC_DENOMINATOR_MASK = 0xffff, + CLK_FRAC_H_NUMERATOR_SHIFT = 8, + CLK_FRAC_H_NUMERATOR_MASK = 0xff << 8, + CLK_FRAC_H_DENOMINATOR_SHIFT = 0, + CLK_FRAC_H_DENOMINATOR_MASK = 0xff, + + /* CRU_CLK_SEL43_CON */ + DCLK_VOP_SEL_SHIFT = 8, + DCLK_VOP_SEL_MASK = 0x1 << DCLK_VOP_SEL_SHIFT, + DCLK_VOP_SEL_GPLL = 0, + DCLK_VOP_SEL_CPLL, + DCLK_VOP_DIV_SHIFT = 0, + DCLK_VOP_DIV_MASK = 0xff << DCLK_VOP_DIV_SHIFT, + + /* CRU_CLK_SEL44_CON */ + HCLK_BUS_SEL_SHIFT = 10, + HCLK_BUS_SEL_MASK = 0x1 << HCLK_BUS_SEL_SHIFT, + HCLK_BUS_SEL_200M = 0, + HCLK_BUS_SEL_100M, + ACLK_BUS_SEL_SHIFT = 8, + ACLK_BUS_SEL_MASK = 0x3 << ACLK_BUS_SEL_SHIFT, + ACLK_BUS_SEL_400M = 0, + ACLK_BUS_SEL_300M, + ACLK_BUS_SEL_200M, + ACLK_TOP_SEL_SHIFT = 6, + ACLK_TOP_SEL_MASK = 0x3 << ACLK_TOP_SEL_SHIFT, + ACLK_TOP_SEL_600M = 0, + ACLK_TOP_SEL_400M, + ACLK_TOP_SEL_200M, + + /* CRU_CLK_SEL45_CON */ + CLK_SDMMC_SEL_SHIFT = 8, + CLK_SDMMC_SEL_MASK = 0x3 << CLK_SDMMC_SEL_SHIFT, + CLK_SDMMC_SEL_GPLL = 0, + CLK_SDMMC_SEL_CPLL, + CLK_SDMMC_SEL_24M, + CLK_SDMMC_DIV_SHIFT = 0, + CLK_SDMMC_DIV_MASK = 0xff << CLK_SDMMC_DIV_SHIFT, + + /* CRU_CLK_SEL46_CON */ + TCLK_WDT_HPMCU_SEL_SHIFT = 14, + TCLK_WDT_HPMCU_SEL_MASK = 0x1 << TCLK_WDT_HPMCU_SEL_SHIFT, + TCLK_WDT_S_SEL_SHIFT = 13, + TCLK_WDT_S_SEL_MASK = 0x1 << TCLK_WDT_S_SEL_SHIFT, + TCLK_WDT_NS_SEL_SHIFT = 12, + TCLK_WDT_NS_SEL_MASK = 0x1 << TCLK_WDT_NS_SEL_SHIFT, + TCLK_WDT_SEL_100M = 0, + TCLK_WDT_SEL_OSC, + + /* CRU_CLK_SEL47_CON */ + ACLK_PERI_SEL_SHIFT = 13, + ACLK_PERI_SEL_MASK = 0x1 << ACLK_PERI_SEL_SHIFT, + ACLK_PERI_SEL_200M = 0, + ACLK_PERI_SEL_24M, + PCLK_PERI_SEL_SHIFT = 12, + PCLK_PERI_SEL_MASK = 0x1 << PCLK_PERI_SEL_SHIFT, + PCLK_PERI_SEL_100M = 0, + PCLK_PERI_SEL_24M, + + /* CRU_CLK_SEL50_CON */ + ACLK_RKCE_SEL_SHIFT = 13, + ACLK_RKCE_SEL_MASK = 0x1 << ACLK_RKCE_SEL_SHIFT, + ACLK_RKCE_SEL_200M = 0, + ACLK_RKCE_SEL_24M, + CLK_PKA_RKCE_SEL_SHIFT = 12, + CLK_PKA_RKCE_SEL_MASK = 0x1 << CLK_PKA_RKCE_SEL_SHIFT, + CLK_PKA_RKCE_SEL_300M = 0, + CLK_PKA_RKCE_SEL_200M, + CLK_PWM3_SEL_SHIFT = 11, + CLK_PWM3_SEL_MASK = 0x1 << CLK_PWM3_SEL_SHIFT, + CLK_PWM2_SEL_SHIFT = 10, + CLK_PWM2_SEL_MASK = 0x1 << CLK_PWM2_SEL_SHIFT, + CLK_PWM0_SEL_SHIFT = 8, + CLK_PWM0_SEL_MASK = 0x1 << CLK_PWM0_SEL_SHIFT, + CLK_PWM_SEL_100M = 0, + CLK_PWM_SEL_24M, + CLK_SPI1_SEL_SHIFT = 4, + CLK_SPI1_SEL_MASK = 0x3 << CLK_SPI1_SEL_SHIFT, + CLK_SPI0_SEL_SHIFT = 2, + CLK_SPI0_SEL_MASK = 0x3 << CLK_SPI0_SEL_SHIFT, + CLK_SPI0_SEL_200M = 0, + CLK_SPI0_SEL_100M, + CLK_SPI0_SEL_50M, + CLK_SPI0_SEL_24M, + CLK_I2C_SEL_SHIFT = 1, + CLK_I2C_SEL_MASK = 0x1 << CLK_I2C_SEL_SHIFT, + CLK_I2C_SEL_200M = 0, + CLK_I2C_SEL_24M, + + /* CRU_CLK_SEL63_CON */ + CLK_SARADC2_SEL_SHIFT = 14, + CLK_SARADC2_SEL_MASK = 0x1 << CLK_SARADC2_SEL_SHIFT, + CLK_SARADC1_SEL_SHIFT = 13, + CLK_SARADC1_SEL_MASK = 0x1 << CLK_SARADC1_SEL_SHIFT, + CLK_SARADC0_SEL_SHIFT = 12, + CLK_SARADC0_SEL_MASK = 0x1 << CLK_SARADC0_SEL_SHIFT, + CLK_SARADC_SEL_200M = 0, + CLK_SARADC_SEL_24M, + CLK_SARADC2_DIV_SHIFT = 8, + CLK_SARADC2_DIV_MASK = 0x7 << CLK_SARADC2_DIV_SHIFT, + CLK_SARADC1_DIV_SHIFT = 4, + CLK_SARADC1_DIV_MASK = 0x7 << CLK_SARADC1_DIV_SHIFT, + CLK_SARADC0_DIV_SHIFT = 0, + CLK_SARADC0_DIV_MASK = 0x7 << CLK_SARADC0_DIV_SHIFT, + + /* PMUCRU_CLK_SEL2_CON */ + CLK_I2C2_SEL_SHIFT = 14, + CLK_I2C2_SEL_MASK = 0x3 << CLK_I2C2_SEL_SHIFT, + CLK_I2C2_SEL_24M = 0, + CLK_I2C2_SEL_RCOSC, + CLK_I2C2_SEL_100M, + CLK_PWM1_SEL_SHIFT = 8, + CLK_PWM1_SEL_MASK = 0x3 << CLK_PWM1_SEL_SHIFT, + CLK_PWM1_SEL_24M = 0, + CLK_PWM1_SEL_RCOSC, + CLK_PWM1_SEL_100M, + CLK_PWM1_DIV_SHIFT = 6, + CLK_PWM1_DIV_MASK = 0x3 << CLK_PWM1_DIV_SHIFT, + + /* PMUCRU_CLK_SEL3_CON */ + TCLK_WDT_LPMCU_SEL_SHIFT = 6, + TCLK_WDT_LPMCU_SEL_MASK = 0x3 << TCLK_WDT_LPMCU_SEL_SHIFT, + TCLK_WDT_LPMCU_SEL_OSC = 0, + TCLK_WDT_LPMCU_SEL_RCOSC, + TCLK_WDT_LPMCU_SEL_100M, + TCLK_WDT_LPMCU_SEL_32K, + SCLK_UART0_SEL_SHIFT = 0, + SCLK_UART0_SEL_MASK = 0x3 << SCLK_UART0_SEL_SHIFT, + SCLK_UART0_SEL_UART0_SRC = 0, + SCLK_UART0_SEL_OSC, + SCLK_UART0_SEL_RCOSC, + + /* PMU1CRU_CLK_SEL0_CON */ + SCLK_1X_FSPI1_DIV_SHIFT = 2, + SCLK_1X_FSPI1_DIV_MASK = 0x7 << SCLK_1X_FSPI1_DIV_SHIFT, + SCLK_1X_FSPI1_SEL_SHIFT = 0, + SCLK_1X_FSPI1_SEL_MASK = 0x3 << SCLK_1X_FSPI1_SEL_SHIFT, + SCLK_1X_FSPI1_SEL_24M = 0, + SCLK_1X_FSPI1_SEL_RCOSC, + SCLK_1X_FSPI1_SEL_100M, +}; +#endif diff --git a/u-boot/arch/arm/include/asm/arch-rockchip/grf_rk3399.h b/u-boot/arch/arm/include/asm/arch-rockchip/grf_rk3399.h index c29e2379d9d..c7155092ee3 100644 --- a/u-boot/arch/arm/include/asm/arch-rockchip/grf_rk3399.h +++ b/u-boot/arch/arm/include/asm/arch-rockchip/grf_rk3399.h @@ -439,18 +439,18 @@ enum { /* GRF_GPIO4C_IOMUX */ GRF_GPIO4C0_SEL_SHIFT = 0, GRF_GPIO4C0_SEL_MASK = 3 << GRF_GPIO4C0_SEL_SHIFT, - GRF_UART2DGBB_SIN = 2, + GRF_UART2DBGB_SIN = 2, GRF_HDMII2C_SCL = 3, GRF_GPIO4C1_SEL_SHIFT = 2, GRF_GPIO4C1_SEL_MASK = 3 << GRF_GPIO4C1_SEL_SHIFT, - GRF_UART2DGBB_SOUT = 2, + GRF_UART2DBGB_SOUT = 2, GRF_HDMII2C_SDA = 3, GRF_GPIO4C2_SEL_SHIFT = 4, GRF_GPIO4C2_SEL_MASK = 3 << GRF_GPIO4C2_SEL_SHIFT, GRF_PWM_0 = 1, GRF_GPIO4C3_SEL_SHIFT = 6, GRF_GPIO4C3_SEL_MASK = 3 << GRF_GPIO4C3_SEL_SHIFT, - GRF_UART2DGBC_SIN = 1, + GRF_UART2DBGC_SIN = 1, GRF_GPIO4C4_SEL_SHIFT = 8, GRF_GPIO4C4_SEL_MASK = 3 << GRF_GPIO4C4_SEL_SHIFT, GRF_UART2DBGC_SOUT = 1, diff --git a/u-boot/arch/arm/include/asm/arch-rockchip/grf_rv1126b.h b/u-boot/arch/arm/include/asm/arch-rockchip/grf_rv1126b.h new file mode 100644 index 00000000000..8226c3ad664 --- /dev/null +++ b/u-boot/arch/arm/include/asm/arch-rockchip/grf_rv1126b.h @@ -0,0 +1,327 @@ +/* + * (C) Copyright 2025 Rockchip Electronics Co., Ltd. + * + * SPDX-License-Identifier: GPL-2.0+ + */ +#ifndef _ASM_ARCH_GRF_RV1126B_H +#define _ASM_ARCH_GRF_RV1126B_H + +#include + +/* cpu_grf register structure define */ +struct rv1126b_cpu_grf_reg { + uint32_t con0; /* address offset: 0x0000 */ + uint32_t con1; /* address offset: 0x0004 */ + uint32_t mem_cfg_uhdspra; /* address offset: 0x0008 */ + uint32_t status0; /* address offset: 0x000c */ + uint32_t status1; /* address offset: 0x0010 */ +}; + +check_member(rv1126b_cpu_grf_reg, status1, 0x0010); + +/* ddr_grf register structure define */ +struct rv1126b_ddr_grf_reg { + uint32_t con0; /* address offset: 0x0000 */ + uint32_t con1; /* address offset: 0x0004 */ + uint32_t reserved0008[2]; /* address offset: 0x0008 */ + uint32_t con4; /* address offset: 0x0010 */ + uint32_t reserved0014[7]; /* address offset: 0x0014 */ + uint32_t con12; /* address offset: 0x0030 */ + uint32_t con13; /* address offset: 0x0034 */ + uint32_t con14; /* address offset: 0x0038 */ + uint32_t con15; /* address offset: 0x003c */ + uint32_t con16; /* address offset: 0x0040 */ + uint32_t con17; /* address offset: 0x0044 */ + uint32_t con18; /* address offset: 0x0048 */ + uint32_t reserved004c; /* address offset: 0x004c */ + uint32_t con20; /* address offset: 0x0050 */ + uint32_t con21; /* address offset: 0x0054 */ + uint32_t con22; /* address offset: 0x0058 */ + uint32_t con23; /* address offset: 0x005c */ + uint32_t reserved0060[8]; /* address offset: 0x0060 */ + uint32_t probe_ctrl; /* address offset: 0x0080 */ + uint32_t reserved0084[31]; /* address offset: 0x0084 */ + uint32_t status0; /* address offset: 0x0100 */ + uint32_t status1; /* address offset: 0x0104 */ + uint32_t status2; /* address offset: 0x0108 */ + uint32_t status3; /* address offset: 0x010c */ + uint32_t status4; /* address offset: 0x0110 */ + uint32_t status5; /* address offset: 0x0114 */ + uint32_t status6; /* address offset: 0x0118 */ + uint32_t status7; /* address offset: 0x011c */ + uint32_t status8; /* address offset: 0x0120 */ + uint32_t status9; /* address offset: 0x0124 */ + uint32_t status10; /* address offset: 0x0128 */ + uint32_t status11; /* address offset: 0x012c */ + uint32_t status12; /* address offset: 0x0130 */ + uint32_t status13; /* address offset: 0x0134 */ + uint32_t status14; /* address offset: 0x0138 */ + uint32_t status15; /* address offset: 0x013c */ + uint32_t status16; /* address offset: 0x0140 */ + uint32_t status17; /* address offset: 0x0144 */ + uint32_t reserved0148; /* address offset: 0x0148 */ + uint32_t status19; /* address offset: 0x014c */ + uint32_t reserved0150[10]; /* address offset: 0x0150 */ + uint32_t status30; /* address offset: 0x0178 */ +}; + +check_member(rv1126b_ddr_grf_reg, status30, 0x0178); + +/* pmu_grf register structure define */ +struct rv1126b_pmu_grf_reg { + uint32_t soc_con0; /* address offset: 0x0000 */ + uint32_t soc_con1; /* address offset: 0x0004 */ + uint32_t soc_con2; /* address offset: 0x0008 */ + uint32_t soc_con3; /* address offset: 0x000c */ + uint32_t soc_con4; /* address offset: 0x0010 */ + uint32_t soc_con5; /* address offset: 0x0014 */ + uint32_t soc_con6; /* address offset: 0x0018 */ + uint32_t soc_con7; /* address offset: 0x001c */ + uint32_t soc_con8; /* address offset: 0x0020 */ + uint32_t soc_con9; /* address offset: 0x0024 */ + uint32_t soc_con10; /* address offset: 0x0028 */ + uint32_t soc_con11; /* address offset: 0x002c */ + uint32_t soc_con12; /* address offset: 0x0030 */ + uint32_t soc_con13; /* address offset: 0x0034 */ + uint32_t soc_con14; /* address offset: 0x0038 */ + uint32_t soc_con15; /* address offset: 0x003c */ + uint32_t reserved0040[16]; /* address offset: 0x0040 */ + uint32_t aad_con0; /* address offset: 0x0080 */ + uint32_t reserved0084[47]; /* address offset: 0x0084 */ + uint32_t men_con0; /* address offset: 0x0140 */ + uint32_t men_con1; /* address offset: 0x0144 */ + uint32_t men_con2; /* address offset: 0x0148 */ + uint32_t reserved014c; /* address offset: 0x014c */ + uint32_t soc_special0; /* address offset: 0x0150 */ + uint32_t reserved0154[3]; /* address offset: 0x0154 */ + uint32_t soc_aov_int_con; /* address offset: 0x0160 */ + uint32_t reserved0164[3]; /* address offset: 0x0164 */ + uint32_t soc_status0; /* address offset: 0x0170 */ + uint32_t soc_status1; /* address offset: 0x0174 */ + uint32_t soc_status2; /* address offset: 0x0178 */ + uint32_t reserved017c[33]; /* address offset: 0x017c */ + uint32_t os_reg0; /* address offset: 0x0200 */ + uint32_t os_reg1; /* address offset: 0x0204 */ + uint32_t os_reg2; /* address offset: 0x0208 */ + uint32_t os_reg3; /* address offset: 0x020c */ + uint32_t os_reg4; /* address offset: 0x0210 */ + uint32_t os_reg5; /* address offset: 0x0214 */ + uint32_t os_reg6; /* address offset: 0x0218 */ + uint32_t os_reg7; /* address offset: 0x021c */ + uint32_t os_reg8; /* address offset: 0x0220 */ + uint32_t os_reg9; /* address offset: 0x0224 */ + uint32_t os_reg10; /* address offset: 0x0228 */ + uint32_t os_reg11; /* address offset: 0x022c */ + uint32_t reset_function_status; /* address offset: 0x0230 */ + uint32_t reset_function_clr; /* address offset: 0x0234 */ + uint32_t reserved0238[82]; /* address offset: 0x0238 */ + uint32_t sig_detect_con; /* address offset: 0x0380 */ + uint32_t reserved0384[3]; /* address offset: 0x0384 */ + uint32_t sig_detect_status; /* address offset: 0x0390 */ + uint32_t reserved0394[3]; /* address offset: 0x0394 */ + uint32_t sig_detect_status_clear; /* address offset: 0x03a0 */ + uint32_t reserved03a4[3]; /* address offset: 0x03a4 */ + uint32_t sdmmc_det_counter; /* address offset: 0x03b0 */ +}; + +check_member(rv1126b_pmu_grf_reg, sdmmc_det_counter, 0x03b0); + +/* npu_grf register structure define */ +struct rv1126b_npu_grf_reg { + uint32_t mem_grf_spra; /* address offset: 0x0000 */ + uint32_t mem_grf_dpra; /* address offset: 0x0004 */ + uint32_t npu_grf_cbuf_mem_soft_gate; /* address offset: 0x0008 */ + uint32_t npu_grf_cfg_nsp_slv_addr; /* address offset: 0x000c */ + uint32_t npu_grf_nsp_mem_soft_gate; /* address offset: 0x0010 */ + uint32_t npu_grf_cfg_use_nsp; /* address offset: 0x0014 */ + uint32_t npu_grf_shape; /* address offset: 0x0018 */ +}; + +check_member(rv1126b_npu_grf_reg, npu_grf_shape, 0x0018); + +/* peri_grf register structure define */ +struct rv1126b_peri_grf_reg { + uint32_t mem_grf_spra; /* address offset: 0x0000 */ + uint32_t mem_grf_dpra; /* address offset: 0x0004 */ + uint32_t reserved0008; /* address offset: 0x0008 */ + uint32_t usb3_grf_con_pending; /* address offset: 0x000c */ + uint32_t reserved0010; /* address offset: 0x0010 */ + uint32_t mem_gate_grf_con; /* address offset: 0x0014 */ + uint32_t hprot_grf_con; /* address offset: 0x0018 */ + uint32_t usbhostphy_con0; /* address offset: 0x001c */ + uint32_t usbotgphy_con0; /* address offset: 0x0020 */ + uint32_t usbotgphy_con1; /* address offset: 0x0024 */ + uint32_t usbotgphy_con2; /* address offset: 0x0028 */ + uint32_t usbotgphy_con3; /* address offset: 0x002c */ + uint32_t host0_con0; /* address offset: 0x0030 */ + uint32_t host0_con1; /* address offset: 0x0034 */ + uint32_t usb3otg0_con0; /* address offset: 0x0038 */ + uint32_t usb3otg0_con1; /* address offset: 0x003c */ + uint32_t reserved0040[13]; /* address offset: 0x0040 */ + uint32_t otgphy_int_en; /* address offset: 0x0074 */ + uint32_t otgphy_int_st; /* address offset: 0x0078 */ + uint32_t otgphy_int_st_clr; /* address offset: 0x007c */ + uint32_t otgphy_ls_con; /* address offset: 0x0080 */ + uint32_t otgphy_dis_con; /* address offset: 0x0084 */ + uint32_t otgphy_bvalid_con; /* address offset: 0x0088 */ + uint32_t otgphy_id_con; /* address offset: 0x008c */ + uint32_t hostphy_int_en; /* address offset: 0x0090 */ + uint32_t hostphy_int_st; /* address offset: 0x0094 */ + uint32_t hostphy_int_st_clr; /* address offset: 0x0098 */ + uint32_t hostphy_ls_con; /* address offset: 0x009c */ + uint32_t hostphy_dis_con; /* address offset: 0x00a0 */ + uint32_t hostphy_bvalid_con; /* address offset: 0x00a4 */ + uint32_t hostphy_id_con; /* address offset: 0x00a8 */ + uint32_t reserved00ac[21]; /* address offset: 0x00ac */ + uint32_t usb3otg0_status; /* address offset: 0x0100 */ + uint32_t usb3otg0_status_cb; /* address offset: 0x0104 */ + uint32_t usb3otg0_status_lat0; /* address offset: 0x0108 */ + uint32_t usb3otg0_status_lat1; /* address offset: 0x010c */ + uint32_t usbphy_st; /* address offset: 0x0110 */ + uint32_t host0_st; /* address offset: 0x0114 */ + uint32_t usb3_host_utmi_st; /* address offset: 0x0118 */ + uint32_t rtc_grf_st; /* address offset: 0x011c */ +}; + +check_member(rv1126b_peri_grf_reg, rtc_grf_st, 0x011c); + +/* usb3_phy_grf register structure define */ +struct rv1126b_usb3_phy_grf_reg { + uint32_t pipe_con0; /* address offset: 0x0000 */ + uint32_t pipe_con1; /* address offset: 0x0004 */ + uint32_t pipe_con2; /* address offset: 0x0008 */ + uint32_t pipe_con3; /* address offset: 0x000c */ + uint32_t pipe_con4; /* address offset: 0x0010 */ + uint32_t reserved0014[8]; /* address offset: 0x0014 */ + uint32_t pipe_status1; /* address offset: 0x0034 */ + uint32_t reserved0038[18]; /* address offset: 0x0038 */ + uint32_t lfps_det_con; /* address offset: 0x0080 */ + uint32_t reserved0084[7]; /* address offset: 0x0084 */ + uint32_t phy_int_en; /* address offset: 0x00a0 */ + uint32_t phy_int_status; /* address offset: 0x00a4 */ +}; + +check_member(rv1126b_usb3_phy_grf_reg, phy_int_status, 0x00a4); + +/* sys_grf register structure define */ +struct rv1126b_sys_grf_reg { + uint32_t mem_grf_spra; /* address offset: 0x0000 */ + uint32_t mem_grf_dpra; /* address offset: 0x0004 */ + uint32_t mem_grf_rom; /* address offset: 0x0008 */ + uint32_t bus_grf_misc; /* address offset: 0x000c */ + uint32_t mem_con_gate; /* address offset: 0x0010 */ + uint32_t bus_grf_hprot_stall; /* address offset: 0x0014 */ + uint32_t hpmcu_cache_misc; /* address offset: 0x0018 */ + uint32_t hpmcu_cache_addr_start; /* address offset: 0x001c */ + uint32_t hpmcu_cache_addr_end; /* address offset: 0x0020 */ + uint32_t hpmcu_code_addr_start; /* address offset: 0x0024 */ + uint32_t hpmcu_sram_addr_start; /* address offset: 0x0028 */ + uint32_t hpmcu_exsram_addr_start; /* address offset: 0x002c */ + uint32_t biu_con0; /* address offset: 0x0030 */ + uint32_t biu_con1; /* address offset: 0x0034 */ + uint32_t uart_grf_rts_cts; /* address offset: 0x0038 */ + uint32_t uart_grf_dma_bypass; /* address offset: 0x003c */ + uint32_t audio_con0; /* address offset: 0x0040 */ + uint32_t reserved0044; /* address offset: 0x0044 */ + uint32_t audio_con2; /* address offset: 0x0048 */ + uint32_t otp_con; /* address offset: 0x004c */ + uint32_t tsadc_grf_con0; /* address offset: 0x0050 */ + uint32_t tsadc_grf_con1; /* address offset: 0x0054 */ + uint32_t tsadc_grf_con2; /* address offset: 0x0058 */ + uint32_t tsadc_grf_con3; /* address offset: 0x005c */ + uint32_t tsadc_grf_con4; /* address offset: 0x0060 */ + uint32_t tsadc_grf_con5; /* address offset: 0x0064 */ + uint32_t tsadc_grf_con6; /* address offset: 0x0068 */ + uint32_t reserved006c[37]; /* address offset: 0x006c */ + uint32_t biu_status0; /* address offset: 0x0100 */ + uint32_t biu_status1; /* address offset: 0x0104 */ + uint32_t biu_status2; /* address offset: 0x0108 */ + uint32_t hpmcu_cache_status; /* address offset: 0x010c */ + uint32_t tsadc_grf_status0; /* address offset: 0x0110 */ + uint32_t tsadc_grf_status1; /* address offset: 0x0114 */ + uint32_t sys_status; /* address offset: 0x0118 */ + uint32_t reserved011c[441]; /* address offset: 0x011c */ + uint32_t chip_id; /* address offset: 0x0800 */ + uint32_t chip_version; /* address offset: 0x0804 */ +}; + +check_member(rv1126b_sys_grf_reg, chip_version, 0x0804); + +/* vcp_grf register structure define */ +struct rv1126b_vcp_grf_reg { + uint32_t mem_grf_spra; /* address offset: 0x0000 */ + uint32_t mem_grf_dpra; /* address offset: 0x0004 */ + uint32_t vcp_grf_aisp_mem_con; /* address offset: 0x0008 */ +}; + +check_member(rv1126b_vcp_grf_reg, vcp_grf_aisp_mem_con, 0x0008); + +/* vdo_grf register structure define */ +struct rv1126b_vdo_grf_reg { + uint32_t mem_grf_spra; /* address offset: 0x0000 */ + uint32_t mem_grf_dpra; /* address offset: 0x0004 */ + uint32_t mem_gate_grf_con; /* address offset: 0x0008 */ + uint32_t dsi_grf_con; /* address offset: 0x000c */ + uint32_t dsiphy_grf_con; /* address offset: 0x0010 */ + uint32_t rkmmu_grf_con; /* address offset: 0x0014 */ + uint32_t reserved0018[14]; /* address offset: 0x0018 */ + uint32_t vdo_grf_status0; /* address offset: 0x0050 */ + uint32_t vdo_grf_status1; /* address offset: 0x0054 */ +}; + +check_member(rv1126b_vdo_grf_reg, vdo_grf_status1, 0x0054); + +/* vepu_grf register structure define */ +struct rv1126b_vepu_grf_reg { + uint32_t mem_grf_spra; /* address offset: 0x0000 */ + uint32_t mem_grf_dpra; /* address offset: 0x0004 */ + uint32_t vepu_grf_con0; /* address offset: 0x0008 */ + uint32_t saradc0_grf_con0; /* address offset: 0x000c */ + uint32_t saradc0_grf_con1; /* address offset: 0x0010 */ + uint32_t saradc0_grf_con2; /* address offset: 0x0014 */ + uint32_t reserved0018[3]; /* address offset: 0x0018 */ + uint32_t sdmmc1_det_cnt; /* address offset: 0x0024 */ + uint32_t sdmmc1_sig_detect_con; /* address offset: 0x0028 */ + uint32_t sdmmc1_sig_detect_status; /* address offset: 0x002c */ + uint32_t sdmmc1_status_clr; /* address offset: 0x0030 */ +}; + +check_member(rv1126b_vepu_grf_reg, sdmmc1_status_clr, 0x0030); + +/* vi_grf register structure define */ +struct rv1126b_vi_grf_reg { + uint32_t mem_con_spra; /* address offset: 0x0000 */ + uint32_t mem_con_dpra; /* address offset: 0x0004 */ + uint32_t vi_grf_status; /* address offset: 0x0008 */ + uint32_t reserved000c; /* address offset: 0x000c */ + uint32_t csiphy0_grf_con; /* address offset: 0x0010 */ + uint32_t csiphy1_grf_con; /* address offset: 0x0014 */ + uint32_t csiphy0_grf_status; /* address offset: 0x0018 */ + uint32_t csiphy1_grf_status; /* address offset: 0x001c */ + uint32_t misc_grf_con; /* address offset: 0x0020 */ + uint32_t reserved0024[11]; /* address offset: 0x0024 */ + uint32_t gmac_grf_con0; /* address offset: 0x0050 */ + uint32_t gmac_dma_ack; /* address offset: 0x0054 */ + uint32_t reserved0058[2]; /* address offset: 0x0058 */ + uint32_t gmac_grf_status0; /* address offset: 0x0060 */ + uint32_t gmac_grf_status1; /* address offset: 0x0064 */ + uint32_t gmac_grf_status2; /* address offset: 0x0068 */ + uint32_t reserved006c[5]; /* address offset: 0x006c */ + uint32_t saradc1_grf_con0; /* address offset: 0x0080 */ + uint32_t saradc1_grf_con1; /* address offset: 0x0084 */ + uint32_t saradc1_grf_con2; /* address offset: 0x0088 */ + uint32_t reserved008c; /* address offset: 0x008c */ + uint32_t saradc2_grf_con0; /* address offset: 0x0090 */ + uint32_t saradc2_grf_con1; /* address offset: 0x0094 */ + uint32_t saradc2_grf_con2; /* address offset: 0x0098 */ + uint32_t reserved009c[6]; /* address offset: 0x009c */ + uint32_t rkmacphy_grf_con0; /* address offset: 0x00b4 */ + uint32_t rkmacphy_grf_con1; /* address offset: 0x00b8 */ + uint32_t rkmacphy_grf_con2; /* address offset: 0x00bc */ + uint32_t rkmacphy_grf_status; /* address offset: 0x00c0 */ + uint32_t rkmacphy_calib_con; /* address offset: 0x00c4 */ +}; + +check_member(rv1126b_vi_grf_reg, rkmacphy_calib_con, 0x00c4); + +#endif /* _ASM_ARCH_GRF_RV1126B_H */ diff --git a/u-boot/arch/arm/include/asm/arch-rockchip/ioc_rv1126b.h b/u-boot/arch/arm/include/asm/arch-rockchip/ioc_rv1126b.h new file mode 100644 index 00000000000..e89098427cc --- /dev/null +++ b/u-boot/arch/arm/include/asm/arch-rockchip/ioc_rv1126b.h @@ -0,0 +1,457 @@ +/* + * (C) Copyright 2025 Rockchip Electronics Co., Ltd. + * + * SPDX-License-Identifier: GPL-2.0+ + */ +#ifndef _ASM_ARCH_IOC_RV1126B_H +#define _ASM_ARCH_IOC_RV1126B_H + +#include + +/* pmuio0_ioc register structure define */ +struct rv1126b_pmuio0_ioc_reg { + uint32_t gpio0a_iomux_sel_0; /* address offset: 0x0000 */ + uint32_t gpio0a_iomux_sel_1; /* address offset: 0x0004 */ + uint32_t gpio0b_iomux_sel_0; /* address offset: 0x0008 */ + uint32_t gpio0b_iomux_sel_1; /* address offset: 0x000c */ + uint32_t reserved0010[60]; /* address offset: 0x0010 */ + uint32_t gpio0a_ds_0; /* address offset: 0x0100 */ + uint32_t gpio0a_ds_1; /* address offset: 0x0104 */ + uint32_t gpio0a_ds_2; /* address offset: 0x0108 */ + uint32_t gpio0a_ds_3; /* address offset: 0x010c */ + uint32_t gpio0b_ds_0; /* address offset: 0x0110 */ + uint32_t gpio0b_ds_1; /* address offset: 0x0114 */ + uint32_t gpio0b_ds_2; /* address offset: 0x0118 */ + uint32_t reserved011c[121]; /* address offset: 0x011c */ + uint32_t gpio0a_pull; /* address offset: 0x0300 */ + uint32_t gpio0b_pull; /* address offset: 0x0304 */ + uint32_t reserved0308[62]; /* address offset: 0x0308 */ + uint32_t gpio0a_ie; /* address offset: 0x0400 */ + uint32_t gpio0b_ie; /* address offset: 0x0404 */ + uint32_t reserved0408[62]; /* address offset: 0x0408 */ + uint32_t gpio0a_smt; /* address offset: 0x0500 */ + uint32_t gpio0b_smt; /* address offset: 0x0504 */ + uint32_t reserved0508[62]; /* address offset: 0x0508 */ + uint32_t gpio0a_sus; /* address offset: 0x0600 */ + uint32_t gpio0b_sus; /* address offset: 0x0604 */ + uint32_t reserved0608[62]; /* address offset: 0x0608 */ + uint32_t gpio0a_sl; /* address offset: 0x0700 */ + uint32_t gpio0b_sl; /* address offset: 0x0704 */ + uint32_t reserved0708[62]; /* address offset: 0x0708 */ + uint32_t gpio0a_od; /* address offset: 0x0800 */ + uint32_t gpio0b_od; /* address offset: 0x0804 */ + uint32_t reserved0808[62]; /* address offset: 0x0808 */ + uint32_t io_vsel; /* address offset: 0x0900 */ + uint32_t grf_jtag_con0; /* address offset: 0x0904 */ + uint32_t grf_jtag_con1; /* address offset: 0x0908 */ + uint32_t reserved090c; /* address offset: 0x090c */ + uint32_t xin_con; /* address offset: 0x0910 */ + uint32_t reserved0914[187]; /* address offset: 0x0914 */ + uint32_t grf_gpio0_filter_con0; /* address offset: 0x0c00 */ + uint32_t grf_gpio0_filter_con1; /* address offset: 0x0c04 */ + uint32_t grf_gpio0_filter_con2; /* address offset: 0x0c08 */ + uint32_t grf_gpio0_filter_con3; /* address offset: 0x0c0c */ + uint32_t grf_gpio0_filter_con4; /* address offset: 0x0c10 */ + uint32_t grf_gpio0_filter_con5; /* address offset: 0x0c14 */ +}; + +check_member(rv1126b_pmuio0_ioc_reg, grf_gpio0_filter_con5, 0x0c14); + +/* pmuio1_ioc register structure define */ +struct rv1126b_pmuio1_ioc_reg { + uint32_t reserved0000[4]; /* address offset: 0x0000 */ + uint32_t gpio0c_iomux_sel_0; /* address offset: 0x0010 */ + uint32_t gpio0c_iomux_sel_1; /* address offset: 0x0014 */ + uint32_t gpio0d_iomux_sel_0; /* address offset: 0x0018 */ + uint32_t reserved001c[65]; /* address offset: 0x001c */ + uint32_t gpio0c_ds_0; /* address offset: 0x0120 */ + uint32_t gpio0c_ds_1; /* address offset: 0x0124 */ + uint32_t gpio0c_ds_2; /* address offset: 0x0128 */ + uint32_t gpio0c_ds_3; /* address offset: 0x012c */ + uint32_t gpio0d_ds_0; /* address offset: 0x0130 */ + uint32_t reserved0134[117]; /* address offset: 0x0134 */ + uint32_t gpio0c_pull; /* address offset: 0x0308 */ + uint32_t gpio0d_pull; /* address offset: 0x030c */ + uint32_t reserved0310[62]; /* address offset: 0x0310 */ + uint32_t gpio0c_ie; /* address offset: 0x0408 */ + uint32_t gpio0d_ie; /* address offset: 0x040c */ + uint32_t reserved0410[62]; /* address offset: 0x0410 */ + uint32_t gpio0c_smt; /* address offset: 0x0508 */ + uint32_t gpio0d_smt; /* address offset: 0x050c */ + uint32_t reserved0510[62]; /* address offset: 0x0510 */ + uint32_t gpio0c_sus; /* address offset: 0x0608 */ + uint32_t gpio0d_sus; /* address offset: 0x060c */ + uint32_t reserved0610[62]; /* address offset: 0x0610 */ + uint32_t gpio0c_sl; /* address offset: 0x0708 */ + uint32_t gpio0d_sl; /* address offset: 0x070c */ + uint32_t reserved0710[62]; /* address offset: 0x0710 */ + uint32_t gpio0c_od; /* address offset: 0x0808 */ + uint32_t gpio0d_od; /* address offset: 0x080c */ + uint32_t reserved0810[60]; /* address offset: 0x0810 */ + uint32_t io_vsel; /* address offset: 0x0900 */ +}; + +check_member(rv1126b_pmuio1_ioc_reg, io_vsel, 0x0900); + +/* vccio1_ioc register structure define */ +struct rv1126b_vccio1_ioc_reg { + uint32_t reserved0000[8]; /* address offset: 0x0000 */ + uint32_t gpio1a_iomux_sel_0; /* address offset: 0x0020 */ + uint32_t gpio1a_iomux_sel_1; /* address offset: 0x0024 */ + uint32_t gpio1b_iomux_sel_0; /* address offset: 0x0028 */ + uint32_t gpio1b_iomux_sel_1; /* address offset: 0x002c */ + uint32_t reserved0030[68]; /* address offset: 0x0030 */ + uint32_t gpio1a_ds_0; /* address offset: 0x0140 */ + uint32_t gpio1a_ds_1; /* address offset: 0x0144 */ + uint32_t gpio1a_ds_2; /* address offset: 0x0148 */ + uint32_t gpio1a_ds_3; /* address offset: 0x014c */ + uint32_t gpio1b_ds_0; /* address offset: 0x0150 */ + uint32_t gpio1b_ds_1; /* address offset: 0x0154 */ + uint32_t gpio1b_ds_2; /* address offset: 0x0158 */ + uint32_t gpio1b_ds_3; /* address offset: 0x015c */ + uint32_t reserved0160[108]; /* address offset: 0x0160 */ + uint32_t gpio1a_pull; /* address offset: 0x0310 */ + uint32_t gpio1b_pull; /* address offset: 0x0314 */ + uint32_t reserved0318[62]; /* address offset: 0x0318 */ + uint32_t gpio1a_ie; /* address offset: 0x0410 */ + uint32_t gpio1b_ie; /* address offset: 0x0414 */ + uint32_t reserved0418[62]; /* address offset: 0x0418 */ + uint32_t gpio1a_smt; /* address offset: 0x0510 */ + uint32_t gpio1b_smt; /* address offset: 0x0514 */ + uint32_t reserved0518[62]; /* address offset: 0x0518 */ + uint32_t gpio1a_sus; /* address offset: 0x0610 */ + uint32_t gpio1b_sus; /* address offset: 0x0614 */ + uint32_t reserved0618[62]; /* address offset: 0x0618 */ + uint32_t gpio1a_sl; /* address offset: 0x0710 */ + uint32_t gpio1b_sl; /* address offset: 0x0714 */ + uint32_t reserved0718[62]; /* address offset: 0x0718 */ + uint32_t gpio1a_od; /* address offset: 0x0810 */ + uint32_t gpio1b_od; /* address offset: 0x0814 */ + uint32_t reserved0818[60]; /* address offset: 0x0818 */ + uint32_t io1_vsel; /* address offset: 0x0908 */ + uint32_t reserved090c[61]; /* address offset: 0x090c */ + uint32_t ioc_misc_con0; /* address offset: 0x0a00 */ + uint32_t ioc_misc_con1; /* address offset: 0x0a04 */ + uint32_t ioc_misc_con2; /* address offset: 0x0a08 */ + uint32_t ioc_misc_con3; /* address offset: 0x0a0c */ + uint32_t ioc_misc_con4; /* address offset: 0x0a10 */ + uint32_t ioc_misc_con5; /* address offset: 0x0a14 */ + uint32_t ioc_misc_con6; /* address offset: 0x0a18 */ +}; + +check_member(rv1126b_vccio1_ioc_reg, ioc_misc_con6, 0x0a18); + +/* vccio2_ioc register structure define */ +struct rv1126b_vccio2_ioc_reg { + uint32_t reserved0000[16]; /* address offset: 0x0000 */ + uint32_t gpio2a_iomux_sel_0; /* address offset: 0x0040 */ + uint32_t gpio2a_iomux_sel_1; /* address offset: 0x0044 */ + uint32_t reserved0048[78]; /* address offset: 0x0048 */ + uint32_t gpio2a_ds_0; /* address offset: 0x0180 */ + uint32_t gpio2a_ds_1; /* address offset: 0x0184 */ + uint32_t gpio2a_ds_2; /* address offset: 0x0188 */ + uint32_t reserved018c[101]; /* address offset: 0x018c */ + uint32_t gpio2a_pull; /* address offset: 0x0320 */ + uint32_t reserved0324[63]; /* address offset: 0x0324 */ + uint32_t gpio2a_ie; /* address offset: 0x0420 */ + uint32_t reserved0424[63]; /* address offset: 0x0424 */ + uint32_t gpio2a_smt; /* address offset: 0x0520 */ + uint32_t reserved0524[63]; /* address offset: 0x0524 */ + uint32_t gpio2a_sus; /* address offset: 0x0620 */ + uint32_t reserved0624[63]; /* address offset: 0x0624 */ + uint32_t gpio2a_sl; /* address offset: 0x0720 */ + uint32_t reserved0724[63]; /* address offset: 0x0724 */ + uint32_t gpio2a_od; /* address offset: 0x0820 */ + uint32_t reserved0824[58]; /* address offset: 0x0824 */ + uint32_t io_vsel; /* address offset: 0x090c */ + uint32_t reserved0910[159]; /* address offset: 0x0910 */ + uint32_t grf_sddet_dly_con; /* address offset: 0x0b8c */ + uint32_t grf_jtag_con; /* address offset: 0x0b90 */ + uint32_t reserved0b94[27]; /* address offset: 0x0b94 */ + uint32_t grf_gpio2_filter_con0; /* address offset: 0x0c00 */ + uint32_t grf_gpio2_filter_con1; /* address offset: 0x0c04 */ + uint32_t grf_gpio2_filter_con2; /* address offset: 0x0c08 */ + uint32_t grf_gpio2_filter_con3; /* address offset: 0x0c0c */ + uint32_t grf_gpio2_filter_con4; /* address offset: 0x0c10 */ + uint32_t grf_gpio2_filter_con5; /* address offset: 0x0c14 */ +}; + +check_member(rv1126b_vccio2_ioc_reg, grf_gpio2_filter_con5, 0x0c14); + +/* vccio3_ioc register structure define */ +struct rv1126b_vccio3_ioc_reg { + uint32_t reserved0000[24]; /* address offset: 0x0000 */ + uint32_t gpio3a_iomux_sel_0; /* address offset: 0x0060 */ + uint32_t gpio3a_iomux_sel_1; /* address offset: 0x0064 */ + uint32_t gpio3b_iomux_sel_0; /* address offset: 0x0068 */ + uint32_t gpio3b_iomux_sel_1; /* address offset: 0x006c */ + uint32_t reserved0070[84]; /* address offset: 0x0070 */ + uint32_t gpio3a_ds_0; /* address offset: 0x01c0 */ + uint32_t gpio3a_ds_1; /* address offset: 0x01c4 */ + uint32_t gpio3a_ds_2; /* address offset: 0x01c8 */ + uint32_t gpio3a_ds_3; /* address offset: 0x01cc */ + uint32_t gpio3b_ds_0; /* address offset: 0x01d0 */ + uint32_t gpio3b_ds_1; /* address offset: 0x01d4 */ + uint32_t gpio3b_ds_2; /* address offset: 0x01d8 */ + uint32_t gpio3b_ds_3; /* address offset: 0x01dc */ + uint32_t reserved01e0[84]; /* address offset: 0x01e0 */ + uint32_t gpio3a_pull; /* address offset: 0x0330 */ + uint32_t gpio3b_pull; /* address offset: 0x0334 */ + uint32_t reserved0338[62]; /* address offset: 0x0338 */ + uint32_t gpio3a_ie; /* address offset: 0x0430 */ + uint32_t gpio3b_ie; /* address offset: 0x0434 */ + uint32_t reserved0438[62]; /* address offset: 0x0438 */ + uint32_t gpio3a_smt; /* address offset: 0x0530 */ + uint32_t gpio3b_smt; /* address offset: 0x0534 */ + uint32_t reserved0538[62]; /* address offset: 0x0538 */ + uint32_t gpio3a_sus; /* address offset: 0x0630 */ + uint32_t gpio3b_sus; /* address offset: 0x0634 */ + uint32_t reserved0638[62]; /* address offset: 0x0638 */ + uint32_t gpio3a_sl; /* address offset: 0x0730 */ + uint32_t gpio3b_sl; /* address offset: 0x0734 */ + uint32_t reserved0738[62]; /* address offset: 0x0738 */ + uint32_t gpio3a_od; /* address offset: 0x0830 */ + uint32_t gpio3b_od; /* address offset: 0x0834 */ + uint32_t reserved0838[54]; /* address offset: 0x0838 */ + uint32_t io3_vsel; /* address offset: 0x0910 */ + uint32_t reserved0914[59]; /* address offset: 0x0914 */ + uint32_t ioc_misc_con0; /* address offset: 0x0a00 */ + uint32_t ioc_misc_con1; /* address offset: 0x0a04 */ + uint32_t ioc_misc_con2; /* address offset: 0x0a08 */ + uint32_t ioc_misc_con3; /* address offset: 0x0a0c */ + uint32_t ioc_misc_con4; /* address offset: 0x0a10 */ + uint32_t ioc_misc_con5; /* address offset: 0x0a14 */ + uint32_t ioc_misc_con6; /* address offset: 0x0a18 */ +}; + +check_member(rv1126b_vccio3_ioc_reg, ioc_misc_con6, 0x0a18); + +/* vccio4_ioc register structure define */ +struct rv1126b_vccio4_ioc_reg { + uint32_t reserved0000[32]; /* address offset: 0x0000 */ + uint32_t gpio4a_iomux_sel_0; /* address offset: 0x0080 */ + uint32_t gpio4a_iomux_sel_1; /* address offset: 0x0084 */ + uint32_t gpio4b_iomux_sel_0; /* address offset: 0x0088 */ + uint32_t reserved008c[93]; /* address offset: 0x008c */ + uint32_t gpio4a_ds_0; /* address offset: 0x0200 */ + uint32_t gpio4a_ds_1; /* address offset: 0x0204 */ + uint32_t gpio4a_ds_2; /* address offset: 0x0208 */ + uint32_t gpio4a_ds_3; /* address offset: 0x020c */ + uint32_t gpio4b_ds_0; /* address offset: 0x0210 */ + uint32_t reserved0214[75]; /* address offset: 0x0214 */ + uint32_t gpio4a_pull; /* address offset: 0x0340 */ + uint32_t gpio4b_pull; /* address offset: 0x0344 */ + uint32_t reserved0348[62]; /* address offset: 0x0348 */ + uint32_t gpio4a_ie; /* address offset: 0x0440 */ + uint32_t gpio4b_ie; /* address offset: 0x0444 */ + uint32_t reserved0448[62]; /* address offset: 0x0448 */ + uint32_t gpio4a_smt; /* address offset: 0x0540 */ + uint32_t gpio4b_smt; /* address offset: 0x0544 */ + uint32_t reserved0548[62]; /* address offset: 0x0548 */ + uint32_t gpio4a_sus; /* address offset: 0x0640 */ + uint32_t gpio4b_sus; /* address offset: 0x0644 */ + uint32_t reserved0648[62]; /* address offset: 0x0648 */ + uint32_t gpio4a_sl; /* address offset: 0x0740 */ + uint32_t gpio4b_sl; /* address offset: 0x0744 */ + uint32_t reserved0748[62]; /* address offset: 0x0748 */ + uint32_t gpio4a_od; /* address offset: 0x0840 */ + uint32_t gpio4b_od; /* address offset: 0x0844 */ + uint32_t reserved0848[51]; /* address offset: 0x0848 */ + uint32_t io_vsel; /* address offset: 0x0914 */ + uint32_t reserved0918[194]; /* address offset: 0x0918 */ + uint32_t grf_gpio4_filter_con0; /* address offset: 0x0c20 */ + uint32_t grf_gpio4_filter_con1; /* address offset: 0x0c24 */ + uint32_t grf_gpio4_filter_con2; /* address offset: 0x0c28 */ + uint32_t grf_gpio4_filter_con3; /* address offset: 0x0c2c */ + uint32_t grf_gpio4_filter_con4; /* address offset: 0x0c30 */ + uint32_t grf_gpio4_filter_con5; /* address offset: 0x0c34 */ +}; + +check_member(rv1126b_vccio4_ioc_reg, grf_gpio4_filter_con5, 0x0c34); + +/* vccio5_ioc register structure define */ +struct rv1126b_vccio5_ioc_reg { + uint32_t reserved0000[40]; /* address offset: 0x0000 */ + uint32_t gpio5a_iomux_sel_0; /* address offset: 0x00a0 */ + uint32_t gpio5a_iomux_sel_1; /* address offset: 0x00a4 */ + uint32_t gpio5b_iomux_sel_0; /* address offset: 0x00a8 */ + uint32_t gpio5b_iomux_sel_1; /* address offset: 0x00ac */ + uint32_t gpio5c_iomux_sel_0; /* address offset: 0x00b0 */ + uint32_t gpio5c_iomux_sel_1; /* address offset: 0x00b4 */ + uint32_t gpio5d_iomux_sel_0; /* address offset: 0x00b8 */ + uint32_t gpio5d_iomux_sel_1; /* address offset: 0x00bc */ + uint32_t reserved00c0[96]; /* address offset: 0x00c0 */ + uint32_t gpio5a_ds_0; /* address offset: 0x0240 */ + uint32_t gpio5a_ds_1; /* address offset: 0x0244 */ + uint32_t gpio5a_ds_2; /* address offset: 0x0248 */ + uint32_t gpio5a_ds_3; /* address offset: 0x024c */ + uint32_t gpio5b_ds_0; /* address offset: 0x0250 */ + uint32_t gpio5b_ds_1; /* address offset: 0x0254 */ + uint32_t gpio5b_ds_2; /* address offset: 0x0258 */ + uint32_t gpio5b_ds_3; /* address offset: 0x025c */ + uint32_t gpio5c_ds_0; /* address offset: 0x0260 */ + uint32_t gpio5c_ds_1; /* address offset: 0x0264 */ + uint32_t gpio5c_ds_2; /* address offset: 0x0268 */ + uint32_t gpio5c_ds_3; /* address offset: 0x026c */ + uint32_t gpio5d_ds_0; /* address offset: 0x0270 */ + uint32_t gpio5d_ds_1; /* address offset: 0x0274 */ + uint32_t gpio5d_ds_2; /* address offset: 0x0278 */ + uint32_t gpio5d_ds_3; /* address offset: 0x027c */ + uint32_t reserved0280[52]; /* address offset: 0x0280 */ + uint32_t gpio5a_pull; /* address offset: 0x0350 */ + uint32_t gpio5b_pull; /* address offset: 0x0354 */ + uint32_t gpio5c_pull; /* address offset: 0x0358 */ + uint32_t gpio5d_pull; /* address offset: 0x035c */ + uint32_t reserved0360[60]; /* address offset: 0x0360 */ + uint32_t gpio5a_ie; /* address offset: 0x0450 */ + uint32_t gpio5b_ie; /* address offset: 0x0454 */ + uint32_t gpio5c_ie; /* address offset: 0x0458 */ + uint32_t gpio5d_ie; /* address offset: 0x045c */ + uint32_t reserved0460[60]; /* address offset: 0x0460 */ + uint32_t gpio5a_smt; /* address offset: 0x0550 */ + uint32_t gpio5b_smt; /* address offset: 0x0554 */ + uint32_t gpio5c_smt; /* address offset: 0x0558 */ + uint32_t gpio5d_smt; /* address offset: 0x055c */ + uint32_t reserved0560[60]; /* address offset: 0x0560 */ + uint32_t gpio5a_sus; /* address offset: 0x0650 */ + uint32_t gpio5b_sus; /* address offset: 0x0654 */ + uint32_t gpio5c_sus; /* address offset: 0x0658 */ + uint32_t gpio5d_sus; /* address offset: 0x065c */ + uint32_t reserved0660[60]; /* address offset: 0x0660 */ + uint32_t gpio5a_sl; /* address offset: 0x0750 */ + uint32_t gpio5b_sl; /* address offset: 0x0754 */ + uint32_t gpio5c_sl; /* address offset: 0x0758 */ + uint32_t gpio5d_sl; /* address offset: 0x075c */ + uint32_t reserved0760[60]; /* address offset: 0x0760 */ + uint32_t gpio5a_od; /* address offset: 0x0850 */ + uint32_t gpio5b_od; /* address offset: 0x0854 */ + uint32_t gpio5c_od; /* address offset: 0x0858 */ + uint32_t gpio5d_od; /* address offset: 0x085c */ + uint32_t reserved0860[46]; /* address offset: 0x0860 */ + uint32_t io_vsel; /* address offset: 0x0918 */ + uint32_t reserved091c[159]; /* address offset: 0x091c */ + uint32_t grf_vicif_m1_con; /* address offset: 0x0b98 */ + uint32_t grf_vop_lcdc_con; /* address offset: 0x0b9c */ + uint32_t reserved0ba0[2]; /* address offset: 0x0ba0 */ + uint32_t grf_gmacio_m1_con0; /* address offset: 0x0ba8 */ + uint32_t grf_gmacio_m1_con1; /* address offset: 0x0bac */ + uint32_t grf_uart0_dly_con; /* address offset: 0x0bb0 */ + uint32_t grf_uart_jtag_con; /* address offset: 0x0bb4 */ + uint32_t reserved0bb8[34]; /* address offset: 0x0bb8 */ + uint32_t grf_gpio5_filter_con0; /* address offset: 0x0c40 */ + uint32_t grf_gpio5_filter_con1; /* address offset: 0x0c44 */ + uint32_t grf_gpio5_filter_con2; /* address offset: 0x0c48 */ + uint32_t grf_gpio5_filter_con3; /* address offset: 0x0c4c */ + uint32_t grf_gpio5_filter_con4; /* address offset: 0x0c50 */ + uint32_t grf_gpio5_filter_con5; /* address offset: 0x0c54 */ +}; + +check_member(rv1126b_vccio5_ioc_reg, grf_gpio5_filter_con5, 0x0c54); + +/* vccio6_ioc register structure define */ +struct rv1126b_vccio6_ioc_reg { + uint32_t reserved0000[48]; /* address offset: 0x0000 */ + uint32_t gpio6a_iomux_sel_0; /* address offset: 0x00c0 */ + uint32_t gpio6a_iomux_sel_1; /* address offset: 0x00c4 */ + uint32_t gpio6b_iomux_sel_0; /* address offset: 0x00c8 */ + uint32_t gpio6b_iomux_sel_1; /* address offset: 0x00cc */ + uint32_t gpio6c_iomux_sel_0; /* address offset: 0x00d0 */ + uint32_t reserved00d4[107]; /* address offset: 0x00d4 */ + uint32_t gpio6a_ds_0; /* address offset: 0x0280 */ + uint32_t gpio6a_ds_1; /* address offset: 0x0284 */ + uint32_t gpio6a_ds_2; /* address offset: 0x0288 */ + uint32_t gpio6a_ds_3; /* address offset: 0x028c */ + uint32_t gpio6b_ds_0; /* address offset: 0x0290 */ + uint32_t gpio6b_ds_1; /* address offset: 0x0294 */ + uint32_t gpio6b_ds_2; /* address offset: 0x0298 */ + uint32_t gpio6b_ds_3; /* address offset: 0x029c */ + uint32_t gpio6c_ds_0; /* address offset: 0x02a0 */ + uint32_t gpio6c_ds_1; /* address offset: 0x02a4 */ + uint32_t reserved02a8[46]; /* address offset: 0x02a8 */ + uint32_t gpio6a_pull; /* address offset: 0x0360 */ + uint32_t gpio6b_pull; /* address offset: 0x0364 */ + uint32_t gpio6c_pull; /* address offset: 0x0368 */ + uint32_t reserved036c[61]; /* address offset: 0x036c */ + uint32_t gpio6a_ie; /* address offset: 0x0460 */ + uint32_t gpio6b_ie; /* address offset: 0x0464 */ + uint32_t gpio6c_ie; /* address offset: 0x0468 */ + uint32_t reserved046c[61]; /* address offset: 0x046c */ + uint32_t gpio6a_smt; /* address offset: 0x0560 */ + uint32_t gpio6b_smt; /* address offset: 0x0564 */ + uint32_t gpio6c_smt; /* address offset: 0x0568 */ + uint32_t reserved056c[61]; /* address offset: 0x056c */ + uint32_t gpio6a_sus; /* address offset: 0x0660 */ + uint32_t gpio6b_sus; /* address offset: 0x0664 */ + uint32_t gpio6c_sus; /* address offset: 0x0668 */ + uint32_t reserved066c[61]; /* address offset: 0x066c */ + uint32_t gpio6a_sl; /* address offset: 0x0760 */ + uint32_t gpio6b_sl; /* address offset: 0x0764 */ + uint32_t gpio6c_sl; /* address offset: 0x0768 */ + uint32_t reserved076c[61]; /* address offset: 0x076c */ + uint32_t gpio6a_od; /* address offset: 0x0860 */ + uint32_t gpio6b_od; /* address offset: 0x0864 */ + uint32_t gpio6c_od; /* address offset: 0x0868 */ + uint32_t reserved086c[44]; /* address offset: 0x086c */ + uint32_t io_vsel; /* address offset: 0x091c */ + uint32_t reserved0920[157]; /* address offset: 0x0920 */ + uint32_t grf_vicif_m0_con; /* address offset: 0x0b94 */ + uint32_t reserved0b98[2]; /* address offset: 0x0b98 */ + uint32_t grf_gmacio_m0_con0; /* address offset: 0x0ba0 */ + uint32_t grf_gmacio_m0_con1; /* address offset: 0x0ba4 */ + uint32_t reserved0ba8[46]; /* address offset: 0x0ba8 */ + uint32_t grf_gpio6_filter_con0; /* address offset: 0x0c60 */ + uint32_t grf_gpio6_filter_con1; /* address offset: 0x0c64 */ + uint32_t grf_gpio6_filter_con2; /* address offset: 0x0c68 */ + uint32_t grf_gpio6_filter_con3; /* address offset: 0x0c6c */ + uint32_t grf_gpio6_filter_con4; /* address offset: 0x0c70 */ + uint32_t grf_gpio6_filter_con5; /* address offset: 0x0c74 */ +}; + +check_member(rv1126b_vccio6_ioc_reg, grf_gpio6_filter_con5, 0x0c74); + +/* vccio7_ioc register structure define */ +struct rv1126b_vccio7_ioc_reg { + uint32_t reserved0000[56]; /* address offset: 0x0000 */ + uint32_t gpio7a_iomux_sel_0; /* address offset: 0x00e0 */ + uint32_t gpio7a_iomux_sel_1; /* address offset: 0x00e4 */ + uint32_t gpio7b_iomux_sel_0; /* address offset: 0x00e8 */ + uint32_t reserved00ec[117]; /* address offset: 0x00ec */ + uint32_t gpio7a_ds_0; /* address offset: 0x02c0 */ + uint32_t gpio7a_ds_1; /* address offset: 0x02c4 */ + uint32_t gpio7a_ds_2; /* address offset: 0x02c8 */ + uint32_t gpio7a_ds_3; /* address offset: 0x02cc */ + uint32_t gpio7b_ds_0; /* address offset: 0x02d0 */ + uint32_t reserved02d4[39]; /* address offset: 0x02d4 */ + uint32_t gpio7a_pull; /* address offset: 0x0370 */ + uint32_t gpio7b_pull; /* address offset: 0x0374 */ + uint32_t reserved0378[62]; /* address offset: 0x0378 */ + uint32_t gpio7a_ie; /* address offset: 0x0470 */ + uint32_t gpio7b_ie; /* address offset: 0x0474 */ + uint32_t reserved0478[62]; /* address offset: 0x0478 */ + uint32_t gpio7a_smt; /* address offset: 0x0570 */ + uint32_t gpio7b_smt; /* address offset: 0x0574 */ + uint32_t reserved0578[62]; /* address offset: 0x0578 */ + uint32_t gpio7a_sus; /* address offset: 0x0670 */ + uint32_t gpio7b_sus; /* address offset: 0x0674 */ + uint32_t reserved0678[62]; /* address offset: 0x0678 */ + uint32_t gpio7a_sl; /* address offset: 0x0770 */ + uint32_t gpio7b_sl; /* address offset: 0x0774 */ + uint32_t reserved0778[62]; /* address offset: 0x0778 */ + uint32_t gpio7a_od; /* address offset: 0x0870 */ + uint32_t gpio7b_od; /* address offset: 0x0874 */ + uint32_t reserved0878[42]; /* address offset: 0x0878 */ + uint32_t io_vsel; /* address offset: 0x0920 */ + uint32_t reserved0924[215]; /* address offset: 0x0924 */ + uint32_t grf_gpio7_filter_con0; /* address offset: 0x0c80 */ + uint32_t grf_gpio7_filter_con1; /* address offset: 0x0c84 */ + uint32_t grf_gpio7_filter_con2; /* address offset: 0x0c88 */ + uint32_t grf_gpio7_filter_con3; /* address offset: 0x0c8c */ + uint32_t grf_gpio7_filter_con4; /* address offset: 0x0c90 */ + uint32_t grf_gpio7_filter_con5; /* address offset: 0x0c94 */ + uint32_t reserved0c98[2]; /* address offset: 0x0c98 */ + uint32_t grf_dsm_ioc_con; /* address offset: 0x0ca0 */ +}; + +check_member(rv1126b_vccio7_ioc_reg, grf_dsm_ioc_con, 0x0ca0); + +#endif /* _ASM_ARCH_GRF_RV1126B_H */ diff --git a/u-boot/arch/arm/mach-rockchip/Kconfig b/u-boot/arch/arm/mach-rockchip/Kconfig index c6f30452e57..63257b0e38a 100644 --- a/u-boot/arch/arm/mach-rockchip/Kconfig +++ b/u-boot/arch/arm/mach-rockchip/Kconfig @@ -32,11 +32,18 @@ config TPL_MAX_SIZE default 10240 config ROCKCHIP_RK3326 - bool "Support Rockchip RK3326 " + bool "Support Rockchip RK3326" help RK3326 can use most code from PX30, but at some situations we have to distinguish between RK3326 and PX30, so this macro gives help. It is usually selected in rk3326 board defconfig. + +config ROCKCHIP_RK3358 + bool "Support Rockchip RK3358" + help + RK3358 can use most code from PX30, but at some situations we have + to distinguish between RK3358 and PX30, so this macro gives help. + It is usually selected in rk3358 board defconfig. endif config ROCKCHIP_RK3036 @@ -51,6 +58,7 @@ config ROCKCHIP_RK3036 select TPL_NEEDS_SEPARATE_TEXT_BASE if TPL select TPL_NEEDS_SEPARATE_STACK if TPL select ARM_SMCCC + select ARM_ERRATA_814220 help The Rockchip RK3036 is a ARM-based SoC with a dual-core Cortex-A7 including NEON and GPU, Mali-400 graphics, several DDR3 options @@ -62,6 +70,7 @@ config ROCKCHIP_RK3128 select CPU_V7 select GICV2 select ARM_SMCCC + select ARM_ERRATA_814220 help The Rockchip RK3128 is a ARM-based SoC with a quad-core Cortex-A7 including NEON and GPU, Mali-400 graphics, several DDR3 options @@ -138,6 +147,7 @@ config ROCKCHIP_RK322X select TPL_LIBGENERIC_SUPPORT select GICV2 select ARM_SMCCC + select ARM_ERRATA_814220 help The Rockchip RK3229 is a ARM-based SoC with a dual-core Cortex-A7 including NEON and GPU, Mali-400 graphics, several DDR3 options @@ -388,6 +398,7 @@ config ROCKCHIP_RK3506 select DEBUG_UART_BOARD_INIT select ARM_SMCCC select GICV2 + select ARM_ERRATA_814220 imply SUPPORT_SPL imply SUPPORT_TPL imply SPL @@ -443,15 +454,15 @@ endif config ROCKCHIP_RK3562 bool "Support Rockchip RK3562" - select GICV2 - select ARM64 select ARM_SMCCC - select SUPPORT_TPL - select SUPPORT_SPL + select ARM64 if !ARM64_BOOT_AARCH32 + select GICV2 if !ARM64_BOOT_AARCH32 + select SUPPORT_TPL if !ARM64_BOOT_AARCH32 + select SUPPORT_SPL if !ARM64_BOOT_AARCH32 select TPL_TINY_FRAMEWORK if TPL select DEBUG_UART_BOARD_INIT - imply TPL - imply SPL + imply TPL if !ARM64_BOOT_AARCH32 + imply SPL if !ARM64_BOOT_AARCH32 imply TPL_SERIAL_SUPPORT help The Rockchip RK3562 is a ARM-based SoC with a quad-core Cortex-A53. @@ -590,6 +601,7 @@ config ROCKCHIP_RV1103B select ARM_ZERO_CNTVOFF select ROCKCHIP_BROM_HELPER select DEBUG_UART_BOARD_INIT + select ARM_ERRATA_814220 imply SUPPORT_SPL imply SUPPORT_TPL imply SPL @@ -619,6 +631,7 @@ config ROCKCHIP_RV1106 bool "Support Rockchip RV1106" select CPU_V7 select DEBUG_UART_BOARD_INIT + select ARM_ERRATA_814220 imply SUPPORT_SPL imply SUPPORT_TPL imply SPL @@ -651,6 +664,7 @@ config ROCKCHIP_RV1108 select SPL select TPL select BOARD_LATE_INIT + select ARM_ERRATA_814220 help The Rockchip RV1108 is a ARM-based SoC with a single-core Cortex-A7 and a DSP. @@ -678,6 +692,7 @@ config ROCKCHIP_RV1126 imply SUPPORT_SPL imply TPL_TINY_FRAMEWORK if TPL select DEBUG_UART_BOARD_INIT + select ARM_ERRATA_814220 imply TPL imply SPL imply GICV2 @@ -701,6 +716,35 @@ config TPL_MAX_SIZE default 32768 endif +config ROCKCHIP_RV1126B + bool "Support Rockchip RV1126B" + select ARM64 if !ARM64_BOOT_AARCH32 + select GICV2 if !ARM64_BOOT_AARCH32 + select ARM_SMCCC + select DEBUG_UART_BOARD_INIT + select ROCKCHIP_BROM_HELPER + select SUPPORT_TPL if !ARM64_BOOT_AARCH32 + select SUPPORT_SPL if !ARM64_BOOT_AARCH32 + select TPL_TINY_FRAMEWORK if TPL + imply TPL if !ARM64_BOOT_AARCH32 + imply SPL if !ARM64_BOOT_AARCH32 + imply TPL_SERIAL_SUPPORT + help + The Rockchip RV1126B is a ARM-based SoC with a quad-core Cortex-A53. + +if ROCKCHIP_RV1126B + +config TPL_LDSCRIPT + default "arch/arm/mach-rockchip/u-boot-tpl-v8.lds" + +config TPL_TEXT_BASE + default 0x3ffb1000 + +config TPL_MAX_SIZE + default 61440 + +endif + config SPL_ROCKCHIP_BACK_TO_BROM bool "SPL returns to bootrom" default y if ROCKCHIP_RK3036 @@ -758,6 +802,7 @@ config ROCKCHIP_BOOT_MODE_REG default 0xff020200 if ROCKCHIP_RV1106 default 0x10300580 if ROCKCHIP_RV1108 default 0xfe020200 if ROCKCHIP_RV1126 + default 0x20130220 if ROCKCHIP_RV1126B default 0 help The Soc will enter to different boot mode(defined in asm/arch/boot_mode.h) @@ -787,6 +832,7 @@ config ROCKCHIP_STIMER_BASE default 0xff590020 if ROCKCHIP_RV1106 default 0x10350020 if ROCKCHIP_RV1108 default 0xff670020 if ROCKCHIP_RV1126 + default 0x20820000 if ROCKCHIP_RV1126B default 0 help The secure timer inited in SPL/TPL in secure word, ARM generic timer @@ -814,6 +860,7 @@ config ROCKCHIP_IRAM_START_ADDR default 0xff6c0000 if ROCKCHIP_RV1106 default 0x10080000 if ROCKCHIP_RV1108 default 0xff700000 if ROCKCHIP_RV1126 + default 0x3ffb0000 if ROCKCHIP_RV1126B default 0 help The IRAM start addr is to locate variant of the boot device from @@ -1272,5 +1319,6 @@ source "arch/arm/mach-rockchip/rv1103b/Kconfig" source "arch/arm/mach-rockchip/rv1106/Kconfig" source "arch/arm/mach-rockchip/rv1108/Kconfig" source "arch/arm/mach-rockchip/rv1126/Kconfig" +source "arch/arm/mach-rockchip/rv1126b/Kconfig" endif diff --git a/u-boot/arch/arm/mach-rockchip/Makefile b/u-boot/arch/arm/mach-rockchip/Makefile index 6d0eb022568..c1d2bebdf9a 100644 --- a/u-boot/arch/arm/mach-rockchip/Makefile +++ b/u-boot/arch/arm/mach-rockchip/Makefile @@ -85,6 +85,7 @@ obj-$(CONFIG_ROCKCHIP_RV1103B) += rv1103b/ obj-$(CONFIG_ROCKCHIP_RV1106) += rv1106/ obj-$(CONFIG_ROCKCHIP_RV1108) += rv1108/ obj-$(CONFIG_ROCKCHIP_RV1126) += rv1126/ +obj-$(CONFIG_ROCKCHIP_RV1126B) += rv1126b/ # Clear out SPL objects, in case this is a TPL build obj-spl-$(CONFIG_TPL_BUILD) = diff --git a/u-boot/arch/arm/mach-rockchip/chip_info.c b/u-boot/arch/arm/mach-rockchip/chip_info.c index 2b110ae9f6c..8aecc43e38b 100644 --- a/u-boot/arch/arm/mach-rockchip/chip_info.c +++ b/u-boot/arch/arm/mach-rockchip/chip_info.c @@ -105,6 +105,8 @@ int rockchip_rockusb_get_chip_info(unsigned int chip_info[]) chip_info[0] = 0x31383041; #elif defined(CONFIG_ROCKCHIP_RV1126) chip_info[0] = 0x31313236; +#elif defined(CONFIG_ROCKCHIP_RV1126B) + chip_info[0] = 0x31313046; #elif defined(CONFIG_ROCKCHIP_RV1106) chip_info[0] = 0x31313036; #endif diff --git a/u-boot/arch/arm/mach-rockchip/fit.c b/u-boot/arch/arm/mach-rockchip/fit.c index c15c9a4498b..310bb57dd81 100644 --- a/u-boot/arch/arm/mach-rockchip/fit.c +++ b/u-boot/arch/arm/mach-rockchip/fit.c @@ -236,6 +236,20 @@ static int fit_image_fixup_alloc(const void *fit, const char *prop_name, if (ret) return ret; +/* + * 1. When need load HWID dtb, gd->fdt_blob points to HWID dtb + * and U-Boot will re-alloc MEM_FDT based on fdt node in + * ITB instead of resource. So alloc the larger size to + * avoid fail in sysmem. It will already skip load DTB in fdt node. + * + * 2. Additionally increase size with CONFIG_SYS_FDT_PAD to reserve + * some space for adding more props to dtb afterwards. + */ + if (!strcmp(prop_name, FIT_FDT_PROP) && !fdt_check_header(gd->fdt_blob)) + size = ((size > fdt_totalsize(gd->fdt_blob)) ? + size : fdt_totalsize(gd->fdt_blob)) + + CONFIG_SYS_FDT_PAD; + if (!sysmem_alloc_base(mem, (phys_addr_t)addr, ALIGN(size, RK_BLK_SIZE))) return -ENOMEM; @@ -257,7 +271,7 @@ int fit_image_pre_process(const void *fit) return ret; } -#if !defined(CONFIG_ARM64) && defined(CONFIG_CMD_BOOTZ) +#if defined(CONFIG_CMD_BOOTZ) int cfg_noffset, noffset; const void *buf; ulong start, end; @@ -271,10 +285,23 @@ int fit_image_pre_process(const void *fit) noffset = fit_conf_get_prop_node_index(fit, cfg_noffset, FIT_KERNEL_PROP, 0); if (noffset < 0) { - printf("Could not find subimage node\n"); + printf("Could not find kernel node\n"); return -ENOENT; } + /* + * "kernel_addr_r" is for 64-bit kernel Image by default. + * Here in case of 64-bit U-Boot load 32-bit kenrel Image. + */ +#ifdef CONFIG_ARM64 + char *kernel_addr_r; + + if (fit_image_check_arch(fit, noffset, IH_ARCH_ARM)) { + kernel_addr_r = env_get("kernel_addr_aarch32_r"); + if (kernel_addr_r) + env_set("kernel_addr_r", kernel_addr_r); + } +#endif /* get image data address and length */ if (fit_image_get_data(fit, noffset, &buf, &size)) { printf("Could not find %s subimage data!\n", FIT_KERNEL_PROP); diff --git a/u-boot/arch/arm/mach-rockchip/fit_args.sh b/u-boot/arch/arm/mach-rockchip/fit_args.sh index d92cbf5a9ea..ea234791c32 100755 --- a/u-boot/arch/arm/mach-rockchip/fit_args.sh +++ b/u-boot/arch/arm/mach-rockchip/fit_args.sh @@ -37,9 +37,12 @@ function help() echo } +DRAM_BASE=`sed -n "/CONFIG_SYS_SDRAM_BASE=/s/CONFIG_SYS_SDRAM_BASE=//p" ${srctree}/include/autoconf.mk|tr -d '\r'` + if [ $# -eq 1 ]; then # default TEE_OFFSET=0x08400000 + TEE_LOAD_ADDR="0x"$(echo "obase=16;$((DRAM_BASE+TEE_OFFSET))"|bc) else # args while [ $# -gt 0 ]; do @@ -52,48 +55,56 @@ else COMPRESSION=$2 shift 2 ;; + -i0) + INIT0_LOAD_ADDR=$2 + shift 2 + ;; -m0) - MCU0_OFFSET=$2 + MCU0_LOAD_ADDR=$2 shift 2 ;; -m1) - MCU1_OFFSET=$2 + MCU1_LOAD_ADDR=$2 shift 2 ;; -m2) - MCU2_OFFSET=$2 + MCU2_LOAD_ADDR=$2 shift 2 ;; -m3) - MCU3_OFFSET=$2 + MCU3_LOAD_ADDR=$2 shift 2 ;; -m4) - MCU4_OFFSET=$2 + MCU4_LOAD_ADDR=$2 shift 2 ;; -l0) - LOAD0_OFFSET=$2 + LOAD0_LOAD_ADDR=$2 shift 2 ;; -l1) - LOAD1_OFFSET=$2 + LOAD1_LOAD_ADDR=$2 shift 2 ;; -l2) - LOAD2_OFFSET=$2 + LOAD2_LOAD_ADDR=$2 shift 2 ;; -l3) - LOAD3_OFFSET=$2 + LOAD3_LOAD_ADDR=$2 shift 2 ;; -l4) - LOAD4_OFFSET=$2 + LOAD4_LOAD_ADDR=$2 shift 2 ;; -t) - TEE_OFFSET=$2 + TEE_LOAD_ADDR=$2 + # Compatible leagcy: Offset + if ((TEE_LOAD_ADDR < DRAM_BASE)); then + TEE_LOAD_ADDR="0x"$(echo "obase=16;$((DRAM_BASE+$2))"|bc) + fi shift 2 ;; *) @@ -105,8 +116,6 @@ else done fi -# Base -DARM_BASE=`sed -n "/CONFIG_SYS_SDRAM_BASE=/s/CONFIG_SYS_SDRAM_BASE=//p" ${srctree}/include/autoconf.mk|tr -d '\r'` if ! grep -q '^CONFIG_FIT_OMIT_UBOOT=y' .config ; then UBOOT_LOAD_ADDR=`sed -n "/CONFIG_SYS_TEXT_BASE=/s/CONFIG_SYS_TEXT_BASE=//p" ${srctree}/include/autoconf.mk|tr -d '\r'` fi @@ -121,43 +130,3 @@ elif grep -q '^CONFIG_ARM64_BOOT_AARCH32=y' .config ; then else ARCH="arm" fi - -# tee -if [ ! -z "${TEE_OFFSET}" ]; then - TEE_LOAD_ADDR="0x"$(echo "obase=16;$((DARM_BASE+TEE_OFFSET))"|bc) -fi - -# mcu -if [ ! -z "${MCU0_OFFSET}" ]; then - MCU0_LOAD_ADDR="0x"$(echo "obase=16;$((DARM_BASE+$MCU0_OFFSET))"|bc) -fi -if [ ! -z "${MCU1_OFFSET}" ]; then - MCU1_LOAD_ADDR="0x"$(echo "obase=16;$((DARM_BASE+$MCU1_OFFSET))"|bc) -fi -if [ ! -z "${MCU2_OFFSET}" ]; then - MCU2_LOAD_ADDR="0x"$(echo "obase=16;$((DARM_BASE+$MCU2_OFFSET))"|bc) -fi -if [ ! -z "${MCU3_OFFSET}" ]; then - MCU3_LOAD_ADDR="0x"$(echo "obase=16;$((DARM_BASE+$MCU3_OFFSET))"|bc) -fi -if [ ! -z "${MCU4_OFFSET}" ]; then - MCU4_LOAD_ADDR="0x"$(echo "obase=16;$$((DARM_BASE+$MCU4_OFFSET))"|bc) -fi - -# loadables -if [ ! -z "${LOAD0_OFFSET}" ]; then - LOAD0_LOAD_ADDR="0x"$(echo "obase=16;$((DARM_BASE+$LOAD0_OFFSET))"|bc) -fi -if [ ! -z "${LOAD1_OFFSET}" ]; then - LOAD1_LOAD_ADDR="0x"$(echo "obase=16;$((DARM_BASE+$LOAD1_OFFSET))"|bc) -fi -if [ ! -z "${LOAD2_OFFSET}" ]; then - LOAD2_LOAD_ADDR="0x"$(echo "obase=16;$((DARM_BASE+$LOAD2_OFFSET))"|bc) -fi -if [ ! -z "${LOAD3_OFFSET}" ]; then - LOAD3_LOAD_ADDR="0x"$(echo "obase=16;$((DARM_BASE+$LOAD3_OFFSET))"|bc) -fi -if [ ! -z "${LOAD4_OFFSET}" ]; then - LOAD4_LOAD_ADDR="0x"$(echo "obase=16;$((DARM_BASE+$LOAD4_OFFSET))"|bc) -fi -# echo " ## $DARM_BASE, $UBOOT_LOAD_ADDR, $TEE_LOAD_ADDR, $MCU0_LOAD_ADDR, $MCU1_LOAD_ADDR, $MCU2_LOAD_ADDR, $MCU3_LOAD_ADDR, $MCU4_LOAD_ADDR" diff --git a/u-boot/arch/arm/mach-rockchip/fit_nodes.sh b/u-boot/arch/arm/mach-rockchip/fit_nodes.sh index 993728b9b86..8ed26337e27 100755 --- a/u-boot/arch/arm/mach-rockchip/fit_nodes.sh +++ b/u-boot/arch/arm/mach-rockchip/fit_nodes.sh @@ -12,6 +12,8 @@ rm -f ${srctree}/*.digest ${srctree}/*.bin.gz ${srctree}/bl31_0x*.bin # Periph register base if grep -q '^CONFIG_ROCKCHIP_RK3576=y' .config ; then MAX_ADDR_VAL=$((0x10000000)) +elif grep -q '^CONFIG_ROCKCHIP_RV1126B=y' .config ; then +MAX_ADDR_VAL=$((0x20000000)) elif grep -q '^CONFIG_ROCKCHIP_RV1103B=y' .config ; then MAX_ADDR_VAL=$((0x20000000)) else @@ -19,7 +21,7 @@ MAX_ADDR_VAL=$((0xf0000000)) fi # dram base -DRAM_BASE_VAL=$((DRAM_BASE)) +DRAM_BASE_VAL=`sed -n "/CONFIG_SYS_SDRAM_BASE=/s/CONFIG_SYS_SDRAM_BASE=//p" ${srctree}/include/autoconf.mk|tr -d '\r'` # compression if [ "${COMPRESSION}" == "gzip" ]; then @@ -247,8 +249,8 @@ function gen_mcu_node() # When allow to be compressed? # DRAM base < load addr < Periph register base # Periph register base < DRAM base < load addr - if [ "${COMPRESSION}" != "none" -a ${MCU_ADDR_VAL} -gt ${DRAM_BASE_VAL} ] && - [ ${DRAM_BASE_VAL} -gt ${MAX_ADDR_VAL} -o ${MCU_ADDR_VAL} -lt ${MAX_ADDR_VAL} ]; then + if [ "${COMPRESSION}" != "none" -a "$((MCU_ADDR_VAL))" -gt "$((DRAM_BASE_VAL))" ] && + [ "$((DRAM_BASE_VAL))" -gt "$((MAX_ADDR_VAL))" -o "$((MCU_ADDR_VAL))" -lt "$((MAX_ADDR_VAL))" ]; then openssl dgst -sha256 -binary -out ${MCU}.bin.digest ${MCU}.bin ${COMPRESS_CMD} ${MCU}.bin echo " data = /incbin/(\"./${MCU}.bin${SUFFIX}\"); @@ -277,6 +279,24 @@ function gen_mcu_node() STANDALONE_SIGN=", \"standalone\"" STANDALONE_MCU="standalone = ${STANDALONE_LIST};" done + + if [ -z ${INIT0_LOAD_ADDR} ]; then + return + fi + + INIT="init0" + echo " ${INIT} { + description = \"${INIT}\"; + type = \"standalone\"; + arch = \"${ARCH}\"; + load = <"${INIT0_LOAD_ADDR}">; + data = /incbin/(\"./${INIT}.bin\"); + compression = \"none\"; + hash { + algo = \"sha256\"; + }; + };" + STANDALONE_MCU="standalone = \"init0\"${STANDALONE_LIST};" } function gen_loadable_node() @@ -310,8 +330,8 @@ function gen_loadable_node() # When allow to be compressed? # DRAM base < load addr < Periph register base # Periph register base < DRAM base < load addr - if [ "${COMPRESSION}" != "none" -a ${LOAD_ADDR_VAL} -gt ${DRAM_BASE_VAL} ] && - [ ${DRAM_BASE_VAL} -gt ${MAX_ADDR_VAL} -o ${LOAD_ADDR_VAL} -lt ${MAX_ADDR_VAL} ]; then + if [ "${COMPRESSION}" != "none" -a "$((MCU_ADDR_VAL))" -gt "$((DRAM_BASE_VAL))" ] && + [ "$((DRAM_BASE_VAL))" -gt "$((MAX_ADDR_VAL))" -o "$((MCU_ADDR_VAL))" -lt "$((MAX_ADDR_VAL))" ]; then openssl dgst -sha256 -binary -out ${LOAD}.bin.digest ${LOAD}.bin ${COMPRESS_CMD} ${LOAD}.bin echo " data = /incbin/(\"./${LOAD}.bin${SUFFIX}\"); diff --git a/u-boot/arch/arm/mach-rockchip/rk3399/rk3399.c b/u-boot/arch/arm/mach-rockchip/rk3399/rk3399.c index b88b757cebe..5d2725ede28 100644 --- a/u-boot/arch/arm/mach-rockchip/rk3399/rk3399.c +++ b/u-boot/arch/arm/mach-rockchip/rk3399/rk3399.c @@ -138,7 +138,7 @@ void board_debug_uart_init(void) /* Enable early UART2 channel on the RK3399/RK3399PRO */ rk_clrsetreg(&grf->gpio4c_iomux, GRF_GPIO4C3_SEL_MASK, - GRF_UART2DGBC_SIN << GRF_GPIO4C3_SEL_SHIFT); + GRF_UART2DBGC_SIN << GRF_GPIO4C3_SEL_SHIFT); rk_clrsetreg(&grf->gpio4c_iomux, GRF_GPIO4C4_SEL_MASK, GRF_UART2DBGC_SOUT << GRF_GPIO4C4_SEL_SHIFT); diff --git a/u-boot/arch/arm/mach-rockchip/rk3506/rk3506.c b/u-boot/arch/arm/mach-rockchip/rk3506/rk3506.c index c8fc4aa1b56..8ef9b586ee4 100644 --- a/u-boot/arch/arm/mach-rockchip/rk3506/rk3506.c +++ b/u-boot/arch/arm/mach-rockchip/rk3506/rk3506.c @@ -16,7 +16,8 @@ DECLARE_GLOBAL_DATA_PTR; #define GRF_BASE 0xff288000 -#define GRF_SOC_CON28 0X0070 +#define GRF_SOC_CON6 0x0018 +#define GRF_SOC_CON28 0x0070 #define USBPHY_APB_BASE 0xff2b0000 #define USBPHY_DIFF_RECEIVER_0 0x0030 @@ -25,6 +26,13 @@ DECLARE_GLOBAL_DATA_PTR; #define FIREWALL_DDR_BASE 0xff5f0000 #define FW_DDR_MST1_REG 0x24 +#define DSI_HOST_BASE 0xff640000 +#define MIPS_DSI_PHY_RSTZ 0xa0 + +#define DPHY_BASE 0xff670000 +#define MIPI_TX_PHY_TTL_MODE_CTRL2 0x38c +#define MIPI_TX_PHY_TTL_MODE_CTRL4 0x3ac + #define GPIO0_IOC_BASE 0xff950000 #define GPIO1_IOC_BASE 0xff660000 @@ -39,6 +47,7 @@ DECLARE_GLOBAL_DATA_PTR; #define CRU_BASE 0xff9a0000 #define CRU_GLB_RST_CON 0xc10 +#define CRU_GATE_CON1 0x0804 #define CRU_GATE_CON5 0x0814 #define CRU_SOFTRST_CON5 0x0a14 @@ -157,6 +166,21 @@ int arch_cpu_init(void) writel(0x01ff01d1, GRF_BASE + GRF_SOC_CON28); writel(0x00000079, USBPHY_APB_BASE + USBPHY_DIFF_RECEIVER_0); writel(0x00000079, USBPHY_APB_BASE + USBPHY_DIFF_RECEIVER_1); + + /* + * Set mcu jtag clock un-gate. + * Configure when in use. + */ + //writel(0x00220000, 0xff960000); + + /* + * gpio4Ax is used as MIPI by default. + * The following command switches MIPI to gpio. + */ + //writel(0x03000300, GRF_BASE + GRF_SOC_CON6); + //writel(0x4, DSI_HOST_BASE + MIPS_DSI_PHY_RSTZ); + //writel(0x4, DPHY_BASE + MIPI_TX_PHY_TTL_MODE_CTRL2); + //writel(0xfd, DPHY_BASE + MIPI_TX_PHY_TTL_MODE_CTRL4); #endif return 0; } @@ -183,7 +207,6 @@ int fit_standalone_release(char *id, uintptr_t entry_point) writel(0x00060004, 0xff90000c); /* select jtag m1 GPIO0C6 GPIO0C7 */ - //writel(0x00220000, 0xff960000); //writel(0x00300020, 0xff288000); //writel(0x00ff0022, 0xff4d8064); //writel(0xff002200, 0xff950014); diff --git a/u-boot/arch/arm/mach-rockchip/rk3568/rk3568.c b/u-boot/arch/arm/mach-rockchip/rk3568/rk3568.c index 3b33322a6c7..89e0eb3ca5a 100644 --- a/u-boot/arch/arm/mach-rockchip/rk3568/rk3568.c +++ b/u-boot/arch/arm/mach-rockchip/rk3568/rk3568.c @@ -61,6 +61,13 @@ DECLARE_GLOBAL_DATA_PTR; #define EBC_PRIORITY_REG (0xfe158008) +#define SATA0_BASE_ADDR 0xfc000000 +#define SATA1_BASE_ADDR 0xfc400000 +#define SATA2_BASE_ADDR 0xfc800000 +#define SATA_PI 0xC +#define SATA_PORT_CMD 0x118 +#define SATA_FBS_ENABLE BIT(22) + enum { /* PMU_GRF_GPIO0C_IOMUX_L */ GPIO0C1_SHIFT = 4, @@ -945,6 +952,15 @@ int arch_cpu_init(void) writel((0x77771111), GRF_BASE + GRF_GPIO1C_IOMUX_L); writel((0x07770111), GRF_BASE + GRF_GPIO1C_IOMUX_H); #endif + /* + * Set SATA FBSCP and PORTS_IMPL for kernel drivers + */ + writel(SATA_FBS_ENABLE, SATA0_BASE_ADDR + SATA_PORT_CMD); + writel(1, SATA0_BASE_ADDR + SATA_PI); + writel(SATA_FBS_ENABLE, SATA1_BASE_ADDR + SATA_PORT_CMD); + writel(1, SATA1_BASE_ADDR + SATA_PI); + writel(SATA_FBS_ENABLE, SATA2_BASE_ADDR + SATA_PORT_CMD); + writel(1, SATA2_BASE_ADDR + SATA_PI); #endif return 0; diff --git a/u-boot/arch/arm/mach-rockchip/rk3576/rk3576.c b/u-boot/arch/arm/mach-rockchip/rk3576/rk3576.c index c664c743f36..d832311caed 100644 --- a/u-boot/arch/arm/mach-rockchip/rk3576/rk3576.c +++ b/u-boot/arch/arm/mach-rockchip/rk3576/rk3576.c @@ -94,6 +94,12 @@ DECLARE_GLOBAL_DATA_PTR; #define PMU1_CRU_GATE_CON03 0x080C #define PMU1_CRU_SOFTRST_CON03 0x0a0C +#define SATA0_BASE_ADDR 0x2a240000 +#define SATA1_BASE_ADDR 0x2a250000 +#define SATA_PI 0xC +#define SATA_PORT_CMD 0x118 +#define SATA_FBS_ENABLE BIT(22) + #ifdef CONFIG_ARM64 #include @@ -121,7 +127,7 @@ static struct mm_region rk3576_mem_map[] = { }, { .virt = 0x100000000UL, .phys = 0x100000000UL, - .size = 0x300000000UL, + .size = 0x400000000UL, .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_INNER_SHARE }, { @@ -400,6 +406,14 @@ int arch_cpu_init(void) * Module: GMAC0/1, MMU0/1(PCIe, SATA, USB3) */ writel(0xffffff00, SYS_SGRF_BASE + SYS_SGRF_SOC_CON20); +#else + /* + * Set SATA FBSCP and PORTS_IMPL for kernel drivers + */ + writel(SATA_FBS_ENABLE, SATA0_BASE_ADDR + SATA_PORT_CMD); + writel(1, SATA0_BASE_ADDR + SATA_PI); + writel(SATA_FBS_ENABLE, SATA1_BASE_ADDR + SATA_PORT_CMD); + writel(1, SATA1_BASE_ADDR + SATA_PI); #endif #if defined(CONFIG_ROCKCHIP_EMMC_IOMUX) diff --git a/u-boot/arch/arm/mach-rockchip/rk3588/rk3588.c b/u-boot/arch/arm/mach-rockchip/rk3588/rk3588.c index e42a1aef996..986bf56519b 100644 --- a/u-boot/arch/arm/mach-rockchip/rk3588/rk3588.c +++ b/u-boot/arch/arm/mach-rockchip/rk3588/rk3588.c @@ -102,6 +102,13 @@ DECLARE_GLOBAL_DATA_PTR; #define MMU600PHP_TCU_PRIORITY_REG 0xfdf3a808 #define QOS_PRIORITY_LEVEL(h, l) ((((h) & 7) << 8) | ((l) & 7)) +#define SATA0_BASE_ADDR 0xfe210000 +#define SATA1_BASE_ADDR 0xfe220000 +#define SATA2_BASE_ADDR 0xfe230000 +#define SATA_PI 0xC +#define SATA_PORT_CMD 0x118 +#define SATA_FBS_ENABLE BIT(22) + #ifdef CONFIG_ARM64 #include @@ -1067,6 +1074,16 @@ int arch_cpu_init(void) */ writel(QOS_PRIORITY_LEVEL(4, 4), MMU600PHP_TBU_PRIORITY_REG); writel(QOS_PRIORITY_LEVEL(4, 4), MMU600PHP_TCU_PRIORITY_REG); + + /* + * Set SATA FBSCP and PORTS_IMPL for kernel drivers + */ + writel(SATA_FBS_ENABLE, SATA0_BASE_ADDR + SATA_PORT_CMD); + writel(1, SATA0_BASE_ADDR + SATA_PI); + writel(SATA_FBS_ENABLE, SATA1_BASE_ADDR + SATA_PORT_CMD); + writel(1, SATA1_BASE_ADDR + SATA_PI); + writel(SATA_FBS_ENABLE, SATA2_BASE_ADDR + SATA_PORT_CMD); + writel(1, SATA2_BASE_ADDR + SATA_PI); #endif /* Select usb otg0 phy status to 0 that make rockusb can work at high-speed */ diff --git a/u-boot/arch/arm/mach-rockchip/rv1126b/Kconfig b/u-boot/arch/arm/mach-rockchip/rv1126b/Kconfig new file mode 100644 index 00000000000..928fe317dc2 --- /dev/null +++ b/u-boot/arch/arm/mach-rockchip/rv1126b/Kconfig @@ -0,0 +1,17 @@ +if ROCKCHIP_RV1126B + +config TARGET_EVB_RV1126B + bool "EVB_RV1126B" + select BOARD_LATE_INIT + help + RV1126B EVB is a evaluation board for Rockchp RV1126B. + +config SYS_SOC + default "rockchip" + +config SYS_MALLOC_F_LEN + default 0x400 + +source board/rockchip/evb_rv1126b/Kconfig + +endif diff --git a/u-boot/arch/arm/mach-rockchip/rv1126b/Makefile b/u-boot/arch/arm/mach-rockchip/rv1126b/Makefile new file mode 100644 index 00000000000..c9e790714e2 --- /dev/null +++ b/u-boot/arch/arm/mach-rockchip/rv1126b/Makefile @@ -0,0 +1,11 @@ +# +# (C) Copyright 2025 Rockchip Electronics Co., Ltd +# +# SPDX-License-Identifier: GPL-2.0+ +# + +ifneq ($(CONFIG_TPL_BUILD)$(CONFIG_TPL_TINY_FRAMEWORK),yy) +obj-y += syscon_rv1126b.o +endif +obj-y += rv1126b.o +obj-y += clk_rv1126b.o diff --git a/u-boot/arch/arm/mach-rockchip/rv1126b/clk_rv1126b.c b/u-boot/arch/arm/mach-rockchip/rv1126b/clk_rv1126b.c new file mode 100644 index 00000000000..359eb1c5c22 --- /dev/null +++ b/u-boot/arch/arm/mach-rockchip/rv1126b/clk_rv1126b.c @@ -0,0 +1,41 @@ +/* + * (C) Copyright 2025 Rockchip Electronics Co., Ltd. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include + +int rockchip_get_clk(struct udevice **devp) +{ + return uclass_get_device_by_driver(UCLASS_CLK, + DM_GET_DRIVER(rockchip_rv1126b_cru), devp); +} + +#if CONFIG_IS_ENABLED(CLK_SCMI) +int rockchip_get_scmi_clk(struct udevice **devp) +{ + return uclass_get_device_by_driver(UCLASS_CLK, + DM_GET_DRIVER(scmi_clock), devp); +} +#endif + +void *rockchip_get_cru(void) +{ + struct rv1126b_clk_priv *priv; + struct udevice *dev; + int ret; + + ret = rockchip_get_clk(&dev); + if (ret) + return ERR_PTR(ret); + + priv = dev_get_priv(dev); + + return priv->cru; +} + diff --git a/u-boot/arch/arm/mach-rockchip/rv1126b/rv1126b.c b/u-boot/arch/arm/mach-rockchip/rv1126b/rv1126b.c new file mode 100644 index 00000000000..ca1deea15b7 --- /dev/null +++ b/u-boot/arch/arm/mach-rockchip/rv1126b/rv1126b.c @@ -0,0 +1,360 @@ +/* + * Copyright (c) 2025 Rockchip Electronics Co., Ltd + * + * SPDX-License-Identifier: GPL-2.0+ + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +/* CRU */ +#define CRU_BUS_BASE 0x20010000 +#define CRU_BUS_GATE_CON06 0x818 +#define CRU_BUS_SOFTRST_CON01 0x0a04 +#define CRU_PMU_BASE 0x20040000 +#define CRU_PMU_SOFTRST_CON03 0x0a0c +#define PERI_CRU_BASE 0x20020000 +#define PERICRU_PERI_SOFTRST_CON01 0x0a04 + +/* GRF */ +#define SYS_GRF_BASE 0x20100000 +#define TSADC_GRF_CON0 0x50 +#define TSADC_GRF_CON1 0x54 +#define TSADC_GRF_CON6 0x68 +#define GRF_JTAG_CON0 0x904 + +#define PERI_GRF_BASE 0x20110000 +#define PERI_GRF_USB2HOSTPHY_CON0 0x001c +#define PERI_GRF_USB3DRD_CON1 0x003C + +#define VI_GRF_BASE 0x20150000 +#define SARADC1_GRF_CON0 0x80 +#define SARADC2_GRF_CON0 0x90 + +#define VEPU_GRF_BASE 0x20160000 +#define SARADC0_GRF_CON0 0x0C + +/* PMU */ +#define PMU_GRF_BASE 0x20130000 +#define PMU_GRF_SOC_CON0 0x0000 +#define PMU2_BASE 0x20838000 +#define PMU2_PWR_GATE_SFTCON0 0x0210 + +/* GPIO/IOC */ +#define GPIO0_BASE 0x20600000 +#define GPIO_SWPORT_DR_L 0x00 +#define GPIO_SWPORT_DDR_L 0x08 + +#define PMUIO0_IOC_BASE 0x201a0000 +#define GPIO0A_IOMUX_SEL_L 0x0 +#define GPIO0A_IOMUX_SEL_H 0x4 +#define GPIO0B_IOMUX_SEL_L 0x8 + +#define VCCIO1_IOC_BASE 0x201b0000 +#define GPIO1A_IOMUX_SEL_L 0x20 +#define GPIO1A_IOMUX_SEL_H 0x24 +#define GPIO1B_IOMUX_SEL_L 0x28 +#define GPIO1B_IOMUX_SEL_H 0x2c + +#define VCCIO2_IOC_BASE 0x201b8000 +#define GPIO2A_IOMUX_SEL_L 0x40 +#define GPIO2A_IOMUX_SEL_H 0x44 +#define GPIO2A_PULL 0x320 + +#define VCCIO3_IOC_BASE 0x201c0000 +#define GPIO3A_IOMUX_SEL_L 0x60 +#define GPIO3A_IOMUX_SEL_H 0x64 +#define GPIO3B_IOMUX_SEL_H 0x6c +#define GPIO3A_PULL 0x330 + +/* SGRF/FIREWALL */ +#define SGRF_SYS_BASE 0x20220000 +#define SGRF_HPMCU_BOOT_ADDR 0x0c +#define SGRF_SYS_AHB_SECURE_SGRF_CON 0x14 +#define SGRF_SYS_AXI_SECURE_SGRF_CON0 0x18 +#define FIREWALL_SLV_CON0 0x20 +#define FIREWALL_SLV_CON1 0x24 +#define FIREWALL_SLV_CON2 0x28 +#define FIREWALL_SLV_CON3 0x2c +#define FIREWALL_SLV_CON4 0x30 +#define FIREWALL_SLV_CON5 0x34 +#define OTP_SGRF_CON 0x1c + +#define SGRF_PMU_BASE 0x20230000 +#define SGRF_PMU_SOC_CON0 0x00 +#define SGRF_LPMCU_BOOT_ADDR 0x20 + +#ifdef CONFIG_ARM64 +#include + +static struct mm_region rv1126b_mem_map[] = { + { + .virt = 0x20000000UL, + .phys = 0x20000000UL, + .size = 0x2800000UL, + .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | + PTE_BLOCK_NON_SHARE | + PTE_BLOCK_PXN | PTE_BLOCK_UXN + }, { + .virt = 0x3ff1e000UL, + .phys = 0x3ff1e000UL, + .size = 0xe2000UL, + .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | + PTE_BLOCK_NON_SHARE | + PTE_BLOCK_PXN | PTE_BLOCK_UXN + }, { + .virt = 0x40000000UL, + .phys = 0x40000000UL, + .size = 0x100000000UL - 0x40000000UL, + .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | + PTE_BLOCK_INNER_SHARE + }, { + /* List terminator */ + 0, + } +}; + +struct mm_region *mem_map = rv1126b_mem_map; +#endif + +void board_debug_uart_init(void) +{ + /* No need to change uart in most time. */ +} + +void board_set_iomux(enum if_type if_type, int devnum, int routing) +{ + switch (if_type) { + case IF_TYPE_MMC: + if (devnum == 0) { + writel(0xffff1111, VCCIO1_IOC_BASE + GPIO1A_IOMUX_SEL_L); + writel(0xffff1111, VCCIO1_IOC_BASE + GPIO1A_IOMUX_SEL_H); + writel(0xf0f01010, VCCIO1_IOC_BASE + GPIO1B_IOMUX_SEL_L); + } else if (devnum == 1) { +#if CONFIG_SPL_BUILD + /* set SDMMC D0-3/CMD/CLK to gpio and pull down */ + writel(0xffff0000, VCCIO2_IOC_BASE + GPIO2A_IOMUX_SEL_L); + writel(0x00ff0000, VCCIO2_IOC_BASE + GPIO2A_IOMUX_SEL_H); + writel(0x00f00000, PMUIO0_IOC_BASE + GPIO0A_IOMUX_SEL_H); + writel(0x0fff0aaa, VCCIO2_IOC_BASE + GPIO2A_PULL); + + /* SDMMC PWREN GPIO0A4 power down and power up */ + writel(0x01000100, GPIO0_BASE + GPIO_SWPORT_DR_L); + writel(0x01000100, GPIO0_BASE + GPIO_SWPORT_DDR_L); + mdelay(50); + writel(0x01000000, GPIO0_BASE + GPIO_SWPORT_DR_L); +#endif + /* set SDMMC D0-3/CMD/CLK and pull up */ + writel(0xffff1111, VCCIO2_IOC_BASE + GPIO2A_IOMUX_SEL_L); + writel(0x00ff0011, VCCIO2_IOC_BASE + GPIO2A_IOMUX_SEL_H); + writel(0x00f00010, PMUIO0_IOC_BASE + GPIO0A_IOMUX_SEL_H); + writel(0x0fff0555, VCCIO2_IOC_BASE + GPIO2A_PULL); + } else if (devnum == 2) { + writel(0xffff1111, VCCIO3_IOC_BASE + GPIO3A_IOMUX_SEL_L); + writel(0x00ff0011, VCCIO3_IOC_BASE + GPIO3A_IOMUX_SEL_H); + writel(0x0f000300, VCCIO3_IOC_BASE + GPIO3B_IOMUX_SEL_H); + /* Pull up */ + writel(0x0ffc0554, VCCIO2_IOC_BASE + GPIO3A_PULL); + } + break; + case IF_TYPE_MTD: + if (routing == 0) { + /* FSPI0 M0 */ + writel(0x0f0f0101, VCCIO1_IOC_BASE + GPIO1B_IOMUX_SEL_L); + writel(0xffff1111, VCCIO1_IOC_BASE + GPIO1B_IOMUX_SEL_H); + writel(0x00f00020, VCCIO1_IOC_BASE + GPIO1A_IOMUX_SEL_H); + } else if (routing == 1) { + /* FSPI1 M0 */ + writel(0x0fff0111, PMUIO0_IOC_BASE + GPIO0B_IOMUX_SEL_L); + writel(0xff001100, PMUIO0_IOC_BASE + GPIO0A_IOMUX_SEL_H); + writel(0x00f00010, PMUIO0_IOC_BASE + GPIO0A_IOMUX_SEL_L); + } else if (routing == 2) { + /* FSPI1 M1 */ + writel(0xffff2222, VCCIO1_IOC_BASE + GPIO1A_IOMUX_SEL_L); + writel(0xf0f02020, VCCIO1_IOC_BASE + GPIO1B_IOMUX_SEL_L); + } + break; + default: + printf("Bootdev 0x%x is not support\n", if_type); + } +} + +void board_unset_iomux(enum if_type if_type, int devnum, int routing) +{ + switch (if_type) { + case IF_TYPE_MMC: + if (devnum == 0) { + writel(0xffff0000, VCCIO1_IOC_BASE + GPIO1A_IOMUX_SEL_L); + writel(0xffff0000, VCCIO1_IOC_BASE + GPIO1A_IOMUX_SEL_H); + writel(0xf0f00000, VCCIO1_IOC_BASE + GPIO1B_IOMUX_SEL_L); + } else if (devnum == 1) { + /* SDMMC0_D2,D3 -> JTAG_TMS_M1, JTAG_TCK_M1 */ + writel(0xffff4400, VCCIO2_IOC_BASE + GPIO2A_IOMUX_SEL_L); + /* Other SDMMC0 PINS -> GPIO */ + writel(0x00ff0000, VCCIO2_IOC_BASE + GPIO2A_IOMUX_SEL_H); + writel(0x00f00000, PMUIO0_IOC_BASE + GPIO0A_IOMUX_SEL_H); + /* Pull down */ + writel(0x0fff0aaa, VCCIO2_IOC_BASE + GPIO2A_PULL); + } else if (devnum == 2) { + writel(0xffff0000, VCCIO3_IOC_BASE + GPIO3A_IOMUX_SEL_L); + writel(0x00ff0000, VCCIO3_IOC_BASE + GPIO3A_IOMUX_SEL_H); + writel(0x0f000000, VCCIO3_IOC_BASE + GPIO3B_IOMUX_SEL_H); + /* Pull down */ + writel(0x0ffc0000, VCCIO2_IOC_BASE + GPIO3A_PULL); + } + break; + case IF_TYPE_MTD: + if (routing == 0) { + /* FSPI0 M0 */ + writel(0x0f0f0000, VCCIO1_IOC_BASE + GPIO1B_IOMUX_SEL_L); + writel(0xffff0000, VCCIO1_IOC_BASE + GPIO1B_IOMUX_SEL_H); + writel(0x00f00000, VCCIO1_IOC_BASE + GPIO1A_IOMUX_SEL_H); + } else if (routing == 1) { + /* FSPI1 M0 */ + writel(0x0fff0000, PMUIO0_IOC_BASE + GPIO0B_IOMUX_SEL_L); + writel(0xff000000, PMUIO0_IOC_BASE + GPIO0A_IOMUX_SEL_H); + writel(0x00f00000, PMUIO0_IOC_BASE + GPIO0A_IOMUX_SEL_L); + } else if (routing == 2) { + /* FSPI1 M1 */ + writel(0xffff0000, VCCIO1_IOC_BASE + GPIO1A_IOMUX_SEL_L); + writel(0xf0f00000, VCCIO1_IOC_BASE + GPIO1B_IOMUX_SEL_L); + } + break; + default: + break; + } +} + +#ifdef CONFIG_SPL_BUILD +void rockchip_stimer_init(void) +{ + u32 reg; + + /* If Timer already enabled, don't re-init it */ + reg = readl(CONFIG_ROCKCHIP_STIMER_BASE + 0x4); + if (reg & 0x1) + return; +#ifdef COUNTER_FREQUENCY + asm volatile("msr CNTFRQ_EL0, %0" : : "r" (COUNTER_FREQUENCY)); +#endif + writel(0xffffffff, CONFIG_ROCKCHIP_STIMER_BASE + 0x14); + writel(0xffffffff, CONFIG_ROCKCHIP_STIMER_BASE + 0x18); + writel(0x00010001, CONFIG_ROCKCHIP_STIMER_BASE + 0x04); +} + +void spl_board_storages_fixup(struct spl_image_loader *loader) +{ + if (!loader) + return; + + if (loader->boot_device == BOOT_DEVICE_MMC2) + /* Unset the sdmmc0 iomux */ + board_unset_iomux(IF_TYPE_MMC, 1, 0); +} + +int spl_fit_standalone_release(char *id, uintptr_t entry_point) +{ + if (!strcmp(id, "mcu0")) { + writel(0x1e001e0, CRU_BUS_BASE + CRU_BUS_SOFTRST_CON01); + writel(entry_point, SGRF_SYS_BASE + SGRF_HPMCU_BOOT_ADDR); + writel(0x1 << 20, SGRF_SYS_BASE + SGRF_SYS_AHB_SECURE_SGRF_CON); + writel(0x1e00000, CRU_BUS_BASE + CRU_BUS_SOFTRST_CON01); + } else if (!strcmp(id, "mcu1")) { + writel(0x1c001c, CRU_PMU_BASE + CRU_PMU_SOFTRST_CON03); + writel(entry_point, SGRF_PMU_BASE + SGRF_LPMCU_BOOT_ADDR); + writel(0x1 << 23, SGRF_PMU_BASE + SGRF_PMU_SOC_CON0); + writel(0x1c0000, CRU_PMU_BASE + CRU_PMU_SOFTRST_CON03); + } + + return 0; +} +#endif + +#ifndef CONFIG_TPL_BUILD +int arch_cpu_init(void) +{ +#if defined(CONFIG_SPL_BUILD) || defined(CONFIG_SUPPORT_USBPLUG) + /* Enable npu pd */ + writel(0x00010000, PMU2_BASE + PMU2_PWR_GATE_SFTCON0); + /* Set emmc master secure */ + writel(0x10000, SGRF_SYS_BASE + SGRF_SYS_AHB_SECURE_SGRF_CON); + /* Set fspi master secure */ + writel(0x20000, SGRF_SYS_BASE + SGRF_SYS_AHB_SECURE_SGRF_CON); + /* Set sdmmc0 master secure */ + writel(0x40000, SGRF_SYS_BASE + SGRF_SYS_AHB_SECURE_SGRF_CON); + /* Set sdmmc1 master secure */ + writel(0x80000, SGRF_SYS_BASE + SGRF_SYS_AHB_SECURE_SGRF_CON); + /* Set rkce master secure */ + writel(0x80030000, SGRF_SYS_BASE + SGRF_SYS_AXI_SECURE_SGRF_CON0); + /* Set decom master secure */ + writel(0xC00000, SGRF_SYS_BASE + SGRF_SYS_AXI_SECURE_SGRF_CON0); + + /* Set all devices slave non-secure */ + writel(0xffff0000, SGRF_SYS_BASE + FIREWALL_SLV_CON0); + writel(0xffff0000, SGRF_SYS_BASE + FIREWALL_SLV_CON1); + writel(0xffff0000, SGRF_SYS_BASE + FIREWALL_SLV_CON2); + writel(0xffff0000, SGRF_SYS_BASE + FIREWALL_SLV_CON3); + writel(0xffff0000, SGRF_SYS_BASE + FIREWALL_SLV_CON4); + writel(0xffff0000, SGRF_SYS_BASE + FIREWALL_SLV_CON5); + /* Set OTP to none secure mode */ + writel(0x00020000, SGRF_SYS_BASE + OTP_SGRF_CON); + + /* Set usb3phy clamp enable */ + writel(0x40000000, PMU_GRF_BASE + PMU_GRF_SOC_CON0); + + /* Assert the pipe phy reset and de-assert when in use */ + writel(0x00800080, PERI_CRU_BASE + PERICRU_PERI_SOFTRST_CON01); + + /* Restore pipe phy status to default from phy */ + writel(0xffff1100, PERI_GRF_BASE + PERI_GRF_USB3DRD_CON1); + + /* Set the USB 2.0 PHY Port1 to enter the sleep mode to save power consumption */ + writel(0x01ff01d1, PERI_GRF_BASE + PERI_GRF_USB2HOSTPHY_CON0); + + /* Enable tsadc phy */ + writel(0x01000000, CRU_BUS_BASE + CRU_BUS_GATE_CON06); + writel(0x80788028, SYS_GRF_BASE + TSADC_GRF_CON0); + writel(0xff000300, SYS_GRF_BASE + TSADC_GRF_CON6); + writel(0x00ff00a5, SYS_GRF_BASE + TSADC_GRF_CON1); + writel(0x01000100, SYS_GRF_BASE + TSADC_GRF_CON1); + writel(0x01000000, SYS_GRF_BASE + TSADC_GRF_CON1); + + /* set saradc ibp to 7 */ + writel(0x00700070, VEPU_GRF_BASE + SARADC0_GRF_CON0); + writel(0x00700070, VI_GRF_BASE + SARADC1_GRF_CON0); + writel(0x00700070, VI_GRF_BASE + SARADC2_GRF_CON0); + +#if defined(CONFIG_ROCKCHIP_EMMC_IOMUX) + board_set_iomux(IF_TYPE_MMC, 0, 0); +#elif defined(CONFIG_ROCKCHIP_SFC_IOMUX) + /* + * (IF_TYPE_MTD, 0, 0) FSPI0 + * (IF_TYPE_MTD, 1, 0) FSPI1 M0 + * (IF_TYPE_MTD, 2, 0) FSPI1 M1 + */ + board_set_iomux(IF_TYPE_MTD, 0, 0); +#endif /* CONFIG_ROCKCHIP_EMMC_IOMUX */ + +#if defined(CONFIG_MMC_DW_ROCKCHIP) + /* Set the sdmmc iomux and power cycle */ + board_set_iomux(IF_TYPE_MMC, 1, 0); +#endif +#endif + + return 0; +} +#endif + +#if defined(CONFIG_ROCKCHIP_EMMC_IOMUX) && defined(CONFIG_ROCKCHIP_SFC_IOMUX) +#error FSPI0 M0 and eMMC iomux is incompatible for rv1126b Soc. You should close one of them. +#endif diff --git a/u-boot/arch/arm/mach-rockchip/rv1126b/syscon_rv1126b.c b/u-boot/arch/arm/mach-rockchip/rv1126b/syscon_rv1126b.c new file mode 100644 index 00000000000..a52dc21bf2d --- /dev/null +++ b/u-boot/arch/arm/mach-rockchip/rv1126b/syscon_rv1126b.c @@ -0,0 +1,25 @@ +/* + * (C) Copyright 2025 Rockchip Electronics Co., Ltd + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include + +static const struct udevice_id rv1126b_syscon_ids[] = { + { .compatible = "rockchip,rv1126b-grf", .data = ROCKCHIP_SYSCON_GRF }, + { .compatible = "rockchip,rv1126b-ioc-grf", .data = ROCKCHIP_SYSCON_IOC }, + { } +}; + +U_BOOT_DRIVER(syscon_rv1126b) = { + .name = "rv1126b_syscon", + .id = UCLASS_SYSCON, + .of_match = rv1126b_syscon_ids, +#if !CONFIG_IS_ENABLED(OF_PLATDATA) + .bind = dm_scan_fdt_dev, +#endif +}; diff --git a/u-boot/arch/arm/mach-rockchip/sdram.c b/u-boot/arch/arm/mach-rockchip/sdram.c index 0fd69686886..61346ea3158 100644 --- a/u-boot/arch/arm/mach-rockchip/sdram.c +++ b/u-boot/arch/arm/mach-rockchip/sdram.c @@ -193,9 +193,9 @@ int dram_init(void) } #endif -ulong board_get_usable_ram_top(ulong total_size) +uint64_t board_get_usable_ram_top(ulong total_size) { - unsigned long top = CONFIG_SYS_SDRAM_BASE + SDRAM_MAX_SIZE; + uint64_t top = CONFIG_SYS_SDRAM_BASE + SDRAM_MAX_SIZE; return (gd->ram_top > top) ? top : gd->ram_top; } diff --git a/u-boot/board/rockchip/evb_rk3576/evb_rk3576.c b/u-boot/board/rockchip/evb_rk3576/evb_rk3576.c index b8a07ce2faa..3114262d860 100644 --- a/u-boot/board/rockchip/evb_rk3576/evb_rk3576.c +++ b/u-boot/board/rockchip/evb_rk3576/evb_rk3576.c @@ -16,6 +16,7 @@ DECLARE_GLOBAL_DATA_PTR; #ifdef CONFIG_USB_DWC3 #define CRU_BASE 0x27200000 #define CRU_SOFTRST_CON47 0x0abc +#define U3PHY_BASE 0x2b010000 static struct dwc3_device dwc3_device_data = { .maximum_speed = USB_SPEED_SUPER, @@ -57,14 +58,14 @@ int board_usb_init(int index, enum usb_init_type init) if (rkusb_switch_usb3_enabled()) { dwc3_device_data.maximum_speed = USB_SPEED_SUPER; - ret = rockchip_u3phy_uboot_init(); + ret = rockchip_u3phy_uboot_init(U3PHY_BASE); if (ret) { rkusb_force_to_usb2(true); dwc3_device_data.maximum_speed = USB_SPEED_HIGH; } } #else - ret = rockchip_u3phy_uboot_init(); + ret = rockchip_u3phy_uboot_init(U3PHY_BASE); if (ret) { rkusb_force_to_usb2(true); dwc3_device_data.maximum_speed = USB_SPEED_HIGH; diff --git a/u-boot/board/rockchip/evb_rk3588/evb_rk3588.c b/u-boot/board/rockchip/evb_rk3588/evb_rk3588.c index fa72f37730a..ad1c5ae8c34 100644 --- a/u-boot/board/rockchip/evb_rk3588/evb_rk3588.c +++ b/u-boot/board/rockchip/evb_rk3588/evb_rk3588.c @@ -16,6 +16,7 @@ DECLARE_GLOBAL_DATA_PTR; #ifdef CONFIG_USB_DWC3 #define CRU_BASE 0xfd7c0000 #define CRU_SOFTRST_CON42 0x0aa8 +#define U3PHY_BASE 0xfed80000 static struct dwc3_device dwc3_device_data = { .maximum_speed = USB_SPEED_SUPER, @@ -57,14 +58,14 @@ int board_usb_init(int index, enum usb_init_type init) if (rkusb_switch_usb3_enabled()) { dwc3_device_data.maximum_speed = USB_SPEED_SUPER; - ret = rockchip_u3phy_uboot_init(); + ret = rockchip_u3phy_uboot_init(U3PHY_BASE); if (ret) { rkusb_force_to_usb2(true); dwc3_device_data.maximum_speed = USB_SPEED_HIGH; } } #else - ret = rockchip_u3phy_uboot_init(); + ret = rockchip_u3phy_uboot_init(U3PHY_BASE); if (ret) { rkusb_force_to_usb2(true); dwc3_device_data.maximum_speed = USB_SPEED_HIGH; diff --git a/u-boot/board/rockchip/evb_rv1126b/Kconfig b/u-boot/board/rockchip/evb_rv1126b/Kconfig new file mode 100644 index 00000000000..1b39c98fbdd --- /dev/null +++ b/u-boot/board/rockchip/evb_rv1126b/Kconfig @@ -0,0 +1,15 @@ +if TARGET_EVB_RV1126B + +config SYS_BOARD + default "evb_rv1126b" + +config SYS_VENDOR + default "rockchip" + +config SYS_CONFIG_NAME + default "evb_rv1126b" + +config BOARD_SPECIFIC_OPTIONS # dummy + def_bool y + +endif diff --git a/u-boot/board/rockchip/evb_rv1126b/Makefile b/u-boot/board/rockchip/evb_rv1126b/Makefile new file mode 100644 index 00000000000..11cdbb0bfc3 --- /dev/null +++ b/u-boot/board/rockchip/evb_rv1126b/Makefile @@ -0,0 +1,7 @@ +# +# SPDX-License-Identifier: GPL-2.0+ +# +# Copyright (c) 2025 Rockchip Electronics Co., Ltd +# + +obj-y += evb_rv1126b.o diff --git a/u-boot/board/rockchip/evb_rv1126b/evb_rv1126b.c b/u-boot/board/rockchip/evb_rv1126b/evb_rv1126b.c new file mode 100644 index 00000000000..8aae6fe9668 --- /dev/null +++ b/u-boot/board/rockchip/evb_rv1126b/evb_rv1126b.c @@ -0,0 +1,33 @@ +/* + * SPDX-License-Identifier: GPL-2.0+ + * + * (C) Copyright 2025 Rockchip Electronics Co., Ltd + */ + +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +#ifdef CONFIG_USB_DWC3 +static struct dwc3_device dwc3_device_data = { + .maximum_speed = USB_SPEED_HIGH, + .base = 0x21500000, + .dr_mode = USB_DR_MODE_PERIPHERAL, + .index = 0, + .dis_u2_susphy_quirk = 1, + .usb2_phyif_utmi_width = 16, +}; + +int usb_gadget_handle_interrupts(void) +{ + dwc3_uboot_handle_interrupt(0); + return 0; +} + +int board_usb_init(int index, enum usb_init_type init) +{ + return dwc3_uboot_init(&dwc3_device_data); +} +#endif diff --git a/u-boot/cmd/blk_common.c b/u-boot/cmd/blk_common.c index 95247f127d1..5c51ad4305c 100644 --- a/u-boot/cmd/blk_common.c +++ b/u-boot/cmd/blk_common.c @@ -89,6 +89,19 @@ int blk_common_cmd(int argc, char * const argv[], enum if_type if_type, n = blk_write_devnum(if_type, *cur_devnump, blk, cnt, (ulong *)addr); + printf("%ld blocks written: %s\n", n, + n == cnt ? "OK" : "ERROR"); + return n == cnt ? 0 : 1; + } else if (strcmp(argv[1], "write_zeroes") == 0) { + lbaint_t blk = simple_strtoul(argv[2], NULL, 16); + ulong cnt = simple_strtoul(argv[3], NULL, 16); + ulong n; + + printf("\n%s write_zeroes: device %d block # "LBAFU", count %lu ... ", + if_name, *cur_devnump, blk, cnt); + + n = blk_write_zeroes_devnum(if_type, *cur_devnump, blk, cnt); + printf("%ld blocks written: %s\n", n, n == cnt ? "OK" : "ERROR"); return n == cnt ? 0 : 1; diff --git a/u-boot/cmd/crypto.c b/u-boot/cmd/crypto.c index bdd1d6e1916..b7d2241e2a3 100644 --- a/u-boot/cmd/crypto.c +++ b/u-boot/cmd/crypto.c @@ -68,6 +68,19 @@ struct rsa_test_data { u32 sign_out_len; }; +struct ec_test_data { + const char *algo_name; + u32 algo; + const u8 *pub_x; + u32 pub_x_len; + const u8 *pub_y; + u32 pub_y_len; + const u8 *hash_in; + u32 hash_in_len; + const u8 *sign_in; + u32 sign_in_len; +}; + #define IS_MAC_MODE(mode) ((mode) == RK_MODE_CBC_MAC || \ (mode) == RK_MODE_CMAC) @@ -152,6 +165,19 @@ struct rsa_test_data { .sign_out_len = sizeof(out) \ } +#define EC_TEST(name, x, y, hash, sign) { \ + .algo_name = #name, \ + .algo = CRYPTO_##name, \ + .pub_x = (x), \ + .pub_x_len = sizeof(x), \ + .pub_y = (y), \ + .pub_y_len = sizeof(y), \ + .hash_in = (hash), \ + .hash_in_len = sizeof(hash), \ + .sign_in = (sign), \ + .sign_in_len = sizeof(sign), \ +} + #define EMPTY_TEST() {} const struct hash_test_data hash_data_set[] = { @@ -236,6 +262,15 @@ const struct rsa_test_data rsa_data_set[] = { #endif }; +const struct ec_test_data ec_data_set[] = { +#if CONFIG_IS_ENABLED(ROCKCHIP_EC) + EC_TEST(ECC_192R1, ecc192r1_pub_x, ecc192r1_pub_y, ecc192r1_hash, ecc192r1_sign), + EC_TEST(SM2, sm2_pub_x, sm2_pub_y, sm2_hash, sm2_sign), +#else + EMPTY_TEST(), +#endif +}; + static void dump_hex(const char *name, const u8 *array, u32 len) { int i; @@ -654,6 +689,58 @@ error: return ret; } +int test_ec_result(void) +{ + const struct ec_test_data *test_data = NULL; + ulong start, time_cost; + struct udevice *dev; + ec_key ec_key; + int ret, i; + + printf("\n====================== ec test ========================\n"); + for (i = 0; i < ARRAY_SIZE(ec_data_set); i++) { + test_data = &ec_data_set[i]; + if (test_data->algo == 0) { + printf("\n"); + continue; + } + + dev = crypto_get_device(test_data->algo); + if (!dev) { + printf("[%s] %-16s unsupported!!!\n", + test_data->algo_name, ""); + continue; + } + + /* verify test */ + memset(&ec_key, 0x00, sizeof(ec_key)); + ec_key.algo = test_data->algo; + ec_key.x = (u32 *)test_data->pub_x; + ec_key.y = (u32 *)test_data->pub_y; + + start = get_timer(0); + ret = crypto_ec_verify(dev, &ec_key, + (u8 *)test_data->hash_in, + test_data->hash_in_len, + (u8 *)test_data->sign_in); + if (ret) { + printf("verify test error, ret = %d\n", ret); + goto error; + } + time_cost = get_timer(start); + + printf("[%-9s] %-8s PASS (%lums)\n", + test_data->algo_name, "verify", time_cost); + + printf("+++++++++++++++++++++++++++++++++++++++++++++++++++\n"); + } + + return 0; +error: + printf("%s test error!\n", test_data->algo_name); + return ret; +} + static int test_all_result(void) { int ret = 0; @@ -670,6 +757,10 @@ static int test_all_result(void) if (ret) goto exit; + ret = test_ec_result(); + if (ret) + goto exit; + exit: return 0; } diff --git a/u-boot/cmd/mmc.c b/u-boot/cmd/mmc.c index 189687eac19..839945f424e 100644 --- a/u-boot/cmd/mmc.c +++ b/u-boot/cmd/mmc.c @@ -647,6 +647,7 @@ static int do_mmc_list(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) { print_mmc_devices('\n'); + do_mmc_rescan(cmdtp, flag, argc, argv); return CMD_RET_SUCCESS; } diff --git a/u-boot/cmd/nvme.c b/u-boot/cmd/nvme.c index 01e9982209c..f7507b46519 100644 --- a/u-boot/cmd/nvme.c +++ b/u-boot/cmd/nvme.c @@ -54,4 +54,5 @@ U_BOOT_CMD( " `blk#' to memory address `addr'\n" "nvme write addr blk# cnt - write `cnt' blocks starting at block\n" " `blk#' from memory address `addr'" + "nvme write_zeroes blk# cnt - write `cnt' blocks of zeroes starting at block\n" ); diff --git a/u-boot/cmd/pci.c b/u-boot/cmd/pci.c index 6eecd69c0ff..0c3e5580239 100644 --- a/u-boot/cmd/pci.c +++ b/u-boot/cmd/pci.c @@ -507,6 +507,9 @@ static int do_pci(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) value = simple_strtoul(argv[4], NULL, 16); case 'h': /* header */ case 'b': /* bars */ + case 'a': /* AER */ + case 'x': /* retrain link */ + case 'f': /* FLR */ if (argc < 3) goto usage; if ((bdf = get_pci_dev(argv[2])) == -1) @@ -595,6 +598,12 @@ static int do_pci(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) break; case 'b': /* bars */ return pci_bar_show(dev); + case 'a': /* AER */ + return pci_aer_dump(dev, bdf); + case 'x': /* retrain link */ + return pci_retrain_link(dev, bdf); + case 'f': /* do FLR */ + return pci_reset_function(dev, bdf); default: ret = CMD_RET_USAGE; break; @@ -611,6 +620,12 @@ static int do_pci(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) static char pci_help_text[] = "[bus|*] [long]\n" " - short or long list of PCI devices on bus 'bus'\n" + "pci aer b.d.f \n" + " - Dump PCI AER info\n" + "pci x b.d.f \n" + " - Retrain the link\n" + "pci f b.d.f \n" + " - Function level reset\n" "pci enum\n" " - Enumerate PCI buses\n" "pci header b.d.f\n" diff --git a/u-boot/common/android_ab.c b/u-boot/common/android_ab.c index 45d38a20082..8baa0aa2659 100644 --- a/u-boot/common/android_ab.c +++ b/u-boot/common/android_ab.c @@ -477,6 +477,7 @@ void ab_update_root_partition(void) /* Judge the partition device type. */ switch (dev_desc->if_type) { case IF_TYPE_MMC: + case IF_TYPE_SCSI: /* scsi 0: UFS */ if (strstr(part_type, "ENV")) snprintf(root_part_dev, 64, "root=/dev/mmcblk0p%d", part_num); else if (strstr(part_type, "EFI")) @@ -500,7 +501,8 @@ void ab_update_root_partition(void) } break; default: - printf("%s: Not found part type, failed to set root part device.\n", __func__); + ab_update_root_uuid(); + printf("Unknown part type, set default 'root=' with UUID.\n"); return; } diff --git a/u-boot/common/android_bootloader.c b/u-boot/common/android_bootloader.c index 16cdce81648..bffbbfbfff7 100644 --- a/u-boot/common/android_bootloader.c +++ b/u-boot/common/android_bootloader.c @@ -965,7 +965,7 @@ out: } #endif -#if defined(CONFIG_CMD_DTIMG) && defined(CONFIG_OF_LIBFDT_OVERLAY) +#if defined(CONFIG_OF_LIBFDT_OVERLAY) /* * Default return index 0. diff --git a/u-boot/common/board_f.c b/u-boot/common/board_f.c index dd76efc7b0d..b64df3980a4 100644 --- a/u-boot/common/board_f.c +++ b/u-boot/common/board_f.c @@ -272,7 +272,7 @@ __weak int mach_cpu_init(void) } /* Get the top of usable RAM */ -__weak ulong board_get_usable_ram_top(ulong total_size) +__weak uint64_t board_get_usable_ram_top(ulong total_size) { #ifdef CONFIG_SYS_SDRAM_BASE /* diff --git a/u-boot/common/fdt_support.c b/u-boot/common/fdt_support.c index 5d7ee590f9d..b741f06ac92 100644 --- a/u-boot/common/fdt_support.c +++ b/u-boot/common/fdt_support.c @@ -251,6 +251,8 @@ int fdt_initrd(void *fdt, ulong initrd_start, ulong initrd_end) } } + fdt_increase_size(fdt, 512); + err = fdt_add_mem_rsv(fdt, initrd_start, initrd_end - initrd_start); if (err < 0) { printf("fdt_initrd: %s\n", fdt_strerror(err)); diff --git a/u-boot/common/id_attestation.c b/u-boot/common/id_attestation.c index 59890e805dd..2fbced62937 100644 --- a/u-boot/common/id_attestation.c +++ b/u-boot/common/id_attestation.c @@ -80,12 +80,10 @@ atap_result write_id_attestation_to_secure_storage(u8* received_data, uint32_t l sizeof(AttestationIds)); MSG("read id attestation ret=%0x\n", ret); if (ret == TEEC_SUCCESS) { - printf("id attestation already exsit,you cannot update it!"); + printf("id attestation already exsit,let's update it!"); #if DEBUG printAttestationIds(&ids_read); #endif - ret = ATAP_RESULT_ERROR_ALREADY_EXSIT; - return ret; } ret = write_id_attestation(ids_file, &ids, ids_len); printf("write id attestation : ret=%d\n", ret); diff --git a/u-boot/common/spl/Kconfig b/u-boot/common/spl/Kconfig index 2b557f08fa8..318116d7bc4 100644 --- a/u-boot/common/spl/Kconfig +++ b/u-boot/common/spl/Kconfig @@ -310,6 +310,14 @@ config SPL_CRYPTO_SUPPORT this option to build the drivers in drivers/crypto as part of an SPL build. +config SPL_KEYLAD_SUPPORT + bool "Support keylad drivers" + help + Enable keylad drivers in SPL. These drivers can be used to pass + otp keys to other IP addresses. (e.g. CRYPTO module). Enable + this option to build the drivers in drivers/keylad as part of an + SPL build. + config SPL_HASH_SUPPORT bool "Support hashing drivers" select SHA1 @@ -884,12 +892,6 @@ config SPL_ATF_NO_PLATFORM_PARAM If your ATF is affected, say Y. -config SPL_ATF_AARCH32_BL33 - bool "Support BL33 runs as AArch32 mode" - depends on SPL_ATF - help - This option setup the AArch32 Mode for BL33. - config SPL_OPTEE bool "Support OP-TEE Trusted OS" depends on ARM diff --git a/u-boot/common/spl/spl_atf.c b/u-boot/common/spl/spl_atf.c index a28387c664d..83d6af37c1f 100644 --- a/u-boot/common/spl/spl_atf.c +++ b/u-boot/common/spl/spl_atf.c @@ -76,13 +76,12 @@ static struct bl31_params *bl2_plat_get_bl31_params(struct spl_image_info *spl_i bl33_ep_info->args.arg0 = 0xffff & read_mpidr(); bl33_ep_info->pc = bl33_entry; -#ifdef CONFIG_SPL_ATF_AARCH32_BL33 - bl33_ep_info->spsr = SPSR_32(MODE32_svc, SPSR_T_ARM, EP_EE_LITTLE, - DISABLE_ALL_EXECPTIONS_32); -#else - bl33_ep_info->spsr = SPSR_64(MODE_EL2, MODE_SP_ELX, - DISABLE_ALL_EXECPTIONS); -#endif + if (spl_image->flags & SPL_ATF_AARCH32_BL33) + bl33_ep_info->spsr = SPSR_32(MODE32_svc, SPSR_T_ARM, EP_EE_LITTLE, + DISABLE_ALL_EXECPTIONS_32); + else + bl33_ep_info->spsr = SPSR_64(MODE_EL2, MODE_SP_ELX, + DISABLE_ALL_EXECPTIONS); /* * Reference: arch/arm/lib/bootm.c * boot_jump_linux(bootm_headers_t *images, int flag) diff --git a/u-boot/common/spl/spl_fit.c b/u-boot/common/spl/spl_fit.c index d31c259636e..bc39298afcf 100644 --- a/u-boot/common/spl/spl_fit.c +++ b/u-boot/common/spl/spl_fit.c @@ -426,7 +426,7 @@ static void *spl_fit_load_blob(struct spl_load_info *info, align_len) & ~align_len); sectors = get_aligned_image_size(info, size, 0); count = info->read(info, sector, sectors, fit); -#ifdef CONFIG_SPL_MTD_SUPPORT +#if defined(CONFIG_SPL_MTD_SUPPORT) && !defined(CONFIG_FPGA_RAM) mtd_blk_map_fit(info->dev, sector, fit); #endif debug("fit read sector %lx, sectors=%d, dst=%p, count=%lu\n", @@ -614,6 +614,9 @@ static int spl_internal_load_simple_fit(struct spl_image_info *spl_image, { struct spl_image_info image_info; char *desc; +#if CONFIG_IS_ENABLED(ATF) + uint8_t ih_arch; +#endif int base_offset; int images, ret; int index = 0; @@ -787,6 +790,10 @@ static int spl_internal_load_simple_fit(struct spl_image_info *spl_image, if (os_type == IH_OS_U_BOOT) { #if CONFIG_IS_ENABLED(ATF) + fit_image_get_arch(fit, node, &ih_arch); + debug("Image ARCH is %s\n", genimg_get_arch_name(ih_arch)); + if (ih_arch == IH_ARCH_ARM) + spl_image->flags |= SPL_ATF_AARCH32_BL33; spl_image->entry_point_bl33 = image_info.load_addr; #elif CONFIG_IS_ENABLED(OPTEE) spl_image->entry_point_os = image_info.load_addr; diff --git a/u-boot/configs/evb-px30_defconfig b/u-boot/configs/evb-px30_defconfig index 0d454c81d3b..36d271ab74c 100644 --- a/u-boot/configs/evb-px30_defconfig +++ b/u-boot/configs/evb-px30_defconfig @@ -7,8 +7,8 @@ CONFIG_ROCKCHIP_PX30=y CONFIG_SPL_FIT_GENERATOR="arch/arm/mach-rockchip/make_fit_atf.py" CONFIG_ROCKCHIP_SPL_RESERVE_IRAM=0x0 CONFIG_ROCKCHIP_VENDOR_PARTITION=y -CONFIG_DM_DMC=y -CONFIG_ROCKCHIP_DMC_FSP=y +CONFIG_UBOOT_SIZE_KB=2048 +CONFIG_UBOOT_NUM=2 CONFIG_TRUST_RSA_MODE=3 CONFIG_TARGET_EVB_PX30=y CONFIG_SPL_DRIVERS_MISC_SUPPORT=y @@ -88,6 +88,8 @@ CONFIG_PWM_ROCKCHIP=y CONFIG_RAM=y CONFIG_SPL_RAM=y CONFIG_TPL_RAM=y +CONFIG_DM_DMC=y +CONFIG_ROCKCHIP_DMC_FSP=y CONFIG_ROCKCHIP_SDRAM_COMMON=y CONFIG_DM_RESET=y CONFIG_RKNAND=y @@ -96,8 +98,6 @@ CONFIG_DEBUG_UART_BASE=0xFF160000 CONFIG_DEBUG_UART_CLOCK=24000000 CONFIG_DEBUG_UART_SHIFT=2 CONFIG_DEBUG_UART_SKIP_INIT=y -CONFIG_UBOOT_SIZE_KB=2048 -CONFIG_UBOOT_NUM=2 CONFIG_SOUND=y CONFIG_I2S_ROCKCHIP=y CONFIG_SOUND_RK817=y diff --git a/u-boot/configs/evb-rk3358_defconfig b/u-boot/configs/evb-rk3358_defconfig new file mode 100644 index 00000000000..ab80ee05efc --- /dev/null +++ b/u-boot/configs/evb-rk3358_defconfig @@ -0,0 +1,139 @@ +CONFIG_ARM=y +CONFIG_ARCH_ROCKCHIP=y +CONFIG_SPL_LIBCOMMON_SUPPORT=y +CONFIG_SPL_LIBGENERIC_SUPPORT=y +CONFIG_SYS_MALLOC_F_LEN=0x2000 +CONFIG_ROCKCHIP_PX30=y +CONFIG_ROCKCHIP_RK3358=y +CONFIG_SPL_FIT_GENERATOR="arch/arm/mach-rockchip/make_fit_atf.py" +CONFIG_ROCKCHIP_SPL_RESERVE_IRAM=0x0 +CONFIG_ROCKCHIP_VENDOR_PARTITION=y +CONFIG_UBOOT_SIZE_KB=2048 +CONFIG_UBOOT_NUM=2 +CONFIG_TRUST_RSA_MODE=3 +CONFIG_TARGET_EVB_PX30=y +CONFIG_SPL_DRIVERS_MISC_SUPPORT=y +CONFIG_SPL_STACK_R_ADDR=0x600000 +CONFIG_DEFAULT_DEVICE_TREE="px30-evb" +CONFIG_DEBUG_UART=y +CONFIG_TPL_SYS_MALLOC_F_LEN=0x600 +CONFIG_FIT=y +CONFIG_FIT_VERBOSE=y +CONFIG_SPL_LOAD_FIT=y +CONFIG_BOOTDELAY=0 +CONFIG_SYS_CONSOLE_INFO_QUIET=y +# CONFIG_DISPLAY_CPUINFO is not set +CONFIG_ANDROID_BOOTLOADER=y +CONFIG_SPL_STACK_R=y +CONFIG_SPL_ATF=y +CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y +CONFIG_FASTBOOT_BUF_ADDR=0x800800 +CONFIG_FASTBOOT_BUF_SIZE=0x04000000 +CONFIG_FASTBOOT_FLASH=y +CONFIG_FASTBOOT_FLASH_MMC_DEV=0 +# CONFIG_CMD_ELF is not set +# CONFIG_CMD_IMI is not set +# CONFIG_CMD_IMLS is not set +# CONFIG_CMD_XIMG is not set +# CONFIG_CMD_LZMADEC is not set +# CONFIG_CMD_UNZIP is not set +# CONFIG_CMD_FLASH is not set +# CONFIG_CMD_FPGA is not set +CONFIG_CMD_GPT=y +# CONFIG_CMD_LOADB is not set +# CONFIG_CMD_LOADS is not set +CONFIG_CMD_BOOT_ANDROID=y +CONFIG_CMD_BOOT_ROCKCHIP=y +CONFIG_CMD_MMC=y +CONFIG_CMD_USB=y +CONFIG_CMD_USB_MASS_STORAGE=y +# CONFIG_CMD_ITEST is not set +# CONFIG_CMD_SETEXPR is not set +# CONFIG_CMD_MISC is not set +# CONFIG_SPL_DOS_PARTITION is not set +# CONFIG_ISO_PARTITION is not set +CONFIG_EFI_PARTITION_ENTRIES_NUMBERS=64 +CONFIG_RKPARM_PARTITION=y +CONFIG_SPL_OF_CONTROL=y +CONFIG_OF_LIVE=y +CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" +CONFIG_REGMAP=y +CONFIG_SPL_REGMAP=y +CONFIG_SYSCON=y +CONFIG_SPL_SYSCON=y +CONFIG_CLK=y +CONFIG_SPL_CLK=y +CONFIG_ROCKCHIP_GPIO=y +CONFIG_SYS_I2C_ROCKCHIP=y +CONFIG_DM_KEY=y +CONFIG_RK8XX_PWRKEY=y +CONFIG_ADC_KEY=y +CONFIG_MMC_DW=y +CONFIG_MMC_DW_ROCKCHIP=y +CONFIG_DM_ETH=y +CONFIG_ETH_DESIGNWARE=y +CONFIG_GMAC_ROCKCHIP=y +CONFIG_PHY_ROCKCHIP_INNO_USB2=y +CONFIG_PINCTRL=y +CONFIG_DM_FUEL_GAUGE=y +CONFIG_DM_PMIC=y +CONFIG_PMIC_RK8XX=y +CONFIG_REGULATOR_PWM=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_REGULATOR_RK8XX=y +CONFIG_DM_DVFS=y +CONFIG_ROCKCHIP_WTEMP_DVFS=y +CONFIG_DM_CHARGE_DISPLAY=y +CONFIG_CHARGE_ANIMATION=y +CONFIG_PWM_ROCKCHIP=y +CONFIG_RAM=y +CONFIG_SPL_RAM=y +CONFIG_TPL_RAM=y +CONFIG_DM_DMC=y +CONFIG_ROCKCHIP_DMC_FSP=y +CONFIG_ROCKCHIP_SDRAM_COMMON=y +CONFIG_DM_RESET=y +CONFIG_RKNAND=y +CONFIG_BAUDRATE=1500000 +CONFIG_DEBUG_UART_BASE=0xFF160000 +CONFIG_DEBUG_UART_CLOCK=24000000 +CONFIG_DEBUG_UART_SHIFT=2 +CONFIG_DEBUG_UART_SKIP_INIT=y +CONFIG_SOUND=y +CONFIG_I2S_ROCKCHIP=y +CONFIG_SOUND_RK817=y +CONFIG_SOUND_ROCKCHIP=y +CONFIG_SYSRESET=y +CONFIG_DM_THERMAL=y +CONFIG_ROCKCHIP_THERMAL=y +CONFIG_USB=y +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_EHCI_GENERIC=y +CONFIG_USB_OHCI_HCD=y +CONFIG_USB_OHCI_GENERIC=y +CONFIG_USB_STORAGE=y +CONFIG_USB_GADGET=y +CONFIG_USB_GADGET_MANUFACTURER="Rockchip" +CONFIG_USB_GADGET_VENDOR_NUM=0x2207 +CONFIG_USB_GADGET_PRODUCT_NUM=0x330d +CONFIG_USB_GADGET_DWC2_OTG=y +CONFIG_USB_GADGET_DOWNLOAD=y +CONFIG_DM_VIDEO=y +CONFIG_DISPLAY=y +CONFIG_DRM_ROCKCHIP=y +CONFIG_DRM_ROCKCHIP_INNO_VIDEO_COMBO_PHY=y +CONFIG_DRM_ROCKCHIP_DW_MIPI_DSI=y +CONFIG_DRM_ROCKCHIP_LVDS=y +CONFIG_DRM_ROCKCHIP_RGB=y +CONFIG_DRM_ROCKCHIP_RK618=y +CONFIG_VIDEO_BRIDGE_ANALOGIX_ANX6345=y +CONFIG_LCD=y +CONFIG_USE_TINY_PRINTF=y +CONFIG_SPL_TINY_MEMSET=y +CONFIG_LZ4=y +CONFIG_LZO=y +CONFIG_ERRNO_STR=y +# CONFIG_EFI_LOADER is not set +CONFIG_OPTEE_CLIENT=y +CONFIG_OPTEE_V2=y +CONFIG_TEST_ROCKCHIP=y diff --git a/u-boot/configs/nanopi_r3_ab_defconfig b/u-boot/configs/nanopi_r3_ab_defconfig new file mode 100644 index 00000000000..1e81347198d --- /dev/null +++ b/u-boot/configs/nanopi_r3_ab_defconfig @@ -0,0 +1,227 @@ +CONFIG_ARM=y +CONFIG_ARCH_ROCKCHIP=y +CONFIG_SPL_LIBCOMMON_SUPPORT=y +CONFIG_SPL_LIBGENERIC_SUPPORT=y +CONFIG_SYS_MALLOC_F_LEN=0x80000 +CONFIG_SPL_FIT_GENERATOR="arch/arm/mach-rockchip/make_fit_atf.sh" +CONFIG_ROCKCHIP_RK3568=y +CONFIG_ROCKCHIP_FIT_IMAGE=y +CONFIG_ROCKCHIP_VENDOR_PARTITION=y +CONFIG_ROCKCHIP_FIT_IMAGE_PACK=y +CONFIG_ROCKCHIP_NEW_IDB=y +CONFIG_LOADER_INI="RK3566MINIALL.ini" +CONFIG_SPL_SERIAL_SUPPORT=y +CONFIG_SPL_DRIVERS_MISC_SUPPORT=y +CONFIG_TARGET_NANOPI_R3=y +CONFIG_SPL_LIBDISK_SUPPORT=y +CONFIG_SPL_NAND_SUPPORT=y +CONFIG_SPL_SPI_FLASH_SUPPORT=y +CONFIG_SPL_SPI_SUPPORT=y +CONFIG_DEFAULT_DEVICE_TREE="rk356x-nanopi-r3" +CONFIG_DEBUG_UART=y +CONFIG_IMAGE_GZIP=y +CONFIG_FIT=y +CONFIG_FIT_IMAGE_POST_PROCESS=y +CONFIG_FIT_HW_CRYPTO=y +CONFIG_SPL_LOAD_FIT=y +CONFIG_SPL_FIT_IMAGE_POST_PROCESS=y +CONFIG_SPL_FIT_HW_CRYPTO=y +# CONFIG_SPL_SYS_DCACHE_OFF is not set +CONFIG_BOOTDELAY=1 +CONFIG_SYS_CONSOLE_INFO_QUIET=y +# CONFIG_DISPLAY_CPUINFO is not set +CONFIG_ANDROID_BOOTLOADER=y +CONFIG_ANDROID_AB=y +CONFIG_ANDROID_AVB=y +CONFIG_ANDROID_BOOT_IMAGE_HASH=y +CONFIG_BOARD_RNG_SEED=y +CONFIG_SPL_BOARD_INIT=y +# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set +# CONFIG_SPL_LEGACY_IMAGE_SUPPORT is not set +CONFIG_SPL_SEPARATE_BSS=y +CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION=y +CONFIG_SPL_SHA256_SUPPORT=y +CONFIG_SPL_CRYPTO_SUPPORT=y +CONFIG_SPL_HASH_SUPPORT=y +CONFIG_SPL_MTD_SUPPORT=y +CONFIG_SPL_SPI_FLASH_SFDP_SUPPORT=y +CONFIG_SPL_ATF=y +CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y +CONFIG_SPL_AB=y +CONFIG_FASTBOOT_BUF_ADDR=0xc00800 +CONFIG_FASTBOOT_BUF_SIZE=0x04000000 +CONFIG_FASTBOOT_FLASH=y +CONFIG_FASTBOOT_FLASH_MMC_DEV=0 +CONFIG_CMD_BOOTZ=y +CONFIG_CMD_DTIMG=y +# CONFIG_CMD_ELF is not set +# CONFIG_CMD_IMI is not set +# CONFIG_CMD_IMLS is not set +# CONFIG_CMD_XIMG is not set +# CONFIG_CMD_LZMADEC is not set +# CONFIG_CMD_UNZIP is not set +# CONFIG_CMD_FLASH is not set +# CONFIG_CMD_FPGA is not set +CONFIG_CMD_GPT=y +# CONFIG_CMD_LOADB is not set +# CONFIG_CMD_LOADS is not set +CONFIG_CMD_BOOT_ANDROID=y +CONFIG_CMD_BOOT_ROCKCHIP=y +CONFIG_CMD_MMC=y +CONFIG_CMD_MTD=y +CONFIG_CMD_NAND=y +CONFIG_CMD_USB=y +CONFIG_CMD_USB_MASS_STORAGE=y +# CONFIG_CMD_ITEST is not set +# CONFIG_CMD_SETEXPR is not set +CONFIG_CMD_TFTPPUT=y +CONFIG_CMD_TFTP_BOOTM=y +CONFIG_CMD_TFTP_FLASH=y +# CONFIG_CMD_MISC is not set +# CONFIG_CMD_CHARGE_DISPLAY is not set +CONFIG_CMD_MTD_BLK=y +# CONFIG_SPL_DOS_PARTITION is not set +# CONFIG_ISO_PARTITION is not set +CONFIG_EFI_PARTITION_ENTRIES_NUMBERS=64 +CONFIG_SPL_OF_CONTROL=y +CONFIG_SPL_DTB_MINIMUM=y +CONFIG_OF_LIVE=y +CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" +# CONFIG_NET_TFTP_VARS is not set +CONFIG_REGMAP=y +CONFIG_SPL_REGMAP=y +CONFIG_SYSCON=y +CONFIG_SPL_SYSCON=y +CONFIG_CLK=y +CONFIG_SPL_CLK=y +CONFIG_CLK_SCMI=y +CONFIG_DM_CRYPTO=y +CONFIG_SPL_DM_CRYPTO=y +CONFIG_ROCKCHIP_CRYPTO_V2=y +CONFIG_SPL_ROCKCHIP_CRYPTO_V2=y +CONFIG_DM_RNG=y +CONFIG_RNG_ROCKCHIP=y +CONFIG_SCMI_FIRMWARE=y +CONFIG_ROCKCHIP_GPIO=y +CONFIG_ROCKCHIP_GPIO_V2=y +CONFIG_SYS_I2C_ROCKCHIP=y +CONFIG_DM_KEY=y +CONFIG_RK8XX_PWRKEY=y +CONFIG_ADC_KEY=y +CONFIG_MISC=y +CONFIG_SPL_MISC=y +CONFIG_ROCKCHIP_OTP=y +CONFIG_SPL_ROCKCHIP_SECURE_OTP=y +CONFIG_MMC_DW=y +CONFIG_MMC_DW_ROCKCHIP=y +CONFIG_MMC_SDHCI=y +CONFIG_MMC_SDHCI_SDMA=y +CONFIG_MMC_SDHCI_ROCKCHIP=y +CONFIG_MTD=y +CONFIG_MTD_BLK=y +CONFIG_MTD_DEVICE=y +CONFIG_NAND=y +CONFIG_NAND_ROCKCHIP_V9=y +CONFIG_SYS_NAND_U_BOOT_LOCATIONS=y +CONFIG_SYS_NAND_U_BOOT_OFFS=0x8000 +CONFIG_SYS_NAND_U_BOOT_OFFS_REDUND=0x10000 +CONFIG_MTD_SPI_NAND=y +CONFIG_SPI_FLASH=y +CONFIG_SF_DEFAULT_SPEED=20000000 +CONFIG_SPI_FLASH_EON=y +CONFIG_SPI_FLASH_GIGADEVICE=y +CONFIG_SPI_FLASH_MACRONIX=y +CONFIG_SPI_FLASH_WINBOND=y +CONFIG_SPI_FLASH_XMC=y +CONFIG_SPI_FLASH_MTD=y +CONFIG_DM_ETH=y +CONFIG_DM_ETH_PHY=y +CONFIG_DWC_ETH_QOS=y +CONFIG_GMAC_ROCKCHIP=y +CONFIG_PHY_ROCKCHIP_INNO_USB2=y +CONFIG_PHY_ROCKCHIP_NANENG_COMBOPHY=y +CONFIG_PHY_ROCKCHIP_NANENG_EDP=y +CONFIG_PINCTRL=y +CONFIG_SPL_PINCTRL=y +CONFIG_DM_FUEL_GAUGE=y +CONFIG_POWER_FG_RK817=y +CONFIG_IO_DOMAIN=y +CONFIG_ROCKCHIP_IO_DOMAIN=y +CONFIG_DM_PMIC=y +CONFIG_PMIC_RK8XX=y +CONFIG_REGULATOR_FAN53555=y +CONFIG_REGULATOR_PWM=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_REGULATOR_RK8XX=y +CONFIG_DM_CHARGE_DISPLAY=y +CONFIG_CHARGE_ANIMATION=y +CONFIG_PWM_ROCKCHIP=y +CONFIG_RAM=y +CONFIG_SPL_RAM=y +CONFIG_TPL_RAM=y +CONFIG_DM_RAMDISK=y +CONFIG_RAMDISK_RO=y +CONFIG_DM_DMC=y +CONFIG_ROCKCHIP_DMC_FSP=y +CONFIG_ROCKCHIP_SDRAM_COMMON=y +CONFIG_ROCKCHIP_TPL_INIT_DRAM_TYPE=0 +CONFIG_DM_RESET=y +CONFIG_SPL_DM_RESET=y +CONFIG_SPL_RESET_ROCKCHIP=y +CONFIG_BAUDRATE=1500000 +CONFIG_DEBUG_UART_BASE=0xFE660000 +CONFIG_DEBUG_UART_CLOCK=24000000 +CONFIG_DEBUG_UART_SHIFT=2 +CONFIG_ROCKCHIP_SFC=y +CONFIG_SYSRESET=y +CONFIG_USB=y +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_XHCI_DWC3=y +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_EHCI_GENERIC=y +CONFIG_USB_OHCI_HCD=y +CONFIG_USB_OHCI_GENERIC=y +CONFIG_USB_DWC3=y +CONFIG_USB_DWC3_GADGET=y +CONFIG_USB_DWC3_GENERIC=y +CONFIG_USB_STORAGE=y +CONFIG_USB_GADGET=y +CONFIG_USB_GADGET_MANUFACTURER="Rockchip" +CONFIG_USB_GADGET_VENDOR_NUM=0x2207 +CONFIG_USB_GADGET_PRODUCT_NUM=0x350a +CONFIG_USB_GADGET_DOWNLOAD=y +CONFIG_DM_VIDEO=y +CONFIG_DISPLAY=y +CONFIG_DRM_ROCKCHIP=y +CONFIG_DRM_ROCKCHIP_DW_HDMI=y +CONFIG_DRM_ROCKCHIP_INNO_MIPI_PHY=y +CONFIG_DRM_ROCKCHIP_INNO_VIDEO_COMBO_PHY=y +CONFIG_DRM_ROCKCHIP_DW_MIPI_DSI=y +CONFIG_DRM_ROCKCHIP_ANALOGIX_DP=y +CONFIG_DRM_ROCKCHIP_LVDS=y +CONFIG_DRM_ROCKCHIP_RGB=y +CONFIG_ROCKCHIP_CUBIC_LUT_SIZE=9 +CONFIG_LCD=y +CONFIG_USE_TINY_PRINTF=y +CONFIG_SPL_TINY_MEMSET=y +CONFIG_RSA=y +CONFIG_SPL_RSA=y +CONFIG_RSA_N_SIZE=0x200 +CONFIG_RSA_E_SIZE=0x10 +CONFIG_RSA_C_SIZE=0x20 +CONFIG_XBC=y +CONFIG_SHA512=y +CONFIG_LZ4=y +CONFIG_LZMA=y +CONFIG_SPL_GZIP=y +CONFIG_ERRNO_STR=y +# CONFIG_EFI_LOADER is not set +CONFIG_AVB_LIBAVB=y +CONFIG_AVB_LIBAVB_AB=y +CONFIG_AVB_LIBAVB_ATX=y +CONFIG_AVB_LIBAVB_USER=y +CONFIG_RK_AVB_LIBAVB_USER=y +CONFIG_OPTEE_CLIENT=y +CONFIG_OPTEE_V2=y +CONFIG_OPTEE_ALWAYS_USE_SECURITY_PARTITION=y diff --git a/u-boot/configs/rk-sfc.config b/u-boot/configs/rk-sfc.config index ce30768a8e7..9c5941b88d2 100644 --- a/u-boot/configs/rk-sfc.config +++ b/u-boot/configs/rk-sfc.config @@ -1 +1,2 @@ CONFIG_ROCKCHIP_SFC_IOMUX=y +# CONFIG_ROCKCHIP_EMMC_IOMUX is not set diff --git a/u-boot/configs/rk-spl-boot-aarch32.config b/u-boot/configs/rk-spl-boot-aarch32.config deleted file mode 100644 index 9ce61e0d0c2..00000000000 --- a/u-boot/configs/rk-spl-boot-aarch32.config +++ /dev/null @@ -1 +0,0 @@ -CONFIG_SPL_ATF_AARCH32_BL33=y diff --git a/u-boot/configs/rk3328_defconfig b/u-boot/configs/rk3328_defconfig index 4f4312e73a6..5e7f68093c3 100644 --- a/u-boot/configs/rk3328_defconfig +++ b/u-boot/configs/rk3328_defconfig @@ -35,7 +35,6 @@ CONFIG_FASTBOOT_BUF_SIZE=0x4000000 CONFIG_FASTBOOT_FLASH=y CONFIG_FASTBOOT_FLASH_MMC_DEV=0 # CONFIG_CMD_BDI is not set -CONFIG_CMD_DTIMG=y # CONFIG_CMD_ELF is not set # CONFIG_CMD_IMI is not set # CONFIG_CMD_IMLS is not set diff --git a/u-boot/configs/rk3506-rt.config b/u-boot/configs/rk3506-rt.config new file mode 100644 index 00000000000..e1e48a112a8 --- /dev/null +++ b/u-boot/configs/rk3506-rt.config @@ -0,0 +1,2 @@ +CONFIG_BASE_DEFCONFIG="rk3506_defconfig" +CONFIG_LOADER_INI="RK3506MINIALL_RT.ini" diff --git a/u-boot/configs/rk3506_defconfig b/u-boot/configs/rk3506_defconfig index d8d861b7d19..8ac7849c6d5 100644 --- a/u-boot/configs/rk3506_defconfig +++ b/u-boot/configs/rk3506_defconfig @@ -8,6 +8,7 @@ CONFIG_SPL_FIT_GENERATOR="arch/arm/mach-rockchip/make_fit_optee.sh" CONFIG_ROCKCHIP_RK3506=y CONFIG_ROCKCHIP_SPL_RESERVE_IRAM=0x0 CONFIG_ROCKCHIP_FIT_IMAGE=y +CONFIG_ROCKCHIP_VENDOR_PARTITION=y CONFIG_USING_KERNEL_DTB_V2=y CONFIG_ROCKCHIP_FIT_IMAGE_PACK=y CONFIG_ROCKCHIP_NEW_IDB=y @@ -40,7 +41,6 @@ CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION=y CONFIG_SPL_SHA256_SUPPORT=y CONFIG_SPL_HASH_SUPPORT=y CONFIG_SPL_MTD_SUPPORT=y -CONFIG_SPI_FLASH_SFDP_SUPPORT=y CONFIG_SPL_OPTEE=y CONFIG_SPL_AB=y # CONFIG_FASTBOOT is not set @@ -65,10 +65,9 @@ CONFIG_CMD_SCRIPT_UPDATE=y # CONFIG_CMD_SETEXPR is not set CONFIG_CMD_TFTP_BOOTM=y CONFIG_CMD_TFTP_FLASH=y -CONFIG_CMD_DHCP=y # CONFIG_CMD_NFS is not set -CONFIG_CMD_PING=y # CONFIG_CMD_MISC is not set +CONFIG_CMD_PMIC=y CONFIG_CMD_MTD_BLK=y # CONFIG_SPL_DOS_PARTITION is not set CONFIG_EFI_PARTITION_ENTRIES_NUMBERS=64 @@ -81,7 +80,6 @@ CONFIG_REGMAP=y CONFIG_SPL_REGMAP=y CONFIG_SYSCON=y CONFIG_SPL_SYSCON=y -CONFIG_ROCKCHIP_VENDOR_PARTITION=y # CONFIG_SARADC_ROCKCHIP is not set CONFIG_SARADC_ROCKCHIP_V2=y CONFIG_CLK=y @@ -110,22 +108,27 @@ CONFIG_MTD_SPI_NAND=y CONFIG_SPI_FLASH=y CONFIG_SF_DEFAULT_MODE=0x1 CONFIG_SF_DEFAULT_SPEED=50000000 +CONFIG_SPI_FLASH_SFDP_SUPPORT=y CONFIG_SPI_FLASH_GIGADEVICE=y CONFIG_SPI_FLASH_MACRONIX=y CONFIG_SPI_FLASH_WINBOND=y CONFIG_SPI_FLASH_XMC=y CONFIG_SPI_FLASH_MTD=y -CONFIG_PHY_ROCKCHIP_INNO_USB2=y CONFIG_DM_ETH=y CONFIG_DM_ETH_PHY=y CONFIG_DWC_ETH_QOS=y # CONFIG_DWC_ETH_QOS_FULL is not set CONFIG_GMAC_ROCKCHIP=y +CONFIG_PHY_ROCKCHIP_INNO_USB2=y CONFIG_PINCTRL=y CONFIG_SPL_PINCTRL=y +CONFIG_DM_PMIC=y +# CONFIG_SPL_PMIC_CHILDREN is not set +CONFIG_PMIC_RK801=y CONFIG_REGULATOR_PWM=y CONFIG_DM_REGULATOR_FIXED=y CONFIG_DM_REGULATOR_GPIO=y +CONFIG_REGULATOR_RK801=y CONFIG_PWM_ROCKCHIP=y CONFIG_RAM=y CONFIG_SPL_RAM=y @@ -148,6 +151,7 @@ CONFIG_USB_GADGET_DOWNLOAD=y CONFIG_DM_VIDEO=y CONFIG_DISPLAY=y CONFIG_DRM_ROCKCHIP=y +CONFIG_DRM_MEM_RESERVED_SIZE_MBYTES=8 CONFIG_DRM_ROCKCHIP_INNO_MIPI_PHY=y CONFIG_DRM_ROCKCHIP_DW_MIPI_DSI=y CONFIG_DRM_ROCKCHIP_RGB=y @@ -155,14 +159,14 @@ CONFIG_DRM_ROCKCHIP_RGB=y CONFIG_USE_TINY_PRINTF=y # CONFIG_REGEX is not set CONFIG_SPL_TINY_MEMSET=y -CONFIG_LZ4=y -CONFIG_LZMA=y -CONFIG_SPL_LZMA=y -CONFIG_SPL_GZIP=y CONFIG_RSA=y CONFIG_SPL_RSA=y CONFIG_RSA_N_SIZE=0x200 CONFIG_RSA_E_SIZE=0x10 CONFIG_RSA_C_SIZE=0x20 +CONFIG_LZ4=y +CONFIG_LZMA=y +CONFIG_SPL_LZMA=y +CONFIG_SPL_GZIP=y CONFIG_ERRNO_STR=y # CONFIG_EFI_LOADER is not set diff --git a/u-boot/configs/rk3506b-rt.config b/u-boot/configs/rk3506b-rt.config new file mode 100644 index 00000000000..09ece094814 --- /dev/null +++ b/u-boot/configs/rk3506b-rt.config @@ -0,0 +1,2 @@ +CONFIG_BASE_DEFCONFIG="rk3506_defconfig" +CONFIG_LOADER_INI="RK3506BMINIALL_RT.ini" diff --git a/u-boot/configs/rk3528-aarch32.config b/u-boot/configs/rk3528-aarch32.config index fbad26b3370..a80ed333bbc 100644 --- a/u-boot/configs/rk3528-aarch32.config +++ b/u-boot/configs/rk3528-aarch32.config @@ -2,7 +2,6 @@ CONFIG_ARM64_BOOT_AARCH32=y # CONFIG_ARM64_SUPPORT_AARCH32 is not set # CONFIG_ARMV7_LPAE is not set CONFIG_BASE_DEFCONFIG="rk3528_defconfig" -CONFIG_LOADER_INI="RK3528MINIALL_BOOT_AARCH32.ini" CONFIG_BOOTP_PXE_CLIENTARCH=0x15 CONFIG_BOOTP_VCI_STRING="U-Boot.armv7" CONFIG_CPU_V7=y diff --git a/u-boot/configs/rk3528_defconfig b/u-boot/configs/rk3528_defconfig index cfa8bbb6069..3614afb46fd 100644 --- a/u-boot/configs/rk3528_defconfig +++ b/u-boot/configs/rk3528_defconfig @@ -199,3 +199,4 @@ CONFIG_AVB_LIBAVB_USER=y CONFIG_RK_AVB_LIBAVB_USER=y CONFIG_OPTEE_CLIENT=y CONFIG_OPTEE_V2=y +CONFIG_OPTEE_ALWAYS_USE_SECURITY_PARTITION=y diff --git a/u-boot/configs/rk3562-aarch32.config b/u-boot/configs/rk3562-aarch32.config new file mode 100644 index 00000000000..834b96410f8 --- /dev/null +++ b/u-boot/configs/rk3562-aarch32.config @@ -0,0 +1,24 @@ +CONFIG_ARM64_BOOT_AARCH32=y +# CONFIG_ARM64_SUPPORT_AARCH32 is not set +# CONFIG_ARMV7_LPAE is not set +CONFIG_BASE_DEFCONFIG="rk3562_defconfig" +CONFIG_BOOTP_PXE_CLIENTARCH=0x15 +CONFIG_BOOTP_VCI_STRING="U-Boot.armv7" +CONFIG_CPU_V7=y +# CONFIG_DEBUG_LL is not set +CONFIG_HAS_THUMB2=y +CONFIG_HAS_VBAR=y +CONFIG_HAVE_PRIVATE_LIBGCC=y +# CONFIG_PHYS_64BIT is not set +# CONFIG_SPL_OF_LIBFDT is not set +CONFIG_SPL_SYS_THUMB_BUILD=y +CONFIG_SPL_USE_ARCH_MEMCPY=y +CONFIG_SPL_USE_ARCH_MEMSET=y +CONFIG_SYS_ARM_ARCH=7 +CONFIG_SYS_CPU="armv7" +CONFIG_SYS_THUMB_BUILD=y +CONFIG_TPL_USE_ARCH_MEMCPY=y +CONFIG_TPL_USE_ARCH_MEMSET=y +CONFIG_USE_ARCH_MEMCPY=y +CONFIG_USE_ARCH_MEMSET=y +CONFIG_USE_PRIVATE_LIBGCC=y diff --git a/u-boot/configs/rk3568-pcie-ep_defconfig b/u-boot/configs/rk3568-pcie-ep_defconfig index fc22f81d67f..52a51ec4497 100644 --- a/u-boot/configs/rk3568-pcie-ep_defconfig +++ b/u-boot/configs/rk3568-pcie-ep_defconfig @@ -1,123 +1,1086 @@ +# +# Automatically generated file; DO NOT EDIT. +# U-Boot 2017.09 Configuration +# +CONFIG_CREATE_ARCH_SYMLINK=y +# CONFIG_ARC is not set CONFIG_ARM=y +# CONFIG_M68K is not set +# CONFIG_MICROBLAZE is not set +# CONFIG_MIPS is not set +# CONFIG_NDS32 is not set +# CONFIG_NIOS2 is not set +# CONFIG_PPC is not set +# CONFIG_RISCV is not set +# CONFIG_SANDBOX is not set +# CONFIG_SH is not set +# CONFIG_X86 is not set +# CONFIG_XTENSA is not set +CONFIG_SYS_ARCH="arm" +CONFIG_SYS_CPU="armv8" +CONFIG_SYS_SOC="rockchip" +CONFIG_SYS_VENDOR="rockchip" +CONFIG_SYS_BOARD="evb_rk3568" +CONFIG_SYS_CONFIG_NAME="evb_rk3568" + +# +# ARM architecture +# +CONFIG_ARM64=y +# CONFIG_POSITION_INDEPENDENT is not set +CONFIG_STATIC_RELA=y +CONFIG_DMA_ADDR_T_64BIT=y +CONFIG_ARM_ASM_UNIFIED=y +CONFIG_SYS_ARM_ARCH=8 +CONFIG_SYS_CACHE_SHIFT_6=y +CONFIG_SYS_CACHELINE_SIZE=64 +CONFIG_ARM_SMCCC=y +CONFIG_ARM_CPU_SUSPEND=y +# CONFIG_SEMIHOSTING is not set +# CONFIG_SYS_L2CACHE_OFF is not set +CONFIG_ENABLE_ARM_SOC_BOOT0_HOOK=y +# CONFIG_ARM_CORTEX_CPU_IS_UP is not set +CONFIG_ARM64_SUPPORT_AARCH32=y +# CONFIG_ARM_SMP is not set +# CONFIG_ARCH_AT91 is not set +# CONFIG_TARGET_EDB93XX is not set +# CONFIG_TARGET_ASPENITE is not set +# CONFIG_TARGET_GPLUGD is not set +# CONFIG_ARCH_DAVINCI is not set +# CONFIG_KIRKWOOD is not set +# CONFIG_ARCH_MVEBU is not set +# CONFIG_TARGET_DEVKIT3250 is not set +# CONFIG_TARGET_WORK_92105 is not set +# CONFIG_TARGET_MX25PDK is not set +# CONFIG_TARGET_ZMX25 is not set +# CONFIG_TARGET_APF27 is not set +# CONFIG_TARGET_APX4DEVKIT is not set +# CONFIG_TARGET_XFI3 is not set +# CONFIG_TARGET_M28EVK is not set +# CONFIG_TARGET_MX23EVK is not set +# CONFIG_TARGET_MX28EVK is not set +# CONFIG_TARGET_MX23_OLINUXINO is not set +# CONFIG_TARGET_BG0900 is not set +# CONFIG_TARGET_SANSA_FUZE_PLUS is not set +# CONFIG_TARGET_SC_SPS_1 is not set +# CONFIG_ORION5X is not set +# CONFIG_TARGET_SPEAR300 is not set +# CONFIG_TARGET_SPEAR310 is not set +# CONFIG_TARGET_SPEAR320 is not set +# CONFIG_TARGET_SPEAR600 is not set +# CONFIG_TARGET_STV0991 is not set +# CONFIG_TARGET_X600 is not set +# CONFIG_TARGET_IMX31_PHYCORE is not set +# CONFIG_TARGET_IMX31_PHYCORE_EET is not set +# CONFIG_TARGET_MX31ADS is not set +# CONFIG_TARGET_MX31PDK is not set +# CONFIG_TARGET_WOODBURN is not set +# CONFIG_TARGET_WOODBURN_SD is not set +# CONFIG_TARGET_FLEA3 is not set +# CONFIG_TARGET_MX35PDK is not set +# CONFIG_ARCH_BCM283X is not set +# CONFIG_TARGET_VEXPRESS_CA15_TC2 is not set +# CONFIG_ARCH_BCMSTB is not set +# CONFIG_TARGET_VEXPRESS_CA5X2 is not set +# CONFIG_TARGET_VEXPRESS_CA9X4 is not set +# CONFIG_TARGET_BCM23550_W1D is not set +# CONFIG_TARGET_BCM28155_AP is not set +# CONFIG_TARGET_BCMCYGNUS is not set +# CONFIG_TARGET_BCMNSP is not set +# CONFIG_TARGET_BCMNS2 is not set +# CONFIG_ARCH_EXYNOS is not set +# CONFIG_ARCH_S5PC1XX is not set +# CONFIG_ARCH_HIGHBANK is not set +# CONFIG_ARCH_INTEGRATOR is not set +# CONFIG_ARCH_KEYSTONE is not set +# CONFIG_ARCH_OMAP2PLUS is not set +# CONFIG_ARCH_MESON is not set +# CONFIG_ARCH_MX7ULP is not set +# CONFIG_ARCH_MX7 is not set +# CONFIG_ARCH_MX6 is not set +CONFIG_SPL_LDSCRIPT="arch/arm/cpu/armv8/u-boot-spl.lds" +# CONFIG_ARCH_MX5 is not set +# CONFIG_ARCH_RMOBILE is not set +# CONFIG_TARGET_S32V234EVB is not set +# CONFIG_ARCH_SNAPDRAGON is not set +# CONFIG_ARCH_SOCFPGA is not set +# CONFIG_ARCH_SUNXI is not set +# CONFIG_TARGET_TS4600 is not set +# CONFIG_ARCH_VF610 is not set +# CONFIG_ARCH_ZYNQ is not set +# CONFIG_ARCH_ZYNQMP is not set +# CONFIG_TEGRA is not set +# CONFIG_TARGET_VEXPRESS64_AEMV8A is not set +# CONFIG_TARGET_VEXPRESS64_BASE_FVP is not set +# CONFIG_TARGET_VEXPRESS64_BASE_FVP_DRAM is not set +# CONFIG_TARGET_VEXPRESS64_JUNO is not set +# CONFIG_TARGET_LS2080A_EMU is not set +# CONFIG_TARGET_LS2080A_SIMU is not set +# CONFIG_TARGET_LS2080AQDS is not set +# CONFIG_TARGET_LS2080ARDB is not set +# CONFIG_TARGET_LS2081ARDB is not set +# CONFIG_TARGET_HIKEY is not set +# CONFIG_TARGET_POPLAR is not set +# CONFIG_TARGET_LS1012AQDS is not set +# CONFIG_TARGET_LS1012ARDB is not set +# CONFIG_TARGET_LS1012AFRDM is not set +# CONFIG_TARGET_LS1021AQDS is not set +# CONFIG_TARGET_LS1021ATWR is not set +# CONFIG_TARGET_LS1021AIOT is not set +# CONFIG_TARGET_LS1043AQDS is not set +# CONFIG_TARGET_LS1043ARDB is not set +# CONFIG_TARGET_LS1046AQDS is not set +# CONFIG_TARGET_LS1046ARDB is not set +# CONFIG_TARGET_H2200 is not set +# CONFIG_TARGET_ZIPITZ2 is not set +# CONFIG_TARGET_COLIBRI_PXA270 is not set +# CONFIG_ARCH_UNIPHIER is not set +# CONFIG_STM32 is not set +# CONFIG_ARCH_STI is not set CONFIG_ARCH_ROCKCHIP=y +# CONFIG_TARGET_THUNDERX_88XX is not set +# CONFIG_ARCH_ASPEED is not set +# CONFIG_SPL_GPIO_SUPPORT is not set CONFIG_SPL_LIBCOMMON_SUPPORT=y CONFIG_SPL_LIBGENERIC_SUPPORT=y CONFIG_SYS_MALLOC_F_LEN=0x80000 +# CONFIG_ROCKCHIP_PX30 is not set +CONFIG_TPL_LDSCRIPT="arch/arm/mach-rockchip/u-boot-tpl-v8.lds" +CONFIG_TPL_TEXT_BASE=0xfdcc1000 +CONFIG_TPL_MAX_SIZE=61440 +# CONFIG_ROCKCHIP_RK3036 is not set +# CONFIG_ROCKCHIP_RK3128 is not set +# CONFIG_ROCKCHIP_RK3066 is not set +# CONFIG_ROCKCHIP_RK3188 is not set +# CONFIG_ROCKCHIP_RK322X is not set +# CONFIG_ROCKCHIP_RK3288 is not set CONFIG_SPL_FIT_GENERATOR="arch/arm/mach-rockchip/make_fit_atf.sh" +# CONFIG_ROCKCHIP_RK3308 is not set +# CONFIG_ROCKCHIP_RK3328 is not set +# CONFIG_ROCKCHIP_RK3368 is not set +# CONFIG_ROCKCHIP_RK3399 is not set +# CONFIG_ROCKCHIP_RK3506 is not set +# CONFIG_ROCKCHIP_RK3528 is not set +# CONFIG_ROCKCHIP_RK3562 is not set CONFIG_ROCKCHIP_RK3568=y +# CONFIG_ROCKCHIP_RK3576 is not set +# CONFIG_ROCKCHIP_RK3588 is not set +# CONFIG_ROCKCHIP_RK1808 is not set +# CONFIG_ROCKCHIP_RV1103B is not set +# CONFIG_ROCKCHIP_RV1106 is not set +# CONFIG_ROCKCHIP_RV1108 is not set +# CONFIG_ROCKCHIP_RV1126 is not set +# CONFIG_SPL_ROCKCHIP_BACK_TO_BROM is not set +CONFIG_TPL_ROCKCHIP_BACK_TO_BROM=y +# CONFIG_ARM64_BOOT_AARCH32 is not set +# CONFIG_ARM64_SWITCH_TO_AARCH32 is not set +CONFIG_ROCKCHIP_BOOT_MODE_REG=0xfdc20200 +CONFIG_ROCKCHIP_STIMER_BASE=0xfdd1c020 +CONFIG_ROCKCHIP_IRAM_START_ADDR=0xfdcc0000 +CONFIG_ROCKCHIP_SPL_RESERVE_IRAM=0 +CONFIG_ROCKCHIP_BROM_HELPER=y +# CONFIG_SPL_ROCKCHIP_EARLYRETURN_TO_BROM is not set +# CONFIG_TPL_ROCKCHIP_EARLYRETURN_TO_BROM is not set +CONFIG_SPL_MMC_SUPPORT=y +CONFIG_RKIMG_BOOTLOADER=y +# CONFIG_RKIMG_ANDROID_BOOTMODE_LEGACY is not set +CONFIG_ROCKCHIP_BOOTDEV="" +CONFIG_ROCKCHIP_RESOURCE_IMAGE=y +CONFIG_ROCKCHIP_DTB_VERIFY=y +# CONFIG_ROCKCHIP_USB_BOOT is not set CONFIG_ROCKCHIP_FIT_IMAGE=y +# CONFIG_ROCKCHIP_UIMAGE is not set +# CONFIG_ROCKCHIP_EARLY_DISTRO_DTB is not set +# CONFIG_ROCKCHIP_HWID_DTB is not set CONFIG_ROCKCHIP_VENDOR_PARTITION=y +CONFIG_USING_KERNEL_DTB=y +# CONFIG_USING_KERNEL_DTB_V2 is not set +# CONFIG_EMBED_KERNEL_DTB is not set +# CONFIG_ROCKCHIP_CRC is not set +CONFIG_ROCKCHIP_SMCCC=y +# CONFIG_ROCKCHIP_DEBUGGER is not set +# CONFIG_ROCKCHIP_CRASH_DUMP is not set +CONFIG_ROCKCHIP_PRELOADER_ATAGS=y +CONFIG_ROCKCHIP_PRELOADER_SERIAL=y +# CONFIG_ROCKCHIP_IMAGE_TINY is not set CONFIG_ROCKCHIP_FIT_IMAGE_PACK=y +CONFIG_ROCKCHIP_UART_MUX_SEL_M=0 +# CONFIG_ROCKCHIP_REBOOT_TEST is not set CONFIG_ROCKCHIP_NEW_IDB=y +CONFIG_ROCKCHIP_HOTKEY=y +CONFIG_ROCKCHIP_CMD="" +# CONFIG_GICV2 is not set +CONFIG_GICV3=y +# CONFIG_ROCKCHIP_EMMC_IOMUX is not set +# CONFIG_ROCKCHIP_NAND_IOMUX is not set +# CONFIG_ROCKCHIP_SFC_IOMUX is not set +CONFIG_ROCKCHIP_SET_SN=y +CONFIG_ROCKCHIP_SET_ETHADDR=y +CONFIG_BASE_DEFCONFIG="" +CONFIG_CHIP_NAME="" +CONFIG_LOADER_INI="" +CONFIG_TRUST_INI="" +# CONFIG_PSTORE is not set +CONFIG_PERSISTENT_RAM_SIZE=0x0 +# CONFIG_ROCKCHIP_MINIDUMP is not set +# CONFIG_SANITY_CPU_SWAP is not set CONFIG_SPL_SERIAL_SUPPORT=y +CONFIG_BOARD_SPECIFIC_OPTIONS=y +# CONFIG_TPL_LIBCOMMON_SUPPORT is not set +# CONFIG_TPL_LIBGENERIC_SUPPORT is not set CONFIG_SPL_DRIVERS_MISC_SUPPORT=y +CONFIG_ENV_SIZE=0x8000 CONFIG_TARGET_EVB_RK3568=y CONFIG_SPL_LIBDISK_SUPPORT=y +# CONFIG_SPL_NAND_SUPPORT is not set CONFIG_SPL_SPI_FLASH_SUPPORT=y CONFIG_SPL_SPI_SUPPORT=y +# CONFIG_SPL_WATCHDOG_SUPPORT is not set +# CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION_TYPE is not set +CONFIG_IDENT_STRING="" +# CONFIG_SPL_FAT_SUPPORT is not set +# CONFIG_ARMV8_MULTIENTRY is not set +# CONFIG_ARMV8_SET_SMPEN is not set + +# +# ARMv8 secure monitor firmware +# +# CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT is not set +# CONFIG_SPL_ARMV8_SEC_FIRMWARE_SUPPORT is not set +CONFIG_PSCI_RESET=y +# CONFIG_ARMV8_PSCI is not set +# CONFIG_ARMV8_CRYPTO is not set +# CONFIG_CMD_DEKBLOB is not set +# CONFIG_CMD_HDMIDETECT is not set + +# +# ARM debug +# CONFIG_DEFAULT_DEVICE_TREE="rk3568-evb" CONFIG_DEBUG_UART=y +# CONFIG_AHCI is not set + +# +# General setup +# +CONFIG_LOCALVERSION="" +CONFIG_LOCALVERSION_AUTO=y +CONFIG_CC_OPTIMIZE_FOR_SIZE=y +CONFIG_DISTRO_DEFAULTS=y +CONFIG_SYS_MALLOC_F=y +CONFIG_SPL_SYS_MALLOC_F_LEN=0x80000 +CONFIG_TPL_SYS_MALLOC_F_LEN=0x80000 +CONFIG_EXPERT=y +# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +# CONFIG_TOOLS_DEBUG is not set +CONFIG_PHYS_64BIT=y + +# +# Boot images +# +# CONFIG_IMAGE_GZIP is not set +CONFIG_ANDROID_BOOT_IMAGE=y CONFIG_FIT=y +CONFIG_FIT_ENABLE_SHA256_SUPPORT=y +# CONFIG_FIT_ENABLE_RSA4096_SUPPORT is not set +# CONFIG_FIT_SIGNATURE is not set +# CONFIG_FIT_VERBOSE is not set +# CONFIG_FIT_BEST_MATCH is not set CONFIG_FIT_IMAGE_POST_PROCESS=y CONFIG_FIT_HW_CRYPTO=y +CONFIG_FIT_PRINT=y +# CONFIG_FIT_OMIT_UBOOT is not set +CONFIG_SPL_FIT=y +# CONFIG_SPL_FIT_SIGNATURE is not set CONFIG_SPL_LOAD_FIT=y CONFIG_SPL_FIT_IMAGE_POST_PROCESS=y CONFIG_SPL_FIT_HW_CRYPTO=y # CONFIG_SPL_SYS_DCACHE_OFF is not set +# CONFIG_SPL_FIT_PRINT is not set +CONFIG_SPL_FIT_SOURCE="" +CONFIG_SPL_FIT_IMAGE_KB=2048 +CONFIG_SPL_FIT_IMAGE_MULTIPLE=2 +# CONFIG_OF_BOARD_SETUP is not set +# CONFIG_OF_SYSTEM_SETUP is not set +# CONFIG_OF_STDOUT_VIA_ALIAS is not set +CONFIG_SYS_EXTRA_OPTIONS="" +CONFIG_ARCH_FIXUP_FDT_MEMORY=y + +# +# API +# +# CONFIG_API is not set + +# +# Boot timing +# +# CONFIG_BOOTSTAGE is not set +CONFIG_BOOTSTAGE_USER_COUNT=20 +CONFIG_BOOTSTAGE_RECORD_COUNT=30 +CONFIG_BOOTSTAGE_STASH_ADDR=0 +CONFIG_BOOTSTAGE_STASH_SIZE=0x1000 +# CONFIG_BOOTSTAGE_PRINTF_TIMESTAMP is not set + +# +# Boot media +# +# CONFIG_NAND_BOOT is not set +# CONFIG_ONENAND_BOOT is not set +# CONFIG_QSPI_BOOT is not set +# CONFIG_SATA_BOOT is not set +# CONFIG_SD_BOOT is not set +# CONFIG_SPI_BOOT is not set +CONFIG_PASS_DEVICE_SERIAL_BY_FDT=y CONFIG_BOOTDELAY=0 +# CONFIG_USE_BOOTARGS is not set +# CONFIG_IO_TRACE is not set + +# +# Console +# +CONFIG_MENU=y +# CONFIG_CONSOLE_RECORD is not set +# CONFIG_CONSOLE_DISABLE_CLI is not set +# CONFIG_DISABLE_CONSOLE is not set +CONFIG_LOGLEVEL=4 +CONFIG_SPL_LOGLEVEL=4 +# CONFIG_SILENT_CONSOLE is not set +# CONFIG_PRE_CONSOLE_BUFFER is not set +CONFIG_CONSOLE_MUX=y +CONFIG_SYS_CONSOLE_IS_IN_ENV=y +# CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE is not set +# CONFIG_SYS_CONSOLE_ENV_OVERWRITE is not set CONFIG_SYS_CONSOLE_INFO_QUIET=y +# CONFIG_SYS_STDIO_DEREGISTER is not set + +# +# Logging +# +# CONFIG_LOG is not set +# CONFIG_SPL_LOG is not set +CONFIG_DEFAULT_FDT_FILE="" +# CONFIG_VERSION_VARIABLE is not set +CONFIG_BOARD_LATE_INIT=y # CONFIG_DISPLAY_CPUINFO is not set +CONFIG_DISPLAY_BOARDINFO=y + +# +# Start-up hooks +# +# CONFIG_ARCH_EARLY_INIT_R is not set +# CONFIG_ARCH_MISC_INIT is not set +# CONFIG_BOARD_EARLY_INIT_F is not set +# CONFIG_BOARD_EARLY_INIT_R is not set + +# +# Android features support +# CONFIG_ANDROID_BOOTLOADER=y +# CONFIG_ANDROID_AB is not set +CONFIG_ANDROID_WRITE_KEYBOX=y CONFIG_ANDROID_AVB=y +# CONFIG_ANDROID_AVB_ROLLBACK_INDEX is not set +CONFIG_ANDROID_KEYMASTER_CA=y CONFIG_ANDROID_BOOT_IMAGE_HASH=y +# CONFIG_SKIP_RELOCATE_UBOOT is not set + +# +# Security support +# +CONFIG_HASH=y CONFIG_BOARD_RNG_SEED=y + +# +# MT support +# +# CONFIG_MP_BOOT is not set + +# +# SPL / TPL +# +CONFIG_SUPPORT_SPL=y +CONFIG_SUPPORT_TPL=y +CONFIG_SPL=y +# CONFIG_SPL_ADC_SUPPORT is not set +# CONFIG_SPL_DECOMP_HEADER is not set CONFIG_SPL_BOARD_INIT=y +# CONFIG_SPL_BOOTROM_SUPPORT is not set # CONFIG_SPL_RAW_IMAGE_SUPPORT is not set # CONFIG_SPL_LEGACY_IMAGE_SUPPORT is not set +CONFIG_SPL_SYS_MALLOC_SIMPLE=y +# CONFIG_TPL_SYS_MALLOC_SIMPLE is not set +# CONFIG_SPL_STACK_R is not set CONFIG_SPL_SEPARATE_BSS=y +# CONFIG_SPL_DISPLAY_PRINT is not set +CONFIG_SPL_SKIP_RELOCATE=y +# CONFIG_SPL_BOOT_IMAGE is not set +CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y +CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x4000 CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION=y +CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION=1 +CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION_NAME="uboot" +# CONFIG_SPL_CRC32_SUPPORT is not set +# CONFIG_SPL_MD5_SUPPORT is not set +# CONFIG_SPL_SHA1_SUPPORT is not set CONFIG_SPL_SHA256_SUPPORT=y +# CONFIG_SPL_FIT_IMAGE_TINY is not set +# CONFIG_SPL_CPU_SUPPORT is not set CONFIG_SPL_CRYPTO_SUPPORT=y CONFIG_SPL_HASH_SUPPORT=y +# CONFIG_SPL_DMA_SUPPORT is not set +# CONFIG_SPL_ENV_SUPPORT is not set +# CONFIG_SPL_EXT_SUPPORT is not set +# CONFIG_SPL_FPGA_SUPPORT is not set +# CONFIG_SPL_I2C_SUPPORT is not set +CONFIG_SPL_MMC_WRITE=y +# CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT is not set CONFIG_SPL_MTD_SUPPORT=y +CONFIG_MTD_BLK_U_BOOT_OFFS=0x4000 +CONFIG_SPL_MTD_WRITE=y +# CONFIG_SPL_MUSB_NEW_SUPPORT is not set +# CONFIG_SPL_NET_SUPPORT is not set +# CONFIG_SPL_NO_CPU_SUPPORT is not set +# CONFIG_SPL_NOR_SUPPORT is not set +# CONFIG_SPL_XIP_SUPPORT is not set +# CONFIG_SPL_ONENAND_SUPPORT is not set +# CONFIG_SPL_OS_BOOT is not set +# CONFIG_SPL_PCI_SUPPORT is not set +# CONFIG_SPL_PCH_SUPPORT is not set CONFIG_SPL_PCIE_EP_SUPPORT=y +# CONFIG_SPL_POST_MEM_SUPPORT is not set +# CONFIG_SPL_POWER_SUPPORT is not set +# CONFIG_SPL_PWM_SUPPORT is not set +# CONFIG_SPL_RAM_SUPPORT is not set +# CONFIG_SPL_RTC_SUPPORT is not set +# CONFIG_SPL_SATA_SUPPORT is not set +# CONFIG_SPL_UFS_SUPPORT is not set +# CONFIG_SPL_RKNAND_SUPPORT is not set +# CONFIG_SPL_SPI_FLASH_TINY is not set +# CONFIG_SPL_SPI_FLASH_SFDP_SUPPORT is not set +# CONFIG_SPL_SPI_LOAD is not set +# CONFIG_SPL_USB_HOST_SUPPORT is not set +# CONFIG_SPL_USB_GADGET is not set +# CONFIG_SPL_YMODEM_SUPPORT is not set CONFIG_SPL_ATF=y +# CONFIG_SPL_OPTEE_SUPPORT is not set CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y +# CONFIG_SPL_ATF_AARCH32_BL33 is not set +# CONFIG_SPL_OPTEE is not set CONFIG_SPL_AB=y +# CONFIG_SPL_LOAD_RKFW is not set +# CONFIG_SPL_KERNEL_BOOT is not set +CONFIG_TPL=y +# CONFIG_TPL_BOARD_INIT is not set +# CONFIG_TPL_NEEDS_SEPARATE_TEXT_BASE is not set +# CONFIG_TPL_NEEDS_SEPARATE_STACK is not set +# CONFIG_TPL_BOOTROM_SUPPORT is not set +# CONFIG_TPL_DRIVERS_MISC_SUPPORT is not set +# CONFIG_TPL_ENV_SUPPORT is not set +# CONFIG_TPL_I2C_SUPPORT is not set +CONFIG_TPL_TINY_FRAMEWORK=y +# CONFIG_TPL_MPC8XXX_INIT_DDR_SUPPORT is not set +# CONFIG_TPL_MMC_SUPPORT is not set +# CONFIG_TPL_NAND_SUPPORT is not set +CONFIG_TPL_SERIAL_SUPPORT=y +# CONFIG_TPL_SPI_FLASH_SUPPORT is not set +# CONFIG_TPL_SPI_SUPPORT is not set + +# +# USBPLUG +# +# CONFIG_SUPPORT_USBPLUG is not set + +# +# Command line interface +# +CONFIG_CMDLINE=y +CONFIG_HUSH_PARSER=y +CONFIG_SYS_PROMPT="=> " + +# +# Autoboot options +# +CONFIG_AUTOBOOT=y +# CONFIG_AUTOBOOT_KEYED is not set + +# +# FASTBOOT +# +CONFIG_FASTBOOT=y +CONFIG_USB_FUNCTION_FASTBOOT=y +# CONFIG_UDP_FUNCTION_FASTBOOT is not set +CONFIG_CMD_FASTBOOT=y CONFIG_FASTBOOT_BUF_ADDR=0xc00800 CONFIG_FASTBOOT_BUF_SIZE=0x04000000 +CONFIG_FASTBOOT_USB_DEV=0 CONFIG_FASTBOOT_FLASH=y CONFIG_FASTBOOT_FLASH_MMC_DEV=0 +# CONFIG_FASTBOOT_OEM_UNLOCK is not set +# CONFIG_RK_AVB_LIBAVB_ENABLE_ATH_UNLOCK is not set + +# +# Commands +# + +# +# Info commands +# +CONFIG_CMD_BDI=y +# CONFIG_CMD_CONFIG is not set +CONFIG_CMD_CONSOLE=y +# CONFIG_CMD_CPU is not set +# CONFIG_CMD_LICENSE is not set + +# +# Boot commands +# +CONFIG_CMD_BOOTD=y +CONFIG_CMD_BOOTM=y CONFIG_CMD_BOOTZ=y +CONFIG_CMD_BOOTI=y +# CONFIG_CMD_BOOTMENU is not set CONFIG_CMD_DTIMG=y # CONFIG_CMD_ELF is not set +CONFIG_CMD_FDT=y +CONFIG_CMD_GO=y +CONFIG_CMD_RUN=y # CONFIG_CMD_IMI is not set # CONFIG_CMD_IMLS is not set # CONFIG_CMD_XIMG is not set +# CONFIG_CMD_POWEROFF is not set +# CONFIG_CMD_SPL is not set +# CONFIG_CMD_THOR_DOWNLOAD is not set +# CONFIG_CMD_ZBOOT is not set + +# +# Environment commands +# +# CONFIG_CMD_ASKENV is not set +CONFIG_CMD_EXPORTENV=y +CONFIG_CMD_IMPORTENV=y +CONFIG_CMD_EDITENV=y +# CONFIG_CMD_GREPENV is not set +CONFIG_CMD_SAVEENV=y +CONFIG_CMD_ENV_EXISTS=y +# CONFIG_CMD_ENV_CALLBACK is not set +# CONFIG_CMD_ENV_FLAGS is not set + +# +# Memory commands +# +CONFIG_CMD_CRC32=y +# CONFIG_CRC32_VERIFY is not set +# CONFIG_CMD_EEPROM is not set +# CONFIG_LOOPW is not set +# CONFIG_CMD_MD5SUM is not set +# CONFIG_CMD_MEMINFO is not set +CONFIG_CMD_MEMORY=y +# CONFIG_CMD_MEMTEST is not set +# CONFIG_CMD_MX_CYCLIC is not set +# CONFIG_CMD_SHA1SUM is not set +# CONFIG_CMD_STRINGS is not set +# CONFIG_CMD_CRYPTO is not set +CONFIG_CMD_CRYPTO_SUM=y + +# +# Compression commands +# # CONFIG_CMD_LZMADEC is not set # CONFIG_CMD_UNZIP is not set +# CONFIG_CMD_ZIP is not set + +# +# Device access commands +# +# CONFIG_CMD_ARMFLASH is not set +# CONFIG_CMD_CLK is not set +# CONFIG_CMD_DEMO is not set +# CONFIG_CMD_DFU is not set +CONFIG_CMD_DM=y +# CONFIG_CMD_FDC is not set # CONFIG_CMD_FLASH is not set # CONFIG_CMD_FPGA is not set +# CONFIG_CMD_FPGAD is not set +# CONFIG_CMD_FUSE is not set +# CONFIG_CMD_GPIO is not set CONFIG_CMD_GPT=y +CONFIG_RANDOM_UUID=y +# CONFIG_CMD_GPT_RENAME is not set +# CONFIG_CMD_IDE is not set +# CONFIG_CMD_IO is not set +# CONFIG_CMD_IOTRACE is not set +# CONFIG_CMD_I2C is not set # CONFIG_CMD_LOADB is not set # CONFIG_CMD_LOADS is not set +# CONFIG_CMD_LOAD_ANDROID is not set CONFIG_CMD_BOOT_ANDROID=y +CONFIG_CMD_BOOT_FIT=y CONFIG_CMD_BOOT_ROCKCHIP=y CONFIG_CMD_MMC=y CONFIG_CMD_MTD=y CONFIG_CMD_NAND=y +# CONFIG_CMD_NAND_TRIMFFS is not set +# CONFIG_CMD_NAND_LOCK_UNLOCK is not set +# CONFIG_CMD_NAND_TORTURE is not set +# CONFIG_CMD_MMC_SPI is not set +# CONFIG_CMD_ONENAND is not set +CONFIG_CMD_PART=y +# CONFIG_CMD_PCI is not set +# CONFIG_CMD_PCMCIA is not set +CONFIG_CMD_PINMUX=y +# CONFIG_CMD_READ is not set +CONFIG_CMD_ROCKUSB=y +# CONFIG_CMD_RK_SECURE_STORAGE is not set +# CONFIG_CMD_SATA is not set +# CONFIG_CMD_SAVES is not set +# CONFIG_CMD_SDRAM is not set +# CONFIG_CMD_SF is not set +# CONFIG_CMD_SF_TEST is not set +# CONFIG_CMD_SPI is not set +# CONFIG_CMD_TSI148 is not set +# CONFIG_CMD_UNIVERSE is not set CONFIG_CMD_USB=y +# CONFIG_CMD_USB_SDP is not set CONFIG_CMD_USB_MASS_STORAGE=y + +# +# Shell scripting commands +# +CONFIG_CMD_ECHO=y # CONFIG_CMD_ITEST is not set +# CONFIG_CMD_SCRIPT_UPDATE is not set +CONFIG_CMD_SOURCE=y # CONFIG_CMD_SETEXPR is not set + +# +# Network commands +# +CONFIG_CMD_NET=y CONFIG_CMD_TFTPPUT=y CONFIG_CMD_TFTP_BOOTM=y CONFIG_CMD_TFTP_FLASH=y +# CONFIG_CMD_TFTP_UPDATE is not set +# CONFIG_CMD_TFTPSRV is not set +# CONFIG_CMD_RARP is not set +CONFIG_CMD_DHCP=y +CONFIG_CMD_PXE=y +CONFIG_CMD_NFS=y +CONFIG_CMD_MII=y +CONFIG_CMD_PING=y +# CONFIG_CMD_CDP is not set +# CONFIG_CMD_SNTP is not set +# CONFIG_CMD_DNS is not set +# CONFIG_CMD_LINK_LOCAL is not set +# CONFIG_CMD_ETHSW is not set + +# +# DDR Tool +# +# CONFIG_CMD_DDR_TOOL is not set + +# +# Misc commands +# +# CONFIG_CMD_BMP is not set +# CONFIG_CMD_BSP is not set +# CONFIG_CMD_BKOPS_ENABLE is not set +# CONFIG_CMD_CACHE is not set +# CONFIG_CMD_DISPLAY is not set +# CONFIG_CMD_LED is not set +# CONFIG_CMD_DATE is not set +# CONFIG_CMD_TIME is not set +# CONFIG_CMD_GETTIME is not set +# CONFIG_CMD_RNG is not set # CONFIG_CMD_MISC is not set +# CONFIG_CMD_TIMER is not set +# CONFIG_CMD_QFW is not set +# CONFIG_CMD_TERMINAL is not set +# CONFIG_CMD_UUID is not set + +# +# Power commands +# +# CONFIG_CMD_PMIC is not set +# CONFIG_CMD_REGULATOR is not set # CONFIG_CMD_CHARGE_DISPLAY is not set + +# +# Security commands +# +# CONFIG_CMD_AES is not set +# CONFIG_CMD_BLOB is not set +# CONFIG_CMD_HASH is not set + +# +# Firmware commands +# + +# +# Filesystem commands +# +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y +# CONFIG_CMD_EXT4_WRITE is not set +# CONFIG_CMD_EXT4_SPARSE_WRITE is not set +CONFIG_CMD_FAT=y +CONFIG_CMD_FS_GENERIC=y +# CONFIG_CMD_FS_UUID is not set +# CONFIG_CMD_JFFS2 is not set +# CONFIG_CMD_MTDPARTS is not set CONFIG_CMD_MTD_BLK=y +CONFIG_MTDIDS_DEFAULT="" +CONFIG_MTDPARTS_DEFAULT="" +# CONFIG_CMD_REISER is not set +# CONFIG_CMD_SCSI is not set +# CONFIG_CMD_ZFS is not set + +# +# Debug commands +# +CONFIG_CMD_ATAGS=y +# CONFIG_CMD_BEDBUG is not set +# CONFIG_CMD_DIAG is not set +# CONFIG_CMD_KGDB is not set +# CONFIG_CMD_LOG is not set +# CONFIG_CMD_TRACE is not set +# CONFIG_CMD_UBI is not set + +# +# Partition Types +# +CONFIG_PARTITIONS=y +# CONFIG_MAC_PARTITION is not set +# CONFIG_SPL_MAC_PARTITION is not set +CONFIG_DOS_PARTITION=y # CONFIG_SPL_DOS_PARTITION is not set # CONFIG_ISO_PARTITION is not set +# CONFIG_SPL_ISO_PARTITION is not set +# CONFIG_AMIGA_PARTITION is not set +# CONFIG_SPL_AMIGA_PARTITION is not set +CONFIG_EFI_PARTITION=y CONFIG_EFI_PARTITION_ENTRIES_NUMBERS=64 +CONFIG_EFI_PARTITION_ENTRIES_OFF=0 +CONFIG_SPL_EFI_PARTITION=y +CONFIG_PARTITION_UUIDS=y +CONFIG_SPL_PARTITION_UUIDS=y +# CONFIG_PARTITION_TYPE_GUID is not set +# CONFIG_ENV_PARTITION is not set +# CONFIG_SPL_ENV_PARTITION is not set +# CONFIG_RKPARM_PARTITION is not set +CONFIG_RKRAM_PARTITION=y +# CONFIG_SPL_ROCKCHIP_PARTITION is not set +CONFIG_SUPPORT_OF_CONTROL=y +CONFIG_DTC=y + +# +# Device Tree Control +# +CONFIG_OF_CONTROL=y +# CONFIG_OF_BOARD_FIXUP is not set CONFIG_SPL_OF_CONTROL=y CONFIG_SPL_DTB_MINIMUM=y +# CONFIG_TPL_OF_CONTROL is not set CONFIG_OF_LIVE=y +CONFIG_OF_SEPARATE=y +# CONFIG_OF_EMBED is not set +# CONFIG_OF_BOARD is not set +# CONFIG_OF_PRIOR_STAGE is not set +CONFIG_OF_LIST="rk3568-evb" +# CONFIG_MULTI_DTB_FIT is not set +# CONFIG_SPL_MULTI_DTB_FIT is not set CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" +CONFIG_OF_U_BOOT_REMOVE_PROPS="" +# CONFIG_SPL_OF_PLATDATA is not set +CONFIG_MKIMAGE_DTC_PATH="dtc" + +# +# Environment +# +CONFIG_ENV_IS_NOWHERE=y +# CONFIG_ENV_IS_IN_EEPROM is not set +# CONFIG_ENV_IS_IN_FAT is not set +# CONFIG_ENV_IS_IN_FLASH is not set +# CONFIG_ENV_IS_IN_MMC is not set +# CONFIG_ENV_IS_IN_NAND is not set +# CONFIG_ENV_IS_IN_NVRAM is not set +# CONFIG_ENV_IS_IN_ONENAND is not set +# CONFIG_ENV_IS_IN_REMOTE is not set +# CONFIG_ENV_IS_IN_SPI_FLASH is not set +# CONFIG_ENV_IS_IN_UBI is not set +# CONFIG_ENV_IS_IN_BLK_DEV is not set +# CONFIG_ENV_AES is not set +# CONFIG_ENVF is not set +# CONFIG_ENV_MEM_LAYOUT is not set +CONFIG_NET=y +# CONFIG_NET_RANDOM_ETHADDR is not set +# CONFIG_NETCONSOLE is not set # CONFIG_NET_TFTP_VARS is not set +CONFIG_BOOTP_PXE_CLIENTARCH=0x16 +CONFIG_BOOTP_VCI_STRING="U-Boot.armv8" + +# +# Device Drivers +# + +# +# Generic Driver Options +# +CONFIG_DM=y +CONFIG_SPL_DM=y +# CONFIG_TPL_DM is not set +CONFIG_DM_WARN=y +# CONFIG_DM_DEBUG is not set +CONFIG_DM_DEVICE_REMOVE=y +CONFIG_DM_STDIO=y +CONFIG_DM_SEQ_ALIAS=y +# CONFIG_SPL_DM_SEQ_ALIAS is not set CONFIG_REGMAP=y CONFIG_SPL_REGMAP=y CONFIG_SYSCON=y CONFIG_SPL_SYSCON=y +# CONFIG_DEVRES is not set +CONFIG_SIMPLE_BUS=y +CONFIG_SPL_SIMPLE_BUS=y +CONFIG_OF_TRANSLATE=y +# CONFIG_SPL_OF_TRANSLATE is not set +CONFIG_ADC=y +# CONFIG_ADC_REQ_REGULATOR is not set +# CONFIG_ADC_EXYNOS is not set +# CONFIG_ADC_SANDBOX is not set +CONFIG_SARADC_ROCKCHIP=y +# CONFIG_SARADC_ROCKCHIP_V2 is not set +# CONFIG_SATA is not set +# CONFIG_SCSI_AHCI is not set + +# +# SATA/SCSI device support +# +CONFIG_BLK=y +CONFIG_SPL_BLK=y +# CONFIG_SPL_BLK_READ_PREPARE is not set +# CONFIG_BLOCK_CACHE is not set +# CONFIG_IDE is not set + +# +# Boot count support +# +# CONFIG_BOOTCOUNT is not set + +# +# Clock +# CONFIG_CLK=y CONFIG_SPL_CLK=y CONFIG_CLK_SCMI=y +# CONFIG_CLK_AT91 is not set +CONFIG_ROCKCHIP_CLK_PLL=y +# CONFIG_CPU is not set +# CONFIG_AMP is not set + +# +# Hardware crypto devices +# CONFIG_DM_CRYPTO=y CONFIG_SPL_DM_CRYPTO=y +# CONFIG_FSL_CAAM is not set +# CONFIG_SYS_FSL_SEC_BE is not set +# CONFIG_SYS_FSL_SEC_LE is not set +CONFIG_ROCKCHIP_RSA=y +CONFIG_SPL_ROCKCHIP_RSA=y +# CONFIG_ROCKCHIP_CIPHER is not set +# CONFIG_SPL_ROCKCHIP_CIPHER is not set +# CONFIG_ROCKCHIP_HMAC is not set +# CONFIG_SPL_ROCKCHIP_HMAC is not set +# CONFIG_ROCKCHIP_CRYPTO_V1 is not set +# CONFIG_SPL_ROCKCHIP_CRYPTO_V1 is not set CONFIG_ROCKCHIP_CRYPTO_V2=y CONFIG_SPL_ROCKCHIP_CRYPTO_V2=y CONFIG_DM_RNG=y CONFIG_RNG_ROCKCHIP=y + +# +# Demo for driver model +# +# CONFIG_DM_DEMO is not set + +# +# DFU support +# + +# +# DMA Support +# +# CONFIG_DMA is not set +# CONFIG_TI_EDMA3 is not set +CONFIG_FIRMWARE=y +CONFIG_ARM_PSCI_FW=y CONFIG_SCMI_FIRMWARE=y +# CONFIG_SPL_SCMI_FIRMWARE is not set + +# +# FPGA support +# +# CONFIG_FPGA_ALTERA is not set +# CONFIG_FPGA_SOCFPGA is not set +# CONFIG_FPGA_XILINX is not set +# CONFIG_SPL_FPGA_ROCKCHIP is not set +# CONFIG_FPGA_ROCKCHIP is not set + +# +# GPIO Support +# +CONFIG_DM_GPIO=y +# CONFIG_GPIO_HOG is not set +# CONFIG_GPIO_NO_UC_FLAG_SEQ_ALIAS is not set +# CONFIG_ALTERA_PIO is not set +# CONFIG_DWAPB_GPIO is not set +# CONFIG_AT91_GPIO is not set +# CONFIG_ATMEL_PIO4 is not set +# CONFIG_INTEL_BROADWELL_GPIO is not set +# CONFIG_INTEL_ICH6_GPIO is not set +# CONFIG_IMX_RGPIO2P is not set +# CONFIG_LPC32XX_GPIO is not set +# CONFIG_MSM_GPIO is not set +# CONFIG_CMD_PCA953X is not set +# CONFIG_PCF8575_GPIO is not set CONFIG_ROCKCHIP_GPIO=y CONFIG_ROCKCHIP_GPIO_V2=y +# CONFIG_CMD_TCA642X is not set +# CONFIG_TEGRA_GPIO is not set +# CONFIG_TEGRA186_GPIO is not set +# CONFIG_VYBRID_GPIO is not set +# CONFIG_DM_74X164 is not set +# CONFIG_DM_PCA953X is not set +# CONFIG_MPC85XX_GPIO is not set +# CONFIG_NCA9539_GPIO is not set + +# +# I2C support +# +CONFIG_DM_I2C=y +# CONFIG_DM_I2C_COMPAT is not set +# CONFIG_I2C_SET_DEFAULT_BUS_NUM is not set +# CONFIG_DM_I2C_GPIO is not set +# CONFIG_SYS_I2C_FSL is not set +# CONFIG_SYS_I2C_CADENCE is not set +# CONFIG_SYS_I2C_DW is not set +# CONFIG_SYS_I2C_INTEL is not set +# CONFIG_SYS_I2C_IMX_LPI2C is not set CONFIG_SYS_I2C_ROCKCHIP=y +# CONFIG_SYS_I2C_MVTWSI is not set +# CONFIG_I2C_MUX is not set +CONFIG_INPUT=y +# CONFIG_SPL_INPUT is not set +# CONFIG_DM_KEYBOARD is not set CONFIG_DM_KEY=y +# CONFIG_DM_RC is not set +# CONFIG_SPL_DM_KEYBOARD is not set +# CONFIG_CROS_EC_KEYB is not set CONFIG_RK8XX_PWRKEY=y CONFIG_ADC_KEY=y +# CONFIG_GPIO_KEY is not set +# CONFIG_RK_KEY is not set +CONFIG_PWRKEY_DNL_TRIGGER_NUM=0 + +# +# LED Support +# +# CONFIG_LED is not set +# CONFIG_SPL_LED is not set +# CONFIG_LED_STATUS is not set + +# +# Mailbox Controller Support +# +# CONFIG_DM_MAILBOX is not set + +# +# Memory Controller drivers +# + +# +# Multifunction device drivers +# CONFIG_MISC=y CONFIG_SPL_MISC=y +# CONFIG_MISC_DECOMPRESS is not set +# CONFIG_SPL_MISC_DECOMPRESS is not set +# CONFIG_ALTERA_SYSID is not set +# CONFIG_ATSHA204A is not set +# CONFIG_ROCKCHIP_EFUSE is not set CONFIG_ROCKCHIP_OTP=y +# CONFIG_ROCKCHIP_PM_CONFIG is not set CONFIG_SPL_ROCKCHIP_SECURE_OTP=y +# CONFIG_CROS_EC is not set +# CONFIG_DS4510 is not set +# CONFIG_FSL_SEC_MON is not set +# CONFIG_MXC_OCOTP is not set +# CONFIG_NUVOTON_NCT6102D is not set +# CONFIG_PWRSEQ is not set +# CONFIG_PCA9551_LED is not set +# CONFIG_WINBOND_W83627 is not set +# CONFIG_I2C_EEPROM is not set + +# +# MMC Host controller Support +# +CONFIG_MMC=y +CONFIG_MMC_WRITE=y +CONFIG_DM_MMC=y +CONFIG_SPL_DM_MMC=y +# CONFIG_SPL_MMC_TINY is not set +# CONFIG_MMC_SIMPLE is not set +CONFIG_SUPPORT_EMMC_RPMB=y CONFIG_MMC_DW=y +CONFIG_MMC_DW_PWREN_VALUE=0 +# CONFIG_MMC_DW_K3 is not set CONFIG_MMC_DW_ROCKCHIP=y +# CONFIG_MMC_MXC is not set +# CONFIG_MMC_PCI is not set +# CONFIG_MMC_OMAP_HS is not set CONFIG_MMC_SDHCI=y CONFIG_MMC_SDHCI_SDMA=y +# CONFIG_MMC_SDHCI_BCMSTB is not set +# CONFIG_MMC_SDHCI_CADENCE is not set +# CONFIG_MMC_SDHCI_KONA is not set +# CONFIG_MMC_SDHCI_MSM is not set CONFIG_MMC_SDHCI_ROCKCHIP=y +# CONFIG_MMC_SDHCI_S5P is not set +# CONFIG_MMC_SDHCI_SPEAR is not set +# CONFIG_MMC_SDHCI_STI is not set +# CONFIG_MMC_SDHCI_XENON is not set +# CONFIG_MMC_SDHCI_TANGIER is not set +# CONFIG_MMC_USE_PRE_CONFIG is not set + +# +# MTD Support +# +CONFIG_MTD_PARTITIONS=y CONFIG_MTD=y CONFIG_MTD_BLK=y +CONFIG_MTD_WRITE=y +# CONFIG_MTD_NOR_FLASH is not set CONFIG_MTD_DEVICE=y +# CONFIG_FLASH_CFI_DRIVER is not set +# CONFIG_CFI_FLASH is not set +# CONFIG_ALTERA_QSPI is not set +CONFIG_MTD_NAND_CORE=y +CONFIG_MTD_NAND_BBT_USING_FLASH=y +# CONFIG_NAND is not set CONFIG_MTD_SPI_NAND=y +CONFIG_SPI_NAND_GIGADEVICE=y +CONFIG_SPI_NAND_MACRONIX=y +CONFIG_SPI_NAND_MICRON=y # CONFIG_SPI_NAND_TOSHIBA is not set +CONFIG_SPI_NAND_WINBOND=y +# CONFIG_SPI_NAND_WINBOND_CONT_READ is not set +CONFIG_SPI_NAND_DOSILICON=y +# CONFIG_SPI_NAND_ESMT is not set +# CONFIG_SPI_NAND_XINCUN is not set +CONFIG_SPI_NAND_XTX=y +CONFIG_SPI_NAND_HYF=y +# CONFIG_SPI_NAND_FMSH is not set +CONFIG_SPI_NAND_FORESEE=y # CONFIG_SPI_NAND_BIWIN is not set # CONFIG_SPI_NAND_ETRON is not set # CONFIG_SPI_NAND_JSC is not set @@ -125,102 +1088,597 @@ CONFIG_MTD_SPI_NAND=y # CONFIG_SPI_NAND_UNIM is not set # CONFIG_SPI_NAND_SKYHIGH is not set # CONFIG_SPI_NAND_GSTO is not set +# CONFIG_SPI_NAND_ZBIT is not set +# CONFIG_SPI_NAND_HIKSEMI is not set + +# +# SPI Flash Support +# +CONFIG_DM_SPI_FLASH=y CONFIG_SPI_FLASH=y +CONFIG_SF_DEFAULT_BUS=0 +CONFIG_SF_DEFAULT_CS=0 +CONFIG_SF_DEFAULT_MODE=3 CONFIG_SF_DEFAULT_SPEED=20000000 -CONFIG_SPI_FLASH_EON=y +# CONFIG_SPI_FLASH_SFDP_SUPPORT is not set +# CONFIG_SPI_FLASH_BAR is not set +# CONFIG_SF_DUAL_FLASH is not set +# CONFIG_SPI_FLASH_ATMEL is not set +# CONFIG_SPI_FLASH_EON is not set CONFIG_SPI_FLASH_GIGADEVICE=y +# CONFIG_SPI_FLASH_ISSI is not set CONFIG_SPI_FLASH_MACRONIX=y +# CONFIG_SPI_FLASH_SPANSION is not set +# CONFIG_SPI_FLASH_STMICRO is not set +# CONFIG_SPI_FLASH_SST is not set CONFIG_SPI_FLASH_WINBOND=y -CONFIG_SPI_FLASH_XMC=y +# CONFIG_SPI_FLASH_XMC is not set +# CONFIG_SPI_FLASH_XTX is not set +# CONFIG_SPI_FLASH_PUYA is not set +# CONFIG_SPI_FLASH_FMSH is not set +# CONFIG_SPI_FLASH_DOSILICON is not set +# CONFIG_SPI_FLASH_BOYA is not set +# CONFIG_SPI_FLASH_NORMEM is not set +CONFIG_SPI_FLASH_USE_4K_SECTORS=y +# CONFIG_SPI_FLASH_DATAFLASH is not set CONFIG_SPI_FLASH_MTD=y +# CONFIG_SPL_SPI_FLASH_MTD is not set +# CONFIG_SPI_FLASH_AUTO_MERGE is not set + +# +# UBI support +# +# CONFIG_CONFIG_UBI_SILENCE_MSG is not set +# CONFIG_MTD_UBI is not set +# CONFIG_BITBANGMII is not set +# CONFIG_MV88E6352_SWITCH is not set +CONFIG_PHYLIB=y +# CONFIG_MV88E61XX_SWITCH is not set +# CONFIG_PHYLIB_10G is not set +# CONFIG_PHY_AQUANTIA is not set +# CONFIG_PHY_ATHEROS is not set +# CONFIG_PHY_BROADCOM is not set +# CONFIG_PHY_CORTINA is not set +# CONFIG_PHY_DAVICOM is not set +# CONFIG_PHY_ET1011C is not set +# CONFIG_PHY_LXT is not set +# CONFIG_PHY_MARVELL is not set +# CONFIG_PHY_MICREL is not set +# CONFIG_PHY_MSCC is not set +# CONFIG_PHY_NATSEMI is not set +# CONFIG_PHY_REALTEK is not set +# CONFIG_PHY_RK630 is not set +# CONFIG_PHY_SMSC is not set +# CONFIG_PHY_TERANETICS is not set +# CONFIG_PHY_TI is not set +# CONFIG_PHY_VITESSE is not set +# CONFIG_PHY_XILINX is not set +# CONFIG_PHY_FIXED is not set CONFIG_DM_ETH=y +# CONFIG_DM_MDIO is not set CONFIG_DM_ETH_PHY=y +CONFIG_NETDEVICES=y +# CONFIG_PHY_GIGE is not set +# CONFIG_ALTERA_TSE is not set +# CONFIG_BCM_SF2_ETH is not set CONFIG_DWC_ETH_QOS=y +CONFIG_DWC_ETH_QOS_FULL=y +# CONFIG_E1000 is not set +# CONFIG_ETH_DESIGNWARE is not set +# CONFIG_ETHOC is not set +# CONFIG_FTMAC100 is not set +# CONFIG_MACB is not set +# CONFIG_RGMII is not set +# CONFIG_RTL8139 is not set +# CONFIG_RTL8169 is not set +# CONFIG_SUN7I_GMAC is not set +# CONFIG_SUN4I_EMAC is not set +# CONFIG_SUN8I_EMAC is not set CONFIG_GMAC_ROCKCHIP=y +# CONFIG_PCI is not set + +# +# PHY Subsystem +# +CONFIG_PHY=y +# CONFIG_SPL_PHY is not set +# CONFIG_NOP_PHY is not set CONFIG_PHY_ROCKCHIP_INNO_USB2=y CONFIG_PHY_ROCKCHIP_NANENG_COMBOPHY=y +# CONFIG_PHY_ROCKCHIP_NANENG_USB2 is not set +# CONFIG_PHY_ROCKCHIP_INNO_USB3 is not set CONFIG_PHY_ROCKCHIP_NANENG_EDP=y +# CONFIG_PHY_ROCKCHIP_SAMSUNG_HDPTX is not set +# CONFIG_PHY_ROCKCHIP_SNPS_PCIE3 is not set +# CONFIG_PHY_ROCKCHIP_USBDP is not set +# CONFIG_PHY_ROCKCHIP_TYPEC is not set +# CONFIG_MVEBU_COMPHY_SUPPORT is not set + +# +# Pin controllers +# CONFIG_PINCTRL=y +CONFIG_PINCTRL_FULL=y +CONFIG_PINCTRL_GENERIC=y +CONFIG_PINMUX=y +# CONFIG_PINCONF is not set +CONFIG_PINCONF_RECURSIVE=y CONFIG_SPL_PINCTRL=y +CONFIG_SPL_PINCTRL_FULL=y +CONFIG_SPL_PINCTRL_GENERIC=y +CONFIG_SPL_PINMUX=y +# CONFIG_SPL_PINCONF is not set +CONFIG_SPL_PINCONF_RECURSIVE=y +# CONFIG_PINCTRL_AT91 is not set +# CONFIG_PINCTRL_AT91PIO4 is not set +CONFIG_PINCTRL_ROCKCHIP=y +CONFIG_SPL_PINCTRL_ROCKCHIP=y +# CONFIG_PINCTRL_SINGLE is not set +# CONFIG_PINCTRL_STM32 is not set + +# +# Power +# + +# +# Power Domain Support +# +# CONFIG_POWER_DOMAIN is not set CONFIG_DM_FUEL_GAUGE=y +# CONFIG_SPL_DM_FUEL_GAUGE is not set +# CONFIG_POWER_FG_CW201X is not set +# CONFIG_POWER_FG_CW221X is not set +# CONFIG_POWER_FG_RK818 is not set CONFIG_POWER_FG_RK817=y +# CONFIG_POWER_FG_RK816 is not set +# CONFIG_SPL_POWER_FG_RK816 is not set + +# +# IO Domain Support +# CONFIG_IO_DOMAIN=y CONFIG_ROCKCHIP_IO_DOMAIN=y CONFIG_DM_PMIC=y +# CONFIG_SPL_DM_PMIC is not set +CONFIG_PMIC_CHILDREN=y +CONFIG_SPL_PMIC_CHILDREN=y +# CONFIG_PMIC_ACT8846 is not set +# CONFIG_PMIC_AS3722 is not set +# CONFIG_DM_PMIC_PFUZE100 is not set +# CONFIG_DM_PMIC_MAX77686 is not set +# CONFIG_DM_PMIC_MAX8998 is not set +# CONFIG_PMIC_FP9931 is not set +# CONFIG_PMIC_MAX8997 is not set +# CONFIG_PMIC_PM8916 is not set CONFIG_PMIC_RK8XX=y +# CONFIG_PMIC_SPI_RK8XX is not set +# CONFIG_PMIC_S2MPS11 is not set +# CONFIG_PMIC_SY7636A is not set +# CONFIG_DM_PMIC_SANDBOX is not set +# CONFIG_PMIC_S5M8767 is not set +# CONFIG_PMIC_RN5T567 is not set +# CONFIG_PMIC_TPS65090 is not set +# CONFIG_PMIC_PALMAS is not set +# CONFIG_PMIC_LP873X is not set +# CONFIG_PMIC_LP87565 is not set +# CONFIG_POWER_MC34VR500 is not set +# CONFIG_DM_POWER_DELIVERY is not set +CONFIG_DM_REGULATOR=y +# CONFIG_SPL_DM_REGULATOR is not set CONFIG_REGULATOR_FAN53555=y CONFIG_REGULATOR_PWM=y CONFIG_DM_REGULATOR_FIXED=y +# CONFIG_SPL_DM_REGULATOR_FIXED is not set CONFIG_DM_REGULATOR_GPIO=y +# CONFIG_REGULATOR_RK860X is not set CONFIG_REGULATOR_RK8XX=y +# CONFIG_DM_DVFS is not set +# CONFIG_CHARGER_BQ25700 is not set +# CONFIG_CHARGER_BQ25890 is not set +# CONFIG_CHARGER_SC8551 is not set +# CONFIG_CHARGER_SGM41542 is not set CONFIG_DM_CHARGE_DISPLAY=y CONFIG_CHARGE_ANIMATION=y +CONFIG_ROCKCHIP_PM=y +CONFIG_DM_PWM=y +# CONFIG_PWM_EXYNOS is not set CONFIG_PWM_ROCKCHIP=y +# CONFIG_PWM_SANDBOX is not set +# CONFIG_PWM_TEGRA is not set CONFIG_RAM=y CONFIG_SPL_RAM=y CONFIG_TPL_RAM=y +# CONFIG_STM32_SDRAM is not set CONFIG_DM_RAMDISK=y CONFIG_RAMDISK_RO=y CONFIG_DM_DMC=y +# CONFIG_ROCKCHIP_DMC is not set CONFIG_ROCKCHIP_DMC_FSP=y CONFIG_ROCKCHIP_SDRAM_COMMON=y +# CONFIG_ROCKCHIP_DRAM_EXTENDED_TEMP_SUPPORT is not set CONFIG_ROCKCHIP_TPL_INIT_DRAM_TYPE=0 + +# +# Remote Processor drivers +# + +# +# Reset Controller Support +# CONFIG_DM_RESET=y CONFIG_SPL_DM_RESET=y +CONFIG_RESET_ROCKCHIP=y CONFIG_SPL_RESET_ROCKCHIP=y +# CONFIG_RESET_SCMI is not set +# CONFIG_RKNAND is not set +# CONFIG_RKFLASH is not set + +# +# Real Time Clock +# +# CONFIG_DM_RTC is not set +# CONFIG_SCSI is not set +# CONFIG_DM_SCSI is not set + +# +# Serial drivers +# CONFIG_BAUDRATE=1500000 +CONFIG_REQUIRE_SERIAL_CONSOLE=y +CONFIG_SERIAL_PRESENT=y +CONFIG_SPL_SERIAL_PRESENT=y +CONFIG_DM_SERIAL=y +# CONFIG_SERIAL_RX_BUFFER is not set +CONFIG_SPL_DM_SERIAL=y +CONFIG_TPL_DM_SERIAL=y +# CONFIG_DEBUG_UART_ALTERA_JTAGUART is not set +# CONFIG_DEBUG_UART_ALTERA_UART is not set +# CONFIG_DEBUG_UART_ATMEL is not set +CONFIG_DEBUG_UART_NS16550=y +# CONFIG_DEBUG_UART_S5P is not set +# CONFIG_DEBUG_UART_UARTLITE is not set +# CONFIG_DEBUG_UART_ARM_DCC is not set +# CONFIG_DEBUG_MVEBU_A3700_UART is not set +# CONFIG_DEBUG_UART_ZYNQ is not set +# CONFIG_DEBUG_UART_PL010 is not set +# CONFIG_DEBUG_UART_PL011 is not set +# CONFIG_DEBUG_UART_OMAP is not set CONFIG_DEBUG_UART_BASE=0xFE660000 CONFIG_DEBUG_UART_CLOCK=24000000 CONFIG_DEBUG_UART_SHIFT=2 +CONFIG_DEBUG_UART_BOARD_INIT=y +# CONFIG_DEBUG_UART_ANNOUNCE is not set +# CONFIG_DEBUG_UART_SKIP_INIT is not set +CONFIG_DEBUG_UART_ALWAYS=y +# CONFIG_ALTERA_JTAG_UART is not set +# CONFIG_ALTERA_UART is not set +# CONFIG_ATMEL_USART is not set +# CONFIG_FSL_LPUART is not set +# CONFIG_MVEBU_A3700_UART is not set +CONFIG_SYS_NS16550=y +# CONFIG_MSM_SERIAL is not set +# CONFIG_PXA_SERIAL is not set + +# +# Sound support +# +# CONFIG_SOUND is not set +CONFIG_SPI=y +CONFIG_DM_SPI=y +CONFIG_SPI_MEM=y +# CONFIG_ALTERA_SPI is not set +# CONFIG_ATCSPI200_SPI is not set +# CONFIG_ATMEL_SPI is not set +# CONFIG_BCMSTB_SPI is not set +# CONFIG_CADENCE_QSPI is not set +# CONFIG_DESIGNWARE_SPI is not set +# CONFIG_EXYNOS_SPI is not set +# CONFIG_FSL_DSPI is not set +# CONFIG_ICH_SPI is not set +# CONFIG_MVEBU_A3700_SPI is not set +# CONFIG_ROCKCHIP_SPI is not set CONFIG_ROCKCHIP_SFC=y +# CONFIG_TEGRA114_SPI is not set +# CONFIG_TEGRA20_SFLASH is not set +# CONFIG_TEGRA20_SLINK is not set +# CONFIG_TEGRA210_QSPI is not set +# CONFIG_XILINX_SPI is not set +# CONFIG_SOFT_SPI is not set +# CONFIG_CF_SPI is not set +# CONFIG_FSL_ESPI is not set +# CONFIG_FSL_QSPI is not set +# CONFIG_SH_SPI is not set +# CONFIG_SH_QSPI is not set +# CONFIG_TI_QSPI is not set +# CONFIG_KIRKWOOD_SPI is not set +# CONFIG_LPC32XX_SSP is not set +# CONFIG_MPC8XXX_SPI is not set +# CONFIG_MXC_SPI is not set +# CONFIG_MXS_SPI is not set +# CONFIG_OMAP3_SPI is not set + +# +# SPMI support +# +# CONFIG_SPMI is not set + +# +# System reset device drivers +# CONFIG_SYSRESET=y +CONFIG_SPL_SYSRESET=y +CONFIG_SYSRESET_PSCI=y +# CONFIG_SYSRESET_SYSCON is not set +CONFIG_SYSRESET_SYSCON_REBOOT=y +# CONFIG_SYSRESET_WATCHDOG is not set +# CONFIG_DM_THERMAL is not set + +# +# Timer Support +# +# CONFIG_TIMER is not set + +# +# TPM support +# CONFIG_USB=y +CONFIG_DM_USB=y +CONFIG_SPL_DM_USB=y +# CONFIG_DM_USB_GADGET is not set +# CONFIG_SPL_DM_USB_GADGET is not set + +# +# USB Host Controller Drivers +# +CONFIG_USB_HOST=y CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y +# CONFIG_USB_XHCI_DWC3_OF_SIMPLE is not set +# CONFIG_USB_XHCI_PCI is not set CONFIG_USB_EHCI_HCD=y +# CONFIG_USB_EHCI_MSM is not set +# CONFIG_USB_EHCI_PCI is not set CONFIG_USB_EHCI_GENERIC=y CONFIG_USB_OHCI_HCD=y +# CONFIG_USB_OHCI_PCI is not set CONFIG_USB_OHCI_GENERIC=y +# CONFIG_USB_OHCI_DA8XX is not set +# CONFIG_USB_UHCI_HCD is not set +# CONFIG_USB_DWC2 is not set +# CONFIG_USB_R8A66597_HCD is not set +# CONFIG_USB_CDNS3 is not set CONFIG_USB_DWC3=y +# CONFIG_USB_DWC3_HOST is not set CONFIG_USB_DWC3_GADGET=y + +# +# Platform Glue Driver Support +# +# CONFIG_USB_DWC3_OMAP is not set CONFIG_USB_DWC3_GENERIC=y + +# +# PHY Subsystem +# +# CONFIG_USB_DWC3_PHY_OMAP is not set +# CONFIG_USB_DWC3_PHY_SAMSUNG is not set + +# +# MUSB Controller Driver +# +# CONFIG_USB_MUSB_HOST is not set +# CONFIG_USB_MUSB_GADGET is not set +# CONFIG_USB_MUSB_DA8XX is not set +# CONFIG_USB_MUSB_TI is not set + +# +# ULPI drivers +# + +# +# USB peripherals +# CONFIG_USB_STORAGE=y +# CONFIG_USB_KEYBOARD is not set CONFIG_USB_GADGET=y CONFIG_USB_GADGET_MANUFACTURER="Rockchip" CONFIG_USB_GADGET_VENDOR_NUM=0x2207 CONFIG_USB_GADGET_PRODUCT_NUM=0x350a +# CONFIG_USB_GADGET_ATMEL_USBA is not set +# CONFIG_USB_GADGET_BCM_UDC_OTG_PHY is not set +# CONFIG_USB_GADGET_DWC2_OTG is not set +# CONFIG_CI_UDC is not set +CONFIG_USB_GADGET_VBUS_DRAW=2 +CONFIG_USB_GADGET_DUALSPEED=y CONFIG_USB_GADGET_DOWNLOAD=y +# CONFIG_USB_FUNCTION_SDP is not set +# CONFIG_USB_ETHER is not set +# CONFIG_USB_HOST_ETHER is not set + +# +# UFS Host Controller Support +# +# CONFIG_TI_J721E_UFS is not set + +# +# Graphics support +# CONFIG_DM_VIDEO=y +# CONFIG_SPL_DM_VIDEO is not set +CONFIG_BACKLIGHT_PWM=y +# CONFIG_BACKLIGHT_GPIO is not set +CONFIG_VIDEO_BPP8=y +CONFIG_VIDEO_BPP16=y +CONFIG_VIDEO_BPP32=y +CONFIG_CONSOLE_NORMAL=y +# CONFIG_CONSOLE_ROTATION is not set +# CONFIG_CONSOLE_TRUETYPE is not set +CONFIG_SYS_WHITE_ON_BLACK=y + +# +# TrueType Fonts +# +# CONFIG_VIDCONSOLE_AS_LCD is not set +# CONFIG_VIDEO_VESA is not set +# CONFIG_VIDEO_LCD_ANX9804 is not set +# CONFIG_VIDEO_LCD_SSD2828 is not set +# CONFIG_VIDEO_MVEBU is not set +CONFIG_I2C_EDID=y CONFIG_DISPLAY=y +# CONFIG_ATMEL_HLCD is not set +# CONFIG_VIDEO_ROCKCHIP is not set CONFIG_DRM_ROCKCHIP=y +CONFIG_DRM_MEM_RESERVED_SIZE_MBYTES=32 +CONFIG_DRM_DP_HELPER=y +# CONFIG_DRM_MAXIM_MAX96745 is not set +# CONFIG_DRM_MAXIM_MAX96755F is not set +# CONFIG_DRM_PANEL_ROHM_BU18RL82 is not set +# CONFIG_DRM_PANEL_MAXIM_MAX96752F is not set +CONFIG_DRM_ROCKCHIP_PANEL=y CONFIG_DRM_ROCKCHIP_DW_HDMI=y +# CONFIG_DRM_ROCKCHIP_DW_HDMI_QP is not set +# CONFIG_DRM_ROCKCHIP_INNO_HDMI is not set +# CONFIG_ROCKCHIP_INNO_HDMI_PHY is not set CONFIG_DRM_ROCKCHIP_INNO_MIPI_PHY=y +# CONFIG_DRM_ROCKCHIP_INNO_VIDEO_PHY is not set CONFIG_DRM_ROCKCHIP_INNO_VIDEO_COMBO_PHY=y +CONFIG_DRM_MIPI_DSI=y CONFIG_DRM_ROCKCHIP_DW_MIPI_DSI=y +# CONFIG_DRM_ROCKCHIP_DW_MIPI_DSI2 is not set +# CONFIG_DRM_ROCKCHIP_DW_DP is not set CONFIG_DRM_ROCKCHIP_ANALOGIX_DP=y CONFIG_DRM_ROCKCHIP_LVDS=y CONFIG_DRM_ROCKCHIP_RGB=y +# CONFIG_DRM_ROCKCHIP_RK618 is not set +# CONFIG_DRM_ROCKCHIP_RK628 is not set +# CONFIG_DRM_ROCKCHIP_RK1000 is not set +# CONFIG_DRM_ROCKCHIP_SAMSUNG_MIPI_DCPHY is not set +# CONFIG_PHY_ROCKCHIP_SAMSUNG_HDPTX_HDMI is not set +# CONFIG_DRM_ROCKCHIP_TVE is not set CONFIG_ROCKCHIP_CUBIC_LUT_SIZE=9 +# CONFIG_DRM_SII902X is not set + +# +# driver for different display serdes +# +# CONFIG_SERDES_DISPLAY is not set +# CONFIG_VIDEO_TEGRA20 is not set +# CONFIG_VIDEO_TEGRA124 is not set +CONFIG_VIDEO_BRIDGE=y +# CONFIG_VIDEO_BRIDGE_PARADE_PS862X is not set +# CONFIG_VIDEO_BRIDGE_NXP_PTN3460 is not set +# CONFIG_VIDEO_BRIDGE_ANALOGIX_ANX6345 is not set +CONFIG_CONSOLE_SCROLL_LINES=1 CONFIG_LCD=y +# CONFIG_ROCKCHIP_EINK is not set + +# +# Watchdog Timer Support +# +# CONFIG_BCM2835_WDT is not set +# CONFIG_ULP_WATCHDOG is not set +# CONFIG_WDT is not set +CONFIG_IRQ=y +# CONFIG_PHYS_TO_BUS is not set + +# +# File systems +# +# CONFIG_FS_CBFS is not set +CONFIG_FS_FAT=y +CONFIG_FAT_WRITE=y +CONFIG_FS_FAT_MAX_CLUSTSIZE=65536 +# CONFIG_FS_JFFS2 is not set +# CONFIG_FS_CRAMFS is not set +# CONFIG_YAFFS2 is not set + +# +# Library routines +# +# CONFIG_BCH is not set +# CONFIG_CC_OPTIMIZE_LIBS_FOR_SPEED is not set +CONFIG_SYS_HZ=1000 +CONFIG_SYS_STACK_SIZE=0x200000 CONFIG_USE_TINY_PRINTF=y +CONFIG_PANIC_HANG=y +CONFIG_REGEX=y +# CONFIG_LIB_RAND is not set CONFIG_SPL_TINY_MEMSET=y +# CONFIG_TPL_TINY_MEMSET is not set +CONFIG_SYSMEM=y +CONFIG_BIDRAM=y +# CONFIG_CMD_DHRYSTONE is not set + +# +# Security support +# +# CONFIG_AES is not set CONFIG_RSA=y CONFIG_SPL_RSA=y +CONFIG_RSA_SOFTWARE_EXP=y CONFIG_RSA_N_SIZE=0x200 CONFIG_RSA_E_SIZE=0x10 CONFIG_RSA_C_SIZE=0x20 +# CONFIG_TPM is not set + +# +# Boot Configuration +# CONFIG_XBC=y + +# +# Hashing Support +# +CONFIG_SHA1=y +CONFIG_SHA256=y CONFIG_SHA512=y +# CONFIG_SHA_HW_ACCEL is not set + +# +# Compression Support +# CONFIG_LZ4=y CONFIG_LZMA=y +# CONFIG_SPL_LZMA is not set +# CONFIG_LZO is not set +# CONFIG_SPL_LZO is not set CONFIG_SPL_GZIP=y +CONFIG_SPL_ZLIB=y CONFIG_ERRNO_STR=y +# CONFIG_HEXDUMP is not set +CONFIG_OF_LIBFDT=y +CONFIG_OF_LIBFDT_OVERLAY=y +CONFIG_SPL_OF_LIBFDT=y +# CONFIG_TPL_OF_LIBFDT is not set +# CONFIG_FDT_FIXUP_PARTITIONS is not set + +# +# System tables +# +# CONFIG_LIB_RATIONAL is not set +# CONFIG_SPL_LIB_RATIONAL is not set # CONFIG_EFI_LOADER is not set CONFIG_AVB_LIBAVB=y +# CONFIG_SPL_AVB_LIBAVB is not set +# CONFIG_TPL_AVB_LIBAVB is not set CONFIG_AVB_LIBAVB_AB=y +# CONFIG_SPL_AVB_LIBAVB_AB is not set +# CONFIG_TPL_AVB_LIBAVB_AB is not set CONFIG_AVB_LIBAVB_ATX=y +# CONFIG_SPL_AVB_LIBAVB_ATX is not set +# CONFIG_TPL_AVB_LIBAVB_ATX is not set CONFIG_AVB_LIBAVB_USER=y +# CONFIG_AVB_VBMETA_PUBLIC_KEY_VALIDATE is not set +# CONFIG_SPL_AVB_LIBAVB_USER is not set +# CONFIG_TPL_AVB_LIBAVB_USER is not set CONFIG_RK_AVB_LIBAVB_USER=y +# CONFIG_SPL_RK_AVB_LIBAVB_USER is not set +# CONFIG_TPL_RK_AVB_LIBAVB_USER is not set +# CONFIG_ROCKCHIP_PRELOADER_PUB_KEY is not set CONFIG_OPTEE_CLIENT=y +# CONFIG_OPTEE_V1 is not set CONFIG_OPTEE_V2=y CONFIG_OPTEE_ALWAYS_USE_SECURITY_PARTITION=y +CONFIG_OPTEE_SECURITY_LEVEL=0 +# CONFIG_UNIT_TEST is not set +# CONFIG_TEST_ROCKCHIP is not set diff --git a/u-boot/configs/rk3576-ipc_defconfig b/u-boot/configs/rk3576-ipc_defconfig new file mode 100644 index 00000000000..7edf5c26007 --- /dev/null +++ b/u-boot/configs/rk3576-ipc_defconfig @@ -0,0 +1,222 @@ +CONFIG_ARM=y +CONFIG_ARCH_ROCKCHIP=y +CONFIG_SPL_GPIO_SUPPORT=y +CONFIG_SPL_LIBCOMMON_SUPPORT=y +CONFIG_SPL_LIBGENERIC_SUPPORT=y +CONFIG_SYS_MALLOC_F_LEN=0x80000 +CONFIG_SPL_FIT_GENERATOR="arch/arm/mach-rockchip/make_fit_atf.sh" +CONFIG_ROCKCHIP_RK3576=y +CONFIG_ROCKCHIP_FIT_IMAGE=y +CONFIG_USING_KERNEL_DTB_V2=y +CONFIG_ROCKCHIP_FIT_IMAGE_PACK=y +CONFIG_ROCKCHIP_NEW_IDB=y +CONFIG_SANITY_CPU_SWAP=y +CONFIG_SPL_SERIAL_SUPPORT=y +CONFIG_SPL_DRIVERS_MISC_SUPPORT=y +CONFIG_TARGET_EVB_RK3576=y +CONFIG_SPL_LIBDISK_SUPPORT=y +CONFIG_SPL_SPI_FLASH_SUPPORT=y +CONFIG_SPL_SPI_SUPPORT=y +CONFIG_ARMV8_CRYPTO=y +CONFIG_DEFAULT_DEVICE_TREE="rk3576-evb" +CONFIG_DEBUG_UART=y +CONFIG_FIT=y +CONFIG_FIT_IMAGE_POST_PROCESS=y +CONFIG_SPL_LOAD_FIT=y +CONFIG_SPL_FIT_IMAGE_POST_PROCESS=y +CONFIG_SPL_FIT_HW_CRYPTO=y +# CONFIG_SPL_SYS_DCACHE_OFF is not set +CONFIG_SPL_FIT_IMAGE_MULTIPLE=1 +CONFIG_BOOTDELAY=0 +CONFIG_SYS_CONSOLE_INFO_QUIET=y +# CONFIG_DISPLAY_CPUINFO is not set +CONFIG_BOARD_RNG_SEED=y +CONFIG_SPL_BOARD_INIT=y +# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set +# CONFIG_SPL_LEGACY_IMAGE_SUPPORT is not set +CONFIG_SPL_SEPARATE_BSS=y +CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION=y +CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION=0x1 +CONFIG_SPL_MTD_SUPPORT=y +CONFIG_SPL_UFS_SUPPORT=y +CONFIG_SPL_ATF=y +CONFIG_SPL_AB=y +# CONFIG_FASTBOOT is not set +CONFIG_CMD_BOOTZ=y +CONFIG_CMD_DTIMG=y +# CONFIG_CMD_ELF is not set +# CONFIG_CMD_IMI is not set +# CONFIG_CMD_IMLS is not set +# CONFIG_CMD_XIMG is not set +# CONFIG_CMD_LZMADEC is not set +# CONFIG_CMD_UNZIP is not set +# CONFIG_CMD_FLASH is not set +# CONFIG_CMD_FPGA is not set +CONFIG_CMD_GPIO=y +CONFIG_CMD_GPT=y +# CONFIG_CMD_LOADB is not set +# CONFIG_CMD_LOADS is not set +CONFIG_CMD_MMC=y +CONFIG_CMD_SF=y +CONFIG_CMD_SPI=y +CONFIG_CMD_UFS=y +CONFIG_CMD_USB=y +CONFIG_CMD_USB_MASS_STORAGE=y +# CONFIG_CMD_ITEST is not set +# CONFIG_CMD_SETEXPR is not set +CONFIG_CMD_TFTPPUT=y +CONFIG_CMD_TFTP_BOOTM=y +CONFIG_CMD_TFTP_FLASH=y +# CONFIG_CMD_MISC is not set +CONFIG_CMD_MTD_BLK=y +# CONFIG_SPL_DOS_PARTITION is not set +# CONFIG_ISO_PARTITION is not set +CONFIG_EFI_PARTITION_ENTRIES_NUMBERS=64 +# CONFIG_SPL_EFI_PARTITION is not set +CONFIG_SPL_OF_CONTROL=y +CONFIG_SPL_DTB_MINIMUM=y +CONFIG_OF_LIVE=y +CONFIG_OF_SPL_REMOVE_PROPS="interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" +CONFIG_OF_U_BOOT_REMOVE_PROPS="interrupt-parent" +CONFIG_ENVF=y +# CONFIG_NET_TFTP_VARS is not set +CONFIG_REGMAP=y +CONFIG_SPL_REGMAP=y +CONFIG_SYSCON=y +CONFIG_SPL_SYSCON=y +# CONFIG_SARADC_ROCKCHIP is not set +CONFIG_SARADC_ROCKCHIP_V2=y +CONFIG_CLK=y +CONFIG_SPL_CLK=y +CONFIG_CLK_SCMI=y +CONFIG_DM_CRYPTO=y +CONFIG_SPL_DM_CRYPTO=y +CONFIG_ROCKCHIP_CRYPTO_V2=y +CONFIG_SPL_ROCKCHIP_CRYPTO_V2=y +CONFIG_DM_RNG=y +CONFIG_RNG_ROCKCHIP=y +CONFIG_SCMI_FIRMWARE=y +CONFIG_GPIO_HOG=y +CONFIG_ROCKCHIP_GPIO=y +CONFIG_ROCKCHIP_GPIO_V2=y +CONFIG_SYS_I2C_ROCKCHIP=y +CONFIG_I2C_MUX=y +CONFIG_DM_KEY=y +CONFIG_RK8XX_PWRKEY=y +CONFIG_ADC_KEY=y +CONFIG_MISC=y +CONFIG_SPL_MISC=y +CONFIG_MISC_DECOMPRESS=y +CONFIG_SPL_MISC_DECOMPRESS=y +CONFIG_ROCKCHIP_OTP=y +CONFIG_ROCKCHIP_HW_DECOMPRESS=y +CONFIG_SPL_ROCKCHIP_HW_DECOMPRESS=y +CONFIG_SPL_ROCKCHIP_SECURE_OTP=y +CONFIG_MMC_DW=y +CONFIG_MMC_DW_ROCKCHIP=y +CONFIG_MMC_SDHCI=y +CONFIG_MMC_SDHCI_SDMA=y +CONFIG_MMC_SDHCI_ROCKCHIP=y +CONFIG_MTD=y +CONFIG_MTD_BLK=y +CONFIG_MTD_DEVICE=y +CONFIG_MTD_SPI_NAND=y +CONFIG_SPI_FLASH=y +CONFIG_SF_DEFAULT_MODE=0x1 +CONFIG_SF_DEFAULT_SPEED=50000000 +CONFIG_SPI_FLASH_GIGADEVICE=y +CONFIG_SPI_FLASH_MACRONIX=y +CONFIG_SPI_FLASH_WINBOND=y +CONFIG_SPI_FLASH_MTD=y +CONFIG_DM_ETH=y +CONFIG_DM_ETH_PHY=y +CONFIG_DWC_ETH_QOS=y +CONFIG_GMAC_ROCKCHIP=y +CONFIG_PHY_ROCKCHIP_INNO_USB2=y +CONFIG_PHY_ROCKCHIP_NANENG_COMBOPHY=y +CONFIG_PHY_ROCKCHIP_SAMSUNG_HDPTX=y +CONFIG_PHY_ROCKCHIP_USBDP=y +CONFIG_PINCTRL=y +CONFIG_SPL_PINCTRL=y +CONFIG_DM_FUEL_GAUGE=y +CONFIG_POWER_FG_CW201X=y +CONFIG_POWER_FG_CW221X=y +CONFIG_DM_PMIC=y +CONFIG_PMIC_RK8XX=y +CONFIG_DM_POWER_DELIVERY=y +CONFIG_TYPEC_TCPM=y +CONFIG_TYPEC_TCPCI=y +CONFIG_TYPEC_HUSB311=y +CONFIG_TYPEC_FUSB302=y +CONFIG_REGULATOR_PWM=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_REGULATOR_RK8XX=y +CONFIG_CHARGER_BQ25700=y +CONFIG_CHARGER_BQ25890=y +CONFIG_CHARGER_SGM41542=y +CONFIG_DM_CHARGE_DISPLAY=y +CONFIG_CHARGE_ANIMATION=y +CONFIG_PWM_ROCKCHIP=y +CONFIG_RAM=y +CONFIG_SPL_RAM=y +CONFIG_TPL_RAM=y +CONFIG_DM_RESET=y +CONFIG_SPL_DM_RESET=y +CONFIG_SPL_RESET_ROCKCHIP=y +CONFIG_SCSI=y +CONFIG_DM_SCSI=y +CONFIG_BAUDRATE=1500000 +CONFIG_DEBUG_UART_BASE=0x2ad40000 +CONFIG_DEBUG_UART_CLOCK=24000000 +CONFIG_DEBUG_UART_SHIFT=2 +CONFIG_ROCKCHIP_SFC=y +CONFIG_SYSRESET=y +CONFIG_USB=y +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_XHCI_DWC3=y +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_EHCI_GENERIC=y +CONFIG_USB_OHCI_HCD=y +CONFIG_USB_OHCI_GENERIC=y +CONFIG_USB_DWC3=y +CONFIG_USB_DWC3_GADGET=y +CONFIG_USB_DWC3_GENERIC=y +CONFIG_USB_STORAGE=y +CONFIG_USB_GADGET=y +CONFIG_USB_GADGET_MANUFACTURER="Rockchip" +CONFIG_USB_GADGET_VENDOR_NUM=0x2207 +CONFIG_USB_GADGET_PRODUCT_NUM=0x350e +CONFIG_USB_GADGET_DOWNLOAD=y +CONFIG_UFS=y +CONFIG_ROCKCHIP_UFS=y +CONFIG_DM_VIDEO=y +CONFIG_DISPLAY=y +CONFIG_DRM_ROCKCHIP=y +CONFIG_DRM_ROCKCHIP_DW_HDMI_QP=y +CONFIG_DRM_ROCKCHIP_DW_MIPI_DSI2=y +CONFIG_DRM_ROCKCHIP_DW_DP=y +CONFIG_DRM_ROCKCHIP_ANALOGIX_DP=y +CONFIG_DRM_ROCKCHIP_RGB=y +CONFIG_DRM_ROCKCHIP_SAMSUNG_MIPI_DCPHY=y +CONFIG_PHY_ROCKCHIP_SAMSUNG_HDPTX_HDMI=y +CONFIG_USE_TINY_PRINTF=y +CONFIG_LIB_RAND=y +CONFIG_SPL_TINY_MEMSET=y +CONFIG_RSA=y +CONFIG_SPL_RSA=y +CONFIG_RSA_N_SIZE=0x200 +CONFIG_RSA_E_SIZE=0x10 +CONFIG_RSA_C_SIZE=0x20 +CONFIG_LZ4=y +CONFIG_SPL_GZIP=y +CONFIG_ERRNO_STR=y +# CONFIG_EFI_LOADER is not set +CONFIG_AVB_LIBAVB=y +CONFIG_AVB_LIBAVB_AB=y +CONFIG_AVB_LIBAVB_ATX=y +CONFIG_AVB_LIBAVB_USER=y +CONFIG_RK_AVB_LIBAVB_USER=y +CONFIG_OPTEE_CLIENT=y +CONFIG_OPTEE_V2=y +CONFIG_OPTEE_ALWAYS_USE_SECURITY_PARTITION=y diff --git a/u-boot/configs/rv1103b_defconfig b/u-boot/configs/rv1103b_defconfig index 90602a14691..a36324ef522 100644 --- a/u-boot/configs/rv1103b_defconfig +++ b/u-boot/configs/rv1103b_defconfig @@ -99,6 +99,7 @@ CONFIG_ROCKCHIP_GPIO=y # CONFIG_INPUT is not set CONFIG_MISC=y CONFIG_SPL_MISC=y +CONFIG_ROCKCHIP_OTP=y CONFIG_MISC_DECOMPRESS=y CONFIG_SPL_MISC_DECOMPRESS=y CONFIG_ROCKCHIP_HW_DECOMPRESS=y diff --git a/u-boot/configs/rv1106b-fastboot-emmc_defconfig b/u-boot/configs/rv1106b-fastboot-emmc_defconfig index e24ec8a34fd..ac8be425225 100644 --- a/u-boot/configs/rv1106b-fastboot-emmc_defconfig +++ b/u-boot/configs/rv1106b-fastboot-emmc_defconfig @@ -91,6 +91,7 @@ CONFIG_SPL_MISC_DECOMPRESS=y CONFIG_SPL_ROCKCHIP_HW_DECOMPRESS=y CONFIG_MMC_DW=y CONFIG_MMC_DW_ROCKCHIP=y +CONFIG_MMC_USE_PRE_CONFIG=y CONFIG_MTD=y CONFIG_MTD_BLK=y CONFIG_MTD_DEVICE=y diff --git a/u-boot/configs/rv1126b-aarch32.config b/u-boot/configs/rv1126b-aarch32.config new file mode 100644 index 00000000000..785eb531954 --- /dev/null +++ b/u-boot/configs/rv1126b-aarch32.config @@ -0,0 +1,23 @@ +CONFIG_ARM64_BOOT_AARCH32=y +# CONFIG_ARM64_SUPPORT_AARCH32 is not set +# CONFIG_ARMV7_LPAE is not set +CONFIG_BOOTP_PXE_CLIENTARCH=0x15 +CONFIG_BOOTP_VCI_STRING="U-Boot.armv7" +CONFIG_CPU_V7=y +# CONFIG_DEBUG_LL is not set +CONFIG_HAS_THUMB2=y +CONFIG_HAS_VBAR=y +CONFIG_HAVE_PRIVATE_LIBGCC=y +# CONFIG_PHYS_64BIT is not set +# CONFIG_SPL_OF_LIBFDT is not set +CONFIG_SPL_SYS_THUMB_BUILD=y +CONFIG_SPL_USE_ARCH_MEMCPY=y +CONFIG_SPL_USE_ARCH_MEMSET=y +CONFIG_SYS_ARM_ARCH=7 +CONFIG_SYS_CPU="armv7" +CONFIG_SYS_THUMB_BUILD=y +CONFIG_TPL_USE_ARCH_MEMCPY=y +CONFIG_TPL_USE_ARCH_MEMSET=y +CONFIG_USE_ARCH_MEMCPY=y +CONFIG_USE_ARCH_MEMSET=y +CONFIG_USE_PRIVATE_LIBGCC=y diff --git a/u-boot/configs/rv1126b-ipc.config b/u-boot/configs/rv1126b-ipc.config new file mode 100644 index 00000000000..d4a324f2933 --- /dev/null +++ b/u-boot/configs/rv1126b-ipc.config @@ -0,0 +1,21 @@ +CONFIG_BASE_DEFCONFIG="rv1126b_defconfig" +# CONFIG_CMD_GPT is not set +CONFIG_CMD_SCRIPT_UPDATE=y +# CONFIG_EFI_PARTITION is not set +CONFIG_ENVF_LIST="blkdevparts mtdparts sys_bootargs app reserved ipaddr serverip netmask gatewayip ethaddr" +CONFIG_ENVF=y +CONFIG_ENV_NAND_OFFSET=0x0 +CONFIG_ENV_NAND_OFFSET_REDUND=0x0 +CONFIG_ENV_NAND_SIZE=0x40000 +CONFIG_ENV_NOR_OFFSET=0x0 +CONFIG_ENV_NOR_OFFSET_REDUND=0x0 +CONFIG_ENV_NOR_SIZE=0x10000 +CONFIG_ENV_OFFSET=0x0 +CONFIG_ENV_OFFSET_REDUND=0x0 +CONFIG_ENV_PARTITION=y +CONFIG_LOADER_INI="RV1126BMINIALL_IPC.ini" +# CONFIG_SPL_EFI_PARTITION is not set +CONFIG_SPL_ENVF=y +CONFIG_SPL_ENV_PARTITION=y +CONFIG_SPL_FIT_IMAGE_KB=512 +CONFIG_SPL_FIT_IMAGE_MULTIPLE=1 diff --git a/u-boot/configs/rv1126b-spi-nor_defconfig b/u-boot/configs/rv1126b-spi-nor_defconfig new file mode 100644 index 00000000000..f86099fd185 --- /dev/null +++ b/u-boot/configs/rv1126b-spi-nor_defconfig @@ -0,0 +1,166 @@ +CONFIG_ARM=y +CONFIG_ARCH_ROCKCHIP=y +CONFIG_SPL_GPIO_SUPPORT=y +CONFIG_SPL_LIBCOMMON_SUPPORT=y +CONFIG_SPL_LIBGENERIC_SUPPORT=y +CONFIG_SYS_MALLOC_F_LEN=0x80000 +CONFIG_SPL_FIT_GENERATOR="arch/arm/mach-rockchip/make_fit_atf.sh" +CONFIG_ROCKCHIP_RV1126B=y +CONFIG_ROCKCHIP_FIT_IMAGE=y +CONFIG_ROCKCHIP_VENDOR_PARTITION=y +CONFIG_USING_KERNEL_DTB_V2=y +CONFIG_ROCKCHIP_FIT_IMAGE_PACK=y +CONFIG_ROCKCHIP_NEW_IDB=y +CONFIG_SPL_SERIAL_SUPPORT=y +CONFIG_SPL_DRIVERS_MISC_SUPPORT=y +CONFIG_TARGET_EVB_RV1126B=y +CONFIG_SPL_LIBDISK_SUPPORT=y +CONFIG_SPL_SPI_FLASH_SUPPORT=y +CONFIG_SPL_SPI_SUPPORT=y +CONFIG_ARMV8_CRYPTO=y +CONFIG_DEFAULT_DEVICE_TREE="rv1126b-evb" +CONFIG_DEBUG_UART=y +CONFIG_FIT=y +CONFIG_FIT_IMAGE_POST_PROCESS=y +CONFIG_SPL_LOAD_FIT=y +CONFIG_SPL_FIT_IMAGE_POST_PROCESS=y +# CONFIG_SPL_SYS_DCACHE_OFF is not set +CONFIG_SPL_FIT_IMAGE_KB=896 +CONFIG_SPL_FIT_IMAGE_MULTIPLE=1 +CONFIG_BOOTDELAY=0 +CONFIG_SYS_CONSOLE_INFO_QUIET=y +# CONFIG_DISPLAY_CPUINFO is not set +CONFIG_ANDROID_BOOTLOADER=y +CONFIG_ANDROID_AVB=y +CONFIG_ANDROID_BOOT_IMAGE_HASH=y +CONFIG_BOARD_RNG_SEED=y +CONFIG_SPL_BOARD_INIT=y +# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set +# CONFIG_SPL_LEGACY_IMAGE_SUPPORT is not set +CONFIG_SPL_SEPARATE_BSS=y +CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION=y +CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION=0x1 +CONFIG_SPL_MTD_SUPPORT=y +CONFIG_SPL_ATF=y +CONFIG_SPL_AB=y +CONFIG_FASTBOOT_BUF_ADDR=0x40c00800 +CONFIG_FASTBOOT_BUF_SIZE=0x07000000 +CONFIG_FASTBOOT_FLASH=y +CONFIG_FASTBOOT_FLASH_MMC_DEV=0 +CONFIG_CMD_BOOTZ=y +CONFIG_CMD_DTIMG=y +# CONFIG_CMD_ELF is not set +# CONFIG_CMD_IMI is not set +# CONFIG_CMD_IMLS is not set +# CONFIG_CMD_XIMG is not set +# CONFIG_CMD_LZMADEC is not set +# CONFIG_CMD_UNZIP is not set +# CONFIG_CMD_FLASH is not set +# CONFIG_CMD_FPGA is not set +CONFIG_CMD_GPIO=y +CONFIG_RANDOM_UUID=y +# CONFIG_CMD_LOADB is not set +# CONFIG_CMD_LOADS is not set +CONFIG_CMD_BOOT_ANDROID=y +CONFIG_CMD_MMC=y +CONFIG_CMD_SF=y +CONFIG_CMD_SPI=y +CONFIG_CMD_USB=y +CONFIG_CMD_USB_MASS_STORAGE=y +# CONFIG_CMD_ITEST is not set +# CONFIG_CMD_SETEXPR is not set +# CONFIG_CMD_MISC is not set +CONFIG_CMD_MTD_BLK=y +# CONFIG_SPL_DOS_PARTITION is not set +# CONFIG_ISO_PARTITION is not set +# CONFIG_EFI_PARTITION is not set +CONFIG_SPL_OF_CONTROL=y +CONFIG_SPL_DTB_MINIMUM=y +CONFIG_OF_LIVE=y +CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" +CONFIG_OF_U_BOOT_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" +# CONFIG_NET_TFTP_VARS is not set +CONFIG_REGMAP=y +CONFIG_SPL_REGMAP=y +CONFIG_SYSCON=y +CONFIG_SPL_SYSCON=y +# CONFIG_SARADC_ROCKCHIP is not set +CONFIG_SARADC_ROCKCHIP_V2=y +CONFIG_CLK=y +CONFIG_SPL_CLK=y +CONFIG_DM_RNG=y +CONFIG_RNG_ROCKCHIP=y +CONFIG_GPIO_HOG=y +CONFIG_ROCKCHIP_GPIO=y +CONFIG_ROCKCHIP_GPIO_V2=y +CONFIG_SYS_I2C_ROCKCHIP=y +CONFIG_I2C_MUX=y +CONFIG_DM_KEY=y +CONFIG_ADC_KEY=y +CONFIG_MISC=y +CONFIG_SPL_MISC=y +CONFIG_MISC_DECOMPRESS=y +CONFIG_SPL_MISC_DECOMPRESS=y +CONFIG_MMC_DW=y +CONFIG_MMC_DW_ROCKCHIP=y +CONFIG_MTD=y +CONFIG_MTD_BLK=y +CONFIG_MTD_DEVICE=y +CONFIG_SPI_FLASH=y +CONFIG_SF_DEFAULT_MODE=0x1 +CONFIG_SF_DEFAULT_SPEED=50000000 +CONFIG_SPI_FLASH_GIGADEVICE=y +CONFIG_SPI_FLASH_MACRONIX=y +CONFIG_SPI_FLASH_WINBOND=y +CONFIG_SPI_FLASH_MTD=y +CONFIG_PHY_ROCKCHIP_INNO_USB2=y +CONFIG_PHY_ROCKCHIP_NANENG_COMBOPHY=y +CONFIG_PINCTRL=y +CONFIG_SPL_PINCTRL=y +CONFIG_DM_PMIC=y +CONFIG_PMIC_RK801=y +CONFIG_REGULATOR_PWM=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_REGULATOR_RK801=y +CONFIG_RAM=y +CONFIG_SPL_RAM=y +CONFIG_TPL_RAM=y +CONFIG_DM_RESET=y +CONFIG_SPL_DM_RESET=y +CONFIG_SPL_RESET_ROCKCHIP=y +CONFIG_BAUDRATE=1500000 +CONFIG_DEBUG_UART_BASE=0x20810000 +CONFIG_DEBUG_UART_CLOCK=24000000 +CONFIG_DEBUG_UART_SHIFT=2 +CONFIG_ROCKCHIP_SFC=y +CONFIG_SYSRESET=y +CONFIG_USB=y +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_XHCI_DWC3=y +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_EHCI_GENERIC=y +CONFIG_USB_OHCI_HCD=y +CONFIG_USB_OHCI_GENERIC=y +CONFIG_USB_DWC3=y +CONFIG_USB_DWC3_GADGET=y +CONFIG_USB_DWC3_GENERIC=y +CONFIG_USB_STORAGE=y +CONFIG_USB_GADGET=y +CONFIG_USB_GADGET_MANUFACTURER="Rockchip" +CONFIG_USB_GADGET_VENDOR_NUM=0x2207 +CONFIG_USB_GADGET_PRODUCT_NUM=0x110f +CONFIG_USB_GADGET_DOWNLOAD=y +CONFIG_USE_TINY_PRINTF=y +CONFIG_LIB_RAND=y +CONFIG_SPL_TINY_MEMSET=y +CONFIG_LZ4=y +CONFIG_SPL_LZMA=y +CONFIG_SPL_GZIP=y +CONFIG_ERRNO_STR=y +# CONFIG_EFI_LOADER is not set +CONFIG_AVB_LIBAVB=y +CONFIG_AVB_LIBAVB_AB=y +CONFIG_AVB_LIBAVB_ATX=y +CONFIG_AVB_LIBAVB_USER=y +CONFIG_RK_AVB_LIBAVB_USER=y diff --git a/u-boot/configs/rv1126b-usbplug.config b/u-boot/configs/rv1126b-usbplug.config new file mode 100644 index 00000000000..01f2e04854a --- /dev/null +++ b/u-boot/configs/rv1126b-usbplug.config @@ -0,0 +1,81 @@ +CONFIG_ARM64=y +CONFIG_ARM_PSCI_FW=y +CONFIG_ARM_SMCCC=y +# CONFIG_ARMV8_CRYPTO is not set +# CONFIG_ARMV8_MULTIENTRY is not set +# CONFIG_ARMV8_PSCI is not set +# CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT is not set +# CONFIG_ARMV8_SET_SMPEN is not set +CONFIG_BASE_DEFCONFIG="rockchip-usbplug_defconfig" +CONFIG_CMD_BOOTI=y +CONFIG_DEBUG_UART_BASE=0x20810000 +CONFIG_DEFAULT_DEVICE_TREE="rv1126b-evb" +CONFIG_DMA_ADDR_T_64BIT=y +CONFIG_DM_RESET=y +CONFIG_FIRMWARE=y +CONFIG_GICV2=y +CONFIG_IRQ=y +CONFIG_MTD_NAND_BBT_USING_FLASH=y +CONFIG_MTD_NAND_CORE=y +CONFIG_MTD_SPI_NAND=y +# CONFIG_NAND_ARASAN is not set +# CONFIG_NAND_ATMEL is not set +# CONFIG_NAND_BRCMNAND is not set +# CONFIG_NAND_DAVINCI is not set +# CONFIG_NAND_DENALI_DT is not set +# CONFIG_NAND_LPC32XX_SLC is not set +# CONFIG_NAND_PXA3XX is not set +# CONFIG_NAND_ROCKCHIP is not set +# CONFIG_NAND_ROCKCHIP_V9 is not set +# CONFIG_NAND_VF610_NFC is not set +CONFIG_NAND=y +# CONFIG_NAND_ZYNQ is not set +# CONFIG_NOP_PHY is not set +CONFIG_OF_LIVE=y +CONFIG_PHYS_64BIT=y +CONFIG_PHY=y +# CONFIG_POSITION_INDEPENDENT is not set +CONFIG_PSCI_RESET=y +CONFIG_RESET_ROCKCHIP=y +CONFIG_ROCKCHIP_BOOT_MODE_REG=0x20130220 +CONFIG_ROCKCHIP_BROM_HELPER=y +# CONFIG_ROCKCHIP_DEBUGGER is not set +CONFIG_ROCKCHIP_IRAM_START_ADDR=0x3ffb0000 +CONFIG_ROCKCHIP_NEW_IDB=y +CONFIG_ROCKCHIP_RV1126B=y +# CONFIG_ROCKCHIP_RV1126 is not set +CONFIG_ROCKCHIP_STIMER_BASE=0x20820000 +# CONFIG_SCMI_FIRMWARE is not set +CONFIG_SPI_FLASH_SFDP_SUPPORT=y +CONFIG_SPI_FLASH_XMC=y +CONFIG_SPI_FLASH_XTX=y +CONFIG_SPI_NAND_BIWIN=y +CONFIG_SPI_NAND_DOSILICON=y +CONFIG_SPI_NAND_ESMT=y +CONFIG_SPI_NAND_ETRON=y +CONFIG_SPI_NAND_FMSH=y +CONFIG_SPI_NAND_FORESEE=y +CONFIG_SPI_NAND_GIGADEVICE=y +CONFIG_SPI_NAND_GSTO=y +CONFIG_SPI_NAND_HYF=y +CONFIG_SPI_NAND_JSC=y +CONFIG_SPI_NAND_MACRONIX=y +CONFIG_SPI_NAND_MICRON=y +CONFIG_SPI_NAND_SILICONGO=y +CONFIG_SPI_NAND_SKYHIGH=y +CONFIG_SPI_NAND_TOSHIBA=y +CONFIG_SPI_NAND_UNIM=y +CONFIG_SPI_NAND_WINBOND=y +CONFIG_SPI_NAND_XINCUN=y +CONFIG_SPI_NAND_XTX=y +# CONFIG_SPL_ARMV8_SEC_FIRMWARE_SUPPORT is not set +CONFIG_SPL_LDSCRIPT="arch/arm/cpu/armv8/u-boot-spl.lds" +# CONFIG_SPL_SCMI_FIRMWARE is not set +CONFIG_STATIC_RELA=y +CONFIG_SYS_ARM_ARCH=8 +CONFIG_SYS_BOARD="evb_rv1126b" +CONFIG_SYS_CONFIG_NAME="evb_rv1126b" +CONFIG_SYS_CPU="armv8" +CONFIG_SYSRESET_PSCI=y +CONFIG_TARGET_EVB_RV1126B=y +CONFIG_OF_ADDR_SIZE_AUTO_NOPARENT=y diff --git a/u-boot/configs/rv1126b_defconfig b/u-boot/configs/rv1126b_defconfig new file mode 100644 index 00000000000..97a1105b7f1 --- /dev/null +++ b/u-boot/configs/rv1126b_defconfig @@ -0,0 +1,175 @@ +CONFIG_ARM=y +CONFIG_ARCH_ROCKCHIP=y +CONFIG_SPL_GPIO_SUPPORT=y +CONFIG_SPL_LIBCOMMON_SUPPORT=y +CONFIG_SPL_LIBGENERIC_SUPPORT=y +CONFIG_SYS_MALLOC_F_LEN=0x80000 +CONFIG_SPL_FIT_GENERATOR="arch/arm/mach-rockchip/make_fit_atf.sh" +CONFIG_ROCKCHIP_RV1126B=y +CONFIG_ROCKCHIP_FIT_IMAGE=y +CONFIG_ROCKCHIP_VENDOR_PARTITION=y +CONFIG_USING_KERNEL_DTB_V2=y +CONFIG_ROCKCHIP_FIT_IMAGE_PACK=y +CONFIG_ROCKCHIP_NEW_IDB=y +CONFIG_ROCKCHIP_EMMC_IOMUX=y +CONFIG_SPL_SERIAL_SUPPORT=y +CONFIG_SPL_DRIVERS_MISC_SUPPORT=y +CONFIG_TARGET_EVB_RV1126B=y +CONFIG_SPL_LIBDISK_SUPPORT=y +CONFIG_SPL_SPI_FLASH_SUPPORT=y +CONFIG_SPL_SPI_SUPPORT=y +CONFIG_ARMV8_CRYPTO=y +CONFIG_DEFAULT_DEVICE_TREE="rv1126b-evb" +CONFIG_DEBUG_UART=y +# CONFIG_ANDROID_BOOT_IMAGE is not set +CONFIG_FIT=y +CONFIG_FIT_IMAGE_POST_PROCESS=y +CONFIG_SPL_LOAD_FIT=y +CONFIG_SPL_FIT_IMAGE_POST_PROCESS=y +# CONFIG_SPL_SYS_DCACHE_OFF is not set +CONFIG_BOOTDELAY=0 +CONFIG_SYS_CONSOLE_INFO_QUIET=y +# CONFIG_DISPLAY_CPUINFO is not set +CONFIG_BOARD_RNG_SEED=y +CONFIG_SPL_BOARD_INIT=y +# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set +# CONFIG_SPL_LEGACY_IMAGE_SUPPORT is not set +CONFIG_SPL_SEPARATE_BSS=y +CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION=y +CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION=0x1 +CONFIG_SPL_MTD_SUPPORT=y +CONFIG_SPL_ATF=y +CONFIG_SPL_AB=y +CONFIG_FASTBOOT_BUF_ADDR=0x40c00800 +CONFIG_FASTBOOT_BUF_SIZE=0x07000000 +CONFIG_FASTBOOT_FLASH=y +CONFIG_FASTBOOT_FLASH_MMC_DEV=0 +CONFIG_CMD_BOOTZ=y +CONFIG_CMD_DTIMG=y +# CONFIG_CMD_ELF is not set +# CONFIG_CMD_IMI is not set +# CONFIG_CMD_IMLS is not set +# CONFIG_CMD_XIMG is not set +# CONFIG_CMD_LZMADEC is not set +# CONFIG_CMD_UNZIP is not set +# CONFIG_CMD_FLASH is not set +# CONFIG_CMD_FPGA is not set +CONFIG_CMD_GPIO=y +CONFIG_CMD_GPT=y +# CONFIG_CMD_LOADB is not set +# CONFIG_CMD_LOADS is not set +CONFIG_CMD_MMC=y +CONFIG_CMD_SF=y +CONFIG_CMD_SPI=y +CONFIG_CMD_USB=y +CONFIG_CMD_USB_MASS_STORAGE=y +# CONFIG_CMD_ITEST is not set +# CONFIG_CMD_SETEXPR is not set +# CONFIG_CMD_MISC is not set +CONFIG_CMD_MTD_BLK=y +# CONFIG_SPL_DOS_PARTITION is not set +# CONFIG_ISO_PARTITION is not set +CONFIG_EFI_PARTITION_ENTRIES_NUMBERS=64 +CONFIG_OF_ADDR_SIZE_AUTO_NOPARENT=y +CONFIG_SPL_OF_CONTROL=y +CONFIG_SPL_DTB_MINIMUM=y +CONFIG_OF_LIVE=y +CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" +CONFIG_OF_U_BOOT_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" +# CONFIG_NET_TFTP_VARS is not set +CONFIG_REGMAP=y +CONFIG_SPL_REGMAP=y +CONFIG_SYSCON=y +CONFIG_SPL_SYSCON=y +# CONFIG_SARADC_ROCKCHIP is not set +CONFIG_SARADC_ROCKCHIP_V2=y +CONFIG_CLK=y +CONFIG_SPL_CLK=y +CONFIG_DM_CRYPTO=y +CONFIG_SPL_DM_CRYPTO=y +CONFIG_ROCKCHIP_EC=y +CONFIG_ROCKCHIP_CRYPTO_CE=y +CONFIG_SPL_ROCKCHIP_CRYPTO_CE=y +CONFIG_DM_RNG=y +CONFIG_RNG_ROCKCHIP=y +CONFIG_GPIO_HOG=y +CONFIG_ROCKCHIP_GPIO=y +CONFIG_ROCKCHIP_GPIO_V2=y +CONFIG_SYS_I2C_ROCKCHIP=y +CONFIG_I2C_MUX=y +CONFIG_DM_KEY=y +CONFIG_RK8XX_PWRKEY=y +CONFIG_ADC_KEY=y +CONFIG_MISC=y +CONFIG_SPL_MISC=y +CONFIG_MISC_DECOMPRESS=y +CONFIG_SPL_MISC_DECOMPRESS=y +CONFIG_ROCKCHIP_OTP=y +CONFIG_ROCKCHIP_HW_DECOMPRESS=y +CONFIG_SPL_ROCKCHIP_HW_DECOMPRESS=y +CONFIG_MMC_DW=y +CONFIG_MMC_DW_ROCKCHIP=y +CONFIG_MTD=y +CONFIG_MTD_BLK=y +CONFIG_MTD_DEVICE=y +CONFIG_MTD_SPI_NAND=y +CONFIG_SPI_FLASH=y +CONFIG_SF_DEFAULT_MODE=0x1 +CONFIG_SF_DEFAULT_SPEED=50000000 +CONFIG_SPI_FLASH_GIGADEVICE=y +CONFIG_SPI_FLASH_MACRONIX=y +CONFIG_SPI_FLASH_WINBOND=y +CONFIG_SPI_FLASH_MTD=y +CONFIG_PHY_ROCKCHIP_INNO_USB2=y +CONFIG_PHY_ROCKCHIP_NANENG_COMBOPHY=y +CONFIG_PINCTRL=y +CONFIG_SPL_PINCTRL=y +CONFIG_DM_PMIC=y +CONFIG_PMIC_RK801=y +CONFIG_PMIC_RK8XX=y +CONFIG_REGULATOR_PWM=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_REGULATOR_RK801=y +CONFIG_REGULATOR_RK8XX=y +CONFIG_RAM=y +CONFIG_SPL_RAM=y +CONFIG_TPL_RAM=y +CONFIG_DM_RESET=y +CONFIG_SPL_DM_RESET=y +CONFIG_SPL_RESET_ROCKCHIP=y +CONFIG_BAUDRATE=1500000 +CONFIG_DEBUG_UART_BASE=0x20810000 +CONFIG_DEBUG_UART_CLOCK=24000000 +CONFIG_DEBUG_UART_SHIFT=2 +CONFIG_ROCKCHIP_SFC=y +CONFIG_SYSRESET=y +CONFIG_USB=y +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_XHCI_DWC3=y +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_EHCI_GENERIC=y +CONFIG_USB_OHCI_HCD=y +CONFIG_USB_OHCI_GENERIC=y +CONFIG_USB_DWC3=y +CONFIG_USB_DWC3_GADGET=y +CONFIG_USB_DWC3_GENERIC=y +CONFIG_USB_STORAGE=y +CONFIG_USB_GADGET=y +CONFIG_USB_GADGET_MANUFACTURER="Rockchip" +CONFIG_USB_GADGET_VENDOR_NUM=0x2207 +CONFIG_USB_GADGET_PRODUCT_NUM=0x110f +CONFIG_USB_GADGET_DOWNLOAD=y +CONFIG_USE_TINY_PRINTF=y +CONFIG_LIB_RAND=y +CONFIG_SPL_TINY_MEMSET=y +CONFIG_LZ4=y +CONFIG_SPL_LZMA=y +CONFIG_SPL_GZIP=y +CONFIG_ERRNO_STR=y +# CONFIG_EFI_LOADER is not set +CONFIG_AVB_LIBAVB=y +CONFIG_AVB_LIBAVB_AB=y +CONFIG_AVB_LIBAVB_ATX=y +CONFIG_AVB_LIBAVB_USER=y +CONFIG_RK_AVB_LIBAVB_USER=y diff --git a/u-boot/drivers/Kconfig b/u-boot/drivers/Kconfig index 892620829a0..72f56ecf34d 100644 --- a/u-boot/drivers/Kconfig +++ b/u-boot/drivers/Kconfig @@ -40,6 +40,8 @@ source "drivers/i2c/Kconfig" source "drivers/input/Kconfig" +source "drivers/keylad/Kconfig" + source "drivers/led/Kconfig" source "drivers/mailbox/Kconfig" diff --git a/u-boot/drivers/Makefile b/u-boot/drivers/Makefile index c2382644d95..54723457ffb 100644 --- a/u-boot/drivers/Makefile +++ b/u-boot/drivers/Makefile @@ -5,6 +5,7 @@ obj-$(CONFIG_$(SPL_TPL_)CLK) += clk/ obj-$(CONFIG_$(SPL_TPL_)DM) += core/ obj-$(CONFIG_$(SPL_TPL_)DM_CRYPTO) += crypto/ +obj-$(CONFIG_$(SPL_TPL_)DM_KEYLAD) += keylad/ obj-$(CONFIG_$(SPL_TPL_)DM_RNG) += rng/ obj-$(CONFIG_$(SPL_TPL_)DRIVERS_MISC_SUPPORT) += misc/ sysreset/ firmware/ obj-$(CONFIG_$(SPL_TPL_)I2C_SUPPORT) += i2c/ @@ -27,6 +28,7 @@ ifdef CONFIG_SPL_BUILD obj-$(CONFIG_SPL_ADC_SUPPORT) += adc/ obj-$(CONFIG_SPL_CPU_SUPPORT) += cpu/ obj-$(CONFIG_SPL_CRYPTO_SUPPORT) += crypto/ +obj-$(CONFIG_SPL_KEYLAD_SUPPORT) += keylad/ obj-$(CONFIG_SPL_GPIO_SUPPORT) += gpio/ obj-$(CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT) += ddr/fsl/ obj-$(CONFIG_ARMADA_38X) += ddr/marvell/a38x/ @@ -85,6 +87,7 @@ obj-y += block/ obj-$(CONFIG_BOOTCOUNT_LIMIT) += bootcount/ obj-$(CONFIG_CPU) += cpu/ obj-y += crypto/ +obj-y += keylad/ obj-y += firmware/ obj-$(CONFIG_FPGA) += fpga/ obj-y += misc/ diff --git a/u-boot/drivers/adc/rockchip-saradc-v2.c b/u-boot/drivers/adc/rockchip-saradc-v2.c index d11c404e23a..8f1baca90fe 100644 --- a/u-boot/drivers/adc/rockchip-saradc-v2.c +++ b/u-boot/drivers/adc/rockchip-saradc-v2.c @@ -93,6 +93,7 @@ struct rockchip_saradc_data { int num_bits; int num_channels; unsigned long clk_rate; + int das_soc_data; }; struct rockchip_saradc_priv { @@ -146,7 +147,10 @@ static int rockchip_saradc_start_channel(struct udevice *dev, int channel) reset_deassert(&priv->rst); #endif writel(0x20, &priv->regs->t_pd_soc); - writel(0xc, &priv->regs->t_das_soc); + if (priv->data->das_soc_data) + writel(priv->data->das_soc_data, &priv->regs->t_das_soc); + else + writel(0xc, &priv->regs->t_das_soc); val = SARADC2_EN_END_INT << 16 | SARADC2_EN_END_INT; writel(val, &priv->regs->end_int_en); val = SARADC2_START | SARADC2_SINGLE_MODE | channel; @@ -250,6 +254,13 @@ static const struct rockchip_saradc_data rv1103b_saradc_data = { .clk_rate = 1000000, }; +static const struct rockchip_saradc_data rv1126b_saradc_data = { + .num_bits = 13, + .num_channels = 8, + .clk_rate = 24000000, + .das_soc_data = 0x14, +}; + static const struct udevice_id rockchip_saradc_ids[] = { { .compatible = "rockchip,rk3588-saradc", @@ -271,6 +282,10 @@ static const struct udevice_id rockchip_saradc_ids[] = { .compatible = "rockchip,rv1103b-saradc", .data = (ulong)&rv1103b_saradc_data }, + { + .compatible = "rockchip,rv1126b-saradc", + .data = (ulong)&rv1126b_saradc_data + }, { } }; diff --git a/u-boot/drivers/block/blk-uclass.c b/u-boot/drivers/block/blk-uclass.c index ea640ac05fc..c901efac542 100644 --- a/u-boot/drivers/block/blk-uclass.c +++ b/u-boot/drivers/block/blk-uclass.c @@ -342,6 +342,18 @@ ulong blk_write_devnum(enum if_type if_type, int devnum, lbaint_t start, return blk_dwrite(desc, start, blkcnt, buffer); } +ulong blk_write_zeroes_devnum(enum if_type if_type, int devnum, lbaint_t start, + lbaint_t blkcnt) +{ + struct blk_desc *desc; + int ret; + + ret = get_desc(if_type, devnum, &desc); + if (ret) + return ret; + return blk_dwrite_zeroes(desc, start, blkcnt); +} + ulong blk_erase_devnum(enum if_type if_type, int devnum, lbaint_t start, lbaint_t blkcnt) { @@ -480,6 +492,19 @@ unsigned long blk_dwrite(struct blk_desc *block_dev, lbaint_t start, return ops->write(dev, start, blkcnt, buffer); } +unsigned long blk_dwrite_zeroes(struct blk_desc *block_dev, lbaint_t start, + lbaint_t blkcnt) +{ + struct udevice *dev = block_dev->bdev; + const struct blk_ops *ops = blk_get_ops(dev); + + if (!ops->write_zeroes) + return -ENOSYS; + + blkcache_invalidate(block_dev->if_type, block_dev->devnum); + return ops->write_zeroes(dev, start, blkcnt); +} + unsigned long blk_derase(struct blk_desc *block_dev, lbaint_t start, lbaint_t blkcnt) { diff --git a/u-boot/drivers/clk/rockchip/Makefile b/u-boot/drivers/clk/rockchip/Makefile index fb9087f412f..9d5da730f01 100644 --- a/u-boot/drivers/clk/rockchip/Makefile +++ b/u-boot/drivers/clk/rockchip/Makefile @@ -27,3 +27,4 @@ obj-$(CONFIG_ROCKCHIP_RV1103B) += clk_rv1103b.o obj-$(CONFIG_ROCKCHIP_RV1106) += clk_rv1106.o obj-$(CONFIG_ROCKCHIP_RV1108) += clk_rv1108.o obj-$(CONFIG_ROCKCHIP_RV1126) += clk_rv1126.o +obj-$(CONFIG_ROCKCHIP_RV1126B) += clk_rv1126b.o diff --git a/u-boot/drivers/clk/rockchip/clk_rk3506.c b/u-boot/drivers/clk/rockchip/clk_rk3506.c index 69d4602dd12..89b21385eb4 100644 --- a/u-boot/drivers/clk/rockchip/clk_rk3506.c +++ b/u-boot/drivers/clk/rockchip/clk_rk3506.c @@ -981,6 +981,7 @@ static ulong rk3506_mac_get_rate(struct rk3506_clk_priv *priv, ulong clk_id) case CLK_MAC_OUT: con = readl(&cru->pmuclksel_con[0]); div = (con & CLK_MAC_OUT_DIV_MASK) >> CLK_MAC_OUT_DIV_SHIFT; + break; default: return -ENOENT; } @@ -1005,6 +1006,7 @@ static ulong rk3506_mac_set_rate(struct rk3506_clk_priv *priv, ulong clk_id, div = DIV_ROUND_UP(priv->gpll_hz, rate); rk_clrsetreg(&cru->pmuclksel_con[0], CLK_MAC_OUT_DIV_MASK, ((div - 1) << CLK_MAC_OUT_DIV_SHIFT)); + break; default: return -ENOENT; } diff --git a/u-boot/drivers/clk/rockchip/clk_rv1126b.c b/u-boot/drivers/clk/rockchip/clk_rv1126b.c new file mode 100644 index 00000000000..d3bf06f3d9b --- /dev/null +++ b/u-boot/drivers/clk/rockchip/clk_rv1126b.c @@ -0,0 +1,1826 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) 2025 Rockchip Electronics Co., Ltd + * Author: Elaine Zhang + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +#define DIV_TO_RATE(input_rate, div) ((input_rate) / ((div) + 1)) + +#ifdef CONFIG_SPL_BUILD +#ifndef BITS_WITH_WMASK +#define BITS_WITH_WMASK(bits, msk, shift) \ + ((bits) << (shift)) | ((msk) << ((shift) + 16)) +#endif +#endif + +static struct rockchip_pll_rate_table rv1126b_pll_rates[] = { + /* _mhz, _refdiv, _fbdiv, _postdiv1, _postdiv2, _dsmpd, _frac */ + RK3036_PLL_RATE(1200000000, 1, 100, 2, 1, 1, 0), + RK3036_PLL_RATE(1188000000, 1, 99, 2, 1, 1, 0), + RK3036_PLL_RATE(1179648000, 1, 49, 1, 1, 0, 2550137), + RK3036_PLL_RATE(1000000000, 3, 250, 2, 1, 1, 0), + RK3036_PLL_RATE(993484800, 1, 41, 1, 1, 0, 6630355), + RK3036_PLL_RATE(983040000, 1, 40, 1, 1, 0, 16106127), + RK3036_PLL_RATE(903168000, 1, 75, 2, 1, 0, 4429185), + { /* sentinel */ }, +}; + +static struct rockchip_pll_clock rv1126b_pll_clks[] = { + [GPLL] = PLL(pll_rk3328, PLL_GPLL, RV1126B_PLL_CON(8), + RV1126B_MODE_CON, 2, 10, 0, rv1126b_pll_rates), + [AUPLL] = PLL(pll_rk3328, PLL_AUPLL, RV1126B_PLL_CON(0), + RV1126B_MODE_CON, 0, 10, 0, rv1126b_pll_rates), + [CPLL] = PLL(pll_rk3328, PLL_CPLL, RV1126B_PERIPLL_CON(0), + RV1126B_MODE_CON, 4, 10, 0, rv1126b_pll_rates), +}; + +#ifndef CONFIG_SPL_BUILD +#define RV1126B_CLK_DUMP(_id, _name, _iscru) \ +{ \ + .id = _id, \ + .name = _name, \ + .is_cru = _iscru, \ +} + +static const struct rv1126b_clk_info clks_dump[] = { + RV1126B_CLK_DUMP(PLL_GPLL, "gpll", true), + RV1126B_CLK_DUMP(PLL_AUPLL, "aupll", true), + RV1126B_CLK_DUMP(PLL_CPLL, "cpll", true), + RV1126B_CLK_DUMP(ACLK_PERI_ROOT, "aclk_peri_root", true), + RV1126B_CLK_DUMP(PCLK_PERI_ROOT, "pclk_peri_root", true), + RV1126B_CLK_DUMP(ACLK_TOP_ROOT, "aclk_top_root", true), + RV1126B_CLK_DUMP(PCLK_TOP_ROOT, "pclk_top_root", true), + RV1126B_CLK_DUMP(ACLK_BUS_ROOT, "aclk_bus_root", true), + RV1126B_CLK_DUMP(HCLK_BUS_ROOT, "hclk_bus_root", true), + RV1126B_CLK_DUMP(PCLK_BUS_ROOT, "pclk_bus_root", true), + RV1126B_CLK_DUMP(BUSCLK_PMU_SRC, "busclk_pmu_src", true), +}; +#endif + +static ulong rv1126b_peri_get_clk(struct rv1126b_clk_priv *priv, ulong clk_id) +{ + struct rv1126b_cru *cru = priv->cru; + u32 con, sel, rate; + + switch (clk_id) { + case ACLK_PERI_ROOT: + con = readl(&cru->clksel_con[47]); + sel = (con & ACLK_PERI_SEL_MASK) >> ACLK_PERI_SEL_SHIFT; + if (sel == ACLK_PERI_SEL_200M) + rate = 200 * MHz; + else + rate = OSC_HZ; + break; + case PCLK_PERI_ROOT: + con = readl(&cru->clksel_con[47]); + sel = (con & PCLK_PERI_SEL_MASK) >> PCLK_PERI_SEL_SHIFT; + if (sel == PCLK_PERI_SEL_100M) + rate = 100 * MHz; + else + rate = OSC_HZ; + break; + case ACLK_TOP_ROOT: + con = readl(&cru->clksel_con[44]); + sel = (con & ACLK_TOP_SEL_MASK) >> ACLK_TOP_SEL_SHIFT; + if (sel == ACLK_TOP_SEL_600M) + rate = 600 * MHz; + else if (sel == ACLK_TOP_SEL_400M) + rate = 400 * MHz; + else + rate = 200 * MHz; + break; + case PCLK_TOP_ROOT: + case PCLK_BUS_ROOT: + case BUSCLK_PMU_SRC: + rate = 100 * MHz; + break; + case ACLK_BUS_ROOT: + con = readl(&cru->clksel_con[44]); + sel = (con & ACLK_BUS_SEL_MASK) >> ACLK_BUS_SEL_SHIFT; + if (sel == ACLK_BUS_SEL_400M) + rate = 400 * MHz; + else if (sel == ACLK_BUS_SEL_300M) + rate = 300 * MHz; + else + rate = 200 * MHz; + break; + case HCLK_BUS_ROOT: + con = readl(&cru->clksel_con[44]); + sel = (con & HCLK_BUS_SEL_MASK) >> HCLK_BUS_SEL_SHIFT; + if (sel == HCLK_BUS_SEL_200M) + rate = 200 * MHz; + else + rate = 100 * MHz; + break; + default: + return -ENOENT; + } + + return rate; +} + +static ulong rv1126b_peri_set_clk(struct rv1126b_clk_priv *priv, + ulong clk_id, ulong rate) +{ + struct rv1126b_cru *cru = priv->cru; + int src_clk; + + switch (clk_id) { + case ACLK_PERI_ROOT: + if (rate >= 198 * MHz) + src_clk = ACLK_PERI_SEL_200M; + else + src_clk = ACLK_PERI_SEL_24M; + rk_clrsetreg(&cru->clksel_con[47], + ACLK_PERI_SEL_MASK, + src_clk << ACLK_PERI_SEL_SHIFT); + break; + case PCLK_PERI_ROOT: + if (rate >= 99 * MHz) + src_clk = PCLK_PERI_SEL_100M; + else + src_clk = PCLK_PERI_SEL_24M; + rk_clrsetreg(&cru->clksel_con[47], + PCLK_PERI_SEL_MASK, + src_clk << PCLK_PERI_SEL_SHIFT); + break; + case ACLK_TOP_ROOT: + if (rate >= 594 * MHz) + src_clk = ACLK_TOP_SEL_600M; + else if (rate >= 396 * MHz) + src_clk = ACLK_TOP_SEL_400M; + else + src_clk = ACLK_TOP_SEL_200M; + rk_clrsetreg(&cru->clksel_con[44], + ACLK_TOP_SEL_MASK, + src_clk << ACLK_TOP_SEL_SHIFT); + break; + case PCLK_TOP_ROOT: + case PCLK_BUS_ROOT: + case BUSCLK_PMU_SRC: + break; + case ACLK_BUS_ROOT: + if (rate >= 396 * MHz) + src_clk = ACLK_BUS_SEL_400M; + else if (rate >= 297 * MHz) + src_clk = ACLK_BUS_SEL_300M; + else + src_clk = ACLK_BUS_SEL_200M; + rk_clrsetreg(&cru->clksel_con[44], + ACLK_BUS_SEL_MASK, + src_clk << ACLK_BUS_SEL_SHIFT); + break; + case HCLK_BUS_ROOT: + if (rate >= 198 * MHz) + src_clk = HCLK_BUS_SEL_200M; + else + src_clk = HCLK_BUS_SEL_100M; + rk_clrsetreg(&cru->clksel_con[44], + HCLK_BUS_SEL_MASK, + src_clk << HCLK_BUS_SEL_SHIFT); + break; + default: + printf("do not support this permid freq\n"); + return -EINVAL; + } + + return rv1126b_peri_get_clk(priv, clk_id); +} + +static ulong rv1126b_i2c_get_clk(struct rv1126b_clk_priv *priv, ulong clk_id) +{ + struct rv1126b_cru *cru = priv->cru; + u32 sel, con; + ulong rate; + + switch (clk_id) { + case CLK_I2C0: + case CLK_I2C1: + case CLK_I2C3: + case CLK_I2C4: + case CLK_I2C5: + case CLK_I2C_BUS_SRC: + con = readl(&cru->clksel_con[50]); + sel = (con & CLK_I2C_SEL_MASK) >> CLK_I2C_SEL_SHIFT; + if (sel == CLK_I2C_SEL_200M) + rate = 200 * MHz; + else + rate = OSC_HZ; + break; + case CLK_I2C2: + con = readl(&cru->pmu_clksel_con[2]); + sel = (con & CLK_I2C2_SEL_MASK) >> CLK_I2C2_SEL_SHIFT; + if (sel == CLK_I2C2_SEL_100M) + rate = 100 * MHz; + else if (sel == CLK_I2C2_SEL_RCOSC) + rate = RC_OSC_HZ; + else + rate = OSC_HZ; + break; + default: + return -ENOENT; + } + + return rate; +} + +static ulong rv1126b_i2c_set_clk(struct rv1126b_clk_priv *priv, ulong clk_id, + ulong rate) +{ + struct rv1126b_cru *cru = priv->cru; + int src_clk; + + switch (clk_id) { + case CLK_I2C0: + case CLK_I2C1: + case CLK_I2C3: + case CLK_I2C4: + case CLK_I2C5: + case CLK_I2C_BUS_SRC: + if (rate == OSC_HZ) + src_clk = CLK_I2C_SEL_24M; + else + src_clk = CLK_I2C_SEL_200M; + rk_clrsetreg(&cru->clksel_con[50], CLK_I2C_SEL_MASK, + src_clk << CLK_I2C_SEL_SHIFT); + break; + case CLK_I2C2: + if (rate == OSC_HZ) + src_clk = CLK_I2C2_SEL_24M; + else if (rate == RC_OSC_HZ) + src_clk = CLK_I2C2_SEL_RCOSC; + else + src_clk = CLK_I2C2_SEL_100M; + rk_clrsetreg(&cru->pmu_clksel_con[2], CLK_I2C2_SEL_MASK, + src_clk << CLK_I2C2_SEL_SHIFT); + break; + default: + return -ENOENT; + } + return rv1126b_i2c_get_clk(priv, clk_id); +} + +static ulong rv1126b_crypto_get_clk(struct rv1126b_clk_priv *priv, ulong clk_id) +{ + struct rv1126b_cru *cru = priv->cru; + u32 sel, con, rate; + + switch (clk_id) { + case PCLK_RKCE: + return rv1126b_peri_get_clk(priv, PCLK_BUS_ROOT); + case HCLK_NS_RKCE: + return rv1126b_peri_get_clk(priv, HCLK_BUS_ROOT); + case ACLK_RKCE_SRC: + case ACLK_NSRKCE: + con = readl(&cru->clksel_con[50]); + sel = (con & ACLK_RKCE_SEL_MASK) >> + ACLK_RKCE_SEL_SHIFT; + if (sel == ACLK_RKCE_SEL_200M) + rate = 200 * MHz; + else + rate = OSC_HZ; + break; + case CLK_PKA_RKCE_SRC: + case CLK_PKA_NSRKCE: + con = readl(&cru->clksel_con[50]); + sel = (con & CLK_PKA_RKCE_SEL_MASK) >> + CLK_PKA_RKCE_SEL_SHIFT; + if (sel == CLK_PKA_RKCE_SEL_300M) + rate = 300 * MHz; + else + rate = 200 * MHz; + break; + default: + return -ENOENT; + } + return rate; +} + +static ulong rv1126b_crypto_set_clk(struct rv1126b_clk_priv *priv, + ulong clk_id, ulong rate) +{ + struct rv1126b_cru *cru = priv->cru; + u32 sel; + + switch (clk_id) { + case PCLK_RKCE: + break; + case HCLK_NS_RKCE: + rv1126b_peri_set_clk(priv, HCLK_BUS_ROOT, rate); + case ACLK_RKCE_SRC: + case ACLK_NSRKCE: + if (rate >= 198 * MHz) + sel = ACLK_RKCE_SEL_200M; + else + sel = ACLK_RKCE_SEL_24M; + rk_clrsetreg(&cru->clksel_con[50], + ACLK_RKCE_SEL_MASK, + (sel << ACLK_RKCE_SEL_SHIFT)); + break; + case CLK_PKA_RKCE_SRC: + case CLK_PKA_NSRKCE: + if (rate >= 297 * MHz) + sel = CLK_PKA_RKCE_SEL_300M; + else + sel = CLK_PKA_RKCE_SEL_200M; + rk_clrsetreg(&cru->clksel_con[50], + CLK_PKA_RKCE_SEL_MASK, + (sel << CLK_PKA_RKCE_SEL_SHIFT)); + break; + default: + return -ENOENT; + } + return rv1126b_crypto_get_clk(priv, clk_id); +} + +static ulong rv1126b_mmc_get_clk(struct rv1126b_clk_priv *priv, ulong clk_id) +{ + struct rv1126b_cru *cru = priv->cru; + u32 div, sel, con, prate; + + switch (clk_id) { + case CCLK_SDMMC0: + case HCLK_SDMMC0: + con = readl(&cru->clksel_con[45]); + sel = (con & CLK_SDMMC_SEL_MASK) >> + CLK_SDMMC_SEL_SHIFT; + div = (con & CLK_SDMMC_DIV_MASK) >> + CLK_SDMMC_DIV_SHIFT; + if (sel == CLK_SDMMC_SEL_GPLL) + prate = priv->gpll_hz; + else if (sel == CLK_SDMMC_SEL_CPLL) + prate = priv->cpll_hz; + else + prate = OSC_HZ; + return DIV_TO_RATE(prate, div); + case CCLK_SDMMC1: + case HCLK_SDMMC1: + con = readl(&cru->clksel_con[46]); + sel = (con & CLK_SDMMC_SEL_MASK) >> + CLK_SDMMC_SEL_SHIFT; + div = (con & CLK_SDMMC_DIV_MASK) >> + CLK_SDMMC_DIV_SHIFT; + if (sel == CLK_SDMMC_SEL_GPLL) + prate = priv->gpll_hz; + else if (sel == CLK_SDMMC_SEL_CPLL) + prate = priv->cpll_hz; + else + prate = OSC_HZ; + return DIV_TO_RATE(prate, div); + case CCLK_EMMC: + case HCLK_EMMC: + con = readl(&cru->clksel_con[47]); + sel = (con & CLK_SDMMC_SEL_MASK) >> + CLK_SDMMC_SEL_SHIFT; + div = (con & CLK_SDMMC_DIV_MASK) >> + CLK_SDMMC_DIV_SHIFT; + if (sel == CLK_SDMMC_SEL_GPLL) + prate = priv->gpll_hz; + else if (sel == CLK_SDMMC_SEL_CPLL) + prate = priv->cpll_hz; + else + prate = OSC_HZ; + return DIV_TO_RATE(prate, div); + case SCLK_2X_FSPI0: + case HCLK_FSPI0: + case HCLK_XIP_FSPI0: + con = readl(&cru->clksel_con[48]); + sel = (con & CLK_SDMMC_SEL_MASK) >> + CLK_SDMMC_SEL_SHIFT; + div = (con & CLK_SDMMC_DIV_MASK) >> + CLK_SDMMC_DIV_SHIFT; + if (sel == CLK_SDMMC_SEL_GPLL) + prate = priv->gpll_hz; + else if (sel == CLK_SDMMC_SEL_CPLL) + prate = priv->cpll_hz; + else + prate = OSC_HZ; + return DIV_TO_RATE(prate, div); + case SCLK_1X_FSPI1: + case HCLK_FSPI1: + case HCLK_XIP_FSPI1: + con = readl(&cru->pmu1_clksel_con[0]); + sel = (con & SCLK_1X_FSPI1_SEL_MASK) >> + SCLK_1X_FSPI1_SEL_SHIFT; + div = (con & SCLK_1X_FSPI1_DIV_MASK) >> + SCLK_1X_FSPI1_DIV_SHIFT; + if (sel == SCLK_1X_FSPI1_SEL_100M) + prate = 100 * MHz; + else if (sel == SCLK_1X_FSPI1_SEL_RCOSC) + prate = RC_OSC_HZ; + else + prate = OSC_HZ; + return DIV_TO_RATE(prate, div); + default: + return -ENOENT; + } +} + +static ulong rv1126b_mmc_set_clk(struct rv1126b_clk_priv *priv, + ulong clk_id, ulong rate) +{ + struct rv1126b_cru *cru = priv->cru; + u32 sel, src_clk_div; + ulong prate = 0; + + if ((OSC_HZ % rate) == 0) { + sel = CLK_SDMMC_SEL_24M; + prate = OSC_HZ; + } else if ((priv->cpll_hz % rate) == 0) { + sel = CLK_SDMMC_SEL_CPLL; + prate = priv->cpll_hz; + } else { + sel = CLK_SDMMC_SEL_GPLL; + prate = priv->gpll_hz; + } + src_clk_div = DIV_ROUND_UP(prate, rate); + + switch (clk_id) { + case CCLK_SDMMC0: + case HCLK_SDMMC0: + src_clk_div = DIV_ROUND_UP(prate, rate); + rk_clrsetreg(&cru->clksel_con[45], + CLK_SDMMC_SEL_MASK | + CLK_SDMMC_DIV_MASK, + (sel << CLK_SDMMC_SEL_SHIFT) | + ((src_clk_div - 1) << + CLK_SDMMC_DIV_SHIFT)); + break; + case CCLK_SDMMC1: + case HCLK_SDMMC1: + src_clk_div = DIV_ROUND_UP(prate, rate); + rk_clrsetreg(&cru->clksel_con[46], + CLK_SDMMC_SEL_MASK | + CLK_SDMMC_DIV_MASK, + (sel << CLK_SDMMC_SEL_SHIFT) | + ((src_clk_div - 1) << + CLK_SDMMC_DIV_SHIFT)); + break; + case CCLK_EMMC: + case HCLK_EMMC: + src_clk_div = DIV_ROUND_UP(prate, rate); + rk_clrsetreg(&cru->clksel_con[47], + CLK_SDMMC_SEL_MASK | + CLK_SDMMC_DIV_MASK, + (sel << CLK_SDMMC_SEL_SHIFT) | + ((src_clk_div - 1) << + CLK_SDMMC_DIV_SHIFT)); + break; + case SCLK_2X_FSPI0: + case HCLK_FSPI0: + case HCLK_XIP_FSPI0: + src_clk_div = DIV_ROUND_UP(prate, rate); + rk_clrsetreg(&cru->clksel_con[48], + CLK_SDMMC_SEL_MASK | + CLK_SDMMC_DIV_MASK, + (sel << CLK_SDMMC_SEL_SHIFT) | + ((src_clk_div - 1) << + CLK_SDMMC_DIV_SHIFT)); + break; + case SCLK_1X_FSPI1: + case HCLK_FSPI1: + case HCLK_XIP_FSPI1: + if ((OSC_HZ % rate) == 0) { + sel = SCLK_1X_FSPI1_SEL_24M; + prate = OSC_HZ; + } else if ((100 * MHz % rate) == 0) { + sel = SCLK_1X_FSPI1_SEL_100M; + prate = priv->cpll_hz; + } else { + sel = SCLK_1X_FSPI1_SEL_RCOSC; + prate = RC_OSC_HZ; + } + src_clk_div = DIV_ROUND_UP(prate, rate); + rk_clrsetreg(&cru->pmu1_clksel_con[0], + SCLK_1X_FSPI1_SEL_MASK | + SCLK_1X_FSPI1_DIV_MASK, + (sel << SCLK_1X_FSPI1_SEL_SHIFT) | + ((src_clk_div - 1) << + SCLK_1X_FSPI1_DIV_SHIFT)); + break; + default: + return -ENOENT; + } + return rv1126b_mmc_get_clk(priv, clk_id); +} + +static ulong rv1126b_spi_get_clk(struct rv1126b_clk_priv *priv, ulong clk_id) +{ + struct rv1126b_cru *cru = priv->cru; + u32 sel, con, rate; + + switch (clk_id) { + case CLK_SPI0: + con = readl(&cru->clksel_con[50]); + sel = (con & CLK_SPI0_SEL_MASK) >> CLK_SPI0_SEL_SHIFT; + break; + case CLK_SPI1: + con = readl(&cru->clksel_con[50]); + sel = (con & CLK_SPI1_SEL_MASK) >> CLK_SPI1_SEL_SHIFT; + break; + default: + return -ENOENT; + } + if (sel == CLK_SPI0_SEL_200M) + rate = 200 * MHz; + else if (sel == CLK_SPI0_SEL_100M) + rate = 100 * MHz; + else if (sel == CLK_SPI0_SEL_50M) + rate = 50 * MHz; + else + rate = OSC_HZ; + + return rate; +} + +static ulong rv1126b_spi_set_clk(struct rv1126b_clk_priv *priv, + ulong clk_id, ulong rate) +{ + struct rv1126b_cru *cru = priv->cru; + int src_clk; + + if (rate >= 198 * MHz) + src_clk = CLK_SPI0_SEL_200M; + else if (rate >= 99 * MHz) + src_clk = CLK_SPI0_SEL_100M; + else if (rate >= 48 * MHz) + src_clk = CLK_SPI0_SEL_50M; + else + src_clk = CLK_SPI0_SEL_24M; + + switch (clk_id) { + case CLK_SPI0: + rk_clrsetreg(&cru->clksel_con[50], CLK_SPI0_SEL_MASK, + src_clk << CLK_SPI0_SEL_SHIFT); + break; + case CLK_SPI1: + rk_clrsetreg(&cru->clksel_con[50], CLK_SPI1_SEL_MASK, + src_clk << CLK_SPI1_SEL_SHIFT); + break; + default: + return -ENOENT; + } + + return rv1126b_spi_get_clk(priv, clk_id); +} + +static ulong rv1126b_pwm_get_clk(struct rv1126b_clk_priv *priv, ulong clk_id) +{ + struct rv1126b_cru *cru = priv->cru; + u32 sel, div, con; + + switch (clk_id) { + case CLK_PWM0: + con = readl(&cru->clksel_con[50]); + sel = (con & CLK_PWM0_SEL_MASK) >> CLK_PWM0_SEL_SHIFT; + break; + case CLK_PWM2: + con = readl(&cru->clksel_con[50]); + sel = (con & CLK_PWM2_SEL_MASK) >> CLK_PWM2_SEL_SHIFT; + break; + case CLK_PWM3: + con = readl(&cru->clksel_con[50]); + sel = (con & CLK_PWM3_SEL_MASK) >> CLK_PWM3_SEL_SHIFT; + break; + case CLK_PWM1: + con = readl(&cru->pmu_clksel_con[2]); + sel = (con & CLK_PWM1_SEL_MASK) >> CLK_PWM1_SEL_SHIFT; + div = (con & CLK_PWM1_DIV_MASK) >> + CLK_PWM1_DIV_SHIFT; + if (sel == CLK_PWM1_SEL_100M) + return DIV_TO_RATE(100 * MHz, div); + else if (sel == CLK_PWM1_SEL_RCOSC) + return DIV_TO_RATE(RC_OSC_HZ, div); + else + return DIV_TO_RATE(OSC_HZ, div); + default: + return -ENOENT; + } + + switch (sel) { + case CLK_PWM_SEL_100M: + return 100 * MHz; + case CLK_PWM_SEL_24M: + return OSC_HZ; + default: + return -ENOENT; + } +} + +static ulong rv1126b_pwm_set_clk(struct rv1126b_clk_priv *priv, + ulong clk_id, ulong rate) +{ + struct rv1126b_cru *cru = priv->cru; + int src_clk, src_clk_div, prate; + + if (rate >= 99 * MHz) + src_clk = CLK_PWM_SEL_100M; + else + src_clk = CLK_PWM_SEL_24M; + + switch (clk_id) { + case CLK_PWM0: + rk_clrsetreg(&cru->clksel_con[50], + CLK_PWM0_SEL_MASK, + src_clk << CLK_PWM0_SEL_SHIFT); + break; + case CLK_PWM2: + rk_clrsetreg(&cru->clksel_con[50], + CLK_PWM2_SEL_MASK, + src_clk << CLK_PWM2_SEL_SHIFT); + break; + case CLK_PWM3: + rk_clrsetreg(&cru->clksel_con[50], + CLK_PWM3_SEL_MASK, + src_clk << CLK_PWM3_SEL_SHIFT); + break; + case CLK_PWM1: + if ((OSC_HZ % rate) == 0) { + src_clk = CLK_PWM1_SEL_24M; + prate = OSC_HZ; + } else if ((100 * MHz % rate) == 0) { + src_clk = CLK_PWM1_SEL_100M; + prate = priv->cpll_hz; + } else { + src_clk = CLK_PWM1_SEL_RCOSC; + prate = RC_OSC_HZ; + } + src_clk_div = DIV_ROUND_UP(prate, rate); + rk_clrsetreg(&cru->pmu1_clksel_con[2], + CLK_PWM1_SEL_MASK | + CLK_PWM1_DIV_MASK, + (src_clk << CLK_PWM1_SEL_SHIFT) | + ((src_clk_div - 1) << + CLK_PWM1_DIV_SHIFT)); + break; + + default: + return -ENOENT; + } + + return rv1126b_pwm_get_clk(priv, clk_id); +} + +static ulong rv1126b_adc_get_clk(struct rv1126b_clk_priv *priv, ulong clk_id) +{ + struct rv1126b_cru *cru = priv->cru; + u32 sel, div, con; + + switch (clk_id) { + case CLK_SARADC0: + case CLK_SARADC0_SRC: + con = readl(&cru->clksel_con[63]); + sel = (con & CLK_SARADC0_SEL_MASK) >> CLK_SARADC0_SEL_SHIFT; + div = (con & CLK_SARADC0_DIV_MASK) >> + CLK_SARADC0_DIV_SHIFT; + break; + case CLK_SARADC1: + case CLK_SARADC1_SRC: + con = readl(&cru->clksel_con[63]); + sel = (con & CLK_SARADC1_SEL_MASK) >> CLK_SARADC1_SEL_SHIFT; + div = (con & CLK_SARADC1_DIV_MASK) >> + CLK_SARADC1_DIV_SHIFT; + break; + case CLK_SARADC2: + case CLK_SARADC2_SRC: + con = readl(&cru->clksel_con[63]); + sel = (con & CLK_SARADC2_SEL_MASK) >> CLK_SARADC2_SEL_SHIFT; + div = (con & CLK_SARADC2_DIV_MASK) >> + CLK_SARADC2_DIV_SHIFT; + break; + case CLK_TSADC: + case CLK_TSADC_PHYCTRL: + return OSC_HZ; + default: + return -ENOENT; + } + + if (sel == CLK_SARADC_SEL_200M) + return DIV_TO_RATE(200 * MHz, div); + else + return DIV_TO_RATE(OSC_HZ, div); +} + +static ulong rv1126b_adc_set_clk(struct rv1126b_clk_priv *priv, + ulong clk_id, ulong rate) +{ + struct rv1126b_cru *cru = priv->cru; + int src_clk_sel, src_clk_div, prate; + + if ((OSC_HZ % rate) == 0) { + src_clk_sel = CLK_SARADC_SEL_24M; + prate = OSC_HZ; + } else { + src_clk_sel = CLK_SARADC_SEL_200M; + prate = 200 * MHz; + } + src_clk_div = DIV_ROUND_UP(prate, rate); + + switch (clk_id) { + case CLK_SARADC0: + case CLK_SARADC0_SRC: + assert(src_clk_div - 1 <= 7); + rk_clrsetreg(&cru->clksel_con[63], + CLK_SARADC0_SEL_MASK | + CLK_SARADC0_DIV_MASK, + (src_clk_sel << CLK_SARADC0_SEL_SHIFT) | + ((src_clk_div - 1) << + CLK_SARADC0_DIV_SHIFT)); + break; + case CLK_SARADC1: + case CLK_SARADC1_SRC: + assert(src_clk_div - 1 <= 7); + rk_clrsetreg(&cru->clksel_con[63], + CLK_SARADC1_SEL_MASK | + CLK_SARADC1_DIV_MASK, + (src_clk_sel << CLK_SARADC1_SEL_SHIFT) | + ((src_clk_div - 1) << + CLK_SARADC1_DIV_SHIFT)); + break; + case CLK_SARADC2: + case CLK_SARADC2_SRC: + assert(src_clk_div - 1 <= 7); + rk_clrsetreg(&cru->clksel_con[63], + CLK_SARADC2_SEL_MASK | + CLK_SARADC2_DIV_MASK, + (src_clk_sel << CLK_SARADC2_SEL_SHIFT) | + ((src_clk_div - 1) << + CLK_SARADC2_DIV_SHIFT)); + break; + case CLK_TSADC: + case CLK_TSADC_PHYCTRL: + break; + default: + return -ENOENT; + } + return rv1126b_adc_get_clk(priv, clk_id); +} + +/* + * + * rational_best_approximation(31415, 10000, + * (1 << 8) - 1, (1 << 5) - 1, &n, &d); + * + * you may look at given_numerator as a fixed point number, + * with the fractional part size described in given_denominator. + * + * for theoretical background, see: + * http://en.wikipedia.org/wiki/Continued_fraction + */ +static void rational_best_approximation(unsigned long given_numerator, + unsigned long given_denominator, + unsigned long max_numerator, + unsigned long max_denominator, + unsigned long *best_numerator, + unsigned long *best_denominator) +{ + unsigned long n, d, n0, d0, n1, d1; + + n = given_numerator; + d = given_denominator; + n0 = 0; + d1 = 0; + n1 = 1; + d0 = 1; + for (;;) { + unsigned long t, a; + + if (n1 > max_numerator || d1 > max_denominator) { + n1 = n0; + d1 = d0; + break; + } + if (d == 0) + break; + t = d; + a = n / d; + d = n % d; + n = t; + t = n0 + a * n1; + n0 = n1; + n1 = t; + t = d0 + a * d1; + d0 = d1; + d1 = t; + } + *best_numerator = n1; + *best_denominator = d1; +} + +static ulong rv1126b_frac_get_rate(struct rv1126b_clk_priv *priv, ulong clk_id) +{ + struct rv1126b_cru *cru = priv->cru; + u32 reg, reg_h, src, con, p_rate; + unsigned long m, n, m_l, n_l, m_h, n_h; + + switch (clk_id) { + case CLK_CM_FRAC0: + con = readl(&cru->clksel_con[10]); + src = (con & CLK_CM_FRAC0_SRC_SEL_MASK) >> + CLK_CM_FRAC0_SRC_SEL_SHIFT; + reg = readl(&cru->clksel_con[25]); + reg_h = readl(&cru->clk_cm_frac0_div_h); + break; + case CLK_CM_FRAC1: + con = readl(&cru->clksel_con[10]); + src = (con & CLK_CM_FRAC1_SRC_SEL_MASK) >> + CLK_CM_FRAC1_SRC_SEL_SHIFT; + reg = readl(&cru->clksel_con[26]); + reg_h = readl(&cru->clk_cm_frac1_div_h); + break; + case CLK_CM_FRAC2: + con = readl(&cru->clksel_con[10]); + src = (con & CLK_CM_FRAC2_SRC_SEL_MASK) >> + CLK_CM_FRAC2_SRC_SEL_SHIFT; + reg = readl(&cru->clksel_con[27]); + reg_h = readl(&cru->clk_cm_frac2_div_h); + break; + case CLK_UART_FRAC0: + con = readl(&cru->clksel_con[10]); + src = (con & CLK_UART_FRAC0_SRC_SEL_MASK) >> + CLK_UART_FRAC0_SRC_SEL_SHIFT; + reg = readl(&cru->clksel_con[28]); + reg_h = readl(&cru->clk_uart_frac0_div_h); + break; + case CLK_UART_FRAC1: + con = readl(&cru->clksel_con[10]); + src = (con & CLK_UART_FRAC1_SRC_SEL_MASK) >> + CLK_UART_FRAC1_SRC_SEL_SHIFT; + reg = readl(&cru->clksel_con[29]); + reg_h = readl(&cru->clk_uart_frac1_div_h); + break; + case CLK_AUDIO_FRAC0: + con = readl(&cru->clksel_con[10]); + src = (con & CLK_AUDIO_FRAC0_SRC_SEL_MASK) >> + CLK_AUDIO_FRAC0_SRC_SEL_SHIFT; + reg = readl(&cru->clksel_con[30]); + reg_h = readl(&cru->clk_audio_frac0_div_h); + break; + case CLK_AUDIO_FRAC1: + con = readl(&cru->clksel_con[10]); + src = (con & CLK_AUDIO_FRAC1_SRC_SEL_MASK) >> + CLK_AUDIO_FRAC1_SRC_SEL_SHIFT; + reg = readl(&cru->clksel_con[31]); + reg_h = readl(&cru->clk_audio_frac1_div_h); + break; + + default: + return -ENOENT; + } + + switch (src) { + case CLK_FRAC_SRC_SEL_24M: + p_rate = OSC_HZ; + break; + case CLK_FRAC_SRC_SEL_GPLL: + p_rate = priv->gpll_hz; + break; + case CLK_FRAC_SRC_SEL_AUPLL: + p_rate = priv->aupll_hz; + break; + case CLK_FRAC_SRC_SEL_CPLL: + p_rate = priv->cpll_hz; + break; + default: + return -ENOENT; + } + + n_l = reg & CLK_FRAC_NUMERATOR_MASK; + n_l >>= CLK_FRAC_NUMERATOR_SHIFT; + m_l = reg & CLK_FRAC_DENOMINATOR_MASK; + m_l >>= CLK_FRAC_DENOMINATOR_SHIFT; + n_h = reg_h & CLK_FRAC_H_NUMERATOR_MASK; + n_h >>= CLK_FRAC_H_NUMERATOR_SHIFT; + m_h = reg_h & CLK_FRAC_H_DENOMINATOR_MASK; + m_h >>= CLK_FRAC_H_DENOMINATOR_SHIFT; + n = n_l | (n_h << 16); + m = m_l | (m_h << 16); + return p_rate * n / m; +} + +static ulong rv1126b_frac_set_rate(struct rv1126b_clk_priv *priv, + ulong clk_id, ulong rate) +{ + struct rv1126b_cru *cru = priv->cru; + u32 src, p_rate, val; + unsigned long m, n, m_l, n_l, m_h, n_h; + + if ((OSC_HZ % rate) == 0) { + src = CLK_FRAC_SRC_SEL_24M; + p_rate = OSC_HZ; + } else if ((priv->aupll_hz % rate) == 0) { + src = CLK_FRAC_SRC_SEL_AUPLL; + p_rate = priv->aupll_hz; + } else if ((priv->cpll_hz % rate) == 0) { + src = CLK_FRAC_SRC_SEL_CPLL; + p_rate = priv->cpll_hz; + } else { + src = CLK_FRAC_SRC_SEL_GPLL; + p_rate = priv->gpll_hz; + } + + rational_best_approximation(rate, p_rate, + GENMASK(24 - 1, 0), + GENMASK(24 - 1, 0), + &m, &n); + + if (m < 4 && m != 0) { + if (n % 2 == 0) + val = 1; + else + val = DIV_ROUND_UP(4, m); + + n *= val; + m *= val; + if (n > 0xffffff) + n = 0xffffff; + } + + n_l = n & 0xffff; + m_l = m & 0xffff; + n_h = (n & 0xff0000) >> 16; + m_h = (m & 0xff0000) >> 16; + + switch (clk_id) { + case CLK_CM_FRAC0: + rk_clrsetreg(&cru->clksel_con[10], + CLK_CM_FRAC0_SRC_SEL_MASK, + (src << CLK_CM_FRAC0_SRC_SEL_SHIFT)); + val = m_h << CLK_FRAC_H_NUMERATOR_SHIFT | n_h; + writel(val, &cru->clk_cm_frac0_div_h); + val = m_l << CLK_FRAC_NUMERATOR_SHIFT | n_l; + writel(val, &cru->clksel_con[25]); + break; + case CLK_CM_FRAC1: + rk_clrsetreg(&cru->clksel_con[10], + CLK_CM_FRAC1_SRC_SEL_MASK, + (src << CLK_CM_FRAC1_SRC_SEL_SHIFT)); + val = m_h << CLK_FRAC_H_NUMERATOR_SHIFT | n_h; + writel(val, &cru->clk_cm_frac1_div_h); + val = m_l << CLK_FRAC_NUMERATOR_SHIFT | n_l; + writel(val, &cru->clksel_con[26]); + break; + case CLK_CM_FRAC2: + rk_clrsetreg(&cru->clksel_con[10], + CLK_CM_FRAC2_SRC_SEL_MASK, + (src << CLK_CM_FRAC2_SRC_SEL_SHIFT)); + val = m_h << CLK_FRAC_H_NUMERATOR_SHIFT | n_h; + writel(val, &cru->clk_cm_frac2_div_h); + val = m_l << CLK_FRAC_NUMERATOR_SHIFT | n_l; + writel(val, &cru->clksel_con[27]); + break; + case CLK_UART_FRAC0: + rk_clrsetreg(&cru->clksel_con[10], + CLK_UART_FRAC0_SRC_SEL_MASK, + (src << CLK_UART_FRAC0_SRC_SEL_SHIFT)); + val = m_h << CLK_FRAC_H_NUMERATOR_SHIFT | n_h; + writel(val, &cru->clk_uart_frac0_div_h); + val = m_l << CLK_FRAC_NUMERATOR_SHIFT | n_l; + writel(val, &cru->clksel_con[28]); + break; + case CLK_UART_FRAC1: + rk_clrsetreg(&cru->clksel_con[10], + CLK_UART_FRAC1_SRC_SEL_MASK, + (src << CLK_UART_FRAC1_SRC_SEL_SHIFT)); + val = m_h << CLK_FRAC_H_NUMERATOR_SHIFT | n_h; + writel(val, &cru->clk_uart_frac1_div_h); + val = m_l << CLK_FRAC_NUMERATOR_SHIFT | n_l; + writel(val, &cru->clksel_con[29]); + break; + case CLK_AUDIO_FRAC0: + rk_clrsetreg(&cru->clksel_con[10], + CLK_AUDIO_FRAC0_SRC_SEL_MASK, + (src << CLK_AUDIO_FRAC0_SRC_SEL_SHIFT)); + val = m_h << CLK_FRAC_H_NUMERATOR_SHIFT | n_h; + writel(val, &cru->clk_audio_frac0_div_h); + val = m_l << CLK_FRAC_NUMERATOR_SHIFT | n_l; + writel(val, &cru->clksel_con[30]); + break; + case CLK_AUDIO_FRAC1: + rk_clrsetreg(&cru->clksel_con[10], + CLK_AUDIO_FRAC0_SRC_SEL_MASK, + (src << CLK_AUDIO_FRAC0_SRC_SEL_SHIFT)); + val = m_h << CLK_FRAC_H_NUMERATOR_SHIFT | n_h; + writel(val, &cru->clk_audio_frac1_div_h); + val = m_l << CLK_FRAC_NUMERATOR_SHIFT | n_l; + writel(val, &cru->clksel_con[31]); + break; + + default: + return -ENOENT; + } + + return rv1126b_frac_get_rate(priv, clk_id); +} + +static ulong rv1126b_uart_get_rate(struct rv1126b_clk_priv *priv, ulong clk_id) +{ + struct rv1126b_cru *cru = priv->cru; + u32 con, div, src, p_rate; + + switch (clk_id) { + case SCLK_UART0: + con = readl(&cru->pmu_clksel_con[3]); + src = (con & SCLK_UART0_SEL_MASK) >> SCLK_UART0_SEL_SHIFT; + if (src == SCLK_UART0_SEL_UART0_SRC) + return rv1126b_uart_get_rate(priv, SCLK_UART0_SRC); + else if (src == SCLK_UART0_SEL_UART0_SRC) + return RC_OSC_HZ; + else + return OSC_HZ; + case SCLK_UART0_SRC: + con = readl(&cru->clksel_con[12]); + src = (con & SCLK_UART0_SRC_SEL_MASK) >> + SCLK_UART0_SRC_SEL_SHIFT; + div = (con & SCLK_UART0_SRC_DIV_MASK) >> + SCLK_UART0_SRC_DIV_SHIFT; + break; + case SCLK_UART1: + con = readl(&cru->clksel_con[12]); + src = (con & SCLK_UART1_SEL_MASK) >> SCLK_UART1_SEL_SHIFT; + div = (con & SCLK_UART1_DIV_MASK) >> SCLK_UART1_DIV_SHIFT; + break; + case SCLK_UART2: + con = readl(&cru->clksel_con[13]); + src = (con & SCLK_UART2_SEL_MASK) >> SCLK_UART2_SEL_SHIFT; + div = (con & SCLK_UART2_DIV_MASK) >> SCLK_UART2_DIV_SHIFT; + break; + case SCLK_UART3: + con = readl(&cru->clksel_con[13]); + src = (con & SCLK_UART3_SEL_MASK) >> SCLK_UART3_SEL_SHIFT; + div = (con & SCLK_UART3_DIV_MASK) >> SCLK_UART3_DIV_SHIFT; + break; + case SCLK_UART4: + con = readl(&cru->clksel_con[14]); + src = (con & SCLK_UART4_SEL_MASK) >> SCLK_UART4_SEL_SHIFT; + div = (con & SCLK_UART4_DIV_MASK) >> SCLK_UART4_DIV_SHIFT; + break; + case SCLK_UART5: + con = readl(&cru->clksel_con[14]); + src = (con & SCLK_UART5_SEL_MASK) >> SCLK_UART5_SEL_SHIFT; + div = (con & SCLK_UART5_DIV_MASK) >> SCLK_UART5_DIV_SHIFT; + break; + case SCLK_UART6: + con = readl(&cru->clksel_con[15]); + src = (con & SCLK_UART6_SEL_MASK) >> SCLK_UART6_SEL_SHIFT; + div = (con & SCLK_UART6_DIV_MASK) >> SCLK_UART6_DIV_SHIFT; + break; + case SCLK_UART7: + con = readl(&cru->clksel_con[15]); + src = (con & SCLK_UART7_SEL_MASK) >> SCLK_UART7_SEL_SHIFT; + div = (con & SCLK_UART7_DIV_MASK) >> SCLK_UART7_DIV_SHIFT; + break; + + default: + return -ENOENT; + } + + switch (src) { + case SCLK_UART_SEL_OSC: + p_rate = OSC_HZ; + break; + case SCLK_UART_SEL_CM_FRAC0: + p_rate = rv1126b_frac_get_rate(priv, CLK_CM_FRAC0); + break; + case SCLK_UART_SEL_CM_FRAC1: + p_rate = rv1126b_frac_get_rate(priv, CLK_CM_FRAC1); + break; + case SCLK_UART_SEL_CM_FRAC2: + p_rate = rv1126b_frac_get_rate(priv, CLK_CM_FRAC2); + break; + case SCLK_UART_SEL_UART_FRAC0: + p_rate = rv1126b_frac_get_rate(priv, CLK_UART_FRAC0); + break; + case SCLK_UART_SEL_UART_FRAC1: + p_rate = rv1126b_frac_get_rate(priv, CLK_UART_FRAC1); + break; + default: + return -ENOENT; + } + + return DIV_TO_RATE(p_rate, div); +} + +static ulong rv1126b_uart_set_rate(struct rv1126b_clk_priv *priv, + ulong clk_id, ulong rate) +{ + struct rv1126b_cru *cru = priv->cru; + u32 uart_src, div, p_rate; + + if (rv1126b_frac_get_rate(priv, CLK_CM_FRAC0) % rate == 0) { + uart_src = SCLK_UART_SEL_CM_FRAC0; + p_rate = rv1126b_frac_get_rate(priv, CLK_CM_FRAC0); + } else if (rv1126b_frac_get_rate(priv, CLK_CM_FRAC1) % rate == 0) { + uart_src = SCLK_UART_SEL_CM_FRAC1; + p_rate = rv1126b_frac_get_rate(priv, CLK_CM_FRAC1); + } else if (rv1126b_frac_get_rate(priv, CLK_CM_FRAC2) % rate == 0) { + uart_src = SCLK_UART_SEL_CM_FRAC2; + p_rate = rv1126b_frac_get_rate(priv, CLK_CM_FRAC2); + } else if (rv1126b_frac_get_rate(priv, CLK_UART_FRAC0) % rate == 0) { + uart_src = SCLK_UART_SEL_UART_FRAC0; + p_rate = rv1126b_frac_get_rate(priv, CLK_UART_FRAC0); + } else if (rv1126b_frac_get_rate(priv, CLK_UART_FRAC1) % rate == 0) { + uart_src = SCLK_UART_SEL_UART_FRAC1; + p_rate = rv1126b_frac_get_rate(priv, CLK_UART_FRAC1); + } else { + uart_src = SCLK_UART_SEL_OSC; + p_rate = OSC_HZ; + } + + div = DIV_ROUND_UP(p_rate, rate); + + switch (clk_id) { + case SCLK_UART0: + if (rate == OSC_HZ) + uart_src = SCLK_UART0_SEL_OSC; + else if (rate == RC_OSC_HZ) + uart_src = SCLK_UART0_SEL_RCOSC; + else + uart_src = SCLK_UART0_SEL_UART0_SRC; + rk_clrsetreg(&cru->pmu_clksel_con[3], + SCLK_UART0_SEL_MASK, + uart_src << SCLK_UART0_SEL_SHIFT); + if (uart_src == SCLK_UART0_SEL_UART0_SRC) + rv1126b_uart_set_rate(priv, SCLK_UART0_SRC, rate); + break; + case SCLK_UART0_SRC: + rk_clrsetreg(&cru->clksel_con[12], + SCLK_UART0_SRC_SEL_MASK | + SCLK_UART0_SRC_DIV_MASK, + (uart_src << SCLK_UART0_SRC_SEL_SHIFT) | + ((div - 1) << + SCLK_UART0_SRC_DIV_SHIFT)); + break; + case SCLK_UART1: + rk_clrsetreg(&cru->clksel_con[12], + SCLK_UART1_SEL_MASK | + SCLK_UART1_DIV_MASK, + (uart_src << SCLK_UART1_SEL_SHIFT) | + ((div - 1) << + SCLK_UART1_DIV_SHIFT)); + break; + case SCLK_UART2: + rk_clrsetreg(&cru->clksel_con[13], + SCLK_UART2_SEL_MASK | + SCLK_UART2_DIV_MASK, + (uart_src << SCLK_UART2_SEL_SHIFT) | + ((div - 1) << + SCLK_UART2_DIV_SHIFT)); + break; + case SCLK_UART3: + rk_clrsetreg(&cru->clksel_con[13], + SCLK_UART3_SEL_MASK | + SCLK_UART3_DIV_MASK, + (uart_src << SCLK_UART3_SEL_SHIFT) | + ((div - 1) << + SCLK_UART3_DIV_SHIFT)); + break; + case SCLK_UART4: + rk_clrsetreg(&cru->clksel_con[14], + SCLK_UART4_SEL_MASK | + SCLK_UART4_DIV_MASK, + (uart_src << SCLK_UART4_SEL_SHIFT) | + ((div - 1) << + SCLK_UART4_DIV_SHIFT)); + break; + case SCLK_UART5: + rk_clrsetreg(&cru->clksel_con[14], + SCLK_UART5_SEL_MASK | + SCLK_UART5_DIV_MASK, + (uart_src << SCLK_UART5_SEL_SHIFT) | + ((div - 1) << + SCLK_UART5_DIV_SHIFT)); + break; + case SCLK_UART6: + rk_clrsetreg(&cru->clksel_con[15], + SCLK_UART6_SEL_MASK | + SCLK_UART6_DIV_MASK, + (uart_src << SCLK_UART6_SEL_SHIFT) | + ((div - 1) << + SCLK_UART6_DIV_SHIFT)); + break; + case SCLK_UART7: + rk_clrsetreg(&cru->clksel_con[15], + SCLK_UART7_SEL_MASK | + SCLK_UART7_DIV_MASK, + (uart_src << SCLK_UART7_SEL_SHIFT) | + ((div - 1) << + SCLK_UART7_DIV_SHIFT)); + break; + default: + return -ENOENT; + } + + return rv1126b_uart_get_rate(priv, clk_id); +} + +static ulong rv1126b_wdt_get_rate(struct rv1126b_clk_priv *priv, ulong clk_id) +{ + struct rv1126b_cru *cru = priv->cru; + u32 sel, con; + + switch (clk_id) { + case TCLK_WDT_NS_SRC: + case TCLK_WDT_NS: + con = readl(&cru->clksel_con[46]); + sel = (con & TCLK_WDT_NS_SEL_MASK) >> + TCLK_WDT_NS_SEL_SHIFT; + break; + case TCLK_WDT_S: + con = readl(&cru->clksel_con[46]); + sel = (con & TCLK_WDT_S_SEL_MASK) >> + TCLK_WDT_S_SEL_SHIFT; + break; + case TCLK_WDT_HPMCU: + con = readl(&cru->clksel_con[46]); + sel = (con & TCLK_WDT_HPMCU_SEL_MASK) >> + TCLK_WDT_HPMCU_SEL_SHIFT; + break; + case TCLK_WDT_LPMCU: + con = readl(&cru->pmu_clksel_con[3]); + sel = (con & TCLK_WDT_LPMCU_SEL_MASK) >> + TCLK_WDT_LPMCU_SEL_SHIFT; + if (sel == TCLK_WDT_LPMCU_SEL_100M) + return 100 * MHz; + else if (sel == TCLK_WDT_LPMCU_SEL_RCOSC) + return RC_OSC_HZ; + else if (sel == TCLK_WDT_LPMCU_SEL_OSC) + return OSC_HZ; + else + return 32768; + default: + return -ENOENT; + } + + if (sel == TCLK_WDT_SEL_100M) + return 100 * MHz; + else + return OSC_HZ; +} + +static ulong rv1126b_wdt_set_rate(struct rv1126b_clk_priv *priv, + ulong clk_id, ulong rate) +{ + struct rv1126b_cru *cru = priv->cru; + int src_clk_sel; + + if (rate == OSC_HZ) + src_clk_sel = TCLK_WDT_SEL_OSC; + else + src_clk_sel = TCLK_WDT_SEL_100M; + + switch (clk_id) { + case TCLK_WDT_NS_SRC: + rk_clrsetreg(&cru->clksel_con[46], + TCLK_WDT_NS_SEL_MASK, + (src_clk_sel << TCLK_WDT_NS_SEL_SHIFT)); + break; + case TCLK_WDT_S: + rk_clrsetreg(&cru->clksel_con[46], + TCLK_WDT_NS_SEL_MASK, + (src_clk_sel << TCLK_WDT_NS_SEL_SHIFT)); + break; + case TCLK_WDT_HPMCU: + rk_clrsetreg(&cru->clksel_con[46], + TCLK_WDT_HPMCU_SEL_MASK, + (src_clk_sel << TCLK_WDT_HPMCU_SEL_SHIFT)); + break; + case TCLK_WDT_LPMCU: + if (rate == OSC_HZ) + src_clk_sel = TCLK_WDT_LPMCU_SEL_OSC; + else if (rate == RC_OSC_HZ) + src_clk_sel = TCLK_WDT_LPMCU_SEL_RCOSC; + else if (rate == 1000000) + src_clk_sel = TCLK_WDT_LPMCU_SEL_100M; + else + src_clk_sel = TCLK_WDT_LPMCU_SEL_32K; + rk_clrsetreg(&cru->pmu_clksel_con[3], + TCLK_WDT_LPMCU_SEL_MASK, + (src_clk_sel << TCLK_WDT_LPMCU_SEL_SHIFT)); + break; + default: + return -ENOENT; + } + return rv1126b_wdt_get_rate(priv, clk_id); +} + +static ulong rv1126b_vop_get_rate(struct rv1126b_clk_priv *priv, ulong clk_id) +{ + struct rv1126b_cru *cru = priv->cru; + u32 sel, div, con, p_rate; + + switch (clk_id) { + case DCLK_VOP: + con = readl(&cru->clksel_con[43]); + sel = (con & DCLK_VOP_SEL_MASK) >> DCLK_VOP_SEL_SHIFT; + div = (con & DCLK_VOP_DIV_MASK) >> DCLK_VOP_DIV_SHIFT; + break; + default: + return -ENOENT; + } + if (sel == DCLK_VOP_SEL_CPLL) + p_rate = priv->cpll_hz; + else + p_rate = priv->gpll_hz; + + return DIV_TO_RATE(p_rate, div); +} + +static ulong rv1126b_vop_set_rate(struct rv1126b_clk_priv *priv, + ulong clk_id, ulong rate) +{ + struct rv1126b_cru *cru = priv->cru; + int src_clk, div, p_rate; + + if (!(priv->cpll_hz % rate)) { + src_clk = DCLK_VOP_SEL_CPLL; + p_rate = priv->cpll_hz; + } else { + src_clk = DCLK_VOP_SEL_GPLL; + p_rate = priv->gpll_hz; + } + + div = DIV_ROUND_UP(p_rate, rate); + switch (clk_id) { + case DCLK_VOP: + rk_clrsetreg(&cru->clksel_con[43], DCLK_VOP_SEL_MASK | DCLK_VOP_DIV_MASK, + (src_clk << DCLK_VOP_SEL_SHIFT) | + ((div - 1) << DCLK_VOP_DIV_SHIFT) ); + break; + default: + return -ENOENT; + } + + return rv1126b_vop_get_rate(priv, clk_id); +} + +static ulong rv1126b_clk_get_rate(struct clk *clk) +{ + struct rv1126b_clk_priv *priv = dev_get_priv(clk->dev); + ulong rate = 0; + + if (!priv->gpll_hz) { + printf("%s gpll=%lu\n", __func__, priv->gpll_hz); + return -ENOENT; + } + + switch (clk->id) { + case PLL_GPLL: + rate = rockchip_pll_get_rate(&rv1126b_pll_clks[GPLL], priv->cru, + GPLL); + break; + case PLL_AUPLL: + rate = rockchip_pll_get_rate(&rv1126b_pll_clks[AUPLL], + priv->cru, AUPLL); + break; + case PLL_CPLL: + rate = rockchip_pll_get_rate(&rv1126b_pll_clks[CPLL], priv->cru, + CPLL); + break; + case ACLK_PERI_ROOT: + case PCLK_PERI_ROOT: + case ACLK_TOP_ROOT: + case PCLK_TOP_ROOT: + case PCLK_BUS_ROOT: + case BUSCLK_PMU_SRC: + case ACLK_BUS_ROOT: + case HCLK_BUS_ROOT: + rate = rv1126b_peri_get_clk(priv, clk->id); + break; + case PCLK_RKCE: + case HCLK_NS_RKCE: + case ACLK_RKCE_SRC: + case ACLK_NSRKCE: + case CLK_PKA_RKCE_SRC: + case CLK_PKA_NSRKCE: + rate = rv1126b_crypto_get_clk(priv, clk->id); + break; + case CCLK_SDMMC0: + case HCLK_SDMMC0: + case CCLK_SDMMC1: + case HCLK_SDMMC1: + case CCLK_EMMC: + case HCLK_EMMC: + case SCLK_2X_FSPI0: + case HCLK_FSPI0: + case HCLK_XIP_FSPI0: + case SCLK_1X_FSPI1: + case HCLK_FSPI1: + case HCLK_XIP_FSPI1: + rate = rv1126b_mmc_get_clk(priv, clk->id); + break; + case CLK_I2C0: + case CLK_I2C1: + case CLK_I2C3: + case CLK_I2C4: + case CLK_I2C5: + case CLK_I2C2: + case CLK_I2C_BUS_SRC: + rate = rv1126b_i2c_get_clk(priv, clk->id); + break; + case CLK_SPI0: + case CLK_SPI1: + rate = rv1126b_spi_get_clk(priv, clk->id); + break; + case CLK_PWM0: + case CLK_PWM2: + case CLK_PWM3: + case CLK_PWM1: + rate = rv1126b_pwm_get_clk(priv, clk->id); + break; + case CLK_SARADC0: + case CLK_SARADC0_SRC: + case CLK_SARADC1: + case CLK_SARADC1_SRC: + case CLK_SARADC2: + case CLK_SARADC2_SRC: + case CLK_TSADC: + case CLK_TSADC_PHYCTRL: + rate = rv1126b_adc_get_clk(priv, clk->id); + break; + case CLK_CM_FRAC0: + case CLK_CM_FRAC1: + case CLK_CM_FRAC2: + case CLK_UART_FRAC0: + case CLK_UART_FRAC1: + case CLK_AUDIO_FRAC0: + case CLK_AUDIO_FRAC1: + rate = rv1126b_frac_get_rate(priv, clk->id); + break; + case SCLK_UART0: + case SCLK_UART0_SRC: + case SCLK_UART1: + case SCLK_UART2: + case SCLK_UART3: + case SCLK_UART4: + case SCLK_UART5: + case SCLK_UART6: + case SCLK_UART7: + rate = rv1126b_uart_get_rate(priv, clk->id); + break; + case DCLK_DECOM: + rate = 400 * MHz; + break; + case TCLK_WDT_NS_SRC: + case TCLK_WDT_NS: + case TCLK_WDT_S: + case TCLK_WDT_HPMCU: + case TCLK_WDT_LPMCU: + rate = rv1126b_wdt_get_rate(priv, clk->id); + break; + case DCLK_VOP: + rate = rv1126b_vop_get_rate(priv, clk->id); + break; + + default: + return -ENOENT; + } + + return rate; +}; + +static ulong rv1126b_clk_set_rate(struct clk *clk, ulong rate) +{ + struct rv1126b_clk_priv *priv = dev_get_priv(clk->dev); + ulong ret = 0; + + if (!priv->gpll_hz) { + printf("%s gpll=%lu\n", __func__, priv->gpll_hz); + return -ENOENT; + } + + switch (clk->id) { + case PLL_GPLL: + ret = rockchip_pll_set_rate(&rv1126b_pll_clks[GPLL], priv->cru, + GPLL, rate); + break; + case PLL_AUPLL: + ret = rockchip_pll_set_rate(&rv1126b_pll_clks[AUPLL], priv->cru, + AUPLL, rate); + break; + case PLL_CPLL: + ret = rockchip_pll_set_rate(&rv1126b_pll_clks[CPLL], priv->cru, + CPLL, rate); + break; + case ACLK_PERI_ROOT: + case PCLK_PERI_ROOT: + case ACLK_TOP_ROOT: + case PCLK_TOP_ROOT: + case PCLK_BUS_ROOT: + case BUSCLK_PMU_SRC: + case ACLK_BUS_ROOT: + case HCLK_BUS_ROOT: + ret = rv1126b_peri_set_clk(priv, clk->id, rate); + break; + case PCLK_RKCE: + case HCLK_NS_RKCE: + case ACLK_RKCE_SRC: + case ACLK_NSRKCE: + case CLK_PKA_RKCE_SRC: + case CLK_PKA_NSRKCE: + ret = rv1126b_crypto_set_clk(priv, clk->id, rate); + break; + case CCLK_SDMMC0: + case HCLK_SDMMC0: + case CCLK_SDMMC1: + case HCLK_SDMMC1: + case CCLK_EMMC: + case HCLK_EMMC: + case SCLK_2X_FSPI0: + case HCLK_FSPI0: + case HCLK_XIP_FSPI0: + case SCLK_1X_FSPI1: + case HCLK_FSPI1: + case HCLK_XIP_FSPI1: + ret = rv1126b_mmc_set_clk(priv, clk->id, rate); + break; + case CLK_I2C0: + case CLK_I2C1: + case CLK_I2C3: + case CLK_I2C4: + case CLK_I2C5: + case CLK_I2C2: + case CLK_I2C_BUS_SRC: + ret = rv1126b_i2c_set_clk(priv, clk->id, rate); + break; + case CLK_SPI0: + case CLK_SPI1: + ret = rv1126b_spi_set_clk(priv, clk->id, rate); + break; + case CLK_PWM0: + case CLK_PWM2: + case CLK_PWM3: + case CLK_PWM1: + ret = rv1126b_pwm_set_clk(priv, clk->id, rate); + break; + case CLK_SARADC0: + case CLK_SARADC0_SRC: + case CLK_SARADC1: + case CLK_SARADC1_SRC: + case CLK_SARADC2: + case CLK_SARADC2_SRC: + case CLK_TSADC: + case CLK_TSADC_PHYCTRL: + ret = rv1126b_adc_set_clk(priv, clk->id, rate); + break; + case CLK_CM_FRAC0: + case CLK_CM_FRAC1: + case CLK_CM_FRAC2: + case CLK_UART_FRAC0: + case CLK_UART_FRAC1: + case CLK_AUDIO_FRAC0: + case CLK_AUDIO_FRAC1: + ret = rv1126b_frac_set_rate(priv, clk->id, rate); + break; + case SCLK_UART0: + case SCLK_UART0_SRC: + case SCLK_UART1: + case SCLK_UART2: + case SCLK_UART3: + case SCLK_UART4: + case SCLK_UART5: + case SCLK_UART6: + case SCLK_UART7: + ret = rv1126b_uart_set_rate(priv, clk->id, rate); + break; + case DCLK_DECOM: + break; + case TCLK_WDT_NS_SRC: + case TCLK_WDT_NS: + case TCLK_WDT_S: + case TCLK_WDT_HPMCU: + case TCLK_WDT_LPMCU: + rate = rv1126b_wdt_set_rate(priv, clk->id, rate); + break; + case DCLK_VOP: + rate = rv1126b_vop_set_rate(priv, clk->id, rate); + break; + + default: + return -ENOENT; + } + + return ret; +}; + +static int rv1126b_clk_set_parent(struct clk *clk, struct clk *parent) +{ + switch (clk->id) { + default: + return -ENOENT; + } + + return 0; +} + +static struct clk_ops rv1126b_clk_ops = { + .get_rate = rv1126b_clk_get_rate, + .set_rate = rv1126b_clk_set_rate, +#if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA) + .set_parent = rv1126b_clk_set_parent, +#endif +}; + +static void rv1126b_clk_init(struct rv1126b_clk_priv *priv) +{ + int ret; + + priv->sync_kernel = false; + priv->gpll_hz = rockchip_pll_get_rate(&rv1126b_pll_clks[GPLL], + priv->cru, GPLL); + if (priv->gpll_hz != GPLL_HZ) { + ret = rockchip_pll_set_rate(&rv1126b_pll_clks[GPLL], priv->cru, + GPLL, GPLL_HZ); + if (!ret) + priv->gpll_hz = GPLL_HZ; + } + priv->aupll_hz = rockchip_pll_get_rate(&rv1126b_pll_clks[AUPLL], + priv->cru, AUPLL); + if (priv->aupll_hz != AUPLL_HZ) { + ret = rockchip_pll_set_rate(&rv1126b_pll_clks[AUPLL], priv->cru, + AUPLL, AUPLL_HZ); + if (!ret) + priv->aupll_hz = AUPLL_HZ; + } + priv->cpll_hz = rockchip_pll_get_rate(&rv1126b_pll_clks[CPLL], + priv->cru, CPLL); + if (priv->cpll_hz != CPLL_HZ) { + ret = rockchip_pll_set_rate(&rv1126b_pll_clks[CPLL], priv->cru, + CPLL, CPLL_HZ); + if (!ret) + priv->cpll_hz = CPLL_HZ; + } +} + +static int rv1126b_clk_probe(struct udevice *dev) +{ + struct rv1126b_clk_priv *priv = dev_get_priv(dev); + int ret; + +#ifdef CONFIG_SPL_BUILD + /* fix gpll and some clks modify by maskrom */ + writel(BITS_WITH_WMASK(9, 0x1fU, 5), + RV1126B_CRU_BASE + RV1126B_CLKSEL_CON(1)); + writel(BITS_WITH_WMASK(1, 0x1U, 15), + RV1126B_CRU_BASE + RV1126B_CLKSEL_CON(1)); + writel(BITS_WITH_WMASK(5, 0x1fU, 5), + RV1126B_CRU_BASE + RV1126B_CLKSEL_CON(2)); + writel(BITS_WITH_WMASK(1, 0x7U, 0), + RV1126B_CRU_BASE + RV1126B_CLKSEL_CON(60)); + writel(BITS_WITH_WMASK(1, 0x7U, 6), + RV1126B_CRU_BASE + RV1126B_PLL_CON(9)); + writel(BITS_WITH_WMASK(1, 0x3U, 4), + RV1126B_CRU_BASE + RV1126B_MODE_CON); +#endif + + rv1126b_clk_init(priv); + + /* Process 'assigned-{clocks/clock-parents/clock-rates}' properties */ + ret = clk_set_defaults(dev); + if (ret) + debug("%s clk_set_defaults failed %d\n", __func__, ret); + else + priv->sync_kernel = true; + return 0; +} + +static int rv1126b_clk_ofdata_to_platdata(struct udevice *dev) +{ + struct rv1126b_clk_priv *priv = dev_get_priv(dev); + + priv->cru = dev_read_addr_ptr(dev); + + return 0; +} + +static int rv1126b_clk_bind(struct udevice *dev) +{ + int ret; + struct udevice *sys_child, *sf_child; + struct sysreset_reg *priv; + struct softreset_reg *sf_priv; + + /* The reset driver does not have a device node, so bind it here */ + ret = device_bind_driver(dev, "rockchip_sysreset", "sysreset", + &sys_child); + if (ret) { + debug("Warning: No sysreset driver: ret=%d\n", ret); + } else { + priv = malloc(sizeof(struct sysreset_reg)); + priv->glb_srst_fst_value = offsetof(struct rv1126b_cru, + glb_srst_fst); + priv->glb_srst_snd_value = offsetof(struct rv1126b_cru, + glb_srst_snd); + sys_child->priv = priv; + } + + ret = device_bind_driver_to_node(dev, "rockchip_reset", "reset", + dev_ofnode(dev), &sf_child); + if (ret) { + debug("Warning: No rockchip reset driver: ret=%d\n", ret); + } else { + sf_priv = malloc(sizeof(struct softreset_reg)); + sf_priv->sf_reset_offset = offsetof(struct rv1126b_cru, + softrst_con[0]); + sf_priv->sf_reset_num = CLK_NR_SRST; + sf_child->priv = sf_priv; + } + + return 0; +} + +static const struct udevice_id rv1126b_clk_ids[] = { + { .compatible = "rockchip,rv1126b-cru" }, + { } +}; + +U_BOOT_DRIVER(rockchip_rv1126b_cru) = { + .name = "rockchip_rv1126b_cru", + .id = UCLASS_CLK, + .of_match = rv1126b_clk_ids, + .priv_auto_alloc_size = sizeof(struct rv1126b_clk_priv), + .ofdata_to_platdata = rv1126b_clk_ofdata_to_platdata, + .ops = &rv1126b_clk_ops, + .bind = rv1126b_clk_bind, + .probe = rv1126b_clk_probe, +}; + +#ifndef CONFIG_SPL_BUILD +/** + * soc_clk_dump() - Print clock frequencies + * Returns zero on success + * + * Implementation for the clk dump command. + */ +int soc_clk_dump(void) +{ + struct udevice *cru_dev; + struct rv1126b_clk_priv *priv; + const struct rv1126b_clk_info *clk_dump; + struct clk clk; + unsigned long clk_count = ARRAY_SIZE(clks_dump); + unsigned long rate; + int i, ret; + + ret = uclass_get_device_by_driver(UCLASS_CLK, + DM_GET_DRIVER(rockchip_rv1126b_cru), + &cru_dev); + if (ret) { + printf("%s failed to get cru device\n", __func__); + return ret; + } + + priv = dev_get_priv(cru_dev); + printf("CLK: (%s. arm: enter %lu KHz, init %lu KHz, kernel %lu%s)\n", + priv->sync_kernel ? "sync kernel" : "uboot", + priv->armclk_enter_hz / 1000, + priv->armclk_init_hz / 1000, + priv->set_armclk_rate ? priv->armclk_hz / 1000 : 0, + priv->set_armclk_rate ? " KHz" : "N/A"); + for (i = 0; i < clk_count; i++) { + clk_dump = &clks_dump[i]; + if (clk_dump->name) { + clk.id = clk_dump->id; + if (clk_dump->is_cru) + ret = clk_request(cru_dev, &clk); + if (ret < 0) + return ret; + + rate = clk_get_rate(&clk); + clk_free(&clk); + if (i == 0) { + if (rate < 0) + printf(" %s %s\n", clk_dump->name, + "unknown"); + else + printf(" %s %lu KHz\n", clk_dump->name, + rate / 1000); + } else { + if (rate < 0) + printf(" %s %s\n", clk_dump->name, + "unknown"); + else + printf(" %s %lu KHz\n", clk_dump->name, + rate / 1000); + } + } + } + + return 0; +} +#endif diff --git a/u-boot/drivers/crypto/crypto-uclass.c b/u-boot/drivers/crypto/crypto-uclass.c index 54e7daa683c..c6cf96544cc 100644 --- a/u-boot/drivers/crypto/crypto-uclass.c +++ b/u-boot/drivers/crypto/crypto-uclass.c @@ -4,6 +4,7 @@ */ #include +#include static const u8 null_hash_sha1_value[] = { 0xda, 0x39, 0xa3, 0xee, 0x5e, 0x6b, 0x4b, 0x0d, @@ -69,6 +70,14 @@ u32 crypto_algo_nbits(u32 algo) return 3072; case CRYPTO_RSA4096: return 4096; + case CRYPTO_SM2: + return 256; + case CRYPTO_ECC_192R1: + return 192; + case CRYPTO_ECC_224R1: + return 224; + case CRYPTO_ECC_256R1: + return 256; } printf("Unknown crypto algorithm: 0x%x\n", algo); @@ -264,6 +273,19 @@ int crypto_rsa_verify(struct udevice *dev, rsa_key *ctx, u8 *sign, u8 *output) return ops->rsa_verify(dev, ctx, sign, output); } +int crypto_ec_verify(struct udevice *dev, ec_key *ctx, u8 *hash, u32 hash_len, u8 *sign) +{ + const struct dm_crypto_ops *ops = device_get_ops(dev); + + if (!ops || !ops->ec_verify) + return -ENOSYS; + + if (!ctx || !ctx->x || !ctx->y || !ctx->y || !hash || hash_len == 0 || !sign) + return -EINVAL; + + return ops->ec_verify(dev, ctx, hash, hash_len, sign); +} + int crypto_cipher(struct udevice *dev, cipher_context *ctx, const u8 *in, u8 *out, u32 len, bool enc) { @@ -272,6 +294,9 @@ int crypto_cipher(struct udevice *dev, cipher_context *ctx, if (!ops || !ops->cipher_crypt) return -ENOSYS; + if (!ctx || !ctx->key || ctx->key_len == 0) + return -EINVAL; + return ops->cipher_crypt(dev, ctx, in, out, len, enc); } @@ -283,6 +308,9 @@ int crypto_mac(struct udevice *dev, cipher_context *ctx, if (!ops || !ops->cipher_mac) return -ENOSYS; + if (!ctx || !ctx->key || ctx->key_len == 0) + return -EINVAL; + return ops->cipher_mac(dev, ctx, in, len, tag); } @@ -295,9 +323,46 @@ int crypto_ae(struct udevice *dev, cipher_context *ctx, if (!ops || !ops->cipher_ae) return -ENOSYS; + if (!ctx || !ctx->key || ctx->key_len == 0) + return -EINVAL; + return ops->cipher_ae(dev, ctx, in, len, aad, aad_len, out, tag); } +int crypto_fw_cipher(struct udevice *dev, cipher_fw_context *ctx, + const u8 *in, u8 *out, u32 len, bool enc) +{ + const struct dm_crypto_ops *ops = device_get_ops(dev); + struct udevice *keylad_dev; + + if (!ops || !ops->cipher_fw_crypt) + return -ENOSYS; + + keylad_dev = keylad_get_device(); + if (!keylad_dev) { + printf("No keylad device found.\n"); + return -ENOSYS; + } + + if (keylad_transfer_fwkey(keylad_dev, crypto_keytable_addr(dev), + ctx->fw_keyid, ctx->key_len)) { + printf("Failed to transfer key from keylad.\n"); + return -ENOSYS; + } + + return ops->cipher_fw_crypt(dev, ctx, in, out, len, enc); +} + +ulong crypto_keytable_addr(struct udevice *dev) +{ + const struct dm_crypto_ops *ops = device_get_ops(dev); + + if (!ops || !ops->keytable_addr) + return 0; + + return ops->keytable_addr(dev); +} + UCLASS_DRIVER(crypto) = { .id = UCLASS_CRYPTO, .name = "crypto", diff --git a/u-boot/drivers/crypto/rockchip/Kconfig b/u-boot/drivers/crypto/rockchip/Kconfig index eb53f782ac4..9b29289cb21 100644 --- a/u-boot/drivers/crypto/rockchip/Kconfig +++ b/u-boot/drivers/crypto/rockchip/Kconfig @@ -1,6 +1,6 @@ config ROCKCHIP_RSA bool "Enable rockchip RSA support" - depends on ROCKCHIP_CRYPTO_V1 || ROCKCHIP_CRYPTO_V2 + depends on ROCKCHIP_CRYPTO_V1 || ROCKCHIP_CRYPTO_V2 || ROCKCHIP_CRYPTO_CE default y help This enable RSA512/RSA1024/RSA2048 algorithm support for @@ -8,15 +8,31 @@ config ROCKCHIP_RSA config SPL_ROCKCHIP_RSA bool "Enable rockchip RSA support in spl" - depends on SPL_ROCKCHIP_CRYPTO_V1 || SPL_ROCKCHIP_CRYPTO_V2 + depends on SPL_ROCKCHIP_CRYPTO_V1 || SPL_ROCKCHIP_CRYPTO_V2 || SPL_ROCKCHIP_CRYPTO_CE default y help This enable RSA512/RSA1024/RSA2048 algorithm support for rockchip crypto module. +config ROCKCHIP_EC + bool "Enable rockchip ECC/SM2 support" + depends on ROCKCHIP_CRYPTO_V1 || ROCKCHIP_CRYPTO_V2 || ROCKCHIP_CRYPTO_CE + default n + help + This enable SM2/ECC192R1/ECC224R1/ECC256R1 algorithm support for + rockchip crypto module. + +config SPL_ROCKCHIP_EC + bool "Enable rockchip ECC/SM2 support in spl" + depends on SPL_ROCKCHIP_CRYPTO_V1 || SPL_ROCKCHIP_CRYPTO_V2 || SPL_ROCKCHIP_CRYPTO_CE + default n + help + This enable SM2/ECC192R1/ECC224R1/ECC256R1 algorithm support for + rockchip crypto module. + config ROCKCHIP_CIPHER bool "Enable rockchip cipher support" - depends on ROCKCHIP_CRYPTO_V1 || ROCKCHIP_CRYPTO_V2 + depends on ROCKCHIP_CRYPTO_V1 || ROCKCHIP_CRYPTO_V2 || ROCKCHIP_CRYPTO_CE default n help This enable DES/AES/SM4 algorithm support for @@ -24,7 +40,7 @@ config ROCKCHIP_CIPHER config SPL_ROCKCHIP_CIPHER bool "Enable rockchip cipher support in spl" - depends on SPL_ROCKCHIP_CRYPTO_V1 || SPL_ROCKCHIP_CRYPTO_V2 + depends on SPL_ROCKCHIP_CRYPTO_V1 || SPL_ROCKCHIP_CRYPTO_V2 || SPL_ROCKCHIP_CRYPTO_CE default n help This enable DES/AES/SM4 algorithm support for @@ -32,7 +48,7 @@ config SPL_ROCKCHIP_CIPHER config ROCKCHIP_HMAC bool "Enable rockchip hmac support" - depends on ROCKCHIP_CRYPTO_V1 || ROCKCHIP_CRYPTO_V2 + depends on ROCKCHIP_CRYPTO_V1 || ROCKCHIP_CRYPTO_V2 || ROCKCHIP_CRYPTO_CE default n help This enable HMAC algorithm support for @@ -40,7 +56,7 @@ config ROCKCHIP_HMAC config SPL_ROCKCHIP_HMAC bool "Enable rockchip hmac support in spl" - depends on SPL_ROCKCHIP_CRYPTO_V1 || SPL_ROCKCHIP_CRYPTO_V2 + depends on SPL_ROCKCHIP_CRYPTO_V1 || SPL_ROCKCHIP_CRYPTO_V2 || SPL_ROCKCHIP_CRYPTO_CE default n help This enable HMAC algorithm support for @@ -73,3 +89,17 @@ config SPL_ROCKCHIP_CRYPTO_V2 help This enable MD5/SHA1/SHA256/RSA512/RSA1024/RSA2048 algorithm support for rockchip crypto v2 on platforms: px30/rk3326/rk1808/rk3308. + +config ROCKCHIP_CRYPTO_CE + bool "Enable rockchip crypto ce support" + depends on DM_CRYPTO + help + This enable MD5/SHA1/SHA256/RSA512/RSA1024/RSA2048/RSA3072/RSA4096 algorithm support for + rockchip crypto ce on platforms: rv1126b. + +config SPL_ROCKCHIP_CRYPTO_CE + bool "Enable rockchip crypto ce support in spl" + depends on SPL_DM_CRYPTO + help + This enable MD5/SHA1/SHA256/RSA512/RSA1024/RSA2048/RSA3072/RSA4096 algorithm support for + rockchip crypto ce on platforms: rv1126b. diff --git a/u-boot/drivers/crypto/rockchip/Makefile b/u-boot/drivers/crypto/rockchip/Makefile index 761d0862eb8..c415c2c6fad 100644 --- a/u-boot/drivers/crypto/rockchip/Makefile +++ b/u-boot/drivers/crypto/rockchip/Makefile @@ -4,9 +4,17 @@ # Copyright (c) 2019 Fuzhou Rockchip Electronics Co., Ltd # +crypto_common_rsa := crypto_v2_pka.o crypto_v2_util.o crypto_mpa.o +crypto_common_ec := crypto_ecc.o crypto_v2_util.o crypto_mpa.o + obj-$(CONFIG_$(SPL_TPL_)ROCKCHIP_CRYPTO_V1) += crypto_v1.o crypto_hash_cache.o obj-$(CONFIG_$(SPL_TPL_)ROCKCHIP_CRYPTO_V2) += crypto_v2.o crypto_hash_cache.o +obj-$(CONFIG_$(SPL_TPL_)ROCKCHIP_CRYPTO_CE) += crypto_ce.o rkce_core.o + +ifneq ($(filter y,$(CONFIG_$(SPL_TPL_)ROCKCHIP_CRYPTO_V2) $(CONFIG_$(SPL_TPL_)ROCKCHIP_CRYPTO_CE))$(CONFIG_$(SPL_TPL_)ROCKCHIP_RSA),) +obj-y += $(crypto_common_rsa) +endif -ifeq ($(CONFIG_$(SPL_TPL_)ROCKCHIP_CRYPTO_V2)$(CONFIG_$(SPL_TPL_)ROCKCHIP_RSA), yy) -obj-y += crypto_v2_pka.o crypto_v2_util.o +ifneq ($(filter y,$(CONFIG_$(SPL_TPL_)ROCKCHIP_CRYPTO_V2) $(CONFIG_$(SPL_TPL_)ROCKCHIP_CRYPTO_CE))$(CONFIG_$(SPL_TPL_)ROCKCHIP_EC),) +obj-y += $(crypto_common_ec) endif diff --git a/u-boot/drivers/crypto/rockchip/crypto_ce.c b/u-boot/drivers/crypto/rockchip/crypto_ce.c new file mode 100644 index 00000000000..cadfa0caf25 --- /dev/null +++ b/u-boot/drivers/crypto/rockchip/crypto_ce.c @@ -0,0 +1,1187 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) 2025 Rockchip Electronics Co., Ltd + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +fdt_addr_t crypto_base; + +#define ROUNDUP(size, alignment) round_up(size, alignment) + +#define RKCE_HASH_TIMEOUT_MS 1000 +#define RKCE_SYMM_TIMEOUT_MS 1000 + +struct rkce_sha_contex { + u32 length; + struct rkce_hash_td_ctrl ctrl; + struct rkce_hash_td *td; + struct rkce_hash_td_buf *td_buf; +}; + +struct rkce_cipher_contex { + struct rkce_symm_td *td; + struct rkce_symm_td *td_aad; + struct rkce_symm_td_buf *td_buf; +}; + +struct rockchip_crypto_priv { + fdt_addr_t reg; + u32 frequency; + char *clocks; + u32 *frequencies; + u32 nclocks; + u32 freq_nclocks; + u32 capability; + + void *hardware; + struct rkce_sha_contex *hash_ctx; +}; + +struct rockchip_map { + u32 crypto; + u32 rkce; +}; + +static const struct rockchip_map rk_hash_map[] = { + {CRYPTO_SM3, RKCE_HASH_ALGO_SM3}, + {CRYPTO_MD5, RKCE_HASH_ALGO_MD5}, + {CRYPTO_SHA1, RKCE_HASH_ALGO_SHA1}, + {CRYPTO_SHA256, RKCE_HASH_ALGO_SHA256}, + {CRYPTO_SHA512, RKCE_HASH_ALGO_SHA512}, +}; + +#if CONFIG_IS_ENABLED(ROCKCHIP_HMAC) +static const struct rockchip_map rk_hmac_map[] = { + {CRYPTO_HMAC_MD5, RKCE_HASH_ALGO_MD5}, + {CRYPTO_HMAC_SHA1, RKCE_HASH_ALGO_SHA1}, + {CRYPTO_HMAC_SHA256, RKCE_HASH_ALGO_SHA256}, + {CRYPTO_HMAC_SHA512, RKCE_HASH_ALGO_SHA512}, + {CRYPTO_HMAC_SM3, RKCE_HASH_ALGO_SM3}, +}; +#endif + +#if CONFIG_IS_ENABLED(ROCKCHIP_CIPHER) +static const struct rockchip_map rk_cipher_map[] = { + {CRYPTO_AES, RKCE_SYMM_ALGO_AES}, + {CRYPTO_DES, RKCE_SYMM_ALGO_TDES}, + {CRYPTO_SM4, RKCE_SYMM_ALGO_SM4}, +}; +#endif + +#if CONFIG_IS_ENABLED(ROCKCHIP_RSA) +static const struct rockchip_map rk_rsa_map[] = { + {CRYPTO_RSA512, RKCE_ASYM_ALGO_RSA}, + {CRYPTO_RSA1024, RKCE_ASYM_ALGO_RSA}, + {CRYPTO_RSA2048, RKCE_ASYM_ALGO_RSA}, + {CRYPTO_RSA3072, RKCE_ASYM_ALGO_RSA}, + {CRYPTO_RSA4096, RKCE_ASYM_ALGO_RSA}, +}; +#endif + +#if CONFIG_IS_ENABLED(ROCKCHIP_EC) +static const struct rockchip_map rk_ec_map[] = { + {CRYPTO_SM2, RKCE_ASYM_ALGO_SM2}, + {CRYPTO_ECC_192R1, RKCE_ASYM_ALGO_ECC_P192}, + {CRYPTO_ECC_224R1, RKCE_ASYM_ALGO_ECC_P224}, + {CRYPTO_ECC_256R1, RKCE_ASYM_ALGO_ECC_P256}, +}; +#endif + +static int rk_crypto_enable_clk(struct udevice *dev); +static int rk_crypto_disable_clk(struct udevice *dev); + +static void crypto_flush_cacheline(ulong addr, ulong size) +{ + ulong alignment = CONFIG_SYS_CACHELINE_SIZE; + ulong aligned_input, aligned_len; + + if (!addr || !size) + return; + + /* Must flush dcache before crypto DMA fetch data region */ + aligned_input = round_down(addr, alignment); + aligned_len = round_up(size + (addr - aligned_input), alignment); + flush_cache(aligned_input, aligned_len); +} + +static u32 rk_get_cemode(const struct rockchip_map *map, u32 num, u32 algo) +{ + u32 i, j; + struct { + const struct rockchip_map *map; + u32 num; + } map_tbl[] = { + {rk_hash_map, ARRAY_SIZE(rk_hash_map)}, +#if CONFIG_IS_ENABLED(ROCKCHIP_HMAC) + {rk_hmac_map, ARRAY_SIZE(rk_hmac_map)}, +#endif +#if CONFIG_IS_ENABLED(ROCKCHIP_CIPHER) + {rk_cipher_map, ARRAY_SIZE(rk_cipher_map)}, +#endif +#if CONFIG_IS_ENABLED(ROCKCHIP_RSA) + {rk_rsa_map, ARRAY_SIZE(rk_rsa_map)}, +#endif +#if CONFIG_IS_ENABLED(ROCKCHIP_EC) + {rk_ec_map, ARRAY_SIZE(rk_ec_map)}, +#endif + }; + + for (i = 0; i < ARRAY_SIZE(map_tbl); i++) { + const struct rockchip_map *map = map_tbl[i].map; + u32 num = map_tbl[i].num; + + for (j = 0; j < num; j++) { + if (map[j].crypto == algo) + return map[j].rkce; + } + } + + return 0; +} + +static u32 rk_load_map(struct rockchip_crypto_priv *priv, u32 algo_type, + const struct rockchip_map *map, u32 num) +{ + u32 i; + u32 capability = 0; + + for (i = 0; i < num; i++) { + if (rkce_hw_algo_valid(priv->hardware, algo_type, map[i].rkce, 0)) + capability |= map[i].crypto; + } + + return capability; +} + +static u32 rockchip_crypto_capability(struct udevice *dev) +{ + struct rockchip_crypto_priv *priv = dev_get_priv(dev); + u32 cap = 0; + + if (priv->capability) + return priv->capability; + + cap |= rk_load_map(priv, RKCE_ALGO_TYPE_HASH, + rk_hash_map, ARRAY_SIZE(rk_hash_map)); + +#if CONFIG_IS_ENABLED(ROCKCHIP_HMAC) + cap |= rk_load_map(priv, RKCE_ALGO_TYPE_HMAC, + rk_hmac_map, ARRAY_SIZE(rk_hmac_map)); +#endif + +#if CONFIG_IS_ENABLED(ROCKCHIP_CIPHER) + cap |= rk_load_map(priv, RKCE_ALGO_TYPE_CIPHER, + rk_cipher_map, ARRAY_SIZE(rk_cipher_map)); +#endif + +#if CONFIG_IS_ENABLED(ROCKCHIP_RSA) + cap |= rk_load_map(priv, RKCE_ALGO_TYPE_ASYM, rk_rsa_map, + ARRAY_SIZE(rk_rsa_map)); +#endif + +#if CONFIG_IS_ENABLED(ROCKCHIP_EC) + cap |= rk_load_map(priv, RKCE_ALGO_TYPE_ASYM, rk_ec_map, + ARRAY_SIZE(rk_ec_map)); +#endif + + return cap; +} + +static void *rkce_sha_ctx_alloc(void) +{ + struct rkce_sha_contex *hw_ctx; + + hw_ctx = malloc(sizeof(*hw_ctx)); + if (!hw_ctx) + return NULL; + + memset(hw_ctx, 0x00, sizeof(*hw_ctx)); + + hw_ctx->td = rkce_cma_alloc(sizeof(struct rkce_hash_td)); + if (!hw_ctx->td) + goto error; + + memset(hw_ctx->td, 0x00, sizeof(struct rkce_hash_td)); + + hw_ctx->td_buf = rkce_cma_alloc(sizeof(struct rkce_hash_td_buf)); + if (!hw_ctx->td_buf) + goto error; + + memset(hw_ctx->td_buf, 0x00, sizeof(struct rkce_hash_td_buf)); + + return hw_ctx; +error: + rkce_cma_free(hw_ctx->td); + rkce_cma_free(hw_ctx->td_buf); + free(hw_ctx); + + return NULL; +} + +static void rkce_sha_ctx_free(struct rkce_sha_contex *hw_ctx) +{ + if (!hw_ctx) + return; + + rkce_cma_free(hw_ctx->td); + rkce_cma_free(hw_ctx->td_buf); + free(hw_ctx); +} + +static int rk_sha_init(struct udevice *dev, sha_context *ctx, + u8 *key, u32 key_len, bool is_hmac) +{ + struct rockchip_crypto_priv *priv = dev_get_priv(dev); + struct rkce_sha_contex *hash_ctx = NULL; + u32 ce_algo = 0; + int ret = 0; + + if ((ctx->algo & priv->capability) == 0) + return -ENOSYS; + + if (priv->hash_ctx) + return -EFAULT; + + rkce_soft_reset(priv->hardware, RKCE_RESET_HASH); + + hash_ctx = rkce_sha_ctx_alloc(); + if (!hash_ctx) + return -ENOMEM; + + ret = rkce_init_hash_td(hash_ctx->td, hash_ctx->td_buf); + if (ret) + goto exit; + + ce_algo = rk_get_cemode(rk_hash_map, ARRAY_SIZE(rk_hash_map), ctx->algo); + + hash_ctx->ctrl.td_type = RKCE_TD_TYPE_HASH; + hash_ctx->ctrl.hw_pad_en = 1; + hash_ctx->ctrl.first_pkg = 1; + hash_ctx->ctrl.last_pkg = 0; + hash_ctx->ctrl.hash_algo = ce_algo; + hash_ctx->ctrl.hmac_en = is_hmac; + hash_ctx->ctrl.is_preemptible = 0; + hash_ctx->ctrl.int_en = 1; + + if (is_hmac) { + if (key_len > 64) { + ret = -EINVAL; + goto exit; + } + + memcpy(hash_ctx->td_buf->key, key, key_len); + } + + priv->hash_ctx = hash_ctx; +exit: + if (ret) { + rkce_sha_ctx_free(hash_ctx); + priv->hash_ctx = NULL; + } + + return ret; +} + +static int rk_sha_update(struct udevice *dev, u32 *input, u32 len, bool is_last) +{ + struct rockchip_crypto_priv *priv = dev_get_priv(dev); + struct rkce_sha_contex *hash_ctx; + struct rkce_hash_td *td; + int ret = 0; + + if (!priv->hash_ctx) + return -EINVAL; + + if (!is_last && (!input || len == 0)) + return -EINVAL; + + hash_ctx = priv->hash_ctx; + td = hash_ctx->td; + + td->ctrl = hash_ctx->ctrl; + memset(&td->sg, 0x00, sizeof(*td->sg)); + + if (hash_ctx->ctrl.first_pkg == 1) + hash_ctx->ctrl.first_pkg = 0; + + if (is_last) { + td->ctrl.last_pkg = 1; + } else { +#ifdef CONFIG_ARM64 + td->sg[0].src_addr_h = rkce_cma_virt2phys(input) >> 32; +#endif + td->sg[0].src_addr_l = rkce_cma_virt2phys(input) & 0xffffffff; + td->sg[0].src_size = len; + hash_ctx->length += len; + crypto_flush_cacheline((ulong)input, len); + } + + rk_crypto_enable_clk(dev); + + crypto_flush_cacheline((ulong)hash_ctx->td, sizeof(*hash_ctx->td)); + crypto_flush_cacheline((ulong)hash_ctx->td_buf, sizeof(*hash_ctx->td_buf)); + + ret = rkce_push_td_sync(priv->hardware, td, RKCE_HASH_TIMEOUT_MS); + if (ret) { + rkce_sha_ctx_free(hash_ctx); + priv->hash_ctx = NULL; + } + + rk_crypto_disable_clk(dev); + + return ret; +} + +static int rockchip_crypto_sha_init(struct udevice *dev, sha_context *ctx) +{ + return rk_sha_init(dev, ctx, NULL, 0, false); +} + +static int rockchip_crypto_sha_update(struct udevice *dev, u32 *input, u32 len) +{ + return rk_sha_update(dev, input, len, false); +} + +static int rockchip_crypto_sha_final(struct udevice *dev, sha_context *ctx, u8 *output) +{ + struct rockchip_crypto_priv *priv = dev_get_priv(dev); + struct rkce_sha_contex *hash_ctx = priv->hash_ctx; + u32 nbits; + int ret; + + if (!priv->hash_ctx) + return -EINVAL; + + nbits = crypto_algo_nbits(ctx->algo); + + if (hash_ctx->length != ctx->length) { + printf("total length(0x%08x) != init length(0x%08x)!\n", + hash_ctx->length, ctx->length); + ret = -EIO; + goto exit; + } + + ret = rk_sha_update(dev, NULL, 0, true); + if (ret == 0) + memcpy(output, hash_ctx->td_buf->hash, BITS2BYTE(nbits)); + +exit: + rkce_sha_ctx_free(hash_ctx); + priv->hash_ctx = NULL; + + return ret; +} + +#if CONFIG_IS_ENABLED(ROCKCHIP_HMAC) +static int rockchip_crypto_hmac_init(struct udevice *dev, sha_context *ctx, u8 *key, u32 key_len) +{ + return rk_sha_init(dev, ctx, key, key_len, true); +} + +static int rockchip_crypto_hmac_update(struct udevice *dev, u32 *input, u32 len) +{ + return rockchip_crypto_sha_update(dev, input, len); +} + +static int rockchip_crypto_hmac_final(struct udevice *dev, sha_context *ctx, u8 *output) +{ + return rockchip_crypto_sha_final(dev, ctx, output); +} +#endif + +#if CONFIG_IS_ENABLED(ROCKCHIP_CIPHER) + +static int hw_crypto_ccm128_setiv(u8 *iv_buf, u8 *nonce, u32 nlen, u32 mlen) +{ + u32 L = iv_buf[0] & 7; /* the L parameter */ + + if (nlen < (14 - L)) + return -1; /* nonce is too short */ + + if (sizeof(mlen) == 8 && L >= 3) { + iv_buf[8] = mlen >> (56 % (sizeof(mlen) * 8)); + iv_buf[9] = mlen >> (48 % (sizeof(mlen) * 8)); + iv_buf[10] = mlen >> (40 % (sizeof(mlen) * 8)); + iv_buf[11] = mlen >> (32 % (sizeof(mlen) * 8)); + } + + iv_buf[12] = mlen >> 24; + iv_buf[13] = mlen >> 16; + iv_buf[14] = mlen >> 8; + iv_buf[15] = mlen; + + iv_buf[0] &= ~0x40; /* clear aad flag */ + memcpy(&iv_buf[1], nonce, 14 - L); + + return 0; +} + +static void hw_get_ccm_aad_padding(u32 aad_len, u8 *padding, u32 *padding_size) +{ + u32 i = 0; + + if (aad_len == 0) { + *padding_size = 0; + return; + } + + if (aad_len < (0x10000 - 0x100)) { + i = 2; + } else if (sizeof(aad_len) == 8 && + aad_len >= (size_t)1 << (32 % (sizeof(aad_len) * 8))) { + i = 10; + } else { + i = 6; + } + + if (i == 2) { + padding[0] = aad_len >> 8; + padding[1] = aad_len; + } else if (i == 10) { + padding[0] = 0xFF; + padding[1] = 0xFF; + padding[2] = aad_len >> (56 % (sizeof(aad_len) * 8)); + padding[3] = aad_len >> (48 % (sizeof(aad_len) * 8)); + padding[4] = aad_len >> (40 % (sizeof(aad_len) * 8)); + padding[5] = aad_len >> (32 % (sizeof(aad_len) * 8)); + padding[6] = aad_len >> 24; + padding[7] = aad_len >> 16; + padding[8] = aad_len >> 8; + padding[9] = aad_len; + } else { + padding[0] = 0xFF; + padding[1] = 0xFE; + padding[2] = aad_len >> 24; + padding[3] = aad_len >> 16; + padding[4] = aad_len >> 8; + } + + *padding_size = i; +} + +static int hw_compose_ccm_aad_iv(u8 *aad_iv, u32 data_len, + u32 aad_len, u32 tag_size) +{ + u32 L; /* the L parameter */ + u8 nonce[AES_BLOCK_SIZE]; + + L = aad_iv[0] & 7; + aad_iv[0] |= ((u8)(((tag_size - 2) / 2) & 7) << 3); + + if (sizeof(data_len) == 8 && L >= 3) { + aad_iv[8] = data_len >> (56 % (sizeof(data_len) * 8)); + aad_iv[9] = data_len >> (48 % (sizeof(data_len) * 8)); + aad_iv[10] = data_len >> (40 % (sizeof(data_len) * 8)); + aad_iv[11] = data_len >> (32 % (sizeof(data_len) * 8)); + } + + /* save nonce */ + memcpy(nonce, &aad_iv[1], 14 - L); + + aad_iv[12] = data_len >> 24; + aad_iv[13] = data_len >> 16; + aad_iv[14] = data_len >> 8; + aad_iv[15] = data_len; + + /* restore nonce */ + memcpy(&aad_iv[1], nonce, 14 - L); + + aad_iv[0] &= ~0x40; /* clear Adata flag */ + + if (aad_len) + aad_iv[0] |= 0x40; //set aad flag + + return 0; +} + +static void rkce_destroy_ccm_aad(u8 *new_aad) +{ + rkce_cma_free(new_aad); +} + +static int rkce_build_ccm_aad(const u8 *aad, u32 aad_len, u32 data_len, + u8 *iv, u32 iv_len, + u8 **new_aad, u32 *new_aad_len, + u8 *new_iv, u32 *new_iv_len) +{ + int ret = -RKCE_INVAL; + u32 L; + u8 nonce[AES_BLOCK_SIZE]; + u8 pad[AES_BLOCK_SIZE]; + u32 pad_size = 0; + u32 tag_len = AES_BLOCK_SIZE; + u8 *aad_tmp = NULL; + u32 aad_tmp_len = 0; + + memset(nonce, 0x00, sizeof(nonce)); + + L = 15 - iv_len; + nonce[0] = (L - 1) & 7; + ret = hw_crypto_ccm128_setiv(nonce, (u8 *)iv, iv_len, 0); + if (ret) + return ret; + + memcpy(new_iv, nonce, sizeof(nonce)); + *new_iv_len = sizeof(nonce); + + memset(pad, 0x00, sizeof(pad)); + hw_get_ccm_aad_padding(aad_len, pad, &pad_size); + + aad_tmp_len = aad_len + AES_BLOCK_SIZE + pad_size; + aad_tmp_len = ROUNDUP(aad_tmp_len, AES_BLOCK_SIZE); + + aad_tmp = rkce_cma_alloc(aad_tmp_len); + if (!aad_tmp) { + ret = -RKCE_NOMEM; + goto exit; + } + + /* clear last block */ + memset(aad_tmp + aad_tmp_len - AES_BLOCK_SIZE, 0x00, AES_BLOCK_SIZE); + memcpy(aad_tmp, nonce, sizeof(nonce)); + hw_compose_ccm_aad_iv(aad_tmp, data_len, aad_len, tag_len); + memcpy(aad_tmp + AES_BLOCK_SIZE, pad, pad_size); + + memcpy(aad_tmp + AES_BLOCK_SIZE + pad_size, aad, aad_len); + + *new_aad = aad_tmp; + *new_aad_len = aad_tmp_len; + +exit: + return ret; +} + +static void *rkce_cipher_ctx_alloc(void) +{ + struct rkce_cipher_contex *hw_ctx; + + hw_ctx = malloc(sizeof(*hw_ctx)); + if (!hw_ctx) + return NULL; + + hw_ctx->td = rkce_cma_alloc(sizeof(struct rkce_symm_td)); + if (!hw_ctx->td) + goto error; + + memset(hw_ctx->td, 0x00, sizeof(struct rkce_symm_td)); + + hw_ctx->td_aad = rkce_cma_alloc(sizeof(struct rkce_symm_td)); + if (!hw_ctx->td_aad) + goto error; + + memset(hw_ctx->td_aad, 0x00, sizeof(struct rkce_symm_td)); + + hw_ctx->td_buf = rkce_cma_alloc(sizeof(struct rkce_symm_td_buf)); + if (!hw_ctx->td_buf) + goto error; + + memset(hw_ctx->td_buf, 0x00, sizeof(struct rkce_symm_td_buf)); + + return hw_ctx; +error: + rkce_cma_free(hw_ctx->td); + rkce_cma_free(hw_ctx->td_aad); + rkce_cma_free(hw_ctx->td_buf); + free(hw_ctx); + + return NULL; +} + +static void rkce_cipher_ctx_free(struct rkce_cipher_contex *hw_ctx) +{ + if (!hw_ctx) + return; + + rkce_cma_free(hw_ctx->td); + rkce_cma_free(hw_ctx->td_aad); + rkce_cma_free(hw_ctx->td_buf); + free(hw_ctx); +} + +static void crypto_invalidate_cacheline(u32 addr, u32 size) +{ + ulong alignment = CONFIG_SYS_CACHELINE_SIZE; + ulong aligned_input, aligned_len; + + if (!addr || !size) + return; + + /* Must invalidate dcache after crypto DMA write data region */ + aligned_input = round_down(addr, alignment); + aligned_len = round_up(size + (addr - aligned_input), alignment); + invalidate_dcache_range(aligned_input, aligned_input + aligned_len); +} + +static const struct rockchip_map rk_cipher_algo_map[] = { + {RK_MODE_ECB, RKCE_SYMM_MODE_ECB}, + {RK_MODE_CBC, RKCE_SYMM_MODE_CBC}, + {RK_MODE_CTS, RKCE_SYMM_MODE_CTS}, + {RK_MODE_CTR, RKCE_SYMM_MODE_CTR}, + {RK_MODE_CFB, RKCE_SYMM_MODE_CFB}, + {RK_MODE_OFB, RKCE_SYMM_MODE_OFB}, + {RK_MODE_XTS, RKCE_SYMM_MODE_XTS}, + {RK_MODE_CCM, RKCE_SYMM_MODE_CCM}, + {RK_MODE_GCM, RKCE_SYMM_MODE_GCM}, + {RK_MODE_CMAC, RKCE_SYMM_MODE_CMAC}, + {RK_MODE_CBC_MAC, RKCE_SYMM_MODE_CBC_MAC}, +}; + +static int rk_get_cipher_cemode(u32 algo, u32 mode, u32 *ce_algo, u32 *ce_mode) +{ + u32 i; + + switch (algo) { + case CRYPTO_DES: + *ce_algo = RKCE_SYMM_ALGO_TDES; + break; + case CRYPTO_AES: + *ce_algo = RKCE_SYMM_ALGO_AES; + break; + case CRYPTO_SM4: + *ce_algo = RKCE_SYMM_ALGO_SM4; + break; + default: + return -EINVAL; + } + + for (i = 0; i < ARRAY_SIZE(rk_cipher_algo_map); i++) { + if (mode == rk_cipher_algo_map[i].crypto) { + *ce_mode = rk_cipher_algo_map[i].rkce; + return 0; + } + } + + return -EINVAL; +} + +u32 rk_get_td_keysize(u32 ce_algo, u32 ce_mode, u32 key_len) +{ + u32 key_size = 0; + + if (ce_algo == RKCE_SYMM_ALGO_AES) { + if (key_len == AES_KEYSIZE_128) + key_size = RKCE_KEY_AES_128; + else if (key_len == AES_KEYSIZE_192) + key_size = RKCE_KEY_AES_192; + else if (key_len == AES_KEYSIZE_256) + key_size = RKCE_KEY_AES_256; + else + ; + } + + return key_size; +} + +int rk_set_symm_td_buf_key(struct rkce_symm_td_buf *td_buf, + u32 ce_algo, u32 ce_mode, cipher_context *ctx) +{ + memset(td_buf->key1, 0x00, sizeof(td_buf->key1)); + memset(td_buf->key2, 0x00, sizeof(td_buf->key2)); + + if (ce_mode == RKCE_SYMM_MODE_XTS) { + memcpy(td_buf->key1, ctx->key, ctx->key_len); + memcpy(td_buf->key2, ctx->twk_key, ctx->key_len); + } else { + memcpy(td_buf->key1, ctx->key, ctx->key_len); + } + + if (ctx->key_len == DES_KEYSIZE * 2 && + (ce_algo == RKCE_SYMM_ALGO_DES || ce_algo == RKCE_SYMM_ALGO_TDES)) + memcpy(td_buf->key1 + DES_KEYSIZE * 2, td_buf->key1, DES_KEYSIZE); + + return 0; +} + +int rk_set_symm_td_sg(struct rkce_symm_td *td, + const u8 *in, u32 in_len, u8 *out, u32 out_len) +{ + memset(td->sg, 0x00, sizeof(td->sg)); + +#ifdef CONFIG_ARM64 + td->sg[0].src_addr_h = rkce_cma_virt2phys(in) >> 32; +#endif + td->sg[0].src_addr_l = rkce_cma_virt2phys(in) & 0xffffffff; + td->sg[0].src_size = in_len; + + if (out && out_len) { +#ifdef CONFIG_ARM64 + td->sg[0].dst_addr_h = rkce_cma_virt2phys(out) >> 32; +#endif + td->sg[0].dst_addr_l = rkce_cma_virt2phys(out) & 0xffffffff; + td->sg[0].dst_size = out_len; + } + + td->next_task = 0; + + return 0; +} + +static int rk_crypto_cipher(struct udevice *dev, cipher_context *ctx, + const u8 *in, u8 *out, u32 len, bool enc, + const u8 *aad, u32 aad_len, u8 *tag) +{ + struct rockchip_crypto_priv *priv = dev_get_priv(dev); + struct rkce_cipher_contex *hw_ctx = NULL; + u32 ce_algo = 0, ce_mode = 0; + int ret = 0; + + rkce_soft_reset(priv->hardware, RKCE_RESET_SYMM); + + ret = rk_get_cipher_cemode(ctx->algo, ctx->mode, &ce_algo, &ce_mode); + if (ret) + return ret; + + hw_ctx = rkce_cipher_ctx_alloc(); + if (!hw_ctx) + return -ENOMEM; + + rkce_init_symm_td(hw_ctx->td, hw_ctx->td_buf); + + hw_ctx->td->ctrl.td_type = RKCE_TD_TYPE_SYMM; + hw_ctx->td->ctrl.is_dec = !enc; + hw_ctx->td->ctrl.symm_algo = ce_algo; + hw_ctx->td->ctrl.symm_mode = ce_mode; + hw_ctx->td->ctrl.key_size = rk_get_td_keysize(ce_algo, ce_mode, ctx->key_len); + hw_ctx->td->ctrl.first_pkg = 1; + hw_ctx->td->ctrl.last_pkg = 1; + hw_ctx->td->ctrl.int_en = 1; + + memcpy(hw_ctx->td_buf->iv, ctx->iv, ctx->iv_len); + hw_ctx->td->ctrl.iv_len = ctx->iv_len; + + ret = rk_set_symm_td_buf_key(hw_ctx->td_buf, ce_algo, ce_mode, ctx); + if (ret) + goto exit; + + ret = rk_set_symm_td_sg(hw_ctx->td, in, len, out, len); + if (ret) + goto exit; + + if (ce_mode == RKCE_SYMM_MODE_CCM) { + u8 *new_aad = NULL; + u32 new_aad_len = 0, new_iv_len = 0; + + rkce_init_symm_td(hw_ctx->td_aad, hw_ctx->td_buf); + + ret = rkce_build_ccm_aad(aad, aad_len, len, + hw_ctx->td_buf->iv, ctx->iv_len, + &new_aad, &new_aad_len, + hw_ctx->td_buf->iv, &new_iv_len); + if (ret) + goto exit; + + ret = rk_set_symm_td_sg(hw_ctx->td_aad, new_aad, new_aad_len, NULL, 0); + if (ret) + goto exit; + + hw_ctx->td->ctrl.iv_len = new_iv_len; + + hw_ctx->td_buf->gcm_len.aad_len_l = new_aad_len; + + hw_ctx->td_aad->ctrl = hw_ctx->td->ctrl; + hw_ctx->td_aad->ctrl.is_aad = 1; + + crypto_flush_cacheline((ulong)hw_ctx->td_aad, sizeof(*hw_ctx->td_aad)); + crypto_flush_cacheline((ulong)hw_ctx->td_buf, sizeof(*hw_ctx->td_buf)); + crypto_flush_cacheline((ulong)new_aad, new_aad_len); + + rk_crypto_enable_clk(dev); + + ret = rkce_push_td_sync(priv->hardware, hw_ctx->td_aad, RKCE_SYMM_TIMEOUT_MS); + + rk_crypto_disable_clk(dev); + + rkce_destroy_ccm_aad(new_aad); + + if (ret) { + printf("CCM calc aad data failed.\n"); + goto exit; + } + } else if (ce_mode == RKCE_SYMM_MODE_GCM) { + rkce_init_symm_td(hw_ctx->td_aad, hw_ctx->td_buf); + + ret = rk_set_symm_td_sg(hw_ctx->td_aad, aad, aad_len, NULL, 0); + if (ret) + goto exit; + + hw_ctx->td_buf->gcm_len.aad_len_l = aad_len; + hw_ctx->td_buf->gcm_len.pc_len_l = len; + + hw_ctx->td_aad->ctrl = hw_ctx->td->ctrl; + hw_ctx->td_aad->ctrl.is_aad = 1; + + crypto_flush_cacheline((ulong)hw_ctx->td_aad, sizeof(*hw_ctx->td_aad)); + crypto_flush_cacheline((ulong)hw_ctx->td_buf, sizeof(*hw_ctx->td_buf)); + crypto_flush_cacheline((ulong)aad, aad_len); + + rk_crypto_enable_clk(dev); + + ret = rkce_push_td_sync(priv->hardware, hw_ctx->td_aad, RKCE_SYMM_TIMEOUT_MS); + + rk_crypto_disable_clk(dev); + if (ret) { + printf("GCM calc aad data failed.\n"); + goto exit; + } + } + + crypto_flush_cacheline((ulong)hw_ctx->td, sizeof(*hw_ctx->td)); + crypto_flush_cacheline((ulong)hw_ctx->td_buf, sizeof(*hw_ctx->td_buf)); + crypto_flush_cacheline((ulong)in, len); + crypto_invalidate_cacheline((ulong)out, len); + + rk_crypto_enable_clk(dev); + + ret = rkce_push_td_sync(priv->hardware, hw_ctx->td, RKCE_SYMM_TIMEOUT_MS); + + crypto_invalidate_cacheline((ulong)out, len); + + rk_crypto_disable_clk(dev); + + if (tag) + memcpy(tag, hw_ctx->td_buf->tag, sizeof(hw_ctx->td_buf->tag)); +exit: + rkce_cipher_ctx_free(hw_ctx); + + return ret; +} + +static int rockchip_crypto_cipher(struct udevice *dev, cipher_context *ctx, + const u8 *in, u8 *out, u32 len, bool enc) +{ + return rk_crypto_cipher(dev, ctx, in, out, len, enc, NULL, 0, NULL); +} + +static int rockchip_crypto_mac(struct udevice *dev, cipher_context *ctx, + const u8 *in, u32 len, u8 *tag) +{ + return rk_crypto_cipher(dev, ctx, in, NULL, len, true, NULL, 0, tag); +} + +static int rockchip_crypto_ae(struct udevice *dev, cipher_context *ctx, + const u8 *in, u32 len, const u8 *aad, u32 aad_len, + u8 *out, u8 *tag) +{ + return rk_crypto_cipher(dev, ctx, in, out, len, true, aad, aad_len, tag); +} + +#endif + +#if CONFIG_IS_ENABLED(ROCKCHIP_RSA) +static int rockchip_crypto_rsa_verify(struct udevice *dev, rsa_key *ctx, + u8 *sign, u8 *output) +{ + struct mpa_num *mpa_m = NULL, *mpa_e = NULL, *mpa_n = NULL; + struct mpa_num *mpa_c = NULL, *mpa_result = NULL; + u32 n_bits, n_words; + int ret; + + if (!ctx) + return -EINVAL; + + if (ctx->algo != CRYPTO_RSA512 && + ctx->algo != CRYPTO_RSA1024 && + ctx->algo != CRYPTO_RSA2048 && + ctx->algo != CRYPTO_RSA3072 && + ctx->algo != CRYPTO_RSA4096) + return -EINVAL; + + n_bits = crypto_algo_nbits(ctx->algo); + n_words = BITS2WORD(n_bits); + + ret = rk_mpa_alloc(&mpa_m, sign, n_words); + if (ret) + goto exit; + + ret = rk_mpa_alloc(&mpa_e, ctx->e, n_words); + if (ret) + goto exit; + + ret = rk_mpa_alloc(&mpa_n, ctx->n, n_words); + if (ret) + goto exit; + + if (ctx->c) { + ret = rk_mpa_alloc(&mpa_c, ctx->c, n_words); + if (ret) + goto exit; + } + + ret = rk_mpa_alloc(&mpa_result, NULL, n_words); + if (ret) + goto exit; + + rk_crypto_enable_clk(dev); + ret = rk_exptmod_np(mpa_m, mpa_e, mpa_n, mpa_c, mpa_result); + if (!ret) + memcpy(output, mpa_result->d, BITS2BYTE(n_bits)); + rk_crypto_disable_clk(dev); + +exit: + rk_mpa_free(&mpa_m); + rk_mpa_free(&mpa_e); + rk_mpa_free(&mpa_n); + rk_mpa_free(&mpa_c); + rk_mpa_free(&mpa_result); + + return ret; +} +#endif + +#if CONFIG_IS_ENABLED(ROCKCHIP_EC) +static int rockchip_crypto_ec_verify(struct udevice *dev, ec_key *ctx, + u8 *hash, u32 hash_len, u8 *sign) +{ + struct mpa_num *bn_sign = NULL; + struct rk_ecp_point point_P, point_sign; + u32 n_bits, n_words; + int ret; + + if (!ctx) + return -EINVAL; + + if (ctx->algo != CRYPTO_SM2 && + ctx->algo != CRYPTO_ECC_192R1 && + ctx->algo != CRYPTO_ECC_224R1 && + ctx->algo != CRYPTO_ECC_256R1) + return -EINVAL; + + n_bits = crypto_algo_nbits(ctx->algo); + n_words = BITS2WORD(n_bits); + + ret = rk_mpa_alloc(&bn_sign, sign, n_words); + if (ret) + goto exit; + + ret = rk_mpa_alloc(&point_P.x, ctx->x, n_words); + ret |= rk_mpa_alloc(&point_P.y, ctx->y, n_words); + if (ret) + goto exit; + + ret = rk_mpa_alloc(&point_sign.x, sign, n_words); + ret |= rk_mpa_alloc(&point_sign.y, sign + WORD2BYTE(n_words), n_words); + if (ret) + goto exit; + + rk_crypto_enable_clk(dev); + ret = rockchip_ecc_verify(ctx->algo, hash, hash_len, &point_P, &point_sign); + rk_crypto_disable_clk(dev); +exit: + rk_mpa_free(&bn_sign); + rk_mpa_free(&point_P.x); + rk_mpa_free(&point_P.y); + rk_mpa_free(&point_sign.x); + rk_mpa_free(&point_sign.y); + + return ret; +} +#endif + +static const struct dm_crypto_ops rockchip_crypto_ops = { + .capability = rockchip_crypto_capability, + .sha_init = rockchip_crypto_sha_init, + .sha_update = rockchip_crypto_sha_update, + .sha_final = rockchip_crypto_sha_final, +#if CONFIG_IS_ENABLED(ROCKCHIP_HMAC) + .hmac_init = rockchip_crypto_hmac_init, + .hmac_update = rockchip_crypto_hmac_update, + .hmac_final = rockchip_crypto_hmac_final, +#endif +#if CONFIG_IS_ENABLED(ROCKCHIP_RSA) + .rsa_verify = rockchip_crypto_rsa_verify, +#endif +#if CONFIG_IS_ENABLED(ROCKCHIP_EC) + .ec_verify = rockchip_crypto_ec_verify, +#endif +#if CONFIG_IS_ENABLED(ROCKCHIP_CIPHER) + .cipher_crypt = rockchip_crypto_cipher, + .cipher_mac = rockchip_crypto_mac, + .cipher_ae = rockchip_crypto_ae, +#endif + +}; + +/* + * Only use "clocks" to parse crypto clock id and use rockchip_get_clk(). + * Because we always add crypto node in U-Boot dts, when kernel dtb enabled : + * + * 1. There is cru phandle mismatch between U-Boot and kernel dtb; + * 2. CONFIG_OF_SPL_REMOVE_PROPS removes clock property; + */ +static int rockchip_crypto_ofdata_to_platdata(struct udevice *dev) +{ + struct rockchip_crypto_priv *priv = dev_get_priv(dev); + int len, ret = -EINVAL; + + memset(priv, 0x00, sizeof(*priv)); + + priv->reg = (fdt_addr_t)dev_read_addr_ptr(dev); + if (priv->reg == FDT_ADDR_T_NONE) + return -EINVAL; + + crypto_base = priv->reg; + + /* if there is no clocks in dts, just skip it */ + if (!dev_read_prop(dev, "clocks", &len)) { + printf("Can't find \"clocks\" property\n"); + return 0; + } + + priv->clocks = malloc(len); + if (!priv->clocks) + return -ENOMEM; + + priv->nclocks = len / (2 * sizeof(u32)); + if (dev_read_u32_array(dev, "clocks", (u32 *)priv->clocks, + priv->nclocks)) { + printf("Can't read \"clocks\" property\n"); + ret = -EINVAL; + goto exit; + } + + if (dev_read_prop(dev, "clock-frequency", &len)) { + priv->frequencies = malloc(len); + if (!priv->frequencies) { + ret = -ENOMEM; + goto exit; + } + priv->freq_nclocks = len / sizeof(u32); + if (dev_read_u32_array(dev, "clock-frequency", priv->frequencies, + priv->freq_nclocks)) { + printf("Can't read \"clock-frequency\" property\n"); + ret = -EINVAL; + goto exit; + } + } + + return 0; +exit: + if (priv->clocks) + free(priv->clocks); + + if (priv->frequencies) + free(priv->frequencies); + + return ret; +} + +static int rk_crypto_do_enable_clk(struct udevice *dev, int enable) +{ + struct rockchip_crypto_priv *priv = dev_get_priv(dev); + struct clk clk; + int i, ret; + + for (i = 0; i < priv->nclocks; i++) { + ret = clk_get_by_index(dev, i, &clk); + if (ret < 0) { + printf("Failed to get clk index %d, ret=%d\n", i, ret); + return ret; + } + + if (enable) + ret = clk_enable(&clk); + else + ret = clk_disable(&clk); + if (ret < 0 && ret != -ENOSYS) { + printf("Failed to enable(%d) clk(%ld): ret=%d\n", + enable, clk.id, ret); + return ret; + } + } + + return 0; +} + +static int rk_crypto_enable_clk(struct udevice *dev) +{ + return rk_crypto_do_enable_clk(dev, 1); +} + +static int rk_crypto_disable_clk(struct udevice *dev) +{ + return rk_crypto_do_enable_clk(dev, 0); +} + +static int rk_crypto_set_clk(struct udevice *dev) +{ + struct rockchip_crypto_priv *priv = dev_get_priv(dev); + struct clk clk; + int i, ret; + + /* use standard "assigned-clock-rates" props */ + if (dev_read_size(dev, "assigned-clock-rates") > 0) + return clk_set_defaults(dev); + + /* use "clock-frequency" props */ + if (priv->freq_nclocks == 0) + return 0; + + for (i = 0; i < priv->freq_nclocks; i++) { + ret = clk_get_by_index(dev, i, &clk); + if (ret < 0) { + printf("Failed to get clk index %d, ret=%d\n", i, ret); + return ret; + } + ret = clk_set_rate(&clk, priv->frequencies[i]); + if (ret < 0) { + printf("%s: Failed to set clk(%ld): ret=%d\n", + __func__, clk.id, ret); + return ret; + } + } + + return 0; +} + +static int rockchip_crypto_probe(struct udevice *dev) +{ + struct rockchip_crypto_priv *priv = dev_get_priv(dev); + int ret = 0; + + ret = rk_crypto_set_clk(dev); + if (ret) + return ret; + + rk_crypto_enable_clk(dev); + + priv->hardware = rkce_hardware_alloc((void *)priv->reg); + + if (!priv->hardware) { + ret = -ENOMEM; + goto exit; + } + + priv->capability = rockchip_crypto_capability(dev); +exit: + rk_crypto_disable_clk(dev); + + return ret; +} + +static const struct udevice_id rockchip_crypto_ids[] = { + { + .compatible = "rockchip,crypto-ce", + }, + { } +}; + +U_BOOT_DRIVER(rockchip_crypto_ce) = { + .name = "rockchip_crypto_ce", + .id = UCLASS_CRYPTO, + .of_match = rockchip_crypto_ids, + .ops = &rockchip_crypto_ops, + .probe = rockchip_crypto_probe, + .ofdata_to_platdata = rockchip_crypto_ofdata_to_platdata, + .priv_auto_alloc_size = sizeof(struct rockchip_crypto_priv), +}; diff --git a/u-boot/drivers/crypto/rockchip/crypto_ecc.c b/u-boot/drivers/crypto/rockchip/crypto_ecc.c new file mode 100644 index 00000000000..0f1627c4e94 --- /dev/null +++ b/u-boot/drivers/crypto/rockchip/crypto_ecc.c @@ -0,0 +1,424 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) 2024 Rockchip Electronics Co., Ltd + */ + +#include +#include +#include +#include +#include +#include +#include + +#define WORDS2BYTES(words) ((words) * 4) + +#define RK_ECP_IS_BIGNUM_INVALID(b) (!b || !b->d || b->size > RK_ECP_MAX_WORDS) +#define RK_ECP_IS_POINT_INVALID(p) (RK_ECP_IS_BIGNUM_INVALID(p->x) && \ + RK_ECP_IS_BIGNUM_INVALID(p->y)) + +/*************************************************************/ +/* Macros for waiting EC machine ready states */ +/*************************************************************/ +#define RK_ECP_WRITE_REG(offset, val) crypto_write((val), (offset)) +#define RK_ECP_READ_REG(offset) crypto_read((offset)) + +#define RK_ECP_RAM_FOR_ECC() \ + RK_ECP_WRITE_REG(RK_ECC_RAM_CTL, RK_ECC_RAM_CTL_SEL_MASK | RK_ECC_RAM_CTL_ECC) + +#define RK_ECP_RAM_FOR_CPU() \ + RK_ECP_WRITE_REG(RK_ECC_RAM_CTL, RK_ECC_RAM_CTL_SEL_MASK | RK_ECC_RAM_CTL_CPU) + +/* big endian to little endian */ +#define RK_ECP_LOAD_DATA(dst, big_src) rk_ecp_load_data(dst, big_src) + +/* little endian to littel endian */ +#define RK_ECP_LOAD_DATA_EXT(dst, src, n_bytes) \ + do { \ + util_word_memset((void *)(dst), 0, RK_ECP_MAX_WORDS);\ + util_word_memcpy((void *)(dst), (void *)(src), (n_bytes) / 4); \ + } while (0) + +#define RK_GET_GRPOUP_NBYTES(grp) ((grp)->p_len) + +#define RK_LOAD_GROUP_A(G) do { \ + grp->curve_name = #G; \ + grp->wide = G ## _wide;\ + grp->p = G ## _p; \ + grp->p_len = sizeof(G ## _p); \ + grp->a = G ## _a; \ + grp->a_len = sizeof(G ## _a); \ + grp->n = G ## _n; \ + grp->n_len = sizeof(G ## _n); \ + grp->gx = G ## _gx; \ + grp->gx_len = sizeof(G ## _gx); \ + grp->gy = G ## _gy; \ + grp->gy_len = sizeof(G ## _gy); \ + } while (0) + +/* transform to big endian */ +/* + * Domain parameters for secp192r1 + */ +static const uint32_t secp192r1_wide = RK_ECC_CURVE_WIDE_192; + +static const uint8_t secp192r1_p[] = { + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, + 0xFE, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, +}; + +static const uint8_t secp192r1_a[] = { + 0xFC, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, + 0xFE, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, +}; + +static const uint8_t secp192r1_gx[] = { + 0x12, 0x10, 0xFF, 0x82, 0xFD, 0x0A, 0xFF, 0xF4, + 0x00, 0x88, 0xA1, 0x43, 0xEB, 0x20, 0xBF, 0x7C, + 0xF6, 0x90, 0x30, 0xB0, 0x0E, 0xA8, 0x8D, 0x18, +}; + +static const uint8_t secp192r1_gy[] = { + 0x11, 0x48, 0x79, 0x1E, 0xA1, 0x77, 0xF9, 0x73, + 0xD5, 0xCD, 0x24, 0x6B, 0xED, 0x11, 0x10, 0x63, + 0x78, 0xDA, 0xC8, 0xFF, 0x95, 0x2B, 0x19, 0x07, +}; + +static const uint8_t secp192r1_n[] = { + 0x31, 0x28, 0xD2, 0xB4, 0xB1, 0xC9, 0x6B, 0x14, + 0x36, 0xF8, 0xDE, 0x99, 0xFF, 0xFF, 0xFF, 0xFF, + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, +}; + +/* + * Domain parameters for secp224r1 + */ +static const uint32_t secp224r1_wide = RK_ECC_CURVE_WIDE_224; + +static const uint8_t secp224r1_p[] = { + 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0xFF, 0xFF, 0xFF, 0xFF, + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, + 0xFF, 0xFF, 0xFF, 0xFF, 0x00, 0x00, 0x00, 0x00, +}; + +static const uint8_t secp224r1_a[] = { + 0xFE, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, + 0xFF, 0xFF, 0xFF, 0xFF, 0xFE, 0xFF, 0xFF, 0xFF, + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, + 0xFF, 0xFF, 0xFF, 0xFF, 0x00, 0x00, 0x00, 0x00, +}; + +static const uint8_t secp224r1_gx[] = { + 0x21, 0x1D, 0x5C, 0x11, 0xD6, 0x80, 0x32, 0x34, + 0x22, 0x11, 0xC2, 0x56, 0xD3, 0xC1, 0x03, 0x4A, + 0xB9, 0x90, 0x13, 0x32, 0x7F, 0xBF, 0xB4, 0x6B, + 0xBD, 0x0C, 0x0E, 0xB7, +}; + +static const uint8_t secp224r1_gy[] = { + 0x34, 0x7E, 0x00, 0x85, 0x99, 0x81, 0xD5, 0x44, + 0x64, 0x47, 0x07, 0x5A, 0xA0, 0x75, 0x43, 0xCD, + 0xE6, 0xDF, 0x22, 0x4C, 0xFB, 0x23, 0xF7, 0xB5, + 0x88, 0x63, 0x37, 0xBD, +}; + +static const uint8_t secp224r1_n[] = { + 0x3D, 0x2A, 0x5C, 0x5C, 0x45, 0x29, 0xDD, 0x13, + 0x3E, 0xF0, 0xB8, 0xE0, 0xA2, 0x16, 0xFF, 0xFF, + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, + 0xFF, 0xFF, 0xFF, 0xFF, +}; + +/* + * Domain parameters for secp256r1 + */ +static const uint32_t secp256r1_wide = RK_ECC_CURVE_WIDE_256; + +static const uint8_t secp256r1_p[] = { + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, + 0xFF, 0xFF, 0xFF, 0xFF, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x01, 0x00, 0x00, 0x00, 0xFF, 0xFF, 0xFF, 0xFF, +}; + +static const uint8_t secp256r1_a[] = { + 0xFC, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, + 0xFF, 0xFF, 0xFF, 0xFF, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x01, 0x00, 0x00, 0x00, 0xFF, 0xFF, 0xFF, 0xFF, +}; + +static const uint8_t secp256r1_gx[] = { + 0x96, 0xC2, 0x98, 0xD8, 0x45, 0x39, 0xA1, 0xF4, + 0xA0, 0x33, 0xEB, 0x2D, 0x81, 0x7D, 0x03, 0x77, + 0xF2, 0x40, 0xA4, 0x63, 0xE5, 0xE6, 0xBC, 0xF8, + 0x47, 0x42, 0x2C, 0xE1, 0xF2, 0xD1, 0x17, 0x6B, +}; + +static const uint8_t secp256r1_gy[] = { + 0xF5, 0x51, 0xBF, 0x37, 0x68, 0x40, 0xB6, 0xCB, + 0xCE, 0x5E, 0x31, 0x6B, 0x57, 0x33, 0xCE, 0x2B, + 0x16, 0x9E, 0x0F, 0x7C, 0x4A, 0xEB, 0xE7, 0x8E, + 0x9B, 0x7F, 0x1A, 0xFE, 0xE2, 0x42, 0xE3, 0x4F, +}; + +static const uint8_t secp256r1_n[] = { + 0x51, 0x25, 0x63, 0xFC, 0xC2, 0xCA, 0xB9, 0xF3, + 0x84, 0x9E, 0x17, 0xA7, 0xAD, 0xFA, 0xE6, 0xBC, + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, + 0x00, 0x00, 0x00, 0x00, 0xFF, 0xFF, 0xFF, 0xFF, +}; + +/* + * Domain parameters for sm2p256v1_p + */ +static const uint32_t sm2p256v1_wide = RK_ECC_CURVE_WIDE_256; + +static const uint8_t sm2p256v1_p[] = { + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, + 0x00, 0x00, 0x00, 0x00, 0xFF, 0xFF, 0xFF, 0xFF, + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, + 0xFF, 0xFF, 0xFF, 0xFF, 0xFE, 0xFF, 0xFF, 0xFF, +}; + +static const uint8_t sm2p256v1_a[] = { + 0xFC, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, + 0x00, 0x00, 0x00, 0x00, 0xFF, 0xFF, 0xFF, 0xFF, + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, + 0xFF, 0xFF, 0xFF, 0xFF, 0xFE, 0xFF, 0xFF, 0xFF, +}; + +static const uint8_t sm2p256v1_gx[] = { + 0xC7, 0x74, 0x4C, 0x33, 0x89, 0x45, 0x5A, 0x71, + 0xE1, 0x0B, 0x66, 0xF2, 0xBF, 0x0B, 0xE3, 0x8F, + 0x94, 0xC9, 0x39, 0x6A, 0x46, 0x04, 0x99, 0x5F, + 0x19, 0x81, 0x19, 0x1F, 0x2C, 0xAE, 0xC4, 0x32, +}; + +static const uint8_t sm2p256v1_gy[] = { + 0xA0, 0xF0, 0x39, 0x21, 0xE5, 0x32, 0xDF, 0x02, + 0x40, 0x47, 0x2A, 0xC6, 0x7C, 0x87, 0xA9, 0xD0, + 0x53, 0x21, 0x69, 0x6B, 0xE3, 0xCE, 0xBD, 0x59, + 0x9C, 0x77, 0xF6, 0xF4, 0xA2, 0x36, 0x37, 0xBC, +}; + +static const uint8_t sm2p256v1_n[] = { + 0x23, 0x41, 0xD5, 0x39, 0x09, 0xF4, 0xBB, 0x53, + 0x2B, 0x05, 0xC6, 0x21, 0x6B, 0xDF, 0x03, 0x72, + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, + 0xFF, 0xFF, 0xFF, 0xFF, 0xFE, 0xFF, 0xFF, 0xFF, +}; + +static inline u32 word_reverse(u32 word) +{ + u32 i; + u32 new_word = 0; + + for (i = 0; i < sizeof(u32); i++) { + new_word |= (word & 0xff) << (8 * (sizeof(u32) - i - 1)); + word >>= 8; + } + + return new_word; +} + +static inline bool is_ec_supported(void) +{ + return !!RK_ECP_READ_REG(RK_ECC_MAX_CURVE_WIDE); +} + +/* reverse endian word copy */ +static int rk_ecp_load_data(u32 *dst, struct mpa_num *src) +{ + u32 i; + u32 dst_pos, src_pos; + + util_word_memset(dst, 0, RK_ECP_MAX_WORDS); + + dst_pos = src->size - 1; + src_pos = 0; + + for (i = 0; i < src->size; i++) + dst[dst_pos--] = word_reverse(src->d[src_pos++]); + + return 0; +} + +static int rk_word_cmp_zero(uint32_t *buf1, uint32_t n_words) +{ + int ret = 0; + uint32_t i; + + for (i = 0 ; i < n_words; i++) { + if (buf1[i] != 0) + ret = -EINVAL; + } + + return ret; +} + +/* + * Set a group using well-known domain parameters + */ +static int rk_ecp_group_load(struct rk_ecp_group *grp, enum rk_ecp_group_id id) +{ + memset(grp, 0x00, sizeof(*grp)); + + grp->id = id; + + switch (id) { + case RK_ECP_DP_SECP192R1: + RK_LOAD_GROUP_A(secp192r1); + return 0; + + case RK_ECP_DP_SECP224R1: + RK_LOAD_GROUP_A(secp224r1); + return 0; + + case RK_ECP_DP_SECP256R1: + RK_LOAD_GROUP_A(secp256r1); + return 0; + + case RK_ECP_DP_SM2P256V1: + RK_LOAD_GROUP_A(sm2p256v1); + return 0; + + default: + return -EINVAL; + } +} + +static int rockchip_ecc_request_set(uint32_t ecc_ctl, uint32_t wide) +{ + RK_ECP_WRITE_REG(RK_ECC_CURVE_WIDE, wide); + + RK_ECP_WRITE_REG(RK_ECC_INT_EN, 0); + RK_ECP_WRITE_REG(RK_ECC_INT_ST, RK_ECP_READ_REG(RK_ECC_INT_ST)); + RK_ECP_WRITE_REG(RK_ECC_CTL, ecc_ctl); + + return 0; +} + +static int rockchip_ecc_request_wait_done(void) +{ + int ret = 0; + u32 reg_val = 0; + + do { + reg_val = crypto_read(RK_ECC_INT_ST); + } while ((reg_val & 0x01) != RK_ECC_INT_ST_DONE); + + if (RK_ECP_READ_REG(RK_ECC_ABN_ST)) { + ret = -EFAULT; + goto exit; + } + +exit: + if (ret) { + printf("RK_ECC_CTL = %08x\n", RK_ECP_READ_REG(RK_ECC_CTL)); + printf("RK_ECC_INT_EN = %08x\n", RK_ECP_READ_REG(RK_ECC_INT_EN)); + printf("RK_ECC_CURVE_WIDE = %08x\n", RK_ECP_READ_REG(RK_ECC_CURVE_WIDE)); + printf("RK_ECC_RAM_CTL = %08x\n", RK_ECP_READ_REG(RK_ECC_RAM_CTL)); + printf("RK_ECC_INT_ST = %08x\n", RK_ECP_READ_REG(RK_ECC_INT_ST)); + printf("RK_ECC_ABN_ST = %08x\n", RK_ECP_READ_REG(RK_ECC_ABN_ST)); + } + + RK_ECP_WRITE_REG(RK_ECC_CTL, 0); + RK_ECP_RAM_FOR_CPU(); + + return ret; +} + +static int rockchip_ecc_request_trigger(void) +{ + uint32_t ecc_ctl = RK_ECP_READ_REG(RK_ECC_CTL); + + RK_ECP_RAM_FOR_ECC(); + + RK_ECP_WRITE_REG(RK_ECC_CTL, ecc_ctl | RK_ECC_CTL_REQ_ECC); + + return rockchip_ecc_request_wait_done(); +} + +static uint32_t rockchip_ecc_get_group_id(uint32_t crypto_algo) +{ + switch (crypto_algo) { + case CRYPTO_ECC_192R1: + return RK_ECP_DP_SECP192R1; + case CRYPTO_ECC_224R1: + return RK_ECP_DP_SECP224R1; + case CRYPTO_ECC_256R1: + return RK_ECP_DP_SECP256R1; + case CRYPTO_SM2: + return RK_ECP_DP_SM2P256V1; + default: + return RK_ECP_DP_NONE; + } +} + +int rockchip_ecc_verify(uint32_t crypto_algo, uint8_t *hash, uint32_t hash_len, + struct rk_ecp_point *point_P, struct rk_ecp_point *point_sign) +{ + int ret; + uint32_t curve_sel = 0; + struct mpa_num *bn_hash = NULL; + uint32_t group_id = rockchip_ecc_get_group_id(crypto_algo); + struct rk_ecp_group grp; + struct rk_ecc_verify *ecc_st = (struct rk_ecc_verify *)SM2_RAM_BASE; + + if (!is_ec_supported()) + return -ENOSYS; + + if (!hash || + hash_len == 0 || + hash_len > RK_ECP_MAX_BYTES || + RK_ECP_IS_POINT_INVALID(point_P) || + RK_ECP_IS_POINT_INVALID(point_sign)) { + ret = -EINVAL; + goto exit; + } + + ret = rk_ecp_group_load(&grp, group_id); + if (ret) + goto exit; + + rk_mpa_alloc(&bn_hash, hash, BYTE2WORD(hash_len)); + if (!bn_hash) { + ret = -ENOMEM; + goto exit; + } + + RK_ECP_RAM_FOR_CPU(); + + curve_sel = group_id == RK_ECP_DP_SM2P256V1 ? + RK_ECC_CTL_FUNC_SM2_CURVER : RK_ECC_CTL_FUNC_ECC_CURVER; + + RK_ECP_LOAD_DATA(ecc_st->e, bn_hash); + RK_ECP_LOAD_DATA(ecc_st->r_, point_sign->x); + RK_ECP_LOAD_DATA(ecc_st->s_, point_sign->y); + RK_ECP_LOAD_DATA(ecc_st->p_x, point_P->x); + RK_ECP_LOAD_DATA(ecc_st->p_y, point_P->y); + + RK_ECP_LOAD_DATA_EXT(ecc_st->A, grp.a, grp.a_len); + RK_ECP_LOAD_DATA_EXT(ecc_st->P, grp.p, grp.p_len); + RK_ECP_LOAD_DATA_EXT(ecc_st->N, grp.n, grp.n_len); + + RK_ECP_LOAD_DATA_EXT(ecc_st->G_x, grp.gx, grp.gx_len); + RK_ECP_LOAD_DATA_EXT(ecc_st->G_y, grp.gy, grp.gy_len); + + rockchip_ecc_request_set(curve_sel | RK_ECC_CTL_FUNC_SEL_VERIFY, grp.wide); + + ret = rockchip_ecc_request_trigger(); + if (ret || + rk_word_cmp_zero(ecc_st->v, RK_ECP_MAX_WORDS) || + rk_word_cmp_zero(ecc_st->r_, RK_ECP_MAX_WORDS) == 0) { + ret = -EKEYREJECTED; + } +exit: + rk_mpa_free(&bn_hash); + + return ret; +} diff --git a/u-boot/drivers/crypto/rockchip/crypto_mpa.c b/u-boot/drivers/crypto/rockchip/crypto_mpa.c new file mode 100644 index 00000000000..320c4b089e5 --- /dev/null +++ b/u-boot/drivers/crypto/rockchip/crypto_mpa.c @@ -0,0 +1,74 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) 2024 Rockchip Electronics Co., Ltd + */ + +#include +#include +#include + +int rk_mpa_alloc(struct mpa_num **mpa, void *data, u32 word_size) +{ + u32 alignment = sizeof(u32); + u32 byte_size = word_size * sizeof(u32); + struct mpa_num *tmp_mpa = NULL; + + if (!mpa || word_size == 0) + return -EINVAL; + + *mpa = NULL; + + tmp_mpa = malloc(sizeof(*tmp_mpa)); + if (!tmp_mpa) + return -ENOMEM; + + memset(tmp_mpa, 0x00, sizeof(*tmp_mpa)); + + if (!data || (unsigned long)data % alignment) { + tmp_mpa->d = memalign(alignment, byte_size); + if (!tmp_mpa->d) { + free(tmp_mpa); + return -ENOMEM; + } + + if (data) + memcpy(tmp_mpa->d, data, byte_size); + else + memset(tmp_mpa->d, 0x00, byte_size); + + tmp_mpa->alloc = MPA_USE_ALLOC; + } else { + tmp_mpa->d = data; + } + + tmp_mpa->size = word_size; + + *mpa = tmp_mpa; + + return 0; +} + +void rk_mpa_free(struct mpa_num **mpa) +{ + struct mpa_num *tmp_mpa = NULL; + + if (mpa && (*mpa)) { + tmp_mpa = *mpa; + if (tmp_mpa->alloc == MPA_USE_ALLOC) + free(tmp_mpa->d); + + free(tmp_mpa); + } +} + +/*get bignum data length*/ +int rk_check_size(u32 *data, u32 max_word_size) +{ + for (int i = (max_word_size - 1); i >= 0; i--) { + if (data[i] == 0) + continue; + else + return (i + 1); + } + return 0; +} diff --git a/u-boot/drivers/crypto/rockchip/crypto_v2.c b/u-boot/drivers/crypto/rockchip/crypto_v2.c index af9df9b0369..6e1a0b474c6 100644 --- a/u-boot/drivers/crypto/rockchip/crypto_v2.c +++ b/u-boot/drivers/crypto/rockchip/crypto_v2.c @@ -11,6 +11,7 @@ #include #include #include +#include #include #include #include @@ -307,6 +308,13 @@ static u32 crypto_v3_dynamic_cap(void) CRYPTO_RSA3072 | CRYPTO_RSA4096; +#if CONFIG_IS_ENABLED(ROCKCHIP_EC) + capability |= (CRYPTO_SM2 | + CRYPTO_ECC_192R1 | + CRYPTO_ECC_224R1 | + CRYPTO_ECC_256R1); +#endif + for (i = 0; i < ARRAY_SIZE(cap_tbl); i++) { ver_reg = crypto_read(cap_tbl[i].ver_offset); @@ -881,6 +889,10 @@ static int hw_cipher_init(u32 chn, const u8 *key, const u8 *twk_key, u32 rk_mode = RK_GET_RK_MODE(mode); u32 key_chn_sel = chn; u32 reg_ctrl = 0; + bool use_otpkey = false; + + if (!key && key_len) + use_otpkey = true; IMSG("%s: key addr is %p, key_len is %d, iv addr is %p", __func__, key, key_len, iv); @@ -925,7 +937,12 @@ static int hw_cipher_init(u32 chn, const u8 *key, const u8 *twk_key, reg_ctrl |= CRYPTO_BC_DECRYPT; /* write key data to reg */ - write_key_reg(key_chn_sel, key, key_len); + if (!use_otpkey) { + write_key_reg(key_chn_sel, key, key_len); + crypto_write(CRYPTO_SEL_USER, CRYPTO_KEY_SEL); + } else { + crypto_write(CRYPTO_SEL_KEYTABLE, CRYPTO_KEY_SEL); + } /* write twk key for xts mode */ if (rk_mode == RK_MODE_XTS) @@ -1290,6 +1307,36 @@ int rockchip_crypto_cipher(struct udevice *dev, cipher_context *ctx, return ret; } +int rockchip_crypto_fw_cipher(struct udevice *dev, cipher_fw_context *ctx, + const u8 *in, u8 *out, u32 len, bool enc) +{ + int ret; + + rk_crypto_enable_clk(dev); + + switch (ctx->algo) { + case CRYPTO_DES: + ret = rk_crypto_des(dev, ctx->mode, NULL, ctx->key_len, + ctx->iv, in, out, len, enc); + break; + case CRYPTO_AES: + ret = rk_crypto_aes(dev, ctx->mode, NULL, NULL, ctx->key_len, + ctx->iv, ctx->iv_len, in, out, len, enc); + break; + case CRYPTO_SM4: + ret = rk_crypto_sm4(dev, ctx->mode, NULL, NULL, ctx->key_len, + ctx->iv, ctx->iv_len, in, out, len, enc); + break; + default: + ret = -EINVAL; + break; + } + + rk_crypto_disable_clk(dev); + + return ret; +} + int rk_crypto_mac(struct udevice *dev, u32 algo, u32 mode, const u8 *key, u32 key_len, const u8 *in, u32 len, u8 *tag) @@ -1383,6 +1430,11 @@ int rockchip_crypto_ae(struct udevice *dev, cipher_context *ctx, return ret; } +static ulong rockchip_crypto_keytable_addr(struct udevice *dev) +{ + return CRYPTO_S_BY_KEYLAD_BASE + CRYPTO_CH0_KEY_0; +} + #endif #if CONFIG_IS_ENABLED(ROCKCHIP_RSA) @@ -1446,6 +1498,55 @@ exit: } #endif +#if CONFIG_IS_ENABLED(ROCKCHIP_EC) +static int rockchip_crypto_ec_verify(struct udevice *dev, ec_key *ctx, + u8 *hash, u32 hash_len, u8 *sign) +{ + struct mpa_num *bn_sign = NULL; + struct rk_ecp_point point_P, point_sign; + u32 n_bits, n_words; + int ret; + + if (!ctx) + return -EINVAL; + + if (ctx->algo != CRYPTO_SM2 && + ctx->algo != CRYPTO_ECC_192R1 && + ctx->algo != CRYPTO_ECC_224R1 && + ctx->algo != CRYPTO_ECC_256R1) + return -EINVAL; + + n_bits = crypto_algo_nbits(ctx->algo); + n_words = BITS2WORD(n_bits); + + ret = rk_mpa_alloc(&bn_sign, sign, n_words); + if (ret) + goto exit; + + ret = rk_mpa_alloc(&point_P.x, ctx->x, n_words); + ret |= rk_mpa_alloc(&point_P.y, ctx->y, n_words); + if (ret) + goto exit; + + ret = rk_mpa_alloc(&point_sign.x, sign, n_words); + ret |= rk_mpa_alloc(&point_sign.y, sign + WORD2BYTE(n_words), n_words); + if (ret) + goto exit; + + rk_crypto_enable_clk(dev); + ret = rockchip_ecc_verify(ctx->algo, hash, hash_len, &point_P, &point_sign); + rk_crypto_disable_clk(dev); +exit: + rk_mpa_free(&bn_sign); + rk_mpa_free(&point_P.x); + rk_mpa_free(&point_P.y); + rk_mpa_free(&point_sign.x); + rk_mpa_free(&point_sign.y); + + return ret; +} +#endif + static const struct dm_crypto_ops rockchip_crypto_ops = { .capability = rockchip_crypto_capability, .sha_init = rockchip_crypto_sha_init, @@ -1454,15 +1555,20 @@ static const struct dm_crypto_ops rockchip_crypto_ops = { #if CONFIG_IS_ENABLED(ROCKCHIP_RSA) .rsa_verify = rockchip_crypto_rsa_verify, #endif +#if CONFIG_IS_ENABLED(ROCKCHIP_EC) + .ec_verify = rockchip_crypto_ec_verify, +#endif #if CONFIG_IS_ENABLED(ROCKCHIP_HMAC) .hmac_init = rockchip_crypto_hmac_init, .hmac_update = rockchip_crypto_hmac_update, .hmac_final = rockchip_crypto_hmac_final, #endif #if CONFIG_IS_ENABLED(ROCKCHIP_CIPHER) - .cipher_crypt = rockchip_crypto_cipher, - .cipher_mac = rockchip_crypto_mac, - .cipher_ae = rockchip_crypto_ae, + .cipher_crypt = rockchip_crypto_cipher, + .cipher_mac = rockchip_crypto_mac, + .cipher_ae = rockchip_crypto_ae, + .cipher_fw_crypt = rockchip_crypto_fw_cipher, + .keytable_addr = rockchip_crypto_keytable_addr, #endif }; diff --git a/u-boot/drivers/crypto/rockchip/crypto_v2_pka.c b/u-boot/drivers/crypto/rockchip/crypto_v2_pka.c index ef34e4c0171..db173e0bfa1 100644 --- a/u-boot/drivers/crypto/rockchip/crypto_v2_pka.c +++ b/u-boot/drivers/crypto/rockchip/crypto_v2_pka.c @@ -15,14 +15,12 @@ void rk_pka_ram_ctrl_enable(void) { - crypto_write((CRYPTO_RAM_PKA_RDY << CRYPTO_WRITE_MASK_SHIFT) | - CRYPTO_RAM_PKA_RDY, CRYPTO_RAM_CTL); + crypto_write(CRYPTO_RAM_CTL_SEL_MASK | CRYPTO_RAM_CTL_PKA, CRYPTO_RAM_CTL); } void rk_pka_ram_ctrl_disable(void) { - crypto_write((CRYPTO_RAM_PKA_RDY << CRYPTO_WRITE_MASK_SHIFT), - CRYPTO_RAM_CTL); + crypto_write(CRYPTO_RAM_CTL_SEL_MASK | CRYPTO_RAM_CTL_CPU, CRYPTO_RAM_CTL); } void rk_pka_wait_on_ram_ready(void) @@ -493,6 +491,7 @@ u32 rk_pka_init(u32 regs_sizes_ptr[RK_PKA_MAX_REGS_COUNT], u32 count_of_sizes, void rk_pka_finish(void) { RK_PKA_Terminate(0); + rk_pka_ram_ctrl_disable(); PKA_CLK_DISABLE(); } @@ -802,71 +801,6 @@ static int mpa_highest_bit_index(const struct mpa_num *src) return (int)(rk_mpanum_size(src) - 1) * RK_WORD_SIZE + b; } -/*get bignum data length*/ -static int rk_check_size(u32 *data, u32 max_word_size) -{ - for (int i = (max_word_size - 1); i >= 0; i--) { - if (data[i] == 0) - continue; - else - return (i + 1); - } - return 0; -} - -int rk_mpa_alloc(struct mpa_num **mpa, void *data, u32 word_size) -{ - u32 alignment = sizeof(u32); - u32 byte_size = word_size * sizeof(u32); - struct mpa_num *tmp_mpa = NULL; - - if (!mpa || word_size == 0) - return -EINVAL; - - *mpa = NULL; - - tmp_mpa = malloc(sizeof(*tmp_mpa)); - if (!tmp_mpa) - return -ENOMEM; - - memset(tmp_mpa, 0x00, sizeof(*tmp_mpa)); - - if (!data || (unsigned long)data % alignment) { - tmp_mpa->d = memalign(alignment, byte_size); - if (!tmp_mpa->d) { - free(tmp_mpa); - return -ENOMEM; - } - - if (data) - memcpy(tmp_mpa->d, data, byte_size); - else - memset(tmp_mpa->d, 0x00, byte_size); - - tmp_mpa->alloc = MPA_USE_ALLOC; - } else { - tmp_mpa->d = data; - } - - tmp_mpa->size = word_size; - - *mpa = tmp_mpa; - - return 0; -} - -void rk_mpa_free(struct mpa_num **mpa) -{ - struct mpa_num *tmp_mpa = NULL; - - if (mpa && (*mpa)) { - tmp_mpa = *mpa; - if (tmp_mpa->alloc == MPA_USE_ALLOC) - free(tmp_mpa->d); - - free(tmp_mpa); - } -} /* c = |a| + |b| */ int rk_abs_add(void *a, void *b, void *c) diff --git a/u-boot/drivers/crypto/rockchip/rkce_core.c b/u-boot/drivers/crypto/rockchip/rkce_core.c new file mode 100644 index 00000000000..574b5cbb5a4 --- /dev/null +++ b/u-boot/drivers/crypto/rockchip/rkce_core.c @@ -0,0 +1,623 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Crypto acceleration support for Rockchip crypto engine + * + * Copyright (c) 2025 Rockchip Electronics Co., Ltd. + * + * Author: Lin Jinhan + * + */ + +#include +#include +#include + +#include "rockchip/rkce_core.h" +#include "rockchip/rkce_debug.h" +#include "rockchip/rkce_error.h" +#include "rockchip/rkce_reg.h" + +struct rkce_chn_info { + void *td_virt; + uint32_t int_st; + uint32_t td_id; + int result; + + request_cb_func cb_func; +}; + +struct rkce_hardware { + struct RKCE_REG *rkce_reg; + + struct rkce_chn_info chn[RKCE_TD_TYPE_MAX]; +}; + +#define RST_TIMEOUT_MS 100 +#define TD_PUSH_TIMEOUT_MS 3000 + +#define IP_VERSION_MASK (0xfU >> 28) +#define IP_VERSION_RKCE (0x1U >> 28) +#define GET_IP_VERSION(ver) ((ver) & IP_VERSION_MASK) + +#define IS_SYMM_TD(td_type) ((td_type) == RKCE_TD_TYPE_SYMM || \ + (td_type) == RKCE_TD_TYPE_SYMM_HASH_IN || \ + (td_type) == RKCE_TD_TYPE_SYMM_HASH_OUT) + +#define IS_HASH_TD(td_type) ((td_type) == RKCE_TD_TYPE_HASH) + +#define GET_RKCE_REG(hardware) (((struct rkce_hardware *)(hardware))->rkce_reg) +#define CHECK_RKCE_INITED(hardware) WARN_ON_ONCE(!(hardware) || \ + !(((struct rkce_hardware *)(hardware))->rkce_reg)) +#define POLL_TIMEOUT(condition, timeout_ms) ({ \ + int timeout = timeout_ms; \ + while ((condition) && timeout--) { \ + udelay(1000); \ + } \ + if (timeout < 0) \ + rk_err("%s timeout!\n", #condition); \ + (timeout < 0) ? -RKCE_TIMEOUT : 0; \ + }) + +static const uint32_t cipher_mode2bit_mask[] = { + [RKCE_SYMM_MODE_ECB] = RKCE_AES_VER_ECB_FLAG_MASK, + [RKCE_SYMM_MODE_CBC] = RKCE_AES_VER_CBC_FLAG_MASK, + [RKCE_SYMM_MODE_CFB] = RKCE_AES_VER_CFB_FLAG_MASK, + [RKCE_SYMM_MODE_OFB] = RKCE_AES_VER_OFB_FLAG_MASK, + [RKCE_SYMM_MODE_CTR] = RKCE_AES_VER_CTR_FLAG_MASK, + [RKCE_SYMM_MODE_XTS] = RKCE_AES_VER_XTS_FLAG_MASK, + [RKCE_SYMM_MODE_CTS] = RKCE_AES_VER_CTS_FLAG_MASK, + [RKCE_SYMM_MODE_CCM] = RKCE_AES_VER_CCM_FLAG_MASK, + [RKCE_SYMM_MODE_GCM] = RKCE_AES_VER_GCM_FLAG_MASK, + [RKCE_SYMM_MODE_CMAC] = RKCE_AES_VER_CMAC_FLAG_MASK, + [RKCE_SYMM_MODE_CBC_MAC] = RKCE_AES_VER_CBC_MAC_FLAG_MASK, +}; + +static const uint32_t hash_algo2bit_mask[] = { + [RKCE_HASH_ALGO_SHA1] = RKCE_HASH_VER_SHA1_FLAG_MASK, + [RKCE_HASH_ALGO_SHA224] = RKCE_HASH_VER_SHA224_FLAG_MASK, + [RKCE_HASH_ALGO_SHA256] = RKCE_HASH_VER_SHA256_FLAG_MASK, + [RKCE_HASH_ALGO_SHA384] = RKCE_HASH_VER_SHA384_FLAG_MASK, + [RKCE_HASH_ALGO_SHA512] = RKCE_HASH_VER_SHA512_FLAG_MASK, + [RKCE_HASH_ALGO_SHA512_224] = RKCE_HASH_VER_SHA512_224_FLAG_MASK, + [RKCE_HASH_ALGO_SHA512_256] = RKCE_HASH_VER_SHA512_256_FLAG_MASK, + [RKCE_HASH_ALGO_MD5] = RKCE_HASH_VER_MD5_FLAG_MASK, + [RKCE_HASH_ALGO_SM3] = RKCE_HASH_VER_SM3_FLAG_MASK, +}; + +static const uint32_t hmac_algo2bit_mask[] = { + [RKCE_HASH_ALGO_SHA1] = RKCE_HMAC_VER_SHA1_FLAG_MASK, + [RKCE_HASH_ALGO_SHA256] = RKCE_HMAC_VER_SHA256_FLAG_MASK, + [RKCE_HASH_ALGO_SHA512] = RKCE_HMAC_VER_SHA512_FLAG_MASK, + [RKCE_HASH_ALGO_MD5] = RKCE_HMAC_VER_MD5_FLAG_MASK, + [RKCE_HASH_ALGO_SM3] = RKCE_HMAC_VER_SM3_FLAG_MASK, +}; + +static bool rk_is_cipher_support(struct RKCE_REG *rkce_reg, + uint32_t algo, uint32_t mode, uint32_t key_len) +{ + uint32_t version = 0; + uint32_t mask = 0; + bool key_len_valid = true; + + switch (algo) { + case RKCE_SYMM_ALGO_DES: + case RKCE_SYMM_ALGO_TDES: + version = rkce_reg->DES_VER; + + if (key_len == RKCE_DES_BLOCK_SIZE) + key_len_valid = true; + else if (key_len == 2 * RKCE_DES_BLOCK_SIZE || + key_len == 3 * RKCE_DES_BLOCK_SIZE) + key_len_valid = version & RKCE_DES_VER_TDES_FLAG_MASK; + else + key_len_valid = false; + break; + case RKCE_SYMM_ALGO_AES: + version = rkce_reg->AES_VER; + + if (key_len == RKCE_AES_KEYSIZE_128) + key_len_valid = version & RKCE_AES_VER_AES128_FLAG_MASK; + else if (key_len == RKCE_AES_KEYSIZE_192) + key_len_valid = version & RKCE_AES_VER_AES192_FLAG_MASK; + else if (key_len == RKCE_KEY_AES_256) + key_len_valid = version & RKCE_AES_VER_AES256_FLAG_MASK; + else + key_len_valid = false; + break; + case RKCE_SYMM_ALGO_SM4: + version = rkce_reg->SM4_VER; + + key_len_valid = (key_len == RKCE_SM4_KEYSIZE) ? true : false; + break; + default: + return false; + } + + mask = cipher_mode2bit_mask[mode]; + + if (key_len == 0) + key_len_valid = true; + + return (version & mask) && key_len_valid; +} + +static bool rk_is_hash_support(struct RKCE_REG *rkce_reg, uint32_t algo, uint32_t type) +{ + uint32_t version = 0; + uint32_t mask = 0; + + if (type == RKCE_ALGO_TYPE_HMAC) { + version = rkce_reg->HMAC_VER; + mask = hmac_algo2bit_mask[algo]; + } else if (type == RKCE_ALGO_TYPE_HASH) { + version = rkce_reg->HASH_VER; + mask = hash_algo2bit_mask[algo]; + } else { + return false; + } + + return version & mask; +} + +static bool rk_is_asym_support(struct RKCE_REG *rkce_reg, uint32_t algo) +{ + switch (algo) { + case RKCE_ASYM_ALGO_RSA: + return !!rkce_reg->PKA_VER; + case RKCE_ASYM_ALGO_ECC_P192: + case RKCE_ASYM_ALGO_ECC_P224: + case RKCE_ASYM_ALGO_ECC_P256: + case RKCE_ASYM_ALGO_SM2: + return !!rkce_reg->ECC_MAX_CURVE_WIDE; + default: + return false; + } +} + +bool rkce_hw_algo_valid(void *rkce_hw, uint32_t type, uint32_t algo, uint32_t mode) +{ + struct RKCE_REG *rkce_reg; + + CHECK_RKCE_INITED(rkce_hw); + + rkce_reg = GET_RKCE_REG(rkce_hw); + + if (type == RKCE_ALGO_TYPE_CIPHER || type == RKCE_ALGO_TYPE_AEAD) { + rk_debug("CIPHER"); + return rk_is_cipher_support(rkce_reg, algo, mode, 0); + } else if (type == RKCE_ALGO_TYPE_HASH || type == RKCE_ALGO_TYPE_HMAC) { + rk_debug("HASH/HMAC"); + return rk_is_hash_support(rkce_reg, algo, type); + } else if (type == RKCE_ALGO_TYPE_ASYM) { + rk_debug("ASYM"); + return rk_is_asym_support(rkce_reg, algo); + } else { + return false; + } +} + +uint32_t rkce_get_td_type(void *td) +{ + if (!td) + return ~((uint32_t)0); + + return ((struct rkce_symm_td *)td)->ctrl.td_type; +} + +int rkce_soft_reset(void *rkce_hw, uint32_t reset_sel) +{ + struct RKCE_REG *rkce_reg; + uint32_t value = 0; + + CHECK_RKCE_INITED(rkce_hw); + + rkce_reg = GET_RKCE_REG(rkce_hw); + + if (reset_sel & RKCE_RESET_SYMM) + value |= RKCE_RST_CTL_SW_SYMM_RESET_SHIFT; + + if (reset_sel & RKCE_RESET_HASH) + value |= RKCE_RST_CTL_SW_HASH_RESET_SHIFT; + + if (reset_sel & RKCE_RESET_PKA) + value |= RKCE_RST_CTL_SW_PKA_RESET_SHIFT; + + rkce_reg->RST_CTL = value | RKCE_WRITE_MASK_ALL; + + return POLL_TIMEOUT(rkce_reg->RST_CTL, RST_TIMEOUT_MS); +} + +static int rkce_check_version(struct RKCE_REG *rkce_reg) +{ + rk_debug("rkce_reg->CE_VER = %08x\n", rkce_reg->CE_VER); + + if (GET_IP_VERSION(rkce_reg->CE_VER) != IP_VERSION_RKCE) { + rk_err("IP version is %08x not a RKCE module.\n", rkce_reg->CE_VER); + return -RKCE_FAULT; + } + + return RKCE_SUCCESS; +} + +static int rkce_init(void *rkce_hw) +{ + struct RKCE_REG *rkce_reg = GET_RKCE_REG(rkce_hw); + uint32_t value = 0; + int ret; + + ret = rkce_check_version(rkce_hw); + if (ret) + goto exit; + + rkce_soft_reset(rkce_hw, RKCE_RESET_SYMM | RKCE_RESET_HASH | RKCE_RESET_PKA); + + /* clear symm interrupt register */ + rkce_reg->SYMM_INT_EN = 0; + value = rkce_reg->SYMM_INT_ST; + rkce_reg->SYMM_INT_ST = value; + + ret = POLL_TIMEOUT(rkce_reg->SYMM_INT_ST, RST_TIMEOUT_MS); + if (ret) + goto exit; + + /* clear hash interrupt register */ + rkce_reg->HASH_INT_EN = 0; + value = rkce_reg->HASH_INT_ST; + rkce_reg->HASH_INT_ST = value; + + ret = POLL_TIMEOUT(rkce_reg->HASH_INT_ST, RST_TIMEOUT_MS); + if (ret) + goto exit; + + if (rkce_reg->SYMM_CONTEXT_SIZE != RKCE_TD_SYMM_CTX_SIZE) { + rk_err("rkce symm context size (%u) != %u\n", + rkce_reg->SYMM_CONTEXT_SIZE, RKCE_TD_SYMM_CTX_SIZE); + return -RKCE_INVAL; + } + + if (rkce_reg->HASH_CONTEXT_SIZE != RKCE_TD_HASH_CTX_SIZE) { + rk_err("rkce hash context size (%u) != %u\n", + rkce_reg->HASH_CONTEXT_SIZE, RKCE_TD_HASH_CTX_SIZE); + return -RKCE_INVAL; + } + +exit: + return ret; +} + +void *rkce_hardware_alloc(void __iomem *reg_base) +{ + struct rkce_hardware *hardware; + + rk_debug("reg_base = %p", reg_base); + + if (!reg_base) + return NULL; + + hardware = malloc(sizeof(*hardware)); + if (!hardware) + return NULL; + + hardware->rkce_reg = reg_base; + + if (rkce_init(hardware) != 0) { + free(hardware); + return NULL; + } + + rk_debug("hardware = %p", hardware); + + return hardware; +} + +void rkce_hardware_free(void *rkce_hw) +{ + if (!rkce_hw) + return; + + free(rkce_hw); +} + +void rkce_dump_reginfo(void *rkce_hw) +{ + struct RKCE_REG *rkce_reg; + + CHECK_RKCE_INITED(rkce_hw); + + rkce_reg = GET_RKCE_REG(rkce_hw); + + rk_info("\n============================== reg info ===========================\n"); + rk_info("FIFO_ST = %08x\n", rkce_reg->FIFO_ST); + rk_info("\n"); + rk_info("SYMM_INT_EN = %08x\n", rkce_reg->SYMM_INT_EN); + rk_info("SYMM_INT_ST = %08x\n", rkce_reg->SYMM_INT_ST); + rk_info("SYMM_TD_ST = %08x\n", rkce_reg->SYMM_TD_ST); + rk_info("SYMM_TD_ID = %08x\n", rkce_reg->SYMM_TD_ID); + rk_info("SYMM_ST_DBG = %08x\n", rkce_reg->SYMM_ST_DBG); + rk_info("SYMM_TD_ADDR_DBG = %08x\n", rkce_reg->SYMM_TD_ADDR_DBG); + rk_info("SYMM_TD_GRANT_DBG = %08x\n", rkce_reg->SYMM_TD_GRANT_DBG); + rk_info("\n"); + rk_info("HASH_INT_EN = %08x\n", rkce_reg->HASH_INT_EN); + rk_info("HASH_INT_ST = %08x\n", rkce_reg->HASH_INT_ST); + rk_info("HASH_TD_ST = %08x\n", rkce_reg->HASH_TD_ST); + rk_info("HASH_TD_ID = %08x\n", rkce_reg->HASH_TD_ID); + rk_info("HASH_ST_DBG = %08x\n", rkce_reg->HASH_ST_DBG); + rk_info("HASH_TD_ADDR_DBG = %08x\n", rkce_reg->HASH_TD_ADDR_DBG); + rk_info("HASH_TD_GRANT_DBG = %08x\n", rkce_reg->HASH_TD_GRANT_DBG); + rk_info("===================================================================\n"); +} + +int rkce_push_td(void *rkce_hw, void *td) +{ + int ret = RKCE_SUCCESS; + struct RKCE_REG *rkce_reg; + uint32_t td_type; + struct rkce_hardware *hardware = rkce_hw; + + CHECK_RKCE_INITED(rkce_hw); + + if (!td) + return -RKCE_INVAL; + + td_type = rkce_get_td_type(td); + rkce_reg = GET_RKCE_REG(rkce_hw); + + rkce_dump_td(td); + + if (IS_SYMM_TD(td_type)) { + rk_debug("rkce symm push td virt(%p), phys(%lx)\n", + td, rkce_cma_virt2phys(td)); + + WRITE_ONCE(rkce_reg->SYMM_INT_EN, 0x3f); + + /* wait symm fifo valid */ + ret = POLL_TIMEOUT(rkce_reg->TD_LOAD_CTRL & RKCE_TD_LOAD_CTRL_SYMM_TLR_MASK, + TD_PUSH_TIMEOUT_MS); + if (ret) + goto exit; + + /* set task desc address */ + rkce_reg->TD_ADDR = rkce_cma_virt2phys(td); + hardware->chn[RKCE_TD_TYPE_SYMM].td_virt = td; + + /* tell rkce to load task desc address as symm td */ + rkce_reg->TD_LOAD_CTRL = 0xffff0000 | RKCE_TD_LOAD_CTRL_SYMM_TLR_MASK; + } else if (IS_HASH_TD(td_type)) { + rk_debug("rkce hash push td virt(%p), phys(%lx)\n", + td, rkce_cma_virt2phys(td)); + + WRITE_ONCE(rkce_reg->HASH_INT_EN, 0x3f); + + /* wait hash fifo valid */ + ret = POLL_TIMEOUT(rkce_reg->TD_LOAD_CTRL & RKCE_TD_LOAD_CTRL_HASH_TLR_MASK, + TD_PUSH_TIMEOUT_MS); + if (ret) + goto exit; + + /* set task desc address */ + rkce_reg->TD_ADDR = rkce_cma_virt2phys(td); + hardware->chn[RKCE_TD_TYPE_HASH].td_virt = td; + + /* tell rkce to load task desc address as hash td */ + rkce_reg->TD_LOAD_CTRL = 0xffff0000 | RKCE_TD_LOAD_CTRL_HASH_TLR_MASK; + } else { + return -RKCE_INVAL; + } + +exit: + return ret; +} + +int rkce_push_td_sync(void *rkce_hw, void *td, uint32_t timeout_ms) +{ + int ret = RKCE_SUCCESS; + struct RKCE_REG *rkce_reg; + uint32_t td_type; + uint32_t value, mask; + + CHECK_RKCE_INITED(rkce_hw); + + if (!td) + return -RKCE_INVAL; + + td_type = rkce_get_td_type(td); + rkce_reg = GET_RKCE_REG(rkce_hw); + + rkce_dump_td(td); + + if (IS_SYMM_TD(td_type)) { + rk_debug("rkce symm push td virt(%p), phys(%lx)\n", + td, rkce_cma_virt2phys(td)); + + WRITE_ONCE(rkce_reg->SYMM_INT_EN, 0x00); + + /* wait symm fifo valid */ + ret = POLL_TIMEOUT(rkce_reg->TD_LOAD_CTRL & RKCE_TD_LOAD_CTRL_SYMM_TLR_MASK, + timeout_ms); + if (ret) + goto exit; + + /* set task desc address */ + rkce_reg->TD_ADDR = rkce_cma_virt2phys(td); + + /* tell rkce to load task desc address as symm td */ + rkce_reg->TD_LOAD_CTRL = 0xffff0000 | RKCE_TD_LOAD_CTRL_SYMM_TLR_MASK; + + /* wait symm done */ + ret = POLL_TIMEOUT(!(rkce_reg->SYMM_INT_ST), timeout_ms); + mask = RKCE_SYMM_INT_ST_TD_DONE_MASK; + value = READ_ONCE(rkce_reg->SYMM_INT_ST); + WRITE_ONCE(rkce_reg->SYMM_INT_ST, value); + rk_debug("symm ret = %d, value = %08x, IN_ST = %08x\n", + ret, value, READ_ONCE(rkce_reg->SYMM_INT_ST)); + } else if (IS_HASH_TD(td_type)) { + rk_debug("rkce hash push td virt(%p), phys(%lx)\n", + td, rkce_cma_virt2phys(td)); + + WRITE_ONCE(rkce_reg->HASH_INT_EN, 0x00); + + /* wait hash fifo valid */ + ret = POLL_TIMEOUT(rkce_reg->TD_LOAD_CTRL & RKCE_TD_LOAD_CTRL_HASH_TLR_MASK, + timeout_ms); + if (ret) + goto exit; + + /* set task desc address */ + rkce_reg->TD_ADDR = rkce_cma_virt2phys(td); + + /* tell rkce to load task desc address as hash td */ + rkce_reg->TD_LOAD_CTRL = 0xffff0000 | RKCE_TD_LOAD_CTRL_HASH_TLR_MASK; + + /* wait hash done */ + ret = POLL_TIMEOUT(!(rkce_reg->HASH_INT_ST), timeout_ms); + mask = RKCE_HASH_INT_ST_TD_DONE_MASK; + value = READ_ONCE(rkce_reg->HASH_INT_ST); + WRITE_ONCE(rkce_reg->HASH_INT_ST, value); + rk_debug("hash ret = %d, value = %08x, INT_ST = %08x\n", + ret, value, READ_ONCE(rkce_reg->HASH_INT_ST)); + } else { + rk_debug("unknown td_type = %u\n", td_type); + return -RKCE_INVAL; + } + + if (ret) + goto exit; + + ret = (value == mask) ? 0 : -RKCE_FAULT; +exit: + return ret; +} + +int rkce_init_symm_td(struct rkce_symm_td *td, struct rkce_symm_td_buf *buf) +{ + if (!td || + !buf || + !rkce_cma_virt2phys(td) || + !rkce_cma_virt2phys(buf)) { + rk_debug("td = %p buf = %p", td, buf); + return -RKCE_INVAL; + } + + memset(td, 0x00, sizeof(*td)); + + td->ctrl.td_type = RKCE_TD_TYPE_SYMM; + td->task_id = rkce_cma_virt2phys(buf); + td->key_addr = rkce_cma_virt2phys(buf->key1); + td->iv_addr = rkce_cma_virt2phys(buf->iv); + td->gcm_len_addr = rkce_cma_virt2phys(&buf->gcm_len); + td->tag_addr = rkce_cma_virt2phys(buf->tag); + td->symm_ctx_addr = rkce_cma_virt2phys(buf->ctx); + + return RKCE_SUCCESS; +} + +int rkce_init_hash_td(struct rkce_hash_td *td, struct rkce_hash_td_buf *buf) +{ + if (!td || + !buf || + !rkce_cma_virt2phys(td) || + !rkce_cma_virt2phys(buf)) { + rk_debug("td = %p buf = %p", td, buf); + return -RKCE_INVAL; + } + + memset(td, 0x00, sizeof(*td)); + + td->ctrl.td_type = RKCE_TD_TYPE_HASH; + td->task_id = rkce_cma_virt2phys(buf); + td->key_addr = rkce_cma_virt2phys(buf->key); + td->hash_addr = rkce_cma_virt2phys(buf->hash); + td->hash_ctx_addr = rkce_cma_virt2phys(buf->ctx); + + return RKCE_SUCCESS; +} + +int rkce_irq_callback_set(void *rkce_hw, enum rkce_td_type td_type, request_cb_func cb_func) +{ + struct rkce_hardware *hardware = rkce_hw; + + CHECK_RKCE_INITED(rkce_hw); + + if (!cb_func) + return -RKCE_INVAL; + + if (td_type == RKCE_TD_TYPE_SYMM) + hardware->chn[RKCE_TD_TYPE_SYMM].cb_func = cb_func; + else if (td_type == RKCE_TD_TYPE_HASH) + hardware->chn[RKCE_TD_TYPE_HASH].cb_func = cb_func; + else + return -RKCE_INVAL; + + return RKCE_SUCCESS; +} + +void rkce_irq_handler(void *rkce_hw) +{ + struct rkce_chn_info *cur_chn; + struct RKCE_REG *rkce_reg; + struct rkce_hardware *hardware = rkce_hw; + + CHECK_RKCE_INITED(rkce_hw); + + rkce_reg = GET_RKCE_REG(rkce_hw); + + if (rkce_reg->SYMM_INT_ST) { + cur_chn = &hardware->chn[RKCE_TD_TYPE_SYMM]; + cur_chn->int_st = READ_ONCE(rkce_reg->SYMM_INT_ST); + cur_chn->td_id = rkce_reg->SYMM_TD_ID; + + /* clear symm int */ + WRITE_ONCE(rkce_reg->SYMM_INT_ST, cur_chn->int_st); + + cur_chn->result = (cur_chn->int_st == RKCE_SYMM_INT_ST_TD_DONE_MASK) ? + RKCE_SUCCESS : cur_chn->int_st; + } + + if (rkce_reg->HASH_INT_ST) { + cur_chn = &hardware->chn[RKCE_TD_TYPE_HASH]; + cur_chn->int_st = READ_ONCE(rkce_reg->HASH_INT_ST); + cur_chn->td_id = rkce_reg->HASH_TD_ID; + + /* clear hash int */ + WRITE_ONCE(rkce_reg->HASH_INT_ST, cur_chn->int_st); + + cur_chn->result = (cur_chn->int_st == RKCE_HASH_INT_ST_TD_DONE_MASK) ? + RKCE_SUCCESS : cur_chn->int_st; + } +} + +void rkce_irq_thread(void *rkce_hw) +{ + uint32_t i; + bool is_fault = false; + struct rkce_hardware *hardware = rkce_hw; + + CHECK_RKCE_INITED(rkce_hw); + + for (i = 0; i < ARRAY_SIZE(hardware->chn); i++) { + struct rkce_chn_info *cur_chn = &hardware->chn[i]; + + if (cur_chn->result) { + is_fault = true; + rk_err("td_type = %u, wrong SISR = %08x, td_id = %08x, td_virt = %p\n", + i, cur_chn->int_st, cur_chn->td_id, cur_chn->td_virt); + } + + if (cur_chn->int_st == 0 || !(cur_chn->cb_func)) + continue; + + rk_debug("##################### finalize td %p, result = %d\n", + cur_chn->td_virt, cur_chn->result); + + if (cur_chn->cb_func && cur_chn->td_virt) + cur_chn->cb_func(cur_chn->result, cur_chn->td_id, cur_chn->td_virt); + + cur_chn->result = 0; + cur_chn->int_st = 0; + cur_chn->td_id = 0; + cur_chn->td_virt = NULL; + } + + if (is_fault) + rkce_dump_reginfo(hardware); +} diff --git a/u-boot/drivers/keylad/Kconfig b/u-boot/drivers/keylad/Kconfig new file mode 100644 index 00000000000..d2c3707293a --- /dev/null +++ b/u-boot/drivers/keylad/Kconfig @@ -0,0 +1,9 @@ +menu "Keylad devices" + +config SPL_DM_KEYLAD + bool "Enable Driver Model for KEYLAD drivers in spl" + depends on SPL_DM + ---help--- + This config enables the dm keylad support. + +endmenu diff --git a/u-boot/drivers/keylad/Makefile b/u-boot/drivers/keylad/Makefile new file mode 100644 index 00000000000..21e27be8f27 --- /dev/null +++ b/u-boot/drivers/keylad/Makefile @@ -0,0 +1,6 @@ +# +# Copyright (c) 2025 Rockchip Electronics Co., Ltd +# +# SPDX-License-Identifier: GPL-2.0+ + +obj-$(CONFIG_$(SPL_TPL_)DM_KEYLAD) += keylad-uclass.o rk_keylad.o diff --git a/u-boot/drivers/keylad/keylad-uclass.c b/u-boot/drivers/keylad/keylad-uclass.c new file mode 100644 index 00000000000..9bca1830550 --- /dev/null +++ b/u-boot/drivers/keylad/keylad-uclass.c @@ -0,0 +1,49 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) 2025 Rockchip Electronics Co., Ltd + */ + +#include + +struct udevice *keylad_get_device(void) +{ + const struct dm_keylad_ops *ops; + struct udevice *dev; + struct uclass *uc; + int ret; + + ret = uclass_get(UCLASS_KEYLAD, &uc); + if (ret) + return NULL; + + for (uclass_first_device(UCLASS_KEYLAD, &dev); + dev; + uclass_next_device(&dev)) { + ops = device_get_ops(dev); + if (!ops || !ops->transfer_fwkey) + continue; + + return dev; + } + + return NULL; +} + +int keylad_transfer_fwkey(struct udevice *dev, ulong dst, + enum RK_FW_KEYID fw_keyid, u32 keylen) +{ + const struct dm_keylad_ops *ops = device_get_ops(dev); + + if (!ops || !ops->transfer_fwkey) + return -ENOSYS; + + if (dst == 0) + return -EINVAL; + + return ops->transfer_fwkey(dev, dst, fw_keyid, keylen); +} + +UCLASS_DRIVER(keylad) = { + .id = UCLASS_KEYLAD, + .name = "keylad", +}; diff --git a/u-boot/drivers/keylad/rk_keylad.c b/u-boot/drivers/keylad/rk_keylad.c new file mode 100644 index 00000000000..e7d5fe00607 --- /dev/null +++ b/u-boot/drivers/keylad/rk_keylad.c @@ -0,0 +1,221 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) 2025 Rockchip Electronics Co., Ltd + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +#define KEYLAD_APB_CMD 0x0450 +#define REG_APB_CMD_EN BIT(0) +#define VALUE_APB_CMD_DISABLE 0 +#define VALUE_APB_CMD_ENABLE BIT(0) + +#define KEYLAD_APB_PADDR 0x0454 +#define KEYLAD_APB_PWDATA 0x0458 +#define KEYLAD_APB_PWRITE 0x045C +#define KEYLAD_DATA_CTL 0x0460 +#define VALUE_DATA_CTL_EN BIT(15) + +#define KEYLAD_KEY_SEL 0x0610 +#define VALUE_KEY_SEL_OUTER_KEY 0x00000000 + +#define KEYLAD_LOCKSTEP_FLAG 0x0618 +#define KEYLAD_LOCKSTEP_EN 0x061C + +#define KEY_LADDER_OTP_KEY_REQ 0x0640 +#define KL_OTP_KEY_REQ_DST_ADDR(addr) ((addr) & 0x3) // 256bit algin address +#define KL_OTP_KEY_REQ_BYTE_SWAP BIT(4) +#define KL_OTP_KEY_REQ_WORD_SWAP BIT(5) +#define KL_OTP_KEY_REQ_EN BIT(8) +#define KL_OTP_KEY_ECC_ST BIT(12) +#define KL_OTP_KEY_REQ_SRC_ADDR(addr) (((addr) & 0xffff) << 16)// byte address, dword align + +#define KEY_LADDER_KEY_LEN 0x0648 +#define KL_KEY_LEN(len) ((len) & 0x3f) + +#define KEYLAD_KEY_REG_SIZE_BYTES 4 +#define KEYLAD_KEY_REG_NUM 32 +#define KEYLAD_AREA_NUM 2 + +#define RK_KEYLAD_TIME_OUT 10000 /* max 10ms */ + +#define KEYLAD_POLL_TIMEOUT(condition, timeout, ret) do { \ + u32 time_out = timeout; \ + while (condition) { \ + if (time_out-- == 0) { \ + printf("[%s] %d: time out!\n", __func__, __LINE__); \ + ret = -ETIMEDOUT; \ + break; \ + } \ + udelay(1); \ + } \ +} while (0) + +struct rockchip_keylad_priv { + fdt_addr_t reg; +}; + +fdt_addr_t keylad_base; + +static inline u32 keylad_read(u32 offset) +{ + return readl(keylad_base + offset); +} + +static inline void keylad_write(u32 offset, u32 val) +{ + writel(val, keylad_base + offset); +} + +static int rk_get_fwkey_param(u32 keyid, u32 *offset, u32 *max_len) +{ + switch (keyid) { + case RK_FW_KEY0: + *offset = OEM_CIPHER_KEY_FW_ADDR; + *max_len = OEM_CIPHER_KEY_FW_LEN; + break; + default: + return -EINVAL; + } + + return 0; +} + +static int rk_keylad_send_key(u32 key_reg, u32 n_words, ulong dst_addr) +{ + int ret = 0; + + /* key_reg of 32bits can be 0-31 */ + if ((key_reg + n_words) > KEYLAD_KEY_REG_NUM) + return -EINVAL; + + for (u32 i = 0; i < n_words; i++) { + /* set destination addr */ + keylad_write(KEYLAD_APB_PADDR, + (dst_addr & 0xffffffff) + (i * KEYLAD_KEY_REG_SIZE_BYTES)); + /* select which word of key table to be sent */ + keylad_write(KEYLAD_APB_PWDATA, key_reg + i); + + keylad_write(KEYLAD_APB_CMD, VALUE_APB_CMD_ENABLE); + KEYLAD_POLL_TIMEOUT((keylad_read(KEYLAD_APB_CMD) & REG_APB_CMD_EN) == + VALUE_APB_CMD_ENABLE, RK_KEYLAD_TIME_OUT, ret); + } + + return ret; +} + +static int rk_keylad_read_otp_key(u32 otp_offset, u32 keylad_area, u32 keylen) +{ + int ret = 0; + u32 val = 0; + u32 nbytes = keylen; + + /* keylad_area of 256bits can be 0-1 */ + if (keylad_area >= KEYLAD_AREA_NUM) + return -EINVAL; + +// rk_otp_keylad_read_init(); + + /* src use byte address, dst use keytable block address */ + val = KL_OTP_KEY_REQ_SRC_ADDR(otp_offset / 2) | + KL_OTP_KEY_REQ_DST_ADDR(keylad_area) | + KL_OTP_KEY_REQ_BYTE_SWAP | + KL_OTP_KEY_REQ_EN; + + keylad_write(KEYLAD_KEY_SEL, VALUE_KEY_SEL_OUTER_KEY); + + keylad_write(KEY_LADDER_KEY_LEN, KL_KEY_LEN(nbytes)); + + keylad_write(KEY_LADDER_OTP_KEY_REQ, val); + + KEYLAD_POLL_TIMEOUT(keylad_read(KEY_LADDER_OTP_KEY_REQ) & KL_OTP_KEY_REQ_EN, + RK_KEYLAD_TIME_OUT, ret); + + val = keylad_read(KEY_LADDER_OTP_KEY_REQ); + if (val & KL_OTP_KEY_ECC_ST) { + printf("KEYLAD transfer OTP key ECC check error!"); + ret = -EIO; + } + +// rk_otp_keylad_read_deinit(); + + return ret; +} + +static int rockchip_keylad_transfer_fwkey(struct udevice *dev, ulong dst, + u32 fw_keyid, u32 keylen) +{ + int res = 0; + u32 fw_key_offset; + u32 max_key_len = 0; + + if (keylen % 4) { + printf("key_len(%u) must be multiple of 4 error.", keylen); + return -EINVAL; + } + + res = rk_get_fwkey_param(fw_keyid, &fw_key_offset, &max_key_len); + if (res) + return res; + + if (keylen > max_key_len) { + printf("key_len(%u) > %u error.", keylen, max_key_len); + return -EINVAL; + } + + res = rk_keylad_read_otp_key(fw_key_offset, 0, keylen); + if (res) { + printf("Keyladder read otp key err: 0x%x.", res); + return res; + } + + /// TODO: enable clock + res = rk_keylad_send_key(0, keylen / 4, dst); + if (res) { + printf("Keyladder transfer key err: 0x%x.", res); + return res; + } + + return res; +} + +static const struct dm_keylad_ops rockchip_keylad_ops = { + .transfer_fwkey = rockchip_keylad_transfer_fwkey, +}; + +static int rockchip_keylad_ofdata_to_platdata(struct udevice *dev) +{ + struct rockchip_keylad_priv *priv = dev_get_priv(dev); + + memset(priv, 0x00, sizeof(*priv)); + + priv->reg = (fdt_addr_t)dev_read_addr_ptr(dev); + if (priv->reg == FDT_ADDR_T_NONE) + return -EINVAL; + + keylad_base = priv->reg; + + return 0; +} + +static const struct udevice_id rockchip_keylad_ids[] = { + { + .compatible = "rockchip,keylad", + }, +}; + +U_BOOT_DRIVER(rockchip_keylad) = { + .name = "rockchip_keylad", + .id = UCLASS_KEYLAD, + .of_match = rockchip_keylad_ids, + .ops = &rockchip_keylad_ops, + .ofdata_to_platdata = rockchip_keylad_ofdata_to_platdata, + .priv_auto_alloc_size = sizeof(struct rockchip_keylad_priv), +}; diff --git a/u-boot/drivers/misc/rockchip-otp.c b/u-boot/drivers/misc/rockchip-otp.c index 95c25cde790..b88812b0da4 100644 --- a/u-boot/drivers/misc/rockchip-otp.c +++ b/u-boot/drivers/misc/rockchip-otp.c @@ -506,6 +506,14 @@ static const struct udevice_id rockchip_otp_ids[] = { .compatible = "rockchip,rv1126-otp", .data = (ulong)&rv1126_data, }, + { + .compatible = "rockchip,rv1126b-otp", + .data = (ulong)&rk3568_data, + }, + { + .compatible = "rockchip,rv1103b-otp", + .data = (ulong)&rk3568_data, + }, {} }; diff --git a/u-boot/drivers/mmc/dw_mmc.c b/u-boot/drivers/mmc/dw_mmc.c index a0abf716aae..f6079175459 100644 --- a/u-boot/drivers/mmc/dw_mmc.c +++ b/u-boot/drivers/mmc/dw_mmc.c @@ -163,43 +163,19 @@ static void dwmci_prepare_data(struct dwmci_host *host, dwmci_writel(host, DWMCI_BYTCNT, data->blocksize * data->blocks); } -#ifdef CONFIG_SPL_BUILD -static unsigned int dwmci_get_drto(struct dwmci_host *host, - const unsigned int size) -{ - unsigned int drto_clks; - unsigned int drto_div; - unsigned int drto_ms; - - drto_clks = dwmci_readl(host, DWMCI_TMOUT) >> 8; - drto_div = (dwmci_readl(host, DWMCI_CLKDIV) & 0xff) * 2; - if (drto_div == 0) - drto_div = 1; - - drto_ms = DIV_ROUND_UP_ULL((u64)MSEC_PER_SEC * drto_clks * drto_div, - host->mmc->clock); - - /* add a bit spare time */ - drto_ms += 50; - - return drto_ms; -} -#else static unsigned int dwmci_get_drto(struct dwmci_host *host, const unsigned int size) { unsigned int timeout; timeout = size * 8; /* counting in bits */ - timeout *= 10; /* wait 10 times as long */ - timeout /= host->mmc->clock; timeout /= host->mmc->bus_width; - timeout *= 1000; /* counting in msec */ - timeout = (timeout < 10000) ? 10000 : timeout; + timeout *= 10; /* wait 10 times as long */ + timeout /= (host->mmc->clock / 1000); /* counting in msec */ + timeout = (timeout < 1000) ? 1000 : timeout; return timeout; } -#endif static unsigned int dwmci_get_cto(struct dwmci_host *host) { @@ -310,7 +286,6 @@ read_again: dwmci_writel(host, DWMCI_RINTSTS, mask & (DWMCI_INTMSK_RXDR | DWMCI_INTMSK_DTO)); - start = get_timer(0); } else if (data->flags == MMC_DATA_WRITE && (mask & DWMCI_INTMSK_TXDR)) { while (size) { @@ -340,7 +315,6 @@ write_again: } dwmci_writel(host, DWMCI_RINTSTS, DWMCI_INTMSK_TXDR); - start = get_timer(0); } } diff --git a/u-boot/drivers/mmc/mmc.c b/u-boot/drivers/mmc/mmc.c index 59805d33aa2..7c932f88efe 100644 --- a/u-boot/drivers/mmc/mmc.c +++ b/u-boot/drivers/mmc/mmc.c @@ -2214,11 +2214,17 @@ static int mmc_select_card(struct mmc *mmc, int n) int mmc_start_init(struct mmc *mmc) { + int bus_width = 1; /* * We use the MMC config set by the bootrom. * So it is no need to reset the eMMC device. */ - mmc_set_bus_width(mmc, 8); + if (mmc->cfg->host_caps & MMC_MODE_8BIT) + bus_width = 8; + else if (mmc->cfg->host_caps & MMC_MODE_4BIT) + bus_width = 4; + mmc_set_bus_width(mmc, bus_width); + mmc_set_clock(mmc, 1); mmc_set_timing(mmc, MMC_TIMING_LEGACY); /* Send cmd7 to return stand-by state*/ diff --git a/u-boot/drivers/mmc/rockchip_dw_mmc.c b/u-boot/drivers/mmc/rockchip_dw_mmc.c index df7f053ff5c..fa9d45fd9ef 100644 --- a/u-boot/drivers/mmc/rockchip_dw_mmc.c +++ b/u-boot/drivers/mmc/rockchip_dw_mmc.c @@ -243,7 +243,7 @@ static int rockchip_mmc_set_phase(struct dwmci_host *host, bool sample, int degr if (sample) dwmci_writel(host, SDMMC_TIMING_CON1, HIWORD_UPDATE(raw_value, 0x07ff, 1)); else - dwmci_writel(host, SDMMC_TIMING_CON1, HIWORD_UPDATE(raw_value, 0x07ff, 1)); + dwmci_writel(host, SDMMC_TIMING_CON0, HIWORD_UPDATE(raw_value, 0x07ff, 1)); debug("set %s_phase(%d) delay_nums=%u actual_degrees=%d\n", sample ? "sample" : "drv", degrees, delay_num, @@ -272,7 +272,7 @@ static int rockchip_dwmmc_execute_tuning(struct dwmci_host *host, u32 opcode) int middle_phase, real_middle_phase; ulong ts; - if (!(priv->sample_clk.dev)) + if (!(priv->sample_clk.dev) && priv->usrid != USRID_INTER_PHASE) return -EIO; ts = get_timer(0); diff --git a/u-boot/drivers/mmc/rockchip_sdhci.c b/u-boot/drivers/mmc/rockchip_sdhci.c index 5823205b6d6..373b634a9ce 100644 --- a/u-boot/drivers/mmc/rockchip_sdhci.c +++ b/u-boot/drivers/mmc/rockchip_sdhci.c @@ -672,7 +672,7 @@ static const struct sdhci_data rk3576_data = { .hs200_tx_tap = 16, .hs400_tx_tap = 7, .hs400_cmd_tap = 7, - .hs400_strbin_tap = 5, + .hs400_strbin_tap = 7, .ddr50_strbin_delay_num = 16, }; diff --git a/u-boot/drivers/mtd/mtd_blk.c b/u-boot/drivers/mtd/mtd_blk.c index da6539a1f84..a5eb0611ad1 100644 --- a/u-boot/drivers/mtd/mtd_blk.c +++ b/u-boot/drivers/mtd/mtd_blk.c @@ -31,6 +31,8 @@ #define MTD_BLK_TABLE_BLOCK_UNKNOWN (-2) #define MTD_BLK_TABLE_BLOCK_SHIFT (-1) +#define FACTORY_UNKNOWN_LBA (0xffffffff - 34) + static int *mtd_map_blk_table; #if CONFIG_IS_ENABLED(SUPPORT_USBPLUG) @@ -432,7 +434,8 @@ char *mtd_part_parse(struct blk_desc *dev_desc) strcat(mtd_part_info, ","); if (part_get_info(dev_desc, p + 1, &info)) { /* Partition with grow tag in parameter will be resized */ - if ((info.size + info.start + 64) >= dev_desc->lba) { + if ((info.size + info.start + 64) >= dev_desc->lba || + (info.size + info.start - 1) == FACTORY_UNKNOWN_LBA) { if (dev_desc->devnum == BLK_MTD_SPI_NOR) { /* Nor is 64KB erase block(kernel) and gpt table just * resserve 33 sectors for the last partition. This diff --git a/u-boot/drivers/mtd/nand/spi/core.c b/u-boot/drivers/mtd/nand/spi/core.c index be2b73aa780..a41c4dd4124 100644 --- a/u-boot/drivers/mtd/nand/spi/core.c +++ b/u-boot/drivers/mtd/nand/spi/core.c @@ -289,8 +289,6 @@ static int spinand_read_from_cache_op(struct spinand_device *spinand, if (ret) return ret; - if (spinand->support_cont_read) - op.addr.nbytes = 3; ret = spi_mem_exec_op(spinand->slave, &op); if (ret) return ret; @@ -593,6 +591,7 @@ static int spinand_mtd_read(struct mtd_info *mtd, loff_t from, bool enable_ecc = false; bool ecc_failed = false; int ret = 0; + bool cont_real = spinand->support_cont_read; if (ops->mode != MTD_OPS_RAW && spinand->eccinfo.ooblayout) enable_ecc = true; @@ -610,6 +609,12 @@ static int spinand_mtd_read(struct mtd_info *mtd, loff_t from, if (ret) break; + /* For misaligned situations, temporarily disable the cont read capability */ + if (iter.req.dataoffs) + spinand->support_cont_read = false; + else + spinand->support_cont_read = cont_real; + if (spinand->support_cont_read) { iter.req.datalen = ops->len; iter.req.ooblen = 0; @@ -643,6 +648,8 @@ static int spinand_mtd_read(struct mtd_info *mtd, loff_t from, if (ecc_failed && !ret) ret = -EBADMSG; + spinand->support_cont_read = cont_real; + return ret ? ret : max_bitflips; } diff --git a/u-boot/drivers/mtd/nand/spi/etron.c b/u-boot/drivers/mtd/nand/spi/etron.c index 03a23abad25..0214212e69c 100644 --- a/u-boot/drivers/mtd/nand/spi/etron.c +++ b/u-boot/drivers/mtd/nand/spi/etron.c @@ -78,6 +78,35 @@ static int em73c044vcf_oh_ecc_get_status(struct spinand_device *spinand, return -EINVAL; } +static int em73e044vce_ooblayout_ecc(struct mtd_info *mtd, int section, + struct mtd_oob_region *region) +{ + if (section) + return -ERANGE; + + region->offset = mtd->oobsize / 2; + region->length = mtd->oobsize / 2; + + return 0; +} + +static int em73e044vce_ooblayout_free(struct mtd_info *mtd, int section, + struct mtd_oob_region *region) +{ + if (section) + return -ERANGE; + + region->offset = 2; + region->length = mtd->oobsize / 2 - 2; + + return 0; +} + +static const struct mtd_ooblayout_ops em73e044vce_ooblayout = { + .ecc = em73e044vce_ooblayout_ecc, + .rfree = em73e044vce_ooblayout_free, +}; + static const struct spinand_info etron_spinand_table[] = { SPINAND_INFO("EM73C044VCF-0H", SPINAND_ID(SPINAND_READID_METHOD_OPCODE_ADDR, 0x36), @@ -89,6 +118,15 @@ static const struct spinand_info etron_spinand_table[] = { SPINAND_HAS_QE_BIT, SPINAND_ECCINFO(&em73c044vcf_oh_ooblayout, em73c044vcf_oh_ecc_get_status)), + SPINAND_INFO("EM73E044VCE-H", + SPINAND_ID(SPINAND_READID_METHOD_OPCODE_ADDR, 0x3B), + NAND_MEMORG(1, 2048, 128, 64, 4096, 1, 1, 1), + NAND_ECCREQ(8, 512), + SPINAND_INFO_OP_VARIANTS(&read_cache_variants, + &write_cache_variants, + &update_cache_variants), + SPINAND_HAS_QE_BIT, + SPINAND_ECCINFO(&em73e044vce_ooblayout, em73c044vcf_oh_ecc_get_status)), }; static const struct spinand_manufacturer_ops etron_spinand_manuf_ops = { diff --git a/u-boot/drivers/mtd/nand/spi/gsto.c b/u-boot/drivers/mtd/nand/spi/gsto.c index 882cb2cf758..0482a3e3753 100644 --- a/u-boot/drivers/mtd/nand/spi/gsto.c +++ b/u-boot/drivers/mtd/nand/spi/gsto.c @@ -125,6 +125,15 @@ static const struct spinand_info gsto_spinand_table[] = { &update_cache_variants), 0, SPINAND_ECCINFO(&gss0xgsax1_ooblayout, NULL)), + SPINAND_INFO("GSS01GSBX1", + SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0xCB, 0x13), + NAND_MEMORG(1, 2048, 128, 64, 1024, 1, 1, 1), + NAND_ECCREQ(8, 512), + SPINAND_INFO_OP_VARIANTS(&read_cache_variants, + &write_cache_variants, + &update_cache_variants), + 0, + SPINAND_ECCINFO(&gss0xgsax1_ooblayout, NULL)), }; static const struct spinand_manufacturer_ops gsto_spinand_manuf_ops = { diff --git a/u-boot/drivers/mtd/nand/spi/winbond.c b/u-boot/drivers/mtd/nand/spi/winbond.c index e1ee48a43d8..a04938dcd79 100644 --- a/u-boot/drivers/mtd/nand/spi/winbond.c +++ b/u-boot/drivers/mtd/nand/spi/winbond.c @@ -25,6 +25,16 @@ static SPINAND_OP_VARIANTS(read_cache_variants, SPINAND_PAGE_READ_FROM_CACHE_OP(true, 0, 1, NULL, 0), SPINAND_PAGE_READ_FROM_CACHE_OP(false, 0, 1, NULL, 0)); +#ifdef CONFIG_SPI_NAND_WINBOND_CONT_READ +static SPINAND_OP_VARIANTS(read_cache_variants_cont, + SPINAND_PAGE_READ_FROM_CACHE_QUADIO_OP(0, 2, NULL, 0), + SPINAND_PAGE_READ_FROM_CACHE_X4_OP_3A(0, 1, NULL, 0), + SPINAND_PAGE_READ_FROM_CACHE_DUALIO_OP(0, 1, NULL, 0), + SPINAND_PAGE_READ_FROM_CACHE_X2_OP(0, 1, NULL, 0), + SPINAND_PAGE_READ_FROM_CACHE_OP(true, 0, 1, NULL, 0), + SPINAND_PAGE_READ_FROM_CACHE_OP(false, 0, 1, NULL, 0)); +#endif + static SPINAND_OP_VARIANTS(write_cache_variants, SPINAND_PROG_LOAD_X4(true, 0, NULL, 0), SPINAND_PROG_LOAD(true, 0, NULL, 0)); @@ -154,9 +164,15 @@ static const struct spinand_info winbond_spinand_table[] = { SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0xAA, 0x21), NAND_MEMORG(1, 2048, 64, 64, 1024, 1, 1, 1), NAND_ECCREQ(1, 512), +#ifdef CONFIG_SPI_NAND_WINBOND_CONT_READ + SPINAND_INFO_OP_VARIANTS(&read_cache_variants_cont, + &write_cache_variants, + &update_cache_variants), +#else SPINAND_INFO_OP_VARIANTS(&read_cache_variants, &write_cache_variants, &update_cache_variants), +#endif 0, SPINAND_ECCINFO(&w25m02gv_ooblayout, NULL), SPINAND_SELECT_TARGET(w25m02gv_select_target)), diff --git a/u-boot/drivers/mtd/nand/spi/xtx.c b/u-boot/drivers/mtd/nand/spi/xtx.c index 6275ddddb5c..6c9003c6cc7 100644 --- a/u-boot/drivers/mtd/nand/spi/xtx.c +++ b/u-boot/drivers/mtd/nand/spi/xtx.c @@ -390,6 +390,42 @@ static const struct spinand_info xtx_spinand_table[] = { &update_cache_variants), SPINAND_HAS_QE_BIT, SPINAND_ECCINFO(&xt26g01c_ooblayout, xt26g11c_ecc_get_status)), + SPINAND_INFO("XT26G12DWSIGA", + SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x35), + NAND_MEMORG(1, 2048, 128, 64, 2048, 1, 1, 1), + NAND_ECCREQ(8, 512), + SPINAND_INFO_OP_VARIANTS(&read_cache_variants, + &write_cache_variants, + &update_cache_variants), + SPINAND_HAS_QE_BIT, + SPINAND_ECCINFO(&xt26g01c_ooblayout, xt26g11c_ecc_get_status)), + SPINAND_INFO("XT26Q12DWSIGA", + SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x55), + NAND_MEMORG(1, 2048, 128, 64, 2048, 1, 1, 1), + NAND_ECCREQ(8, 512), + SPINAND_INFO_OP_VARIANTS(&read_cache_variants, + &write_cache_variants, + &update_cache_variants), + SPINAND_HAS_QE_BIT, + SPINAND_ECCINFO(&xt26g01c_ooblayout, xt26g11c_ecc_get_status)), + SPINAND_INFO("XT26G11DWSIGA", + SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x34), + NAND_MEMORG(1, 2048, 128, 64, 1024, 1, 1, 1), + NAND_ECCREQ(8, 512), + SPINAND_INFO_OP_VARIANTS(&read_cache_variants, + &write_cache_variants, + &update_cache_variants), + SPINAND_HAS_QE_BIT, + SPINAND_ECCINFO(&xt26g01c_ooblayout, xt26g11c_ecc_get_status)), + SPINAND_INFO("XT26Q14DWSIGA", + SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x56), + NAND_MEMORG(1, 4096, 256, 64, 2048, 1, 1, 1), + NAND_ECCREQ(8, 512), + SPINAND_INFO_OP_VARIANTS(&read_cache_variants, + &write_cache_variants, + &update_cache_variants), + SPINAND_HAS_QE_BIT, + SPINAND_ECCINFO(&xt26g01c_ooblayout, xt26g11c_ecc_get_status)), }; static const struct spinand_manufacturer_ops xtx_spinand_manuf_ops = { diff --git a/u-boot/drivers/mtd/spi/Kconfig b/u-boot/drivers/mtd/spi/Kconfig index 48f02a22973..fd5c8946998 100644 --- a/u-boot/drivers/mtd/spi/Kconfig +++ b/u-boot/drivers/mtd/spi/Kconfig @@ -181,6 +181,12 @@ config SPI_FLASH_BOYA Add support for various BOYA (BOYA Co., Ltd) SPI flash chips (BY25Qxxxx). +config SPI_FLASH_ZBIT + bool "ZBIT SPI flash support" + help + Add support for various ZBIT (ZBIT Co., Ltd) + SPI flash chips (ZB25Qxxxx). + config SPI_FLASH_NORMEM bool "NORMEM SPI flash support" help diff --git a/u-boot/drivers/mtd/spi/spi-nor-ids.c b/u-boot/drivers/mtd/spi/spi-nor-ids.c index 5111d95de8e..d6dd65bef12 100644 --- a/u-boot/drivers/mtd/spi/spi-nor-ids.c +++ b/u-boot/drivers/mtd/spi/spi-nor-ids.c @@ -88,6 +88,7 @@ const struct flash_info spi_nor_ids[] = { { INFO("en25qh256a", 0x1c7019, 0, 64 * 1024, 512, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) }, { INFO("en25qx256a", 0x1c7119, 0, 64 * 1024, 512, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) }, { INFO("en25qx128a", 0x1c7118, 0, 64 * 1024, 256, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, + { INFO("en25qx64a", 0x1c7117, 0, 64 * 1024, 128, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, #endif #ifdef CONFIG_SPI_FLASH_GIGADEVICE /* GIGADEVICE */ /* GigaDevice */ @@ -526,6 +527,7 @@ const struct flash_info spi_nor_ids[] = { { INFO("XM25QH128C", 0x204018, 0, 64 * 1024, 256, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, { INFO("XM25QH256C", 0x204019, 0, 64 * 1024, 512, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, { INFO("XM25QU128C", 0x204118, 0, 64 * 1024, 256, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, + { INFO("XM25QU256C", 0x204119, 0, 64 * 1024, 512, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, #endif #ifdef CONFIG_SPI_FLASH_XTX /* XTX Technology (Shenzhen) Limited */ @@ -545,6 +547,8 @@ const struct flash_info spi_nor_ids[] = { { INFO("PY25Q128HA", 0x852018, 0, 64 * 1024, 256, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, { INFO("PY25Q256HB", 0x852019, 0, 64 * 1024, 512, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) }, { INFO("PY25Q128LA", 0x856518, 0, 64 * 1024, 256, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, + { INFO("PY25Q256LC", 0x856519, 0, 64 * 1024, 512, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) }, + { INFO("PY25F128LA", 0x856318, 0, 64 * 1024, 256, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, #endif #ifdef CONFIG_SPI_FLASH_FMSH /* FUDAN MICRO (Shanghai) Co., Ltd. */ @@ -561,10 +565,15 @@ const struct flash_info spi_nor_ids[] = { #ifdef CONFIG_SPI_FLASH_BOYA /* Boya Microelectronics Co., Ltd. */ { INFO("BY25Q256FSEIG", 0x684919, 0, 64 * 1024, 512, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) }, + { INFO("BY25Q64ESSIG", 0x684017, 0, 64 * 1024, 128, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, #endif #ifdef CONFIG_SPI_FLASH_NORMEM /* NORMEM Microelectronics Co., Ltd. */ { INFO("NM25Q128EVB", 0x522118, 0, 64 * 1024, 256, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, +#endif +#ifdef CONFIG_SPI_FLASH_ZBIT + /* Zbit Microelectronics Co., Ltd. */ + { INFO("ZB25Q256A", 0x5E4019, 0, 64 * 1024, 512, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) }, #endif { }, }; diff --git a/u-boot/drivers/nvme/nvme.c b/u-boot/drivers/nvme/nvme.c index 4f5abf6a008..a32f18b5a5d 100644 --- a/u-boot/drivers/nvme/nvme.c +++ b/u-boot/drivers/nvme/nvme.c @@ -312,6 +312,9 @@ static int nvme_disable_ctrl(struct nvme_dev *dev) dev->ctrl_config &= ~NVME_CC_ENABLE; writel(dev->ctrl_config, &dev->bar->cc); + if (dev->quirks & NVME_QUIRK_DELAY_BEFORE_CHK_RDY) + mdelay(NVME_QUIRK_DELAY_AMOUNT); + return nvme_wait_ready(dev, false); } @@ -850,9 +853,32 @@ static ulong nvme_blk_erase(struct udevice *udev, lbaint_t blknr, return blkcnt; } +static ulong nvme_blk_write_zeroes(struct udevice *udev, lbaint_t blknr, lbaint_t blkcnt) +{ + struct nvme_ns *ns = dev_get_priv(udev); + struct nvme_dev *dev = ns->dev; + struct nvme_command cmnd; + + if (dev->quirks & NVME_QUIRK_DEALLOCATE_ZEROES) + nvme_blk_erase(udev, blknr, blkcnt); + + memset(&cmnd, 0, sizeof(cmnd)); + + cmnd.write_zeroes.opcode = nvme_cmd_write_zeroes; + cmnd.write_zeroes.nsid = cpu_to_le32(ns->ns_id); + cmnd.write_zeroes.slba = cpu_to_le64(blknr); + cmnd.write_zeroes.length = cpu_to_le16(blkcnt - 1); + cmnd.write_zeroes.control = 0; + cmnd.write_zeroes.command_id = nvme_get_cmd_id(); + + nvme_submit_cmd(dev->queues[NVME_IO_Q], &cmnd); + return blkcnt; +} + static const struct blk_ops nvme_blk_ops = { .read = nvme_blk_read, .write = nvme_blk_write, + .write_zeroes = nvme_blk_write_zeroes, .erase = nvme_blk_erase, }; @@ -874,6 +900,50 @@ static int nvme_bind(struct udevice *udev) return device_set_name(udev, name); } +static const struct pci_device_id nvme_id_table[] = { + { PCI_VDEVICE(INTEL, 0x0953), /* Intel 750/P3500/P3600/P3700 */ + .driver_data = NVME_QUIRK_DEALLOCATE_ZEROES, }, + { PCI_VDEVICE(INTEL, 0x0a53), /* Intel P3520 */ + .driver_data = NVME_QUIRK_DEALLOCATE_ZEROES, }, + { PCI_VDEVICE(INTEL, 0x0a54), /* Intel P4500/P4600 */ + .driver_data = NVME_QUIRK_DEALLOCATE_ZEROES }, + { PCI_VDEVICE(INTEL, 0x0a55), /* Dell Express Flash P4600 */ + .driver_data = NVME_QUIRK_DEALLOCATE_ZEROES, }, + { PCI_DEVICE(0x1bb1, 0x0100), /* Seagate Nytro Flash Storage */ + .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, }, + { PCI_DEVICE(0x1c58, 0x0003), /* HGST adapter */ + .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, }, + { PCI_DEVICE(0x1c58, 0x0023), /* WDC SN200 adapter */ + .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, }, + { PCI_DEVICE(0x1c5f, 0x0540), /* Memblaze Pblaze4 adapter */ + .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, }, + { PCI_DEVICE(0x144d, 0xa821), /* Samsung PM1725 */ + .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, }, + { PCI_DEVICE(0x144d, 0xa822), /* Samsung PM1725a */ + .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, }, + { PCI_DEVICE(0x1987, 0x5013), /* Phison E13 */ + .driver_data = NVME_QUIRK_LIMIT_IOQD32}, +}; + +static void nvme_apply_quirks(struct udevice *udev) +{ + struct nvme_dev *ndev = dev_get_priv(udev); + u16 vendor_id, device_id; + unsigned int i; + + dm_pci_read_config16(udev, PCI_VENDOR_ID, &vendor_id); + dm_pci_read_config16(udev, PCI_DEVICE_ID, &device_id); + + for (i = 0; i < ARRAY_SIZE(nvme_id_table); i++) { + if (vendor_id == nvme_id_table[i].vendor && + device_id == nvme_id_table[i].device) { + ndev->quirks |= nvme_id_table[i].driver_data; + debug("vid 0x%x, pid 0x%x apply quirks 0x%lx\n", + vendor_id, device_id, nvme_id_table[i].driver_data); + } + } +} + static int nvme_probe(struct udevice *udev) { int ret; @@ -899,8 +969,12 @@ static int nvme_probe(struct udevice *udev) } memset(ndev->queues, 0, NVME_Q_NUM * sizeof(struct nvme_queue *)); + nvme_apply_quirks(udev); + ndev->cap = nvme_readq(&ndev->bar->cap); ndev->q_depth = min_t(int, NVME_CAP_MQES(ndev->cap) + 1, NVME_Q_DEPTH); + if (ndev->quirks & NVME_QUIRK_LIMIT_IOQD32) + ndev->q_depth = min_t(int, ndev->q_depth, 32); ndev->db_stride = 1 << NVME_CAP_STRIDE(ndev->cap); ndev->dbs = ((void __iomem *)ndev->bar) + 4096; diff --git a/u-boot/drivers/nvme/nvme.h b/u-boot/drivers/nvme/nvme.h index 88d3f34fa01..e051dbbf285 100644 --- a/u-boot/drivers/nvme/nvme.h +++ b/u-boot/drivers/nvme/nvme.h @@ -305,6 +305,24 @@ struct nvme_dsm_range { __le64 slba; }; +struct nvme_write_zeroes_cmd { + __u8 opcode; + __u8 flags; + __u16 command_id; + __le32 nsid; + __u64 rsvd2; + __le64 metadata; + __le64 prp1; + __le64 prp2; + __le64 slba; + __le16 length; + __le16 control; + __le32 dsmgmt; + __le32 reftag; + __le16 apptag; + __le16 appmask; +}; + /* Admin commands */ enum nvme_admin_opcode { @@ -464,6 +482,7 @@ struct nvme_command { struct nvme_download_firmware dlfw; struct nvme_format_cmd format; struct nvme_dsm_cmd dsm; + struct nvme_write_zeroes_cmd write_zeroes; struct nvme_abort_cmd abort; }; }; @@ -605,6 +624,31 @@ enum { NVME_CSTS_SHST_MASK = 3 << 2, }; +#define NVME_QUIRK_DELAY_AMOUNT 2300 + +/* + * List of workarounds for devices that required behavior not specified in + * the standard. + */ +enum nvme_quirks { + /* + * The controller deterministically returns O's on reads to + * logical blocks that deallocate was called on. + */ + NVME_QUIRK_DEALLOCATE_ZEROES = (1 << 2), + + /* + * The controller needs a delay before starts checking the device + * readiness, which is done by reading the NVME_CSTS_RDY bit. + */ + NVME_QUIRK_DELAY_BEFORE_CHK_RDY = (1 << 3), + + /* + * Limit io queue depth to 32 + */ + NVME_QUIRK_LIMIT_IOQD32 = (1 << 31), +}; + /* Represents an NVM Express device. Each nvme_dev is a PCI function. */ struct nvme_dev { struct list_head node; @@ -614,6 +658,7 @@ struct nvme_dev { unsigned queue_count; unsigned online_queues; unsigned max_qid; + unsigned long quirks; int q_depth; u32 db_stride; u32 ctrl_config; diff --git a/u-boot/drivers/pci/Makefile b/u-boot/drivers/pci/Makefile index 6c9f4cedc2f..13407de58ac 100644 --- a/u-boot/drivers/pci/Makefile +++ b/u-boot/drivers/pci/Makefile @@ -17,6 +17,7 @@ obj-$(CONFIG_PCI) += pci.o pci_auto_old.o endif obj-$(CONFIG_PCI) += pci_auto_common.o pci_common.o +obj-$(CONFIG_PCI) += aer.o obj-$(CONFIG_FSL_PCI_INIT) += fsl_pci_init.o obj-$(CONFIG_PCI_INDIRECT_BRIDGE) += pci_indirect.o obj-$(CONFIG_PCI_GT64120) += pci_gt64120.o diff --git a/u-boot/drivers/pci/aer.c b/u-boot/drivers/pci/aer.c new file mode 100644 index 00000000000..020b5a9ad58 --- /dev/null +++ b/u-boot/drivers/pci/aer.c @@ -0,0 +1,126 @@ +/* + * PCI AER infomation display library + * + * Author: Shawn Lin + * + * Copyright 2025 Rockchip Co., Ltd. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include + +/** + * pci_aer_dump - Parse and print AER information in a human-readable format + * @dev: PCI device + * + * Return: 0 on success, negative error code on failure. + */ +int pci_aer_dump(struct udevice *udev, pci_dev_t dev) +{ + int aer_cap_ptr; + u32 aer_status, aer_mask, aer_severity; + u32 aer_capabilities; + struct dm_pci_ops *ops; + struct udevice *bus; + + /* Find the AER Capability */ + aer_cap_ptr = dm_pci_find_ext_capability(udev, PCI_EXT_CAP_ID_ERR); + if (!aer_cap_ptr) { + printf("AER Capability not found for device %04x:%04x\n", + PCI_BUS(dev), PCI_DEV(dev)); + return -ENODEV; + } + + /* Read AER-related registers */ + dm_pci_read_config32(udev, aer_cap_ptr + PCI_AER_STATUS, &aer_status); + dm_pci_read_config32(udev, aer_cap_ptr + PCI_AER_MASK, &aer_mask); + dm_pci_read_config32(udev, aer_cap_ptr + PCI_AER_SEVERITY, &aer_severity); + dm_pci_read_config32(udev, aer_cap_ptr + 0x18, &aer_capabilities); /* AER Capabilities Register */ + + /* Print AER Capability information */ + printf("AER Capability found at offset 0x%x\n", aer_cap_ptr); + + /* Print Uncorrectable Error Status (UES) */ + printf(" UESta: "); + printf("DLP-%c ", (aer_status & (1 << 0)) ? '+' : '-'); + printf("SDES-%c ", (aer_status & (1 << 1)) ? '+' : '-'); + printf("TLP-%c ", (aer_status & (1 << 2)) ? '+' : '-'); + printf("FCP-%c ", (aer_status & (1 << 3)) ? '+' : '-'); + printf("CmpltTO-%c ", (aer_status & (1 << 4)) ? '+' : '-'); + printf("CmpltAbrt-%c ", (aer_status & (1 << 5)) ? '+' : '-'); + printf("UnxCmplt-%c ", (aer_status & (1 << 6)) ? '+' : '-'); + printf("RxOF-%c ", (aer_status & (1 << 7)) ? '+' : '-'); + printf("MalfTLP-%c ", (aer_status & (1 << 8)) ? '+' : '-'); + printf("ECRC-%c ", (aer_status & (1 << 9)) ? '+' : '-'); + printf("UnsupReq-%c ", (aer_status & (1 << 10)) ? '+' : '-'); + printf("ACSViol-%c\n", (aer_status & (1 << 11)) ? '+' : '-'); + + /* Print Uncorrectable Error Mask (UEMsk) */ + printf(" UEMsk: "); + printf("DLP-%c ", (aer_mask & (1 << 0)) ? '+' : '-'); + printf("SDES-%c ", (aer_mask & (1 << 1)) ? '+' : '-'); + printf("TLP-%c ", (aer_mask & (1 << 2)) ? '+' : '-'); + printf("FCP-%c ", (aer_mask & (1 << 3)) ? '+' : '-'); + printf("CmpltTO-%c ", (aer_mask & (1 << 4)) ? '+' : '-'); + printf("CmpltAbrt-%c ", (aer_mask & (1 << 5)) ? '+' : '-'); + printf("UnxCmplt-%c ", (aer_mask & (1 << 6)) ? '+' : '-'); + printf("RxOF-%c ", (aer_mask & (1 << 7)) ? '+' : '-'); + printf("MalfTLP-%c ", (aer_mask & (1 << 8)) ? '+' : '-'); + printf("ECRC-%c ", (aer_mask & (1 << 9)) ? '+' : '-'); + printf("UnsupReq-%c ", (aer_mask & (1 << 10)) ? '+' : '-'); + printf("ACSViol-%c\n", (aer_mask & (1 << 11)) ? '+' : '-'); + + /* Print Uncorrectable Error Severity (UESvrt) */ + printf(" UESvrt: "); + printf("DLP%c ", (aer_severity & (1 << 0)) ? '+' : '-'); + printf("SDES%c ", (aer_severity & (1 << 1)) ? '+' : '-'); + printf("TLP%c ", (aer_severity & (1 << 2)) ? '+' : '-'); + printf("FCP%c ", (aer_severity & (1 << 3)) ? '+' : '-'); + printf("CmpltTO%c ", (aer_severity & (1 << 4)) ? '+' : '-'); + printf("CmpltAbrt%c ", (aer_severity & (1 << 5)) ? '+' : '-'); + printf("UnxCmplt%c ", (aer_severity & (1 << 6)) ? '+' : '-'); + printf("RxOF%c ", (aer_severity & (1 << 7)) ? '+' : '-'); + printf("MalfTLP%c ", (aer_severity & (1 << 8)) ? '+' : '-'); + printf("ECRC%c ", (aer_severity & (1 << 9)) ? '+' : '-'); + printf("UnsupReq%c ", (aer_severity & (1 << 10)) ? '+' : '-'); + printf("ACSViol%c\n", (aer_severity & (1 << 11)) ? '+' : '-'); + + /* Print Correctable Error Status (CESta) */ + printf(" CESta: "); + printf("RxErr-%c ", (aer_status & (1 << 12)) ? '+' : '-'); + printf("BadTLP-%c ", (aer_status & (1 << 13)) ? '+' : '-'); + printf("BadDLLP-%c ", (aer_status & (1 << 14)) ? '+' : '-'); + printf("Rollover-%c ", (aer_status & (1 << 15)) ? '+' : '-'); + printf("Timeout-%c ", (aer_status & (1 << 16)) ? '+' : '-'); + printf("NonFatalErr-%c\n", (aer_status & (1 << 17)) ? '+' : '-'); + + /* Print Correctable Error Mask (CEMsk) */ + printf(" CEMsk: "); + printf("RxErr-%c ", (aer_mask & (1 << 12)) ? '+' : '-'); + printf("BadTLP-%c ", (aer_mask & (1 << 13)) ? '+' : '-'); + printf("BadDLLP-%c ", (aer_mask & (1 << 14)) ? '+' : '-'); + printf("Rollover-%c ", (aer_mask & (1 << 15)) ? '+' : '-'); + printf("Timeout-%c ", (aer_mask & (1 << 16)) ? '+' : '-'); + printf("NonFatalErr-%c\n", (aer_mask & (1 << 17)) ? '+' : '-'); + + /* Print AER Capabilities (AERCap) */ + printf(" AERCap: "); + printf("First Error Pointer: %02x, ", (aer_capabilities >> 0) & 0x1F); + printf("GenCap%c ", (aer_capabilities & (1 << 5)) ? '+' : '-'); + printf("CGenEn%c ", (aer_capabilities & (1 << 6)) ? '+' : '-'); + printf("ChkCap%c ", (aer_capabilities & (1 << 7)) ? '+' : '-'); + printf("ChkEn%c\n", (aer_capabilities & (1 << 8)) ? '+' : '-'); + + for (bus = udev; device_is_on_pci_bus(bus);) + bus = bus->parent; + + ops = pci_get_ops(bus); + if (ops->vendor_aer_dump) + return ops->vendor_aer_dump(bus); + + return 0; +} diff --git a/u-boot/drivers/pci/pci-uclass.c b/u-boot/drivers/pci/pci-uclass.c index 67c5180b1f0..38bb96c4b5b 100644 --- a/u-boot/drivers/pci/pci-uclass.c +++ b/u-boot/drivers/pci/pci-uclass.c @@ -237,6 +237,163 @@ int dm_pci_find_class(uint find_class, int index, struct udevice **devp) return -ENODEV; } +/** + * pci_retrain_link - Trigger PCIe link retrain for a device + * @udev: PCI device to retrain link + * @dev: PCI device and function address + * + * Return: 0 on success, negative error code on failure. + */ +int pci_retrain_link(struct udevice *udev, pci_dev_t dev) +{ + u16 link_control, link_status; + int pcie_cap_ptr; + int timeout = 100; /* Timeout in milliseconds */ + + /* Find the PCIe Capability */ + pcie_cap_ptr = dm_pci_find_capability(udev, PCI_CAP_ID_EXP); + if (!pcie_cap_ptr) { + printf("PCIe Capability not found for device %04x:%04x\n", + PCI_BUS(dev), PCI_DEV(dev)); + return -ENODEV; + } + + /* Read the Link Control Register */ + dm_pci_read_config16(udev, pcie_cap_ptr + PCI_EXP_LNKCTL, &link_control); + + /* Set the Retrain Link bit (bit 5) */ + link_control |= (1 << 5); + + /* Write the updated value back to the Link Control Register */ + dm_pci_write_config16(udev, pcie_cap_ptr + PCI_EXP_LNKCTL, link_control); + + printf("Retrain triggered for device %04x:%04x\n", PCI_BUS(dev), PCI_DEV(dev)); + + /* Wait for the link to complete training */ + while (timeout--) { + /* Read the Link Status Register */ + dm_pci_read_config16(udev, pcie_cap_ptr + PCI_EXP_LNKSTA, &link_status); + + /* Check if the link is up and training is complete */ + if (!(link_status & PCI_EXP_LNKSTA_LT)) + break; + + mdelay(10); /* Wait 1 millisecond */ + } + + if (link_status & PCI_EXP_LNKSTA_LT) { + printf("Link training failed for device %04x:%04x\n", + PCI_BUS(dev), PCI_DEV(dev)); + return -ETIMEDOUT; + } + + printf("Link Status for device %04x:%04x: 0x%x\n", + PCI_BUS(dev), PCI_DEV(dev), link_status); + printf(" Speed: Gen%d\n", (link_status & PCI_EXP_LNKSTA_CLS) >> 0); + printf(" Width: x%d\n", (link_status & PCI_EXP_LNKSTA_NLW) >> 4); + printf(" Link Up: %s\n", (link_status & PCI_EXP_LNKSTA_LT) ? "No" : "Yes"); + + return 0; +} + +static int pci_is_bridge(pci_dev_t dev) +{ + u8 header_type; + + pci_read_config8(dev, PCI_HEADER_TYPE, &header_type); + header_type = header_type & 0x7f; + + return (header_type == PCI_HEADER_TYPE_BRIDGE); +} + +static void save_pci_state(pci_dev_t dev, struct pci_device_state *state) +{ + int i; + + /* Save BARs */ + for (i = 0; i < 6; i++) + pci_read_config32(dev, PCI_BASE_ADDRESS_0 + i * 4, &state->bar[i]); + + /* Save Command Register */ + pci_read_config16(dev, PCI_COMMAND, &state->command); + + /* Save Bus Numbers (for bridge devices) */ + if (pci_is_bridge(dev)) { + pci_read_config8(dev, PCI_PRIMARY_BUS, &state->primary_bus); + pci_read_config8(dev, PCI_SECONDARY_BUS, &state->secondary_bus); + pci_read_config8(dev, PCI_SUBORDINATE_BUS, &state->subordinate_bus); + } +} + +static void restore_pci_state(pci_dev_t dev, struct pci_device_state *state) +{ + int i; + + /* Restore BARs */ + for (i = 0; i < 6; i++) + pci_write_config32(dev, PCI_BASE_ADDRESS_0 + i * 4, + state->bar[i]); + + /* Restore Command Register */ + pci_write_config16(dev, PCI_COMMAND, state->command); + + /* Restore Bus Numbers (for bridge devices) */ + if (pci_is_bridge(dev)) { + pci_write_config8(dev, PCI_PRIMARY_BUS, state->primary_bus); + pci_write_config8(dev, PCI_SECONDARY_BUS, state->secondary_bus); + pci_write_config8(dev, PCI_SUBORDINATE_BUS, state->subordinate_bus); + } +} + +static int pci_flr(struct udevice *udev, pci_dev_t dev) +{ + u32 pcie_cap; + u16 devctl; + int pos; + + pos = dm_pci_find_capability(udev, PCI_CAP_ID_EXP); + if (!pos) { + printf("PCIe Capability not found\n"); + return -1; + } + + /* Check if FLR is supported */ + dm_pci_read_config32(udev, pos + PCI_EXP_DEVCAP, &pcie_cap); + if (!(pcie_cap & PCI_EXP_DEVCAP_FLR)) { + printf("FLR not supported by device, pos 0x%x, cap 0x%x\n", pos, pcie_cap); + return -1; + } + + devctl = pcie_cap | PCI_EXP_DEVCTL_FLR; + dm_pci_write_config16(udev, pos + PCI_EXP_DEVCTL, devctl); + mdelay(100); + dm_pci_write_config16(udev, pos + PCI_EXP_DEVCTL, pcie_cap); + + return 0; +} + +int pci_reset_function(struct udevice *udev, pci_dev_t dev) +{ + struct pci_device_state state; + + /* Save the current state */ + save_pci_state(dev, &state); + + /* Trigger FLR */ + if (pci_flr(udev, dev)) { + printf("FLR failed\n"); + return -1; + } + + /* Restore the saved state */ + restore_pci_state(dev, &state); + + printf("FLR completed and state restored for device %02x:%02x.%d\n", + PCI_BUS(dev), PCI_DEV(dev), PCI_FUNC(dev)); + + return 0; +} + int pci_bus_write_config(struct udevice *bus, pci_dev_t bdf, int offset, unsigned long value, enum pci_size_t size) { @@ -1239,6 +1396,95 @@ void *dm_pci_map_bar(struct udevice *dev, int bar, int flags) return dm_pci_bus_to_virt(dev, pci_bus_addr, flags, 0, MAP_NOCACHE); } +static int _dm_pci_find_next_capability(struct udevice *dev, u8 pos, int cap) +{ + int ttl = PCI_FIND_CAP_TTL; + u8 id; + u16 ent; + + dm_pci_read_config8(dev, pos, &pos); + + while (ttl--) { + if (pos < PCI_STD_HEADER_SIZEOF) + break; + pos &= ~3; + dm_pci_read_config16(dev, pos, &ent); + + id = ent & 0xff; + if (id == 0xff) + break; + if (id == cap) + return pos; + pos = (ent >> 8); + } + + return 0; +} + +int dm_pci_find_next_capability(struct udevice *dev, u8 start, int cap) +{ + return _dm_pci_find_next_capability(dev, start + PCI_CAP_LIST_NEXT, + cap); +} + +int dm_pci_find_capability(struct udevice *dev, int cap) +{ + u16 status; + u8 header_type; + u8 pos; + + dm_pci_read_config16(dev, PCI_STATUS, &status); + if (!(status & PCI_STATUS_CAP_LIST)) + return 0; + + dm_pci_read_config8(dev, PCI_HEADER_TYPE, &header_type); + if ((header_type & 0x7f) == PCI_HEADER_TYPE_CARDBUS) + pos = PCI_CB_CAPABILITY_LIST; + else + pos = PCI_CAPABILITY_LIST; + + return _dm_pci_find_next_capability(dev, pos, cap); +} + +int dm_pci_find_next_ext_capability(struct udevice *dev, int start, int cap) +{ + u32 header; + int ttl; + int pos = PCI_CFG_SPACE_SIZE; + + /* minimum 8 bytes per capability */ + ttl = (PCI_CFG_SPACE_EXP_SIZE - PCI_CFG_SPACE_SIZE) / 8; + + if (start) + pos = start; + + dm_pci_read_config32(dev, pos, &header); + /* + * If we have no capabilities, this is indicated by cap ID, + * cap version and next pointer all being 0. + */ + if (header == 0) + return 0; + + while (ttl--) { + if (PCI_EXT_CAP_ID(header) == cap) + return pos; + + pos = PCI_EXT_CAP_NEXT(header); + if (pos < PCI_CFG_SPACE_SIZE) + break; + + dm_pci_read_config32(dev, pos, &header); + } + + return 0; +} + +int dm_pci_find_ext_capability(struct udevice *dev, int cap) +{ + return dm_pci_find_next_ext_capability(dev, 0, cap); +} + UCLASS_DRIVER(pci) = { .id = UCLASS_PCI, .name = "pci", diff --git a/u-boot/drivers/pci/pcie_dw_rockchip.c b/u-boot/drivers/pci/pcie_dw_rockchip.c index 99b9d9b8f88..171675afc18 100644 --- a/u-boot/drivers/pci/pcie_dw_rockchip.c +++ b/u-boot/drivers/pci/pcie_dw_rockchip.c @@ -72,6 +72,7 @@ struct rk_pcie { struct pci_region mem; struct pci_region mem64; bool is_bifurcation; + u32 rasdes_off; u32 gen; u32 lanes; }; @@ -87,6 +88,7 @@ enum { /* Parameters for the waiting for iATU enabled routine */ #define PCIE_CLIENT_GENERAL_DEBUG 0x104 +#define PCIE_CLIENT_CDM_RASDES_TBA_INFO_CMN 0x154 #define PCIE_CLIENT_HOT_RESET_CTRL 0x180 #define PCIE_LTSSM_ENABLE_ENHANCE BIT(4) #define PCIE_CLIENT_LTSSM_STATUS 0x300 @@ -246,6 +248,41 @@ static inline void rk_pcie_writel_apb(struct rk_pcie *rk_pcie, u32 reg, __rk_pcie_write_apb(rk_pcie, rk_pcie->apb_base, reg, 0x4, val); } +static int rk_pci_find_ext_capability(struct rk_pcie *rk_pcie, int cap) +{ + u32 header; + int ttl; + int start = 0; + int pos = PCI_CFG_SPACE_SIZE; + + /* minimum 8 bytes per capability */ + ttl = (PCI_CFG_SPACE_EXP_SIZE - PCI_CFG_SPACE_SIZE) / 8; + + header = readl(rk_pcie->dbi_base + pos); + + /* + * If we have no capabilities, this is indicated by cap ID, + * cap version and next pointer all being 0. + */ + if (header == 0) + return 0; + + while (ttl-- > 0) { + if (PCI_EXT_CAP_ID(header) == cap && pos != start) + return pos; + + pos = PCI_EXT_CAP_NEXT(header); + if (pos < PCI_CFG_SPACE_SIZE) + break; + + header = readl(rk_pcie->dbi_base + pos); + if (!header) + break; + } + + return 0; +} + static int rk_pcie_get_link_speed(struct rk_pcie *rk_pcie) { return (readl(rk_pcie->dbi_base + PCIE_LINK_STATUS_REG) & @@ -931,15 +968,88 @@ static int rockchip_pcie_probe(struct udevice *dev) priv->mem.phys_start, priv->mem.bus_start, priv->mem.size); + priv->rasdes_off = rk_pci_find_ext_capability(priv, PCI_EXT_CAP_ID_VNDR); + if (priv->rasdes_off) { + /* Enable RC's err dump */ + writel(0x1c, priv->dbi_base + priv->rasdes_off + 8); + writel(0x3, priv->dbi_base + priv->rasdes_off + 8); + } + return 0; free_rst: dm_gpio_free(dev, &priv->rst_gpio); return ret; } +#define RAS_DES_EVENT(ss, v) \ +do { \ + writel(v, priv->dbi_base + cap_base + 8); \ + printf(ss "0x%x\n", readl(priv->dbi_base + cap_base + 0xc)); \ +} while (0) + +static int rockchip_pcie_err_dump(struct udevice *bus) +{ + struct rk_pcie *priv = dev_get_priv(bus); + u32 val = rk_pcie_readl_apb(priv, PCIE_CLIENT_CDM_RASDES_TBA_INFO_CMN); + int cap_base; + char *pm; + + if (val & BIT(6)) + pm = "In training"; + else if (val & BIT(5)) + pm = "L1.2"; + else if (val & BIT(4)) + pm = "L1.1"; + else if (val & BIT(3)) + pm = "L1"; + else if (val & BIT(2)) + pm = "L0"; + else if (val & 0x3) + pm = (val == 0x3) ? "L0s" : (val & BIT(1) ? "RX L0s" : "TX L0s"); + else + pm = "Invalid"; + + printf("Common event signal status: %s\n", pm); + + cap_base = priv->rasdes_off; + if (!priv->rasdes_off) + return 0; + + RAS_DES_EVENT("EBUF Overflow: ", 0); + RAS_DES_EVENT("EBUF Under-run: ", 0x0010000); + RAS_DES_EVENT("Decode Error: ", 0x0020000); + RAS_DES_EVENT("Running Disparity Error: ", 0x0030000); + RAS_DES_EVENT("SKP OS Parity Error: ", 0x0040000); + RAS_DES_EVENT("SYNC Header Error: ", 0x0050000); + RAS_DES_EVENT("CTL SKP OS Parity Error: ", 0x0060000); + RAS_DES_EVENT("Detect EI Infer: ", 0x1050000); + RAS_DES_EVENT("Receiver Error: ", 0x1060000); + RAS_DES_EVENT("Rx Recovery Request: ", 0x1070000); + RAS_DES_EVENT("N_FTS Timeout: ", 0x1080000); + RAS_DES_EVENT("Framing Error: ", 0x1090000); + RAS_DES_EVENT("Deskew Error: ", 0x10a0000); + RAS_DES_EVENT("BAD TLP: ", 0x2000000); + RAS_DES_EVENT("LCRC Error: ", 0x2010000); + RAS_DES_EVENT("BAD DLLP: ", 0x2020000); + RAS_DES_EVENT("Replay Number Rollover: ", 0x2030000); + RAS_DES_EVENT("Replay Timeout: ", 0x2040000); + RAS_DES_EVENT("Rx Nak DLLP: ", 0x2050000); + RAS_DES_EVENT("Tx Nak DLLP: ", 0x2060000); + RAS_DES_EVENT("Retry TLP: ", 0x2070000); + RAS_DES_EVENT("FC Timeout: ", 0x3000000); + RAS_DES_EVENT("Poisoned TLP: ", 0x3010000); + RAS_DES_EVENT("ECRC Error: ", 0x3020000); + RAS_DES_EVENT("Unsupported Request: ", 0x3030000); + RAS_DES_EVENT("Completer Abort: ", 0x3040000); + RAS_DES_EVENT("Completion Timeout: ", 0x3050000); + + return 0; +} + static const struct dm_pci_ops rockchip_pcie_ops = { .read_config = rockchip_pcie_rd_conf, .write_config = rockchip_pcie_wr_conf, + .vendor_aer_dump = rockchip_pcie_err_dump, }; static const struct udevice_id rockchip_pcie_ids[] = { diff --git a/u-boot/drivers/phy/phy-rockchip-inno-usb2.c b/u-boot/drivers/phy/phy-rockchip-inno-usb2.c index b4f055bcf86..63f59ebf016 100644 --- a/u-boot/drivers/phy/phy-rockchip-inno-usb2.c +++ b/u-boot/drivers/phy/phy-rockchip-inno-usb2.c @@ -904,6 +904,29 @@ static int rv1106_usb2phy_tuning(struct rockchip_usb2phy *rphy) return 0; } +static int rv1126b_usb2phy_tuning(struct rockchip_usb2phy *rphy) +{ + /* Turn off differential receiver by default to save power */ + phy_clear_bits(rphy->phy_base + 0x0030, BIT(2)); + phy_clear_bits(rphy->phy_base + 0x0430, BIT(2)); + + /* Enable pre-emphasis during non-chirp phase */ + phy_update_bits(rphy->phy_base, GENMASK(2, 0), 0x04); + phy_update_bits(rphy->phy_base + 0x0400, GENMASK(2, 0), 0x04); + + /* Set HS eye height to 425mv(default is 400mv) */ + phy_update_bits(rphy->phy_base + 0x0030, GENMASK(6, 4), (0x05 << 4)); + phy_update_bits(rphy->phy_base + 0x0430, GENMASK(6, 4), (0x05 << 4)); + + /* Set Rx squelch trigger point configure to 112.5mv */ + phy_update_bits(rphy->phy_base + 0x0004, GENMASK(7, 5), (0x00 << 5)); + phy_update_bits(rphy->phy_base + 0x0008, GENMASK(0, 0), (0x00 << 0)); + phy_update_bits(rphy->phy_base + 0x0404, GENMASK(7, 5), (0x00 << 5)); + phy_update_bits(rphy->phy_base + 0x0408, GENMASK(0, 0), (0x00 << 0)); + + return 0; +} + static int rk3506_usb2phy_tuning(struct rockchip_usb2phy *rphy) { /* Turn off otg0 port differential receiver in suspend mode */ @@ -1648,6 +1671,58 @@ static const struct rockchip_usb2phy_cfg rv1108_phy_cfgs[] = { { /* sentinel */ } }; +static const struct rockchip_usb2phy_cfg rv1126b_phy_cfgs[] = { + { + .reg = 0x21400000, + .num_ports = 2, + .phy_tuning = rv1126b_usb2phy_tuning, + .clkout_ctl = { 0x10028, 3, 3, 1, 0 }, + .port_cfgs = { + [USB2PHY_PORT_OTG] = { + .phy_sus = { 0x10020, 8, 0, 0, 0x1d1 }, + .bvalid_det_en = { 0x10074, 2, 2, 0, 1 }, + .bvalid_det_st = { 0x10078, 2, 2, 0, 1 }, + .bvalid_det_clr = { 0x1007c, 2, 2, 0, 1 }, + .iddig_output = { 0x10020, 10, 10, 0, 1 }, + .iddig_en = { 0x10020, 9, 9, 0, 1 }, + .idfall_det_en = { 0x10074, 5, 5, 0, 1 }, + .idfall_det_st = { 0x10078, 5, 5, 0, 1 }, + .idfall_det_clr = { 0x1007c, 5, 5, 0, 1 }, + .idrise_det_en = { 0x10074, 4, 4, 0, 1 }, + .idrise_det_st = { 0x10078, 4, 4, 0, 1 }, + .idrise_det_clr = { 0x1007c, 4, 4, 0, 1 }, + .ls_det_en = { 0x10074, 0, 0, 0, 1 }, + .ls_det_st = { 0x10078, 0, 0, 0, 1 }, + .ls_det_clr = { 0x1007c, 0, 0, 0, 1 }, + .utmi_avalid = { 0x10110, 1, 1, 0, 1 }, + .utmi_bvalid = { 0x10110, 0, 0, 0, 1 }, + .utmi_iddig = { 0x10110, 6, 6, 0, 1 }, + .utmi_ls = { 0x10110, 5, 4, 0, 1 }, + }, + [USB2PHY_PORT_HOST] = { + .phy_sus = { 0x1001c, 8, 0, 0x1d2, 0x1d1 }, + .ls_det_en = { 0x10090, 0, 0, 0, 1 }, + .ls_det_st = { 0x10094, 0, 0, 0, 1 }, + .ls_det_clr = { 0x10098, 0, 0, 0, 1 }, + .utmi_ls = { 0x10110, 13, 12, 0, 1 }, + } + }, + .chg_det = { + .opmode = { 0x10020, 3, 0, 5, 1 }, + .cp_det = { 0x10110, 19, 19, 0, 1 }, + .dcp_det = { 0x10110, 18, 18, 0, 1 }, + .dp_det = { 0x10110, 20, 20, 0, 1 }, + .idm_sink_en = { 0x1002c, 1, 1, 0, 1 }, + .idp_sink_en = { 0x1002c, 0, 0, 0, 1 }, + .idp_src_en = { 0x1002c, 2, 2, 0, 1 }, + .rdm_pdwn_en = { 0x1002c, 3, 3, 0, 1 }, + .vdm_src_en = { 0x1002c, 5, 5, 0, 1 }, + .vdp_src_en = { 0x1002c, 4, 4, 0, 1 }, + }, + }, + { /* sentinel */ } +}; + static const struct rockchip_usb2phy_cfg rk3506_phy_cfgs[] = { { .reg = 0xff2b0000, @@ -2064,6 +2139,9 @@ static const struct udevice_id rockchip_usb2phy_ids[] = { #endif #ifdef CONFIG_ROCKCHIP_RV1108 { .compatible = "rockchip,rv1108-usb2phy", .data = (ulong)&rv1108_phy_cfgs }, +#endif +#ifdef CONFIG_ROCKCHIP_RV1126B + { .compatible = "rockchip,rv1126b-usb2phy", .data = (ulong)&rv1126b_phy_cfgs }, #endif { } }; diff --git a/u-boot/drivers/phy/phy-rockchip-naneng-combphy.c b/u-boot/drivers/phy/phy-rockchip-naneng-combphy.c index aa2378354aa..b325dec99b0 100644 --- a/u-boot/drivers/phy/phy-rockchip-naneng-combphy.c +++ b/u-boot/drivers/phy/phy-rockchip-naneng-combphy.c @@ -63,6 +63,7 @@ struct rockchip_combphy_grfcfg { struct combphy_reg pipe_con1_for_sata; struct combphy_reg pipe_sgmii_mac_sel; struct combphy_reg pipe_xpcs_phy_ready; + struct combphy_reg u3otg0_clamp_dis; struct combphy_reg u3otg0_port_en; struct combphy_reg u3otg1_port_en; struct combphy_reg u3otg0_pipe_clk_sel; @@ -149,6 +150,9 @@ static int rockchip_combphy_usb3_init(struct rockchip_combphy_priv *priv) param_write(priv->phy_grf, &cfg->usb_mode_set, true); #endif return ret; + } else { + if (cfg->u3otg0_clamp_dis.enable) + param_write(priv->pipe_grf, &cfg->u3otg0_clamp_dis, true); } if (priv->cfg->combphy_cfg) { @@ -581,6 +585,19 @@ static int rk3562_combphy_cfg(struct rockchip_combphy_priv *priv) writel(0xf0, priv->mmio + (0xa << 2)); } + if (dev_read_bool(priv->dev, "rockchip,ext-refclk")) { + param_write(priv->phy_grf, &cfg->pipe_clk_ext, true); + if (priv->mode == PHY_TYPE_PCIE) { + val = readl(priv->mmio + (0xc << 2)); + val |= 0x3 << 4 | 0x1 << 7; + writel(val, priv->mmio + (0xc << 2)); + + val = readl(priv->mmio + (0xd << 2)); + val |= 0x1; + writel(val, priv->mmio + (0xd << 2)); + } + } + if (dev_read_bool(priv->dev, "rockchip,enable-ssc")) { val = readl(priv->mmio + (0x7 << 2)); val |= BIT(4); @@ -1045,6 +1062,95 @@ static const struct rockchip_combphy_cfg rk3576_combphy_cfgs = { }; #endif +#ifdef CONFIG_ROCKCHIP_RV1126B +static int rv1126b_combphy_cfg(struct rockchip_combphy_priv *priv) +{ + const struct rockchip_combphy_grfcfg *cfg = priv->cfg->grfcfg; + u32 val; + + switch (priv->mode) { + case PHY_TYPE_USB3: + /* Set SSC downward spread spectrum */ + val = readl(priv->mmio + (0x1f << 2)); + val &= ~GENMASK(5, 4); + val |= 0x01 << 4; + writel(val, priv->mmio + 0x7c); + + /* Enable adaptive CTLE for USB3.0 Rx */ + val = readl(priv->mmio + (0x0e << 2)); + val &= ~GENMASK(0, 0); + val |= 0x01; + writel(val, priv->mmio + (0x0e << 2)); + + /* Set PLL KVCO fine tuning signals */ + val = readl(priv->mmio + (0x20 << 2)); + val &= ~(0x7 << 2); + val |= 0x2 << 2; + writel(val, priv->mmio + (0x20 << 2)); + + /* Set PLL LPF R1 to su_trim[10:7]=1001 */ + writel(0x4, priv->mmio + (0x0b << 2)); + + /* Set PLL input clock divider 1/2 */ + val = readl(priv->mmio + (0x5 << 2)); + val &= ~(0x3 << 6); + val |= 0x1 << 6; + writel(val, priv->mmio + (0x5 << 2)); + + /* Set PLL loop divider */ + writel(0x32, priv->mmio + (0x11 << 2)); + + /* Set PLL KVCO to min and set PLL charge pump current to max */ + writel(0xf0, priv->mmio + (0x0a << 2)); + + /* Set Rx squelch input filler bandwidth */ + writel(0x0e, priv->mmio + (0x14 << 2)); + + param_write(priv->phy_grf, &cfg->pipe_sel_usb, true); + param_write(priv->phy_grf, &cfg->pipe_txcomp_sel, false); + param_write(priv->phy_grf, &cfg->pipe_txelec_sel, false); + param_write(priv->phy_grf, &cfg->usb_mode_set, true); + break; + default: + dev_err(priv->dev, "incompatible PHY type\n"); + return -EINVAL; + } + + clk_set_rate(&priv->ref_clk, 100000000); + param_write(priv->phy_grf, &cfg->pipe_clk_100m, true); + + return 0; +} + +static const struct rockchip_combphy_grfcfg rv1126b_combphy_grfcfgs = { + /* pipe-phy-grf */ + .usb_mode_set = { 0x18000, 5, 0, 0x00, 0x04 }, + .pipe_rxterm_set = { 0x18000, 12, 12, 0x00, 0x01 }, + .pipe_txelec_set = { 0x18004, 1, 1, 0x00, 0x01 }, + .pipe_txcomp_set = { 0x18004, 4, 4, 0x00, 0x01 }, + .pipe_clk_25m = { 0x18004, 14, 13, 0x00, 0x01 }, + .pipe_clk_100m = { 0x18004, 14, 13, 0x00, 0x02 }, + .pipe_phymode_sel = { 0x18008, 1, 1, 0x00, 0x01 }, + .pipe_rate_sel = { 0x18008, 2, 2, 0x00, 0x01 }, + .pipe_rxterm_sel = { 0x18008, 8, 8, 0x00, 0x01 }, + .pipe_txelec_sel = { 0x18008, 12, 12, 0x00, 0x01 }, + .pipe_txcomp_sel = { 0x18008, 15, 15, 0x00, 0x01 }, + .pipe_clk_ext = { 0x1800c, 9, 8, 0x02, 0x01 }, + .pipe_sel_usb = { 0x1800c, 14, 13, 0x00, 0x01 }, + .pipe_phy_status = { 0x18034, 6, 6, 0x01, 0x00 }, + /* peri-grf */ + .u3otg0_port_en = { 0x1003c, 15, 0, 0x0189, 0x1100 }, + /* pmu-grf */ + .u3otg0_clamp_dis = { 0x30000, 14, 14, 0x00, 0x01 }, +}; + +static const struct rockchip_combphy_cfg rv1126b_combphy_cfgs = { + .grfcfg = &rv1126b_combphy_grfcfgs, + .combphy_cfg = rv1126b_combphy_cfg, + .force_det_out = true, +}; +#endif + static const struct udevice_id rockchip_combphy_ids[] = { #ifdef CONFIG_ROCKCHIP_RK3528 { @@ -1075,6 +1181,12 @@ static const struct udevice_id rockchip_combphy_ids[] = { .compatible = "rockchip,rk3576-naneng-combphy", .data = (ulong)&rk3576_combphy_cfgs }, +#endif +#ifdef CONFIG_ROCKCHIP_RV1126B + { + .compatible = "rockchip,rv1126b-usb3-phy", + .data = (ulong)&rv1126b_combphy_cfgs + }, #endif { } }; diff --git a/u-boot/drivers/phy/phy-rockchip-samsung-hdptx.c b/u-boot/drivers/phy/phy-rockchip-samsung-hdptx.c index 2966d026791..46050923133 100644 --- a/u-boot/drivers/phy/phy-rockchip-samsung-hdptx.c +++ b/u-boot/drivers/phy/phy-rockchip-samsung-hdptx.c @@ -332,6 +332,7 @@ struct rockchip_hdptx_phy { struct reset_ctl init_reset; struct reset_ctl lane_reset; u32 lane_polarity_invert[4]; + bool dp_mode; }; enum { @@ -542,6 +543,62 @@ static struct tx_drv_ctrl tx_drv_ctrl_r432[4][4] = { } }; +static struct tx_drv_ctrl tx_drv_ctrl_rbr_dp_mode[4][4] = { + /* voltage swing 0, pre-emphasis 0->3 */ + { + { 0x2, 0x0, 0x2, 0x2, 0x1, 0x4, 0x1, 0x1, 0x7, 0x7 }, + { 0x4, 0x3, 0x4, 0x6, 0x0, 0x4, 0x0, 0x1, 0x7, 0x7 }, + { 0x7, 0x6, 0x4, 0x6, 0x0, 0x4, 0x0, 0x1, 0x7, 0x7 }, + { 0xd, 0xb, 0x1, 0x1, 0x1, 0x7, 0x0, 0x1, 0x7, 0x7 }, + }, + + /* voltage swing 1, pre-emphasis 0->2 */ + { + { 0x4, 0x0, 0x4, 0x4, 0x1, 0x4, 0x1, 0x1, 0x7, 0x7 }, + { 0x9, 0x5, 0x4, 0x6, 0x0, 0x4, 0x0, 0x1, 0x7, 0x7 }, + { 0xc, 0x9, 0x2, 0x2, 0x1, 0x7, 0x0, 0x1, 0x7, 0x7 }, + }, + + /* voltage swing 2, pre-emphasis 0->1 */ + { + { 0x8, 0x0, 0x4, 0x6, 0x0, 0x4, 0x1, 0x1, 0x7, 0x7 }, + { 0xc, 0x5, 0x3, 0x3, 0x1, 0x7, 0x0, 0x1, 0x7, 0x7 }, + }, + + /* voltage swing 3, pre-emphasis 0 */ + { + { 0xb, 0x0, 0x7, 0x7, 0x1, 0x4, 0x1, 0x1, 0x7, 0x7 }, + } +}; + +static struct tx_drv_ctrl tx_drv_ctrl_hbr_dp_mode[4][4] = { + /* voltage swing 0, pre-emphasis 0->3 */ + { + { 0x2, 0x0, 0x1, 0x1, 0x0, 0x4, 0x1, 0x1, 0x7, 0x7 }, + { 0x5, 0x4, 0x4, 0x6, 0x0, 0x4, 0x0, 0x1, 0x7, 0x7 }, + { 0x9, 0x8, 0x4, 0x6, 0x0, 0x4, 0x0, 0x1, 0x7, 0x7 }, + { 0xd, 0xc, 0x1, 0x1, 0x1, 0x7, 0x0, 0x1, 0x7, 0x7 }, + }, + + /* voltage swing 1, pre-emphasis 0->2 */ + { + { 0x6, 0x1, 0x2, 0x2, 0x0, 0x4, 0x1, 0x1, 0x7, 0x7 }, + { 0xa, 0x6, 0x4, 0x6, 0x0, 0x4, 0x0, 0x1, 0x7, 0x7 }, + { 0xc, 0x9, 0x2, 0x2, 0x1, 0x7, 0x0, 0x1, 0x7, 0x7 }, + }, + + /* voltage swing 2, pre-emphasis 0->1 */ + { + { 0x9, 0x1, 0x4, 0x6, 0x0, 0x4, 0x1, 0x1, 0x7, 0x7 }, + { 0xd, 0x6, 0x3, 0x3, 0x1, 0x7, 0x0, 0x1, 0x7, 0x7 }, + }, + + /* voltage swing 3, pre-emphasis 0 */ + { + { 0xc, 0x1, 0x7, 0x7, 0x1, 0x4, 0x1, 0x1, 0x7, 0x7 }, + } +}; + /* pll configurations for link rate R216/R243/R324/R432 */ static const struct tx_pll_ctrl tx_pll_ctrl_extra[4] = { { 0x5a, 0x01, 0x32, 0x00, 0x00, 0x00, 0x01, 0x04, 0x0d, 0x1d }, /* R216 */ @@ -598,6 +655,10 @@ static inline void rockchip_grf_write(struct regmap *grf, uint reg, uint mask, static int rockchip_hdptx_phy_set_mode(struct phy *phy, enum phy_mode mode, int submode) { + struct rockchip_hdptx_phy *hdptx = dev_get_priv(phy->dev); + + hdptx->dp_mode = (submode == PHY_SUBMODE_DP); + return 0; } @@ -651,7 +712,10 @@ static void rockchip_hdptx_phy_set_voltage(struct rockchip_hdptx_phy *hdptx, switch (dp->link_rate) { case 1620: - ctrl = &tx_drv_ctrl_rbr[dp->voltage[lane]][dp->pre[lane]]; + if (hdptx->dp_mode) + ctrl = &tx_drv_ctrl_rbr_dp_mode[dp->voltage[lane]][dp->pre[lane]]; + else + ctrl = &tx_drv_ctrl_rbr[dp->voltage[lane]][dp->pre[lane]]; regmap_update_bits(hdptx->regmap, LANE_REG(lane, 0x0c44), LN_TX_SER_40BIT_EN_RBR, FIELD_PREP(LN_TX_SER_40BIT_EN_RBR, 0x1)); @@ -676,7 +740,10 @@ static void rockchip_hdptx_phy_set_voltage(struct rockchip_hdptx_phy *hdptx, FIELD_PREP(LN_TX_JEQ_ODD_CTRL_HBR, ctrl->tx_jeq_odd_ctrl)); break; case 2700: - ctrl = &tx_drv_ctrl_hbr[dp->voltage[lane]][dp->pre[lane]]; + if (hdptx->dp_mode) + ctrl = &tx_drv_ctrl_hbr_dp_mode[dp->voltage[lane]][dp->pre[lane]]; + else + ctrl = &tx_drv_ctrl_hbr[dp->voltage[lane]][dp->pre[lane]]; regmap_update_bits(hdptx->regmap, LANE_REG(lane, 0x0c44), LN_TX_SER_40BIT_EN_HBR, FIELD_PREP(LN_TX_SER_40BIT_EN_HBR, 0x1)); diff --git a/u-boot/drivers/phy/phy-rockchip-usbdp.c b/u-boot/drivers/phy/phy-rockchip-usbdp.c index 1d41c40e25f..a287abbff48 100644 --- a/u-boot/drivers/phy/phy-rockchip-usbdp.c +++ b/u-boot/drivers/phy/phy-rockchip-usbdp.c @@ -11,6 +11,7 @@ #include #include #include +#include #include #include #include @@ -1209,23 +1210,36 @@ static const struct phy_ops rockchip_u3phy_ops = { .exit = rockchip_u3phy_exit, }; -int rockchip_u3phy_uboot_init(void) +int rockchip_u3phy_uboot_init(fdt_addr_t phy_addr) { - struct udevice *udev; + struct udevice *udev = NULL; + struct udevice *dev; + struct uclass *uc; + const struct driver *find_drv; struct rockchip_udphy *udphy; unsigned int val; int ret; - ret = uclass_get_device_by_driver(UCLASS_PHY, - DM_GET_DRIVER(rockchip_udphy_u3_port), - &udev); - if (ret) { - pr_err("%s: get u3-port failed: %d\n", __func__, ret); + ret = uclass_get(UCLASS_PHY, &uc); + if (ret) + return ret; + + find_drv = DM_GET_DRIVER(rockchip_udphy); + list_for_each_entry(dev, &uc->dev_head, uclass_node) { + if (dev->driver == find_drv && dev_read_addr(dev) == phy_addr) { + ret = uclass_get_device_tail(dev, 0, &udev); + break; + } + } + + if (!udev || ret) { + ret = ret ? ret : -ENODEV; + pr_err("%s: get usb3-phy node failed: %d\n", __func__, ret); return ret; } /* DP only or high-speed, disable U3 port */ - udphy = dev_get_priv(udev->parent); + udphy = dev_get_priv(udev); if (!(udphy->mode & UDPHY_MODE_USB) || udphy->hs) { pr_err("%s: udphy mode not support usb3\n", __func__); goto disable_u3; diff --git a/u-boot/drivers/pinctrl/pinctrl-rockchip.c b/u-boot/drivers/pinctrl/pinctrl-rockchip.c index ee3e4f3ab59..ccee25e2168 100644 --- a/u-boot/drivers/pinctrl/pinctrl-rockchip.c +++ b/u-boot/drivers/pinctrl/pinctrl-rockchip.c @@ -706,23 +706,68 @@ static struct rockchip_mux_recalced_data rk3308b_mux_recalced_data[] = { static struct rockchip_mux_recalced_data rk3328_mux_recalced_data[] = { { - .num = 2, - .pin = 12, - .reg = 0x24, - .bit = 8, - .mask = 0x3 - }, { + /* gpio2_b7_sel */ .num = 2, .pin = 15, .reg = 0x28, .bit = 0, .mask = 0x7 }, { + /* gpio2_c7_sel */ .num = 2, .pin = 23, .reg = 0x30, .bit = 14, .mask = 0x3 + }, { + /* gpio3_b1_sel */ + .num = 3, + .pin = 9, + .reg = 0x44, + .bit = 2, + .mask = 0x3 + }, { + /* gpio3_b2_sel */ + .num = 3, + .pin = 10, + .reg = 0x44, + .bit = 4, + .mask = 0x3 + }, { + /* gpio3_b3_sel */ + .num = 3, + .pin = 11, + .reg = 0x44, + .bit = 6, + .mask = 0x3 + }, { + /* gpio3_b4_sel */ + .num = 3, + .pin = 12, + .reg = 0x44, + .bit = 8, + .mask = 0x3 + }, { + /* gpio3_b5_sel */ + .num = 3, + .pin = 13, + .reg = 0x44, + .bit = 10, + .mask = 0x3 + }, { + /* gpio3_b6_sel */ + .num = 3, + .pin = 14, + .reg = 0x44, + .bit = 12, + .mask = 0x3 + }, { + /* gpio3_b7_sel */ + .num = 3, + .pin = 15, + .reg = 0x44, + .bit = 14, + .mask = 0x3 }, }; @@ -3648,7 +3693,7 @@ static struct rockchip_pin_bank rk3328_pin_banks[] = { PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", 0, 0, 0, 0), PIN_BANK_IOMUX_FLAGS(1, 32, "gpio1", 0, 0, 0, 0), PIN_BANK_IOMUX_FLAGS(2, 32, "gpio2", 0, - IOMUX_WIDTH_3BIT, + IOMUX_8WIDTH_2BIT, IOMUX_WIDTH_3BIT, 0), PIN_BANK_IOMUX_FLAGS(3, 32, "gpio3", diff --git a/u-boot/drivers/pinctrl/rockchip/Makefile b/u-boot/drivers/pinctrl/rockchip/Makefile index 66beacadb2b..0e0f744305d 100644 --- a/u-boot/drivers/pinctrl/rockchip/Makefile +++ b/u-boot/drivers/pinctrl/rockchip/Makefile @@ -22,3 +22,4 @@ obj-$(CONFIG_ROCKCHIP_RV1103B) += pinctrl-rv1103b.o obj-$(CONFIG_ROCKCHIP_RV1106) += pinctrl-rv1106.o #obj-$(CONFIG_ROCKCHIP_RV1108) += pinctrl-rv1108.o obj-$(CONFIG_ROCKCHIP_RV1126) += pinctrl-rv1126.o +obj-$(CONFIG_ROCKCHIP_RV1126B) += pinctrl-rv1126b.o diff --git a/u-boot/drivers/pinctrl/rockchip/pinctrl-rk3328.c b/u-boot/drivers/pinctrl/rockchip/pinctrl-rk3328.c index 8e0535f357b..944c3c26026 100644 --- a/u-boot/drivers/pinctrl/rockchip/pinctrl-rk3328.c +++ b/u-boot/drivers/pinctrl/rockchip/pinctrl-rk3328.c @@ -13,23 +13,68 @@ static struct rockchip_mux_recalced_data rk3328_mux_recalced_data[] = { { - .num = 2, - .pin = 12, - .reg = 0x24, - .bit = 8, - .mask = 0x3 - }, { + /* gpio2_b7_sel */ .num = 2, .pin = 15, .reg = 0x28, .bit = 0, .mask = 0x7 }, { + /* gpio2_c7_sel */ .num = 2, .pin = 23, .reg = 0x30, .bit = 14, .mask = 0x3 + }, { + /* gpio3_b1_sel */ + .num = 3, + .pin = 9, + .reg = 0x44, + .bit = 2, + .mask = 0x3 + }, { + /* gpio3_b2_sel */ + .num = 3, + .pin = 10, + .reg = 0x44, + .bit = 4, + .mask = 0x3 + }, { + /* gpio3_b3_sel */ + .num = 3, + .pin = 11, + .reg = 0x44, + .bit = 6, + .mask = 0x3 + }, { + /* gpio3_b4_sel */ + .num = 3, + .pin = 12, + .reg = 0x44, + .bit = 8, + .mask = 0x3 + }, { + /* gpio3_b5_sel */ + .num = 3, + .pin = 13, + .reg = 0x44, + .bit = 10, + .mask = 0x3 + }, { + /* gpio3_b6_sel */ + .num = 3, + .pin = 14, + .reg = 0x44, + .bit = 12, + .mask = 0x3 + }, { + /* gpio3_b7_sel */ + .num = 3, + .pin = 15, + .reg = 0x44, + .bit = 14, + .mask = 0x3 }, }; @@ -274,7 +319,7 @@ static struct rockchip_pin_bank rk3328_pin_banks[] = { PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", 0, 0, 0, 0), PIN_BANK_IOMUX_FLAGS(1, 32, "gpio1", 0, 0, 0, 0), PIN_BANK_IOMUX_FLAGS(2, 32, "gpio2", 0, - IOMUX_WIDTH_3BIT, + IOMUX_8WIDTH_2BIT, IOMUX_WIDTH_3BIT, 0), PIN_BANK_IOMUX_FLAGS(3, 32, "gpio3", diff --git a/u-boot/drivers/pinctrl/rockchip/pinctrl-rockchip.h b/u-boot/drivers/pinctrl/rockchip/pinctrl-rockchip.h index 63c58f97ff3..72bd6e0b646 100644 --- a/u-boot/drivers/pinctrl/rockchip/pinctrl-rockchip.h +++ b/u-boot/drivers/pinctrl/rockchip/pinctrl-rockchip.h @@ -515,6 +515,13 @@ struct rockchip_pin_bank { #define RK3588_PIN_BANK_FLAGS(ID, PIN, LABEL, M, P) \ PIN_BANK_IOMUX_FLAGS_PULL_FLAGS(ID, PIN, LABEL, M, M, M, M, P, P, P, P) +#define PIN_BANK_IOMUX_4_OFFSET(id, pins, label, offset0, offset1, \ + offset2, offset3) \ + PIN_BANK_IOMUX_FLAGS_OFFSET(id, pins, label, IOMUX_WIDTH_4BIT, \ + IOMUX_WIDTH_4BIT, IOMUX_WIDTH_4BIT, \ + IOMUX_WIDTH_4BIT, offset0, offset1, \ + offset2, offset3) + /** * struct rockchip_mux_recalced_data: recalculate a pin iomux data. * @num: bank number. diff --git a/u-boot/drivers/pinctrl/rockchip/pinctrl-rv1126b.c b/u-boot/drivers/pinctrl/rockchip/pinctrl-rv1126b.c new file mode 100644 index 00000000000..49805c10ffb --- /dev/null +++ b/u-boot/drivers/pinctrl/rockchip/pinctrl-rv1126b.c @@ -0,0 +1,295 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * (C) Copyright 2025 Rockchip Electronics Co., Ltd + */ + +#include +#include +#include +#include +#include + +#include "pinctrl-rockchip.h" + +static int rv1126b_set_mux(struct rockchip_pin_bank *bank, int pin, int mux) +{ + struct rockchip_pinctrl_priv *priv = bank->priv; + int iomux_num = (pin / 8); + struct regmap *regmap; + int reg, ret, mask; + u8 bit; + u32 data; + + debug("setting mux of GPIO%d-%d to %d\n", bank->bank_num, pin, mux); + + regmap = priv->regmap_base; + reg = bank->iomux[iomux_num].offset; + if ((pin % 8) >= 4) + reg += 0x4; + bit = (pin % 4) * 4; + mask = 0xf; + + if (bank->recalced_mask & BIT(pin)) + rockchip_get_recalced_mux(bank, pin, ®, &bit, &mask); + data = (mask << (bit + 16)); + data |= (mux & mask) << bit; + + debug("iomux write reg = %x data = %x\n", reg, data); + + ret = regmap_write(regmap, reg, data); + + return ret; +} + +#define RV1126B_DRV_BITS_PER_PIN 8 +#define RV1126B_DRV_PINS_PER_REG 2 +#define RV1126B_DRV_GPIO0_A_OFFSET 0x100 +#define RV1126B_DRV_GPIO0_C_OFFSET 0x8120 +#define RV1126B_DRV_GPIO_OFFSET(GPION) (0x8100 + GPION * 0x8040) + +static int rv1126b_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank, + int pin_num, struct regmap **regmap, + int *reg, u8 *bit) +{ + struct rockchip_pinctrl_priv *priv = bank->priv; + + *regmap = priv->regmap_base; + switch (bank->bank_num) { + case 0: + if (pin_num < 16) + *reg = RV1126B_DRV_GPIO0_A_OFFSET; + else + *reg = RV1126B_DRV_GPIO0_C_OFFSET - 0x20; + break; + + case 1: + case 2: + case 3: + case 4: + case 5: + case 6: + case 7: + *reg = RV1126B_DRV_GPIO_OFFSET(bank->bank_num); + break; + + default: + dev_err(info->dev, "unsupported bank_num %d\n", bank->bank_num); + + return -EINVAL; + } + + *reg += ((pin_num / RV1126B_DRV_PINS_PER_REG) * 4); + *bit = pin_num % RV1126B_DRV_PINS_PER_REG; + *bit *= RV1126B_DRV_BITS_PER_PIN; + + return 0; +} + +static int rv1126b_set_drive(struct rockchip_pin_bank *bank, + int pin_num, int strength) +{ + struct regmap *regmap; + int reg, ret; + u32 data; + u8 bit; + int rmask_bits = RV1126B_DRV_BITS_PER_PIN; + + ret = rv1126b_calc_drv_reg_and_bit(bank, pin_num, ®map, ®, &bit); + if (ret) + return ret; + + /* enable the write to the equivalent lower bits */ + data = ((1 << rmask_bits) - 1) << (bit + 16); + ret = (1 << (strength + 1)) - 1; + data |= (ret << bit); + ret = regmap_write(regmap, reg, data); + + return ret; +} + +#define RV1126B_PULL_BITS_PER_PIN 2 +#define RV1126B_PULL_PINS_PER_REG 8 +#define RV1126B_PULL_GPIO0_A_OFFSET 0x300 +#define RV1126B_PULL_GPIO0_C_OFFSET 0x8308 +#define RV1126B_PULL_GPIO_OFFSET(GPION) (0x8300 + GPION * 0x8010) + +static int rv1126b_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank, + int pin_num, struct regmap **regmap, + int *reg, u8 *bit) +{ + struct rockchip_pinctrl_priv *priv = bank->priv; + + *regmap = priv->regmap_base; + switch (bank->bank_num) { + case 0: + if (pin_num < 16) + *reg = RV1126B_PULL_GPIO0_A_OFFSET; + else + *reg = RV1126B_PULL_GPIO0_C_OFFSET - 0x8; + break; + + case 1: + case 2: + case 3: + case 4: + case 5: + case 6: + case 7: + *reg = RV1126B_PULL_GPIO_OFFSET(bank->bank_num); + break; + + default: + dev_err(info->dev, "unsupported bank_num %d\n", bank->bank_num); + + return -EINVAL; + } + + *reg += ((pin_num / RV1126B_PULL_PINS_PER_REG) * 4); + *bit = pin_num % RV1126B_PULL_PINS_PER_REG; + *bit *= RV1126B_PULL_BITS_PER_PIN; + + return 0; +} + +static int rv1126b_set_pull(struct rockchip_pin_bank *bank, + int pin_num, int pull) +{ + struct regmap *regmap; + int reg, ret; + u8 bit, type; + u32 data; + + if (pull == PIN_CONFIG_BIAS_PULL_PIN_DEFAULT) + return -ENOTSUPP; + + ret = rv1126b_calc_pull_reg_and_bit(bank, pin_num, ®map, ®, &bit); + if (ret) + return ret; + type = bank->pull_type[pin_num / 8]; + + ret = rockchip_translate_pull_value(type, pull); + if (ret < 0) { + debug("unsupported pull setting %d\n", pull); + + return ret; + } + + /* enable the write to the equivalent lower bits */ + data = ((1 << RV1126B_PULL_BITS_PER_PIN) - 1) << (bit + 16); + data |= (ret << bit); + ret = regmap_write(regmap, reg, data); + + return ret; +} + +#define RV1126B_SMT_BITS_PER_PIN 1 +#define RV1126B_SMT_PINS_PER_REG 8 +#define RV1126B_SMT_GPIO0_A_OFFSET 0x500 +#define RV1126B_SMT_GPIO0_C_OFFSET 0x8508 +#define RV1126B_SMT_GPIO_OFFSET(GPION) (0x8500 + GPION * 0x8010) + +static int rv1126b_calc_schmitt_reg_and_bit(struct rockchip_pin_bank *bank, + int pin_num, + struct regmap **regmap, + int *reg, u8 *bit) +{ + struct rockchip_pinctrl_priv *priv = bank->priv; + + *regmap = priv->regmap_base; + switch (bank->bank_num) { + case 0: + if (pin_num < 16) + *reg = RV1126B_SMT_GPIO0_A_OFFSET; + else + *reg = RV1126B_SMT_GPIO0_C_OFFSET - 0x8; + break; + + case 1: + case 2: + case 3: + case 4: + case 5: + case 6: + case 7: + *reg = RV1126B_SMT_GPIO_OFFSET(bank->bank_num); + break; + + default: + dev_err(info->dev, "unsupported bank_num %d\n", bank->bank_num); + return -EINVAL; + } + + *reg += ((pin_num / RV1126B_SMT_PINS_PER_REG) * 4); + *bit = pin_num % RV1126B_SMT_PINS_PER_REG; + *bit *= RV1126B_SMT_BITS_PER_PIN; + + return 0; +} + +static int rv1126b_set_schmitt(struct rockchip_pin_bank *bank, + int pin_num, int enable) +{ + struct regmap *regmap; + int reg, ret; + u32 data; + u8 bit; + + ret = rv1126b_calc_schmitt_reg_and_bit(bank, pin_num, ®map, ®, &bit); + if (ret) + return ret; + + /* enable the write to the equivalent lower bits */ + data = ((1 << RV1126B_SMT_BITS_PER_PIN) - 1) << (bit + 16); + data |= (enable << bit); + ret = regmap_write(regmap, reg, data); + + return ret; +} + +static struct rockchip_pin_bank rv1126b_pin_banks[] = { + PIN_BANK_IOMUX_4_OFFSET(0, 32, "gpio0", + 0x0, 0x8, 0x8010, 0x8018), + PIN_BANK_IOMUX_4_OFFSET(1, 32, "gpio1", + 0x10020, 0x10028, 0x10030, 0x10038), + PIN_BANK_IOMUX_4_OFFSET(2, 32, "gpio2", + 0x18040, 0x18048, 0x18050, 0x18058), + PIN_BANK_IOMUX_4_OFFSET(3, 32, "gpio3", + 0x20060, 0x20068, 0x20070, 0x20078), + PIN_BANK_IOMUX_4_OFFSET(4, 32, "gpio4", + 0x28080, 0x28088, 0x28090, 0x28098), + PIN_BANK_IOMUX_4_OFFSET(5, 32, "gpio5", + 0x300a0, 0x300a8, 0x300b0, 0x300b8), + PIN_BANK_IOMUX_4_OFFSET(6, 32, "gpio6", + 0x380c0, 0x380c8, 0x380d0, 0x380d8), + PIN_BANK_IOMUX_4_OFFSET(7, 32, "gpio7", + 0x400e0, 0x400e8, 0x400f0, 0x400f8), +}; +static struct rockchip_pin_ctrl rv1126b_pin_ctrl __maybe_unused = { + .pin_banks = rv1126b_pin_banks, + .nr_banks = ARRAY_SIZE(rv1126b_pin_banks), + .nr_pins = 256, + .set_mux = rv1126b_set_mux, + .set_pull = rv1126b_set_pull, + .set_drive = rv1126b_set_drive, + .set_schmitt = rv1126b_set_schmitt, +}; + +static const struct udevice_id rv1126b_pinctrl_ids[] = { + { + .compatible = "rockchip,rv1126b-pinctrl", + .data = (ulong)&rv1126b_pin_ctrl + }, + { } +}; + +U_BOOT_DRIVER(pinctrl_rv1126b) = { + .name = "rockchip_rv1126b_pinctrl", + .id = UCLASS_PINCTRL, + .of_match = rv1126b_pinctrl_ids, + .priv_auto_alloc_size = sizeof(struct rockchip_pinctrl_priv), + .ops = &rockchip_pinctrl_ops, +#if !CONFIG_IS_ENABLED(OF_PLATDATA) + .bind = dm_scan_fdt_dev, +#endif + .probe = rockchip_pinctrl_probe, +}; diff --git a/u-boot/drivers/power/charge/Kconfig b/u-boot/drivers/power/charge/Kconfig index 4f747890365..8dc4fcae638 100644 --- a/u-boot/drivers/power/charge/Kconfig +++ b/u-boot/drivers/power/charge/Kconfig @@ -10,6 +10,12 @@ config CHARGER_BQ25890 help This adds support for BQ25890 charger support. +config CHARGER_CPS5601X + bool "CPS5601X charger support" + depends on DM_FUEL_GAUGE + help + This adds support for cps5601x charger support. + config CHARGER_SC8551 bool "SC8551 charger support" depends on DM_FUEL_GAUGE diff --git a/u-boot/drivers/power/charge/Makefile b/u-boot/drivers/power/charge/Makefile index a4fc731c23f..c867c32f18d 100644 --- a/u-boot/drivers/power/charge/Makefile +++ b/u-boot/drivers/power/charge/Makefile @@ -8,3 +8,4 @@ obj-$(CONFIG_CHARGER_BQ25700) += bq25700_charger.o obj-$(CONFIG_CHARGER_BQ25890) += bq25890_charger.o obj-$(CONFIG_CHARGER_SC8551) += sc8551_charger.o obj-$(CONFIG_CHARGER_SGM41542) += sgm41542_charger.o +obj-$(CONFIG_CHARGER_CPS5601X) += cps5601x_charger.o diff --git a/u-boot/drivers/power/charge/cps5601x_charger.c b/u-boot/drivers/power/charge/cps5601x_charger.c new file mode 100644 index 00000000000..57e5c76fcef --- /dev/null +++ b/u-boot/drivers/power/charge/cps5601x_charger.c @@ -0,0 +1,570 @@ +/* + * (C) Copyright 2025 Rockchip Electronics Co., Ltd + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +static int dbg_enable; + +#define CPS_DBG(args...) \ + do { \ + if (dbg_enable) { \ + printf(args); \ + } \ + } while (0) + +#define UPDATE(x, h, l) (((x) << (l)) & GENMASK((h), (l))) + +/* Register 00h */ +#define CPS5601X_REG_00 0x00 +#define CPS5601X_PRODUCT_ID_MASK GENMASK(7, 0) +/* default 0xA9=CPS5601 */ + +/* Register 01h */ +#define CPS5601X_REG_01 0x01 + +/* Register 02h */ +#define CPS5601X_REG_02 0x02 + +/* Register 03h */ +#define CPS5601X_REG_03 0x03 +#define VREG_MASK GENMASK(6, 0) +#define VREG_BASE 3600000 +#define VREG_LSB 10000 +#define VREG_MAXVAL 0x6e + +/* Register 04h */ +#define CPS5601X_REG_04 0x04 +#define ICHG_MASK GENMASK(6, 0) +#define ICHG_BASE 0 +#define ICHG_LSB 25000 +#define ICHG_MINVAL 0x4 +#define ICHG_MAXVAL 0x78 + +/* Register 05h */ +#define CPS5601X_REG_05 0x05 +#define EN_TERM_MASK BIT(6) +#define EN_TERM_ENABLE(x) UPDATE(x, 6, 6) +#define IPRECHG_MASK GENMASK(5, 0) +#define IPRECHG_BASE 0 +#define IPRECHG_LSB 12500 +#define IPRECHG_MINVAL 0x1 +#define IPRECHG_MAXVAL 0x3c + +/* Register 06h */ +#define CPS5601X_REG_06 0x06 +#define ITERM_MASK GENMASK(5, 0) +#define ITERM_BASE 0 +#define ITERM_LSB 10000 +#define ITERM_MINVAL 0x5 +#define ITERM_MAXVAL 0x3c + +/* Register 07h */ +#define CPS5601X_REG_07 0x07 +#define VINDPM_MASK GENMASK(5, 0) +#define VINDPM_BASE 3400000 +#define VINDPM_LSB 100000 +#define VINDPM_MINVAL 0x4 +#define VINDPM_MAXVAL 0x3e + +/* Register 08h */ +#define CPS5601X_REG_08 0x08 +#define IINDPM_MASK GENMASK(5, 0) +#define IINDPM_BASE 50000 +#define IINDPM_LSB 50000 +#define IINDPM_MINVAL 0x1 + +/* Register 09h */ +#define CPS5601X_REG_09 0x09 +#define VOTG_MASK GENMASK(5, 0) +#define VOTG_BASE 3400000 +#define VOTG_LSB 100000 +#define VOTG_MAXVAL 0x3e + +/* Register 0Ah */ +#define CPS5601X_REG_0A 0x0A +#define IOTG_MASK GENMASK(5, 0) +#define IOTG_BASE 50000 +#define IOTG_LSB 50000 +#define IOTG_MINVAL 0x1 + +/* Register 0Bh */ +#define CPS5601X_REG_0B 0x0B +#define WATCHDOG_MASK GENMASK(7, 6) +#define WATCHDOG_TIME(x) UPDATE(x, 7, 6) +#define WATCHDOG_BASE 0 +#define WATCHDOG_LSB 40 +#define WD_RST_MASK BIT(5) +#define WD_RST(x) UPDATE(x, 5, 5) +#define EN_CHG_MASK BIT(3) +#define EN_CHG(x) UPDATE(x, 3, 3) + +/* Register 0Ch */ +#define CPS5601X_REG_0C 0x0C +#define EN_OTG_MASK BIT(3) +#define EN_OTG(x) UPDATE(x, 3, 3) + +/* Register 0Dh */ +#define CPS5601X_REG_0D 0x0D + +/* Register 0Eh */ +#define CPS5601X_REG_0E 0x0E +#define TS_IGNORE_MASK BIT(0) +#define EN_TS_IGNORE(x) UPDATE(x, 0, 0) + +/* Register 0Fh */ +#define CPS5601X_REG_0F 0x0F +#define PG_STAT_MASK BIT(3) + +/* Register 10h */ +#define CPS5601X_REG_10 0x10 +#define CHG_STAT_MASK GENMASK(7, 5) +#define CHG_STAT_SHIFT 5 +#define CHG_STAT_NOTCHG 0 +#define CHG_STAT_TRICKLECHG 1 +#define CHG_STAT_PRECHG 2 +#define CHG_STAT_FASTCHG 3 +#define CHG_STAT_TAPERCHG 4 +#define CHG_STAT_RESERVED 5 +#define CHG_STAT_TOTACHG 6 +#define CHG_STAT_CHGTERM 7 +#define VBUS_STAT_MASK GENMASK(4, 1) +#define VBUS_STAT_SHIFT 1 +#define VBUS_STAT_NOT 0 +#define VBUS_STAT_USBSDP 1 +#define VBUS_STAT_USBCDP 2 +#define VBUS_STAT_USBDCP 3 +#define VBUS_STAT_HVDCP 4 +#define VBUS_STAT_UNKNOWN 5 +#define VBUS_STAT_NONSTANDARD 6 +#define VBUS_STAT_OTGMODE 7 +#define VBUS_STAT_NOTQUALIFIED 8 + +/* Register 11h */ +#define CPS5601X_REG_11 0x11 + +/* Register 12h */ +#define CPS5601X_REG_12 0x12 + +/* Register 13h */ +#define CPS5601X_REG_13 0x13 + +/* Register 14h */ +#define CPS5601X_REG_14 0x14 + +/* Register 15h */ +#define CPS5601X_REG_15 0x15 + +/* Register 16h */ +#define CPS5601X_REG_16 0x16 + +/* Register 17h */ +#define CPS5601X_REG_17 0x17 + +/* Register 18h */ +#define CPS5601X_REG_18 0x18 + +/* Register 19h */ +#define CPS5601X_REG_19 0x19 +#define TREG_MK_MASK BIT(7) + +/* Register 1Ah */ +#define CPS5601X_REG_1A 0x1A + +/* Register 1Bh */ +#define CPS5601X_REG_1B 0x1B + +#define CPS5601X_ICHRG_I_DEF_uA 2040000 +#define CPS5601X_VREG_V_DEF_uV 4208000 +#define CPS5601X_PRECHRG_I_DEF_uA 180000 +#define CPS5601X_TERMCHRG_I_DEF_uA 180000 +#define CPS5601X_ICHRG_I_MIN_uA 100000 +#define CPS5601X_ICHRG_I_MAX_uA 3000000 +#define CPS5601X_VINDPM_DEF_uV 4500000 +#define CPS5601X_VINDPM_V_MIN_uV 3800000 +#define CPS5601X_VINDPM_V_MAX_uV 9600000 +#define CPS5601X_IINDPM_DEF_uA 2400000 +#define CPS5601X_IINDPM_I_MIN_uA 100000 +#define CPS5601X_IINDPM_I_MAX_uA 3200000 +#define DEFAULT_INPUT_CURRENT (500 * 1000) + +struct cps5601x { + struct udevice *dev; + struct udevice *pd; + bool pd_online; + u32 init_count; + u32 ichg; + u32 vchg; + int irq; +}; + +enum power_supply_type { + POWER_SUPPLY_TYPE_UNKNOWN = 0, + POWER_SUPPLY_TYPE_USB, /* Standard Downstream Port */ + POWER_SUPPLY_TYPE_USB_DCP, /* Dedicated Charging Port */ + POWER_SUPPLY_TYPE_USB_CDP, /* Charging Downstream Port */ + POWER_SUPPLY_TYPE_USB_FLOATING, /* DCP without shorting D+/D- */ +}; + +static int cps5601x_read(struct cps5601x *charger, uint reg, u8 *buffer) +{ + u8 val; + int ret; + + ret = dm_i2c_read(charger->dev, reg, &val, 1); + if (ret) { + printf("cps5601x: read %#x error, ret=%d", reg, ret); + return ret; + } + + *buffer = val; + + return 0; +} + +static int cps5601x_write(struct cps5601x *charger, uint reg, u8 val) +{ + int ret; + + ret = dm_i2c_write(charger->dev, reg, &val, 1); + if (ret) + printf("cps5601x: write %#x error, ret=%d", reg, ret); + + return ret; +} + +static int cps5601x_update_bits(struct cps5601x *charger, + u8 offset, + u8 mask, + u8 val) +{ + u8 reg; + int ret; + + ret = cps5601x_read(charger, offset, ®); + if (ret) + return ret; + + reg &= ~mask; + + return cps5601x_write(charger, offset, reg | val); +} + +static int cps5601x_set_input_current_limit(struct cps5601x *cps, int curr) +{ + u8 val; + + if (curr < IINDPM_BASE + (IINDPM_MINVAL * IINDPM_LSB)) + curr = IINDPM_BASE + (IINDPM_MINVAL * IINDPM_LSB); + + val = (curr - IINDPM_BASE) / IINDPM_LSB; + + return cps5601x_update_bits(cps, CPS5601X_REG_08, IINDPM_MASK, val); +} + +static int cps5601x_get_usb_type(void) +{ +#ifdef CONFIG_PHY_ROCKCHIP_INNO_USB2 + return rockchip_chg_get_type(); +#else + return 0; +#endif +} + +static int cps5601x_charger_capability(struct udevice *dev) +{ + return FG_CAP_CHARGER; +} + +static int cps5601x_set_chargecurrent(struct cps5601x *cps, int curr) +{ + u8 ichg; + + if (curr < (ICHG_BASE + (ICHG_MINVAL * ICHG_LSB))) + curr = ICHG_BASE + (ICHG_MINVAL * ICHG_LSB); + else if (curr > (ICHG_BASE + (ICHG_MAXVAL * ICHG_LSB))) + curr = ICHG_BASE + (ICHG_MAXVAL * ICHG_LSB); + + ichg = (curr - ICHG_BASE) / ICHG_LSB; + + return cps5601x_update_bits(cps, CPS5601X_REG_04, ICHG_MASK, ichg); +} + +static int cps5601x_set_iprechg(struct cps5601x *cps, int curr) +{ + u8 iprechg; + + if (curr < (IPRECHG_BASE + (IPRECHG_MINVAL * IPRECHG_LSB))) + curr = IPRECHG_BASE + (IPRECHG_MINVAL * IPRECHG_LSB); + else if (curr > (IPRECHG_BASE + (IPRECHG_MAXVAL * IPRECHG_LSB))) + curr = IPRECHG_BASE + (IPRECHG_MAXVAL * IPRECHG_LSB); + + iprechg = (curr - IPRECHG_BASE) / IPRECHG_LSB; + + return cps5601x_update_bits(cps, CPS5601X_REG_05, IPRECHG_MASK, + iprechg); +} + +static int cps5601x_set_chargevolt(struct cps5601x *cps, int volt) +{ + u8 val; + + if (volt < VREG_BASE) + volt = VREG_BASE; + else if (volt > (VREG_BASE + (VREG_MAXVAL * VREG_LSB))) + volt = VREG_BASE + (VREG_MAXVAL * VREG_LSB); + + val = (volt - VREG_BASE) / VREG_LSB; + + return cps5601x_update_bits(cps, CPS5601X_REG_03, VREG_MASK, val); +} + +static int cps5601x_set_charger_voltage(struct udevice *dev, int uV) +{ + struct cps5601x *charger = dev_get_priv(dev); + + CPS_DBG("CPS5601X: charger voltage %d\n", uV); + return cps5601x_set_chargevolt(charger, uV); +} + +static int cps5601x_charger_enable(struct udevice *dev) +{ + struct cps5601x *charger = dev_get_priv(dev); + + CPS_DBG("CPS5601X: charger enable\n"); + return cps5601x_update_bits(charger, CPS5601X_REG_0B, EN_CHG_MASK, + EN_CHG(1)); +} + +static int cps5601x_charger_disable(struct udevice *dev) +{ + struct cps5601x *charger = dev_get_priv(dev); + + CPS_DBG("CPS5601X: charger disable\n"); + return cps5601x_update_bits(charger, CPS5601X_REG_0B, EN_CHG_MASK, + EN_CHG(0)); +} + +static int cps5601x_iprechg_current(struct udevice *dev, int iprechrg_uA) +{ + struct cps5601x *charger = dev_get_priv(dev); + + CPS_DBG("CPS5601x: charger current:iprechrg_uA: %d\n", + iprechrg_uA); + + return cps5601x_set_iprechg(charger, iprechrg_uA); +} + +static int cps5601x_charger_current(struct udevice *dev, int ichrg_uA) +{ + struct cps5601x *charger = dev_get_priv(dev); + + CPS_DBG("CPS5601X: charger current:ichrg_uA%d\n", + ichrg_uA); + + return cps5601x_set_chargecurrent(charger, ichrg_uA); +} + +static int cps5601x_get_pd_output_val(struct cps5601x *charger, + int *vol, + int *cur) +{ + struct power_delivery_data pd_data; + int ret; + + if (!charger->pd) + return -EINVAL; + + memset(&pd_data, 0, sizeof(pd_data)); + ret = power_delivery_get_data(charger->pd, &pd_data); + if (ret) + return ret; + if (!pd_data.online || !pd_data.voltage || !pd_data.current) + return -EINVAL; + + *vol = pd_data.voltage; + *cur = pd_data.current; + charger->pd_online = pd_data.online; + + return 0; +} + +static void cps5601x_charger_input_current_init(struct cps5601x *charger) +{ + int sdp_inputcurrent = 500 * 1000; + int dcp_inputcurrent = 2000 * 1000; + int pd_inputvol, pd_inputcurrent; + int ret; + + if (!charger->pd) { + ret = uclass_get_device(UCLASS_PD, 0, &charger->pd); + if (ret) { + if (ret == -ENODEV) + printf("cps5601x: Can't find PD\n"); + else + printf("cps5601x: Get UCLASS PD failed: %d\n", ret); + charger->pd = NULL; + } + } + + if (!cps5601x_get_pd_output_val(charger, &pd_inputvol, &pd_inputcurrent)) { + CPS_DBG("pd adapter\n"); + cps5601x_set_input_current_limit(charger, pd_inputcurrent); + } else { + CPS_DBG("normal adapter: %d\n", cps5601x_get_usb_type()); + if (cps5601x_get_usb_type() == POWER_SUPPLY_TYPE_USB_DCP) + cps5601x_set_input_current_limit(charger, dcp_inputcurrent); + else if (cps5601x_get_usb_type() == POWER_SUPPLY_TYPE_USB_CDP) + cps5601x_set_input_current_limit(charger, dcp_inputcurrent); + else if (cps5601x_get_usb_type() == POWER_SUPPLY_TYPE_USB_FLOATING) + cps5601x_set_input_current_limit(charger, dcp_inputcurrent); + else + cps5601x_set_input_current_limit(charger, sdp_inputcurrent); + } +} + +static bool cps5601x_charger_status(struct udevice *dev) +{ + struct cps5601x *charger = dev_get_priv(dev); + int state_of_charger; + u8 value; + int i = 0; + +__retry: + cps5601x_read(charger, CPS5601X_REG_0F, &value); + state_of_charger = !!(value & PG_STAT_MASK); + if (!state_of_charger && charger->pd_online) { + if (i < 3) { + i++; + mdelay(20); + goto __retry; + } + } + + if ((state_of_charger) && (charger->init_count < 5)) { + cps5601x_charger_input_current_init(charger); + cps5601x_charger_enable(dev); + charger->init_count++; + } + + if (!state_of_charger) + cps5601x_set_iprechg(charger, CPS5601X_PRECHRG_I_DEF_uA); + + CPS_DBG("dump register:\n"); + for (i = CPS5601X_REG_00; i < CPS5601X_REG_1B; i++) { + cps5601x_read(charger, i, &value); + CPS_DBG("[%d]: 0x%x\n", i, value); + } + return state_of_charger; +} + +static void cps5601x_irq_handler(int irq, void *data) +{ +} + +static int cps5601x_ofdata_to_platdata(struct udevice *dev) +{ + struct cps5601x *charger = dev_get_priv(dev); + u32 interrupt, phandle; + int ret; + + charger->dev = dev; + charger->ichg = dev_read_u32_default(dev, + "vbat-current-limit-microamp", + 0); + if (charger->ichg == 0) + charger->ichg = 3000 * 1000; + charger->vchg = dev_read_u32_default(dev, + "vbat-voltage-limit-microamp", + 0); + if (charger->vchg == 0) + charger->vchg = 4400 * 1000; + CPS_DBG("charger->ichg: %d\n", charger->ichg); + CPS_DBG("charger->vchg: %d\n", charger->vchg); + + phandle = dev_read_u32_default(dev, "interrupt-parent", -ENODATA); + if (phandle == -ENODATA) { + printf("cps5601x: read 'interrupt-parent' failed, ret=%d\n", + phandle); + return phandle; + } + + ret = dev_read_u32_array(dev, "interrupts", &interrupt, 1); + if (ret) { + printf("cps5601x: read 'interrupts' failed, ret=%d\n", ret); + return ret; + } + + charger->irq = phandle_gpio_to_irq(phandle, interrupt); + if (charger->irq < 0) + printf("cps5601x: failed to request irq: %d\n", charger->irq); + + return 0; +} + +static int cps5601x_probe(struct udevice *dev) +{ + struct cps5601x *charger = dev_get_priv(dev); + u8 value; + int i; + + CPS_DBG("cps5601x: driver version-202502024\n"); + CPS_DBG("cps5601x: dump register:\n"); + for (i = CPS5601X_REG_00; i < CPS5601X_REG_1B; i++) { + cps5601x_read(charger, i, &value); + CPS_DBG("cps5601x: [%d]: 0x%x\n", i, value); + } + + charger->dev = dev; + /* disable watchdog */ + cps5601x_update_bits(charger, CPS5601X_REG_0B, WATCHDOG_MASK, WATCHDOG_TIME(0)); + + cps5601x_update_bits(charger, CPS5601X_REG_0E, TS_IGNORE_MASK, EN_TS_IGNORE(1)); + + cps5601x_set_chargecurrent(charger, charger->ichg); + cps5601x_set_chargevolt(charger, charger->vchg); + + if (0 && charger->irq) { + CPS_DBG("cps5601x: enable cps5601x irq\n"); + irq_install_handler(charger->irq, cps5601x_irq_handler, dev); + irq_handler_enable(charger->irq); + } + + return 0; +} + +static const struct udevice_id charger_ids[] = { + { .compatible = "cps,cps5601x" }, + { }, +}; + +static struct dm_fuel_gauge_ops charger_ops = { + .get_chrg_online = cps5601x_charger_status, + .capability = cps5601x_charger_capability, + .set_charger_voltage = cps5601x_set_charger_voltage, + .set_charger_enable = cps5601x_charger_enable, + .set_charger_disable = cps5601x_charger_disable, + .set_charger_current = cps5601x_charger_current, + .set_iprechg_current = cps5601x_iprechg_current, + +}; + +U_BOOT_DRIVER(cps5601x_charger) = { + .name = "cps5601x_charger", + .id = UCLASS_FG, + .probe = cps5601x_probe, + .of_match = charger_ids, + .ops = &charger_ops, + .ofdata_to_platdata = cps5601x_ofdata_to_platdata, + .priv_auto_alloc_size = sizeof(struct cps5601x), +}; diff --git a/u-boot/drivers/power/fuel_gauge/fg_rk817.c b/u-boot/drivers/power/fuel_gauge/fg_rk817.c index 75b1be981ee..6d20966aa3f 100644 --- a/u-boot/drivers/power/fuel_gauge/fg_rk817.c +++ b/u-boot/drivers/power/fuel_gauge/fg_rk817.c @@ -20,7 +20,7 @@ DECLARE_GLOBAL_DATA_PTR; -static int dbg_enable = 0; +static int dbg_enable; #define DBG(args...) \ do { \ if (dbg_enable) { \ @@ -162,8 +162,6 @@ static int dbg_enable = 0; /* sample resistor and division */ #define SAMPLE_RES_10mR 10 #define SAMPLE_RES_20mR 20 -#define SAMPLE_RES_DIV1 1 -#define SAMPLE_RES_DIV2 2 #define CHRG_CT_EN BIT(1) #define MIN_FCC 500 @@ -176,19 +174,19 @@ static int dbg_enable = 0; #define VOL_OUPUT_INSTANT_MODE 0x02 #define ADC_TO_CURRENT(adc_value, samp_res) \ - (adc_value * 172 / 1000 / samp_res) + (adc_value * 1720 / 1000 / samp_res) #define CURRENT_TO_ADC(current, samp_res) \ - (current * 1000 * samp_res / 172) + (current * 1000 * samp_res / 1720) #define ADC_TO_CAPACITY(adc_value, samp_res) \ - (adc_value / 1000 * 172 / 3600 / samp_res) + (adc_value / 1000 * 1720 / 3600 / samp_res) #define CAPACITY_TO_ADC(capacity, samp_res) \ - (capacity * samp_res * 3600 / 172 * 1000) + (capacity * samp_res * 3600 / 1720 * 1000) #define ADC_TO_CAPACITY_UAH(adc_value, samp_res) \ - (adc_value / 3600 * 172 / samp_res) + (adc_value / 3600 * 1720 / samp_res) #define ADC_TO_CAPACITY_MAH(adc_value, samp_res) \ - (adc_value / 1000 * 172 / 3600 / samp_res) + (adc_value / 1000 * 1720 / 3600 / samp_res) /* charger type definition */ enum charger_type { @@ -481,9 +479,15 @@ static void rk817_bat_init_coulomb_cap(struct rk817_battery_device *battery, rk817_bat_write(battery, Q_INIT_H2, buf); buf = (cap >> 8) & 0xff; rk817_bat_write(battery, Q_INIT_L1, buf); - buf = (cap >> 0) & 0xff; - rk817_bat_write(battery, Q_INIT_L0, buf); + buf = (cap >> 0) & 0xff; + val = rk817_bat_read(battery, Q_INIT_L0); + if (val == buf) { + rk817_bat_write(battery, Q_INIT_L0, buf + 1); + cap += 1; + } else { + rk817_bat_write(battery, Q_INIT_L0, buf); + } val = rk817_bat_read(battery, Q_INIT_H3) << 24; val |= rk817_bat_read(battery, Q_INIT_H2) << 16; val |= rk817_bat_read(battery, Q_INIT_L1) << 8; @@ -515,9 +519,9 @@ static u32 rk817_bat_get_capacity_uah(struct rk817_battery_device *battery) return capacity; } -static u32 rk817_bat_get_capacity_mah(struct rk817_battery_device *battery) +static int rk817_bat_get_capacity_mah(struct rk817_battery_device *battery) { - u32 val, capacity = 0; + int val, capacity = 0; if (rk817_bat_remain_cap_is_valid(battery)) { val = rk817_bat_read(battery, Q_PRES_H3) << 24; @@ -787,16 +791,15 @@ static void rk817_bat_not_first_pwron(struct rk817_battery_device *battery) pre_soc = rk817_bat_get_prev_dsoc(battery); pre_cap = rk817_bat_get_prev_cap(battery); - now_cap = rk817_bat_get_capacity_mah(battery); + now_cap = rk817_bat_get_capacity_uah(battery) / 1000; battery->halt_cnt = rk817_bat_get_halt_cnt(battery); battery->nac = rk817_bat_vol_to_cap(battery, battery->pwron_voltage); - battery->remain_cap = pre_cap * 1000; battery->is_halt = is_rk817_bat_last_halt(battery); DBG("now_cap: %d, pre_cap: %d\n", now_cap, pre_cap); - - if (now_cap > pre_cap) { + /* determine if there is charging */ + if ((now_cap > 0) && (now_cap > pre_cap + 10)) { if (now_cap >= battery->fcc) now_cap = battery->fcc; @@ -812,8 +815,8 @@ static void rk817_bat_not_first_pwron(struct rk817_battery_device *battery) } rk817_bat_init_coulomb_cap(battery, pre_cap); - rk817_bat_init_coulomb_cap(battery, pre_cap + 1); - rk817_bat_get_capacity_mah(battery); + + battery->remain_cap = rk817_bat_get_capacity_uah(battery); battery->dsoc = pre_soc; if (battery->dsoc > 100000) @@ -1208,12 +1211,11 @@ static int rk817_is_bat_exist(struct rk817_battery_device *battery) static int rk817_bat_bat_is_exist(struct udevice *dev) { - struct rk817_battery_device *battery = dev_get_priv(dev); + struct rk817_battery_device *battery = dev_get_priv(dev); - return rk817_is_bat_exist(battery); + return rk817_is_bat_exist(battery); } - static struct dm_fuel_gauge_ops fg_ops = { .bat_is_exist = rk817_bat_bat_is_exist, .get_soc = rk817_bat_update_get_soc, @@ -1295,11 +1297,12 @@ static int rk817_fg_ofdata_to_platdata(struct udevice *dev) battery->drv_version = 0; value = dev_read_u32_default(dev, "sample_res", -1); - if (battery->res_div < 0) + if (value < 0) { printf("read sample_res error\n"); - - battery->res_div = (value == SAMPLE_RES_20mR) ? - SAMPLE_RES_DIV2 : SAMPLE_RES_DIV1; + battery->res_div = SAMPLE_RES_10mR; + } else { + battery->res_div = value; + } DBG("OCV Value:"); for (i = 0; i < battery->ocv_size; i++) diff --git a/u-boot/drivers/power/pmic/Kconfig b/u-boot/drivers/power/pmic/Kconfig index c68d1191c76..755638a1ebe 100644 --- a/u-boot/drivers/power/pmic/Kconfig +++ b/u-boot/drivers/power/pmic/Kconfig @@ -123,6 +123,15 @@ config PMIC_PM8916 Driver binding info: doc/device-tree-bindings/pmic/pm8916.txt +config PMIC_RK801 + bool "Enable support for Rockchip PMIC RK801" + depends on DM_PMIC + ---help--- + The Rockchip RK801 PMIC provides four buck DC-DC convertors, 2 LDOs, + 1 SWITCH and 1 Power key. It is accessed via an I2C interface. + The device is used with Rockchip SoCs. + This driver implements register read/write operations. + config PMIC_RK8XX bool "Enable support for Rockchip PMIC RK8XX" depends on DM_PMIC diff --git a/u-boot/drivers/power/pmic/Makefile b/u-boot/drivers/power/pmic/Makefile index 6c6e989877d..73f70967194 100644 --- a/u-boot/drivers/power/pmic/Makefile +++ b/u-boot/drivers/power/pmic/Makefile @@ -16,6 +16,7 @@ obj-$(CONFIG_PMIC_AS3722) += as3722.o as3722_gpio.o obj-$(CONFIG_PMIC_FP9931) += pmic_fp9931.o obj-$(CONFIG_PMIC_MAX8997) += max8997.o obj-$(CONFIG_PMIC_PM8916) += pm8916.o +obj-$(CONFIG_PMIC_RK801) += pmic_rk801.o obj-$(CONFIG_PMIC_RK8XX) += rk8xx.o obj-$(CONFIG_PMIC_SPI_RK8XX) += rk8xx_spi.o obj-$(CONFIG_PMIC_SY7636A) += pmic_sy7636a.o diff --git a/u-boot/drivers/power/pmic/pmic_rk801.c b/u-boot/drivers/power/pmic/pmic_rk801.c new file mode 100644 index 00000000000..075d7e48d50 --- /dev/null +++ b/u-boot/drivers/power/pmic/pmic_rk801.c @@ -0,0 +1,236 @@ +/* + * (C) Copyright 2024 Rockchip Electronics Co., Ltd. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +#if CONFIG_IS_ENABLED(IRQ) +static const struct virq_reg rk801_irqs[] = { + [RK801_IRQ_PWRON_FALL] = { + .mask = RK801_IRQ_PWRON_FALL_MSK, + .reg_offset = 0, + }, + [RK801_IRQ_PWRON_RISE] = { + .mask = RK801_IRQ_PWRON_RISE_MSK, + .reg_offset = 0, + }, +}; + +static struct virq_chip rk801_irq_chip = { + .status_base = RK801_INT_STS0_REG, + .mask_base = RK801_INT_STS0_REG, + .num_regs = 1, + .read = pmic_reg_read, + .write = pmic_reg_write, + .irqs = rk801_irqs, + .num_irqs = ARRAY_SIZE(rk801_irqs), +}; +#endif + +static struct reg_data rk801_init_reg[] = { + { RK801_SLEEP_CFG_REG, RK801_NONE_FUN, RK801_SLEEP_FUN_MSK }, + { RK801_SYS_CFG2_REG, RK801_SLEEP_ACT_H, RK801_SLEEP_POL_MSK }, + { RK801_SYS_CFG2_REG, RK801_RST_RESTART_REG, RK801_RST_MSK }, + { RK801_INT_CONFIG_REG, RK801_INT_ACT_L, RK801_INT_POL_MSK }, + { RK801_POWER_FPWM_EN_REG, RK801_PLDO_HRDEC_EN, RK801_PLDO_HRDEC_EN }, + { RK801_BUCK_DEBUG5_REG, 0x54, 0xff }, + { RK801_CON_BACK1_REG, 0x18, 0xff }, +}; + +static const struct pmic_child_info pmic_children_info[] = { + { .prefix = "DCDC", .driver = "rk801_buck"}, + { .prefix = "LDO", .driver = "rk801_ldo"}, + { .prefix = "SWITCH", .driver = "rk801_switch"}, + { }, +}; + +static const struct pmic_child_info power_key_info[] = { + { .prefix = "pwrkey", .driver = "rk8xx_pwrkey"}, + { }, +}; + +static int rk801_reg_count(struct udevice *dev) +{ + return RK801_SYS_CFG3_OTP_REG + 1; +} + +static int rk801_write(struct udevice *dev, uint reg, const uint8_t *buff, int len) +{ + int ret; + + ret = dm_i2c_write(dev, reg, buff, len); + if (ret) { + printf("rk801: write reg 0x%02x failed, ret=%d\n", reg, ret); + return ret; + } + + return 0; +} + +static int rk801_read(struct udevice *dev, uint reg, uint8_t *buff, int len) +{ + int ret; + + ret = dm_i2c_read(dev, reg, buff, len); + if (ret) { + printf("rk801: read reg 0x%02x failed, ret=%d\n", reg, ret); + return ret; + } + + return 0; +} + +static int rk801_shutdown(struct udevice *dev) +{ + int ret; + u8 val; + + ret = rk801_read(dev, RK801_SYS_CFG2_REG, &val, 1); + if (ret) + return ret; + + val |= DEV_OFF; + + return rk801_write(dev, RK801_SYS_CFG2_REG, &val, 1); +} + +#if CONFIG_IS_ENABLED(PMIC_CHILDREN) +static int rk801_bind(struct udevice *dev) +{ + ofnode regulators_node; + int children; + + regulators_node = dev_read_subnode(dev, "regulators"); + if (!ofnode_valid(regulators_node)) + return -ENXIO; + + children = pmic_bind_children(dev, regulators_node, pmic_children_info); + if (!children) + debug("%s: %s - no child found\n", __func__, dev->name); + + children = pmic_bind_children(dev, dev->node, power_key_info); + if (!children) + debug("%s: %s - no child found\n", __func__, dev->name); + + return 0; +} +#endif + +static int rk801_ofdata_to_platdata(struct udevice *dev) +{ +#if CONFIG_IS_ENABLED(IRQ) + struct rk801_priv *priv = dev_get_priv(dev); + u32 interrupt, phandle; + int ret; + + phandle = dev_read_u32_default(dev, "interrupt-parent", -ENODATA); + if (phandle == -ENODATA) { + printf("Read 'interrupt-parent' failed, ret=%d\n", phandle); + return phandle; + } + + ret = dev_read_u32_array(dev, "interrupts", &interrupt, 1); + if (ret) { + printf("Read 'interrupts' failed, ret=%d\n", ret); + return ret; + } + + priv->irq = phandle_gpio_to_irq(phandle, interrupt); + if (priv->irq < 0) { + printf("priv to request rk801 irq, ret=%d\n", priv->irq); + return priv->irq; + } +#endif + + return 0; +} + +static int rk801_probe(struct udevice *dev) +{ + struct rk801_priv *priv = dev_get_priv(dev); + uint8_t msb, lsb, on, off; + int i, ret; + + ret = rk801_read(dev, RK801_ID_MSB, &msb, 1); + if (ret) + return ret; + + ret = rk801_read(dev, RK801_ID_LSB, &lsb, 1); + if (ret) + return ret; + + priv->variant = ((msb << 8) | lsb) & RK8XX_ID_MSK; + priv->req_pwrctrl_dvs = (lsb & 0x0f) < 4; + + rk801_read(dev, RK801_ON_SOURCE_REG, &on, 1); + rk801_read(dev, RK801_OFF_SOURCE_REG, &off, 1); + + printf("PMIC: RK%x (on=0x%02x, off=0x%02x, req_dvs=%d)\n", + priv->variant, on, off, priv->req_pwrctrl_dvs); + + if (priv->req_pwrctrl_dvs) { + ret = gpio_request_by_name(dev, "pwrctrl-gpios", 0, + &priv->pwrctrl_gpio, GPIOD_IS_OUT); + if (ret) { + printf("failed to get pwrctrl gpio! ret=%d\n", ret); + return ret; + } + } + + for (i = 0; i < ARRAY_SIZE(rk801_init_reg); i++) { + ret = pmic_clrsetbits(dev, + rk801_init_reg[i].reg, + rk801_init_reg[i].mask, + rk801_init_reg[i].val); + if (ret < 0) { + printf("rk801: set reg 0x%x failed, ret=%d\n", + rk801_init_reg[i].reg, ret); + } + } + +#if CONFIG_IS_ENABLED(IRQ) + priv->irq_chip = &rk801_irq_chip; + ret = virq_add_chip(dev, priv->irq_chip, priv->irq); + if (ret) { + printf("rk801: failed to add irqchip(irq=%d), ret=%d\n", + priv->irq, ret); + return ret; + } +#endif + return 0; +} + +static struct dm_pmic_ops rk801_ops = { + .reg_count = rk801_reg_count, + .read = rk801_read, + .write = rk801_write, + .shutdown = rk801_shutdown, +}; + +static const struct udevice_id rk801_ids[] = { + { .compatible = "rockchip,rk801" }, + { } +}; + +U_BOOT_DRIVER(pmic_rk801) = { + .name = "rk801 pmic", + .id = UCLASS_PMIC, + .of_match = rk801_ids, +#if CONFIG_IS_ENABLED(PMIC_CHILDREN) + .bind = rk801_bind, +#endif + .ofdata_to_platdata = rk801_ofdata_to_platdata, + .priv_auto_alloc_size = sizeof(struct rk801_priv), + .probe = rk801_probe, + .ops = &rk801_ops, +}; + diff --git a/u-boot/drivers/power/pmic/rk8xx.c b/u-boot/drivers/power/pmic/rk8xx.c index 86c3dc40be4..0820881a80c 100644 --- a/u-boot/drivers/power/pmic/rk8xx.c +++ b/u-boot/drivers/power/pmic/rk8xx.c @@ -171,13 +171,13 @@ static struct reg_data rk817_init_reg[] = { /* enable the under-voltage protection, * the under-voltage protection will shutdown the LDO3 and reset the PMIC */ - { RK817_BUCK4_CMIN, 0x6b, 0x6e}, + { RK817_BUCK4_CMIN, 0x6e, 0x6e}, { RK817_PMIC_SYS_CFG1, 0x20, 0x70}, /* Set pmic_sleep as none function */ { RK817_PMIC_SYS_CFG3, 0x00, 0x18 }, /* GATE pin function: gate function */ { RK817_GPIO_INT_CFG, 0x00, 0x20 }, -#ifdef CONFIG_DM_CHARGE_DISPLAY +#if CONFIG_IS_ENABLED(IRQ) /* Set pmic_int active low */ { RK817_GPIO_INT_CFG, 0x00, 0x02 }, #endif @@ -905,6 +905,13 @@ static int rk8xx_probe(struct udevice *dev) return ret; } + if ((priv->rst_fun > RK8xx_RST_MODE0) && + (priv->rst_fun <= RK8xx_RST_MODE2)) { + rk8xx_read(dev, RK817_PMIC_SYS_CFG3, &value, 1); + value &= RK8xx_RESET_FUN_CLR; + value |= (priv->rst_fun << 6); + rk8xx_write(dev, RK817_PMIC_SYS_CFG3, &value, 1); + } /* judge whether save the PMIC_POWER_EN register */ if (!priv->not_save_power_en) { ret = rk8xx_read(dev, RK817_POWER_EN0, &power_en0, 1); diff --git a/u-boot/drivers/power/regulator/Kconfig b/u-boot/drivers/power/regulator/Kconfig index 07025d24c51..1b74718a499 100644 --- a/u-boot/drivers/power/regulator/Kconfig +++ b/u-boot/drivers/power/regulator/Kconfig @@ -107,6 +107,13 @@ config DM_REGULATOR_GPIO features for gpio regulators. The driver implements get/set for voltage value. +config REGULATOR_RK801 + bool "Enable driver for rk801 regulators" + depends on DM_REGULATOR + ---help--- + Enable support for the regulator functions of the rk801 DCDC/LDO/SWITCH. + This driver is controlled by a device tree node which includes voltage limits. + config REGULATOR_RK860X bool "Enable driver for rk860x regulators" depends on DM_REGULATOR diff --git a/u-boot/drivers/power/regulator/Makefile b/u-boot/drivers/power/regulator/Makefile index 9dfe9491dda..f52c2cfc517 100644 --- a/u-boot/drivers/power/regulator/Makefile +++ b/u-boot/drivers/power/regulator/Makefile @@ -16,6 +16,7 @@ obj-$(CONFIG_REGULATOR_FAN53555) += fan53555_regulator.o obj-$(CONFIG_$(SPL_)DM_REGULATOR_FIXED) += fixed.o obj-$(CONFIG_$(SPL_)DM_REGULATOR_GPIO) += gpio-regulator.o obj-$(CONFIG_REGULATOR_RK860X) += rk860x_regulator.o +obj-$(CONFIG_REGULATOR_RK801) += rk801_regulator.o obj-$(CONFIG_REGULATOR_RK8XX) += rk8xx.o obj-$(CONFIG_REGULATOR_S5M8767) += s5m8767.o obj-$(CONFIG_REGULATOR_SY7636A) += sy7636a_regulator.o diff --git a/u-boot/drivers/power/regulator/regulator-uclass.c b/u-boot/drivers/power/regulator/regulator-uclass.c index f6c7ff77bcb..70828b4e9df 100644 --- a/u-boot/drivers/power/regulator/regulator-uclass.c +++ b/u-boot/drivers/power/regulator/regulator-uclass.c @@ -54,7 +54,7 @@ int regulator_set_value(struct udevice *dev, int uV) if (!ops || !ops->set_value) return -ENOSYS; - if (uc_pdata->ramp_delay != -ENODATA) { + if ((uc_pdata->ramp_delay != -ENODATA) || ops->get_ramp_delay) { if (!ops->get_value) return -ENOSYS; old_uV = ops->get_value(dev); @@ -65,7 +65,10 @@ int regulator_set_value(struct udevice *dev, int uV) ret = ops->set_value(dev, uV); if (!ret && (old_uV != -ENODATA) && (old_uV != uV)) { - us = DIV_ROUND_UP(abs(uV - old_uV), uc_pdata->ramp_delay); + if (ops->get_ramp_delay) + us = ops->get_ramp_delay(dev, old_uV, uV); + else + us = DIV_ROUND_UP(abs(uV - old_uV), uc_pdata->ramp_delay); udelay(us); debug("%s: ramp=%d, old_uV=%d, uV=%d, us=%d\n", uc_pdata->name, uc_pdata->ramp_delay, old_uV, uV, us); @@ -148,10 +151,17 @@ int regulator_get_enable(struct udevice *dev) int regulator_set_enable(struct udevice *dev, bool enable) { const struct dm_regulator_ops *ops = dev_get_driver_ops(dev); + struct dm_regulator_uclass_platdata *uc_pdata; if (!ops || !ops->set_enable) return -ENOSYS; + uc_pdata = dev_get_uclass_platdata(dev); + if (!enable && uc_pdata->always_on) { + printf("the always on regulator (%s) should never be disabled!\n", dev->name); + return -EACCES; + } + return ops->set_enable(dev, enable); } diff --git a/u-boot/drivers/power/regulator/rk801_regulator.c b/u-boot/drivers/power/regulator/rk801_regulator.c new file mode 100644 index 00000000000..321815d88b8 --- /dev/null +++ b/u-boot/drivers/power/regulator/rk801_regulator.c @@ -0,0 +1,718 @@ +/* + * (C) Copyright 2024 Rockchip Electronics Co., Ltd. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include + +#define RK801_BUCK_VSEL_MASK 0x7f +#define RK801_LDO_VSEL_MASK 0x3f +#define ENABLE_MASK(id) (BIT(4 + (id)) | BIT(id)) +#define ENABLE_VAL(id) (BIT(4 + (id)) | BIT(id)) +#define DISABLE_VAL(id) (BIT(4 + (id)) | 0) + +enum { + PM_SLEEP = 0, + PM_RUNTIME = 1, +}; + +struct runtime_device { + int reg_src; + int reg_dst; +}; + +struct regulator_desc { + int id; + unsigned int min_uV; + unsigned int uV_step; + const struct linear_range *linear_ranges; + int n_linear_ranges; + unsigned int vsel_reg; + unsigned int vsel_mask; + unsigned int enable_reg; + unsigned int enable_mask; + unsigned int enable_val; + unsigned int disable_val; + unsigned int ramp_delay; +}; + +struct linear_range { + unsigned int min; + unsigned int min_sel; + unsigned int max_sel; + unsigned int step; +}; + +#define REGULATOR_LINEAR_RANGE(_min_uV, _min_sel, _max_sel, _step_uV) \ +{ \ + .min = _min_uV, \ + .min_sel = _min_sel, \ + .max_sel = _max_sel, \ + .step = _step_uV, \ +} + +static const struct linear_range rk801_buck1_voltage_ranges[] = { + REGULATOR_LINEAR_RANGE(500000, 0, 80, 12500), /* 0.5v - 1.5v */ + REGULATOR_LINEAR_RANGE(1800000, 81, 82, 400000),/* 1.8v - 2.2v */ + REGULATOR_LINEAR_RANGE(3300000, 83, 83, 0), /* 3.3v */ + REGULATOR_LINEAR_RANGE(5000000, 84, 84, 0), /* 5.0v */ + REGULATOR_LINEAR_RANGE(5250000, 85, 85, 0), /* 5.25v */ +}; + +static const struct linear_range rk801_buck2_voltage_ranges[] = { + REGULATOR_LINEAR_RANGE(800000, 0, 2, 50000), /* 0.8v - 0.9v */ + REGULATOR_LINEAR_RANGE(1800000, 3, 4, 400000), /* 1.8v - 2.2v */ + REGULATOR_LINEAR_RANGE(3300000, 5, 5, 0), /* 3.3v */ + REGULATOR_LINEAR_RANGE(5000000, 6, 6, 0), /* 5.0v */ + REGULATOR_LINEAR_RANGE(5250000, 7, 7, 0), /* 5.25v */ +}; + +static const struct linear_range rk801_buck4_voltage_ranges[] = { + REGULATOR_LINEAR_RANGE(500000, 0, 80, 12500), /* 0.5v - 1.5v */ + REGULATOR_LINEAR_RANGE(1800000, 81, 82, 400000),/* 1.8v - 2.2v */ + REGULATOR_LINEAR_RANGE(2500000, 83, 83, 0), /* 2.5v */ + REGULATOR_LINEAR_RANGE(2800000, 84, 84, 0), /* 2.8v */ + REGULATOR_LINEAR_RANGE(3000000, 85, 85, 0), /* 3.0v */ + REGULATOR_LINEAR_RANGE(3300000, 86, 86, 0), /* 3.3v */ +}; + +static const struct linear_range rk801_ldo1_voltage_ranges[] = { + REGULATOR_LINEAR_RANGE(500000, 0, 58, 50000), /* 0.5v - 3.4v */ +}; + +static const struct linear_range rk801_ldo2_voltage_ranges[] = { + REGULATOR_LINEAR_RANGE(500000, 0, 58, 50000), /* 0.5v - 3.4v */ +}; + +static const struct regulator_desc rk801_desc[] = { + { + .id = RK801_ID_DCDC1, + .linear_ranges = rk801_buck1_voltage_ranges, + .n_linear_ranges = ARRAY_SIZE(rk801_buck1_voltage_ranges), + .vsel_reg = RK801_BUCK1_ON_VSEL_REG, + .vsel_mask = RK801_BUCK_VSEL_MASK, + .enable_reg = RK801_POWER_EN0_REG, + .enable_mask = ENABLE_MASK(RK801_ID_DCDC1), + .enable_val = ENABLE_VAL(RK801_ID_DCDC1), + .disable_val = DISABLE_VAL(RK801_ID_DCDC1), + .ramp_delay = 1, // TODO: +32 + }, { + .id = RK801_ID_DCDC2, + .linear_ranges = rk801_buck2_voltage_ranges, + .n_linear_ranges = ARRAY_SIZE(rk801_buck2_voltage_ranges), + .vsel_reg = RK801_BUCK2_ON_VSEL_REG, + .vsel_mask = RK801_BUCK_VSEL_MASK, + .enable_reg = RK801_POWER_EN0_REG, + .enable_mask = ENABLE_MASK(RK801_ID_DCDC2), + .enable_val = ENABLE_VAL(RK801_ID_DCDC2), + .disable_val = DISABLE_VAL(RK801_ID_DCDC2), + .ramp_delay = 1, + }, { + .id = RK801_ID_DCDC3, + .enable_reg = RK801_POWER_EN0_REG, + .enable_mask = ENABLE_MASK(RK801_ID_DCDC3), + .enable_val = ENABLE_VAL(RK801_ID_DCDC3), + .disable_val = DISABLE_VAL(RK801_ID_DCDC3), + }, { + .id = RK801_ID_DCDC4, + .linear_ranges = rk801_buck4_voltage_ranges, + .n_linear_ranges = ARRAY_SIZE(rk801_buck4_voltage_ranges), + .vsel_reg = RK801_BUCK4_ON_VSEL_REG, + .vsel_mask = RK801_BUCK_VSEL_MASK, + .enable_reg = RK801_POWER_EN0_REG, + .enable_mask = ENABLE_MASK(RK801_ID_DCDC4), + .enable_val = ENABLE_VAL(RK801_ID_DCDC4), + .disable_val = DISABLE_VAL(RK801_ID_DCDC4), + .ramp_delay = 1, + }, { + .id = RK801_ID_LDO1, + .linear_ranges = rk801_ldo1_voltage_ranges, + .n_linear_ranges = ARRAY_SIZE(rk801_ldo1_voltage_ranges), + .vsel_reg = RK801_LDO1_ON_VSEL_REG, + .vsel_mask = RK801_LDO_VSEL_MASK, + .enable_reg = RK801_POWER_EN1_REG, + .enable_mask = ENABLE_MASK(0), + .enable_val = ENABLE_VAL(0), + .disable_val = DISABLE_VAL(0), + .ramp_delay = 1, + }, { + .id = RK801_ID_LDO2, + .linear_ranges = rk801_ldo2_voltage_ranges, + .n_linear_ranges = ARRAY_SIZE(rk801_ldo2_voltage_ranges), + .vsel_reg = RK801_LDO2_ON_VSEL_REG, + .vsel_mask = RK801_LDO_VSEL_MASK, + .enable_reg = RK801_POWER_EN1_REG, + .enable_mask = ENABLE_MASK(1), + .enable_val = ENABLE_VAL(1), + .disable_val = DISABLE_VAL(1), + .ramp_delay = 1, + }, { + .id = RK801_ID_SWITCH, + .n_linear_ranges = 0, + .enable_reg = RK801_POWER_EN1_REG, + .enable_mask = ENABLE_MASK(2), + .enable_val = ENABLE_VAL(2), + .disable_val = DISABLE_VAL(2), + .ramp_delay = 1, + }, +}; + +static int linear_range_get_value(const struct linear_range *r, + unsigned int selector, unsigned int *val) +{ + if (r->min_sel > selector || r->max_sel < selector) + return -EINVAL; + + *val = r->min + (selector - r->min_sel) * r->step; + + return 0; +} + +static int linear_range_get_value_array(const struct linear_range *r, int ranges, + unsigned int selector, unsigned int *uV) +{ + int i; + + for (i = 0; i < ranges; i++) { + if (r[i].min_sel <= selector && r[i].max_sel >= selector) + return linear_range_get_value(&r[i], selector, uV); + } + + return -EINVAL; +} + +static unsigned int linear_range_get_max_value(const struct linear_range *r) +{ + return r->min + (r->max_sel - r->min_sel) * r->step; +} + +static int linear_range_get_selector_high(const struct linear_range *r, + unsigned int val, + unsigned int *selector, + bool *found) +{ + *found = false; + + if (linear_range_get_max_value(r) < val) + return -EINVAL; + + if (r->min > val) { + *selector = r->min_sel; + return 0; + } + + *found = true; + + if (r->step == 0) + *selector = r->max_sel; + else + *selector = DIV_ROUND_UP(val - r->min, r->step) + r->min_sel; + + return 0; +} + +int regulator_map_voltage_linear_range(const struct regulator_desc *desc, + int min_uV, int max_uV) +{ + const struct linear_range *range; + int ret = -EINVAL; + unsigned int sel; + bool found; + uint voltage, i; + + if (!desc->n_linear_ranges) + return -EINVAL; + + for (i = 0; i < desc->n_linear_ranges; i++) { + range = &desc->linear_ranges[i]; + + ret = linear_range_get_selector_high(range, min_uV, &sel, + &found); + if (ret) + continue; + + ret = sel; + + /* + * Map back into a voltage to verify we're still in bounds. + * If we are not, then continue checking rest of the ranges. + */ + if (linear_range_get_value_array(desc->linear_ranges, + desc->n_linear_ranges, sel, &voltage)) + continue; + + if (voltage >= min_uV && voltage <= max_uV) + break; + } + + if (i == desc->n_linear_ranges) + return -EINVAL; + + return ret; +} + +static const struct regulator_desc *rk801_get_desc(struct udevice *dev) +{ + struct dm_regulator_uclass_platdata *uc_pdata; + int i, id; + + /* Why? Because: RK801_ID_DCDC3=4, RK801_ID_DCDC4=3 */ + uc_pdata = dev_get_uclass_platdata(dev); + if (uc_pdata->type == REGULATOR_TYPE_BUCK) { + switch (dev->driver_data) { + case 1: + id = RK801_ID_DCDC1; + break; + case 2: + id = RK801_ID_DCDC2; + break; + case 3: + id = RK801_ID_DCDC3; + break; + case 4: + id = RK801_ID_DCDC4; + break; + default: + id = -EINVAL; + } + } else if (uc_pdata->type == REGULATOR_TYPE_LDO) { + switch (dev->driver_data) { + case 1: + id = RK801_ID_LDO1; + break; + case 2: + id = RK801_ID_LDO2; + break; + default: + id = -EINVAL; + } + } else { + id = RK801_ID_SWITCH; + } + + if (id != -EINVAL) { + for (i = 0; i < ARRAY_SIZE(rk801_desc); i++) { + if (rk801_desc[i].id == id) + return &rk801_desc[i]; + } + } + + return NULL; +} + +static int rk801_regulator_get_value(struct udevice *dev, bool runtime) +{ + const struct regulator_desc *desc = rk801_get_desc(dev); + struct udevice *pmic = dev->parent; + int sel, val, vsel_reg, ret; + uint uV; + + if (!desc) + return -ENODEV; + + if (desc->id == RK801_ID_DCDC3) + return -ENOSYS; + + if (runtime) + vsel_reg = desc->vsel_reg; + else + vsel_reg = desc->vsel_reg + RK801_SLP_REG_OFFSET; + + val = pmic_reg_read(pmic, vsel_reg); + if (val < 0) + return val; + + sel = (val & desc->vsel_mask) >> (ffs(desc->vsel_mask) - 1); + ret = linear_range_get_value_array(desc->linear_ranges, + desc->n_linear_ranges, sel, &uV); + + debug("%s, %s, desc[%d]: reg=%02x, ret=%d, sel=0x%02x(%d), uV=%d\n", + __func__, dev->name, desc->id, vsel_reg, ret, sel, sel, uV); + + return ret ? ret : uV; +} + +static int rk801_regulator_set_value(struct udevice *dev, int uV, bool runtime) +{ + const struct regulator_desc *desc = rk801_get_desc(dev); + struct udevice *pmic = dev->parent; + struct rk801_priv *priv = dev_get_priv(pmic); + const struct gpio_desc *gpio = &priv->pwrctrl_gpio; + uint reg, reg0, reg1, sel; + int ret, gpio_level; + + if (!desc) + return -ENODEV; + + if (desc->id == RK801_ID_DCDC3) + return -ENOSYS; + + if (priv->req_pwrctrl_dvs) { + reg0 = desc->vsel_reg; + reg1 = desc->vsel_reg + RK801_SLP_REG_OFFSET; + + gpio_level = dm_gpio_get_value(gpio); + reg = (gpio_level == 1) ? reg0 : reg1; + + sel = regulator_map_voltage_linear_range(desc, uV, uV); + if (sel < 0) + return sel; + + sel <<= ffs(desc->vsel_mask) - 1; + + debug("%s, %s, desc[%d]: reg=%02x, uV=%d, sel=0x%02x(%d), gpio=%d\n", + __func__, dev->name, desc->id, reg, uV, sel, sel, gpio_level); + + ret = pmic_clrsetbits(pmic, reg, desc->vsel_mask, sel); + if (ret) + return ret; + + udelay(40); /* hw sync */ + + dm_gpio_set_value(gpio, !gpio_level); + + if (reg == reg0) + ret = pmic_clrsetbits(pmic, reg1, desc->vsel_mask, sel); + else + ret = pmic_clrsetbits(pmic, reg0, desc->vsel_mask, sel); + + /* if sleep mode: set pwrctrl pin low-level anyway */ + if (!runtime) { + dm_gpio_set_value(gpio, 0); + udelay(40); /* hw sync */ + } + + return ret; + } else { + if (runtime) + reg = desc->vsel_reg; + else + reg = desc->vsel_reg + RK801_SLP_REG_OFFSET; + + sel = regulator_map_voltage_linear_range(desc, uV, uV); + if (sel < 0) + return sel; + + debug("%s, %s, desc[%d]: reg=%02x, uV=%d, sel=0x%02x(%d)\n", + __func__, dev->name, desc->id, reg, uV, sel, sel); + + sel <<= ffs(desc->vsel_mask) - 1; + + return pmic_clrsetbits(pmic, reg, desc->vsel_mask, sel); + } +} + +static int rk801_regulator_get_enable(struct udevice *dev, bool runtime) +{ + const struct regulator_desc *desc = rk801_get_desc(dev); + struct udevice *pmic = dev->parent; + int val; + + if (!desc) + return -ENODEV; + + if (runtime) { + val = pmic_reg_read(pmic, desc->enable_reg); + if (val < 0) + return val; + + val &= desc->enable_mask; + + return val == desc->enable_val; + } else { + val = pmic_reg_read(pmic, RK801_POWER_SLP_EN_REG); + if (val < 0) + return val; + + return (val & BIT(desc->id)); + } +} + +static int rk801_regulator_set_enable(struct udevice *dev, bool enable) +{ + const struct regulator_desc *desc = rk801_get_desc(dev); + struct udevice *pmic = dev->parent; + int val; + + if (!desc) + return -ENODEV; + + val = enable ? desc->enable_val : desc->disable_val; + + debug("%s, %s, desc[%d]: reg=%02x, mask=%02x, enable=%d, val=0x%02x(%d)\n", + __func__, dev->name, desc->id, desc->enable_reg, + desc->enable_mask, enable, val, val); + + return pmic_clrsetbits(pmic, desc->enable_reg, desc->enable_mask, val); +} + +static int rk801_regulator_set_suspend_enable(struct udevice *dev, bool enable) +{ + const struct regulator_desc *desc = rk801_get_desc(dev); + struct udevice *pmic = dev->parent; + + if (!desc) + return -ENODEV; + + debug("%s, %s, desc[%d]: reg=%02x, mask=%02lx, enable=0x%02x, val=0x%02lx\n", + __func__, dev->name, desc->id, RK801_POWER_SLP_EN_REG, + BIT(desc->id), enable, BIT(desc->id)); + + return pmic_clrsetbits(pmic, RK801_POWER_SLP_EN_REG, + BIT(desc->id), BIT(desc->id)); +} + +static int buck_ldo_get_value(struct udevice *dev) +{ + return rk801_regulator_get_value(dev, PM_RUNTIME); +} + +static int buck_ldo_set_value(struct udevice *dev, int uV) +{ + return rk801_regulator_set_value(dev, uV, PM_RUNTIME); +} + +static int buck_ldo_get_enable(struct udevice *dev) +{ + return rk801_regulator_get_enable(dev, PM_RUNTIME); +} + +static int buck_ldo_set_enable(struct udevice *dev, bool enable) +{ + struct rk801_priv *priv = dev_get_priv(dev->parent); + int ret; + + ret = rk801_regulator_set_enable(dev, enable); + if (ret) + return ret; + + if (priv->req_pwrctrl_dvs) + return rk801_regulator_set_suspend_enable(dev, enable); + + return 0; +} + +static int buck_ldo_get_suspend_value(struct udevice *dev) +{ + return rk801_regulator_get_value(dev, PM_SLEEP); +} + +static int buck_ldo_set_suspend_value(struct udevice *dev, int uV) +{ + return rk801_regulator_set_value(dev, uV, PM_SLEEP); +} + +static int buck_ldo_get_suspend_enable(struct udevice *dev) +{ + return rk801_regulator_get_enable(dev, PM_SLEEP); +} + +static int buck_ldo_set_suspend_enable(struct udevice *dev, bool enable) +{ + struct rk801_priv *priv = dev_get_priv(dev->parent); + int ret; + + ret = rk801_regulator_set_suspend_enable(dev, enable); + if (ret) + return ret; + + if (priv->req_pwrctrl_dvs) + return rk801_regulator_set_enable(dev, enable); + + return 0; +} + +int buck_ldo_get_ramp_delay(struct udevice *dev, int old_uV, int new_uV) +{ + const struct regulator_desc *desc = rk801_get_desc(dev); + struct dm_regulator_uclass_platdata *uc_pdata; + + if (!desc) + return 0; + + uc_pdata = dev_get_uclass_platdata(dev); + if (uc_pdata->type != REGULATOR_TYPE_BUCK) + return 0; + + return abs(new_uV - old_uV) / 1000 + 32; +} + +static int switch_set_enable(struct udevice *dev, bool enable) +{ + return buck_ldo_set_enable(dev, enable); +} + +static int switch_get_enable(struct udevice *dev) +{ + return rk801_regulator_get_enable(dev, PM_RUNTIME); +} + +static int switch_set_suspend_enable(struct udevice *dev, bool enable) +{ + return buck_ldo_set_suspend_enable(dev, enable); +} + +static int switch_get_suspend_enable(struct udevice *dev) +{ + return rk801_regulator_get_enable(dev, PM_SLEEP); +} + +static int switch_get_value(struct udevice *dev) +{ + return 0; +} + +static int switch_set_value(struct udevice *dev, int uV) +{ + return 0; +} + +static int switch_set_suspend_value(struct udevice *dev, int uV) +{ + return 0; +} + +static int switch_get_suspend_value(struct udevice *dev) +{ + return 0; +} + +static int rk801_buck_probe(struct udevice *dev) +{ + struct dm_regulator_uclass_platdata *uc_pdata; + struct udevice *pmic = dev->parent; + struct runtime_device rdev[] = { + { RK801_BUCK1_ON_VSEL_REG, RK801_BUCK1_SLP_VSEL_REG }, + { RK801_BUCK2_ON_VSEL_REG, RK801_BUCK2_SLP_VSEL_REG }, + { RK801_BUCK4_ON_VSEL_REG, RK801_BUCK4_SLP_VSEL_REG }, + { RK801_LDO1_ON_VSEL_REG, RK801_LDO1_SLP_VSEL_REG }, + { RK801_LDO2_ON_VSEL_REG, RK801_LDO2_SLP_VSEL_REG }, + }; + uint val, en0, en1; + int i, ret; + + uc_pdata = dev_get_uclass_platdata(dev); + uc_pdata->type = REGULATOR_TYPE_BUCK; + uc_pdata->mode_count = 0; + + /* probe only once by buck1 */ + if (dev->driver_data != 1) + return 0; + + /* pwrctrl gpio active high and use sleep function */ + ret = pmic_clrsetbits(pmic, RK801_SYS_CFG2_REG, + RK801_SLEEP_POL_MSK, RK801_SLEEP_ACT_H); + if (ret < 0) + return ret; + + ret = pmic_clrsetbits(pmic, RK801_SLEEP_CFG_REG, + RK801_SLEEP_FUN_MSK, RK801_SLEEP_FUN); + if (ret < 0) + return ret; + + /* disable buck/pldo slp lp */ + ret = pmic_clrsetbits(pmic, RK801_SLP_LP_CONFIG_REG, + RK801_SLP_LP_MASK, 0); + if (ret < 0) + return ret; + + /* copy on/slp enabel */ + en0 = pmic_reg_read(pmic, RK801_POWER_EN0_REG); + if (en0 < 0) + return en0; + + en1 = pmic_reg_read(pmic, RK801_POWER_EN1_REG); + if (en1 < 0) + return en1; + + val = (en0 & 0x0f) | ((en1 & 0x0f) << 4); + ret = pmic_reg_write(pmic, RK801_POWER_SLP_EN_REG, val); + if (ret < 0) + return ret; + + /* copy on/slp vsel */ + for (i = 0; i < ARRAY_SIZE(rdev); i++) { + val = pmic_reg_read(pmic, rdev[i].reg_src); + if (val < 0) + return val; + + ret = pmic_reg_write(pmic, rdev[i].reg_dst, val); + if (ret < 0) + return ret; + } + + return 0; +} + +static int rk801_ldo_probe(struct udevice *dev) +{ + struct dm_regulator_uclass_platdata *uc_pdata; + + uc_pdata = dev_get_uclass_platdata(dev); + uc_pdata->type = REGULATOR_TYPE_LDO; + uc_pdata->mode_count = 0; + + return 0; +} + +static int rk801_switch_probe(struct udevice *dev) +{ + struct dm_regulator_uclass_platdata *uc_pdata; + + uc_pdata = dev_get_uclass_platdata(dev); + uc_pdata->type = REGULATOR_TYPE_FIXED; + uc_pdata->mode_count = 0; + + return 0; +} + +static const struct dm_regulator_ops rk801_buck_ldo_ops = { + .get_value = buck_ldo_get_value, + .set_value = buck_ldo_set_value, + .set_enable = buck_ldo_set_enable, + .get_enable = buck_ldo_get_enable, + .set_suspend_value = buck_ldo_set_suspend_value, + .get_suspend_value = buck_ldo_get_suspend_value, + .set_suspend_enable = buck_ldo_set_suspend_enable, + .get_suspend_enable = buck_ldo_get_suspend_enable, + .get_ramp_delay = buck_ldo_get_ramp_delay, +}; + +static const struct dm_regulator_ops rk801_switch_ops = { + .get_value = switch_get_value, + .set_value = switch_set_value, + .set_enable = switch_set_enable, + .get_enable = switch_get_enable, + .set_suspend_enable = switch_set_suspend_enable, + .get_suspend_enable = switch_get_suspend_enable, + .set_suspend_value = switch_set_suspend_value, + .get_suspend_value = switch_get_suspend_value, +}; + +U_BOOT_DRIVER(rk801_buck) = { + .name = "rk801_buck", + .id = UCLASS_REGULATOR, + .ops = &rk801_buck_ldo_ops, + .probe = rk801_buck_probe, +}; + +U_BOOT_DRIVER(rk801_ldo) = { + .name = "rk801_ldo", + .id = UCLASS_REGULATOR, + .ops = &rk801_buck_ldo_ops, + .probe = rk801_ldo_probe, +}; + +U_BOOT_DRIVER(rk801_switch) = { + .name = "rk801_switch", + .id = UCLASS_REGULATOR, + .ops = &rk801_switch_ops, + .probe = rk801_switch_probe, +}; + diff --git a/u-boot/drivers/pwm/rk_pwm.c b/u-boot/drivers/pwm/rk_pwm.c index c04c1725498..45468130ce5 100644 --- a/u-boot/drivers/pwm/rk_pwm.c +++ b/u-boot/drivers/pwm/rk_pwm.c @@ -94,9 +94,9 @@ static int rk_pwm_set_invert_v4(struct udevice *dev, uint channel, bool polarity debug("%s: polarity=%u\n", __func__, polarity); if (polarity) - priv->conf_polarity = PWM_DUTY_NEGATIVE | PWM_INACTIVE_POSTIVE; + priv->conf_polarity = DUTY_NEGATIVE | INACTIVE_POSITIVE; else - priv->conf_polarity = PWM_DUTY_POSTIVE | PWM_INACTIVE_NEGATIVE; + priv->conf_polarity = DUTY_POSITIVE | INACTIVE_NEGATIVE; return 0; } @@ -291,8 +291,13 @@ static int rk_pwm_probe(struct udevice *dev) priv->freq = ret; priv->data = (struct rockchip_pwm_data *)dev_get_driver_data(dev); - if (priv->data->supports_polarity) - priv->conf_polarity = PWM_DUTY_POSTIVE | PWM_INACTIVE_POSTIVE; + if (priv->data->supports_polarity) { + if (priv->data->main_version >= 4) { + priv->conf_polarity = DUTY_POSITIVE | INACTIVE_NEGATIVE; + } else { + priv->conf_polarity = PWM_DUTY_POSTIVE | PWM_INACTIVE_POSTIVE; + } + } return 0; } diff --git a/u-boot/drivers/ram/rockchip/Makefile b/u-boot/drivers/ram/rockchip/Makefile index 14adc2241f1..a527756d6ed 100644 --- a/u-boot/drivers/ram/rockchip/Makefile +++ b/u-boot/drivers/ram/rockchip/Makefile @@ -10,6 +10,7 @@ obj-$(CONFIG_ROCKCHIP_RV1108) += sdram_rv1108_pctl_phy.o sdram_rv1108.o obj-$(CONFIG_ROCKCHIP_RV1103B) += sdram_rv1103b.o obj-$(CONFIG_ROCKCHIP_RV1106) += sdram_rv1106.o obj-$(CONFIG_ROCKCHIP_RV1126) += sdram_rv1126.o sdram_pctl_px30.o +obj-$(CONFIG_ROCKCHIP_RV1126B) += sdram_rv1126b.o obj-$(CONFIG_ROCKCHIP_RK3128) += sdram_rk3128.o obj-$(CONFIG_ROCKCHIP_RK3188) += sdram_rk3188.o obj-$(CONFIG_ROCKCHIP_RK322X) += sdram_rk322x.o diff --git a/u-boot/drivers/ram/rockchip/sdram_inc/rv1126/sdram-rv1126-loader_params.inc b/u-boot/drivers/ram/rockchip/sdram_inc/rv1126/sdram-rv1126-loader_params.inc index 4b75f166d36..a5b0ffb320b 100644 --- a/u-boot/drivers/ram/rockchip/sdram_inc/rv1126/sdram-rv1126-loader_params.inc +++ b/u-boot/drivers/ram/rockchip/sdram_inc/rv1126/sdram-rv1126-loader_params.inc @@ -1,5 +1,5 @@ 0x12345678, -2,/* version */ +3,/* version */ (0 << 0) | (1 << 8) | (9 << 16) | (8 << 24),/* cpu_gen,global index */ (0 << 0) | (9 << 8) | (17 << 16) | (9 << 24),/* d2,d3 index */ (26 << 0) | (9 << 8) | (0 << 16) | (0 << 24),/* d4,d5 index */ diff --git a/u-boot/drivers/ram/rockchip/sdram_rv1126.c b/u-boot/drivers/ram/rockchip/sdram_rv1126.c index d12beb848ff..bb600c90353 100644 --- a/u-boot/drivers/ram/rockchip/sdram_rv1126.c +++ b/u-boot/drivers/ram/rockchip/sdram_rv1126.c @@ -3663,7 +3663,7 @@ int sdram_init(void) #ifdef CONFIG_ROCKCHIP_DRAM_EXTENDED_TEMP_SUPPORT printascii("extended temp support\n"); #endif - if (index->version_info != 2 || + if (index->version_info != 3 || (index->global_index.size != sizeof(struct global_info) / 4) || (index->ddr3_index.size != sizeof(struct ddr2_3_4_lp2_3_info) / 4) || diff --git a/u-boot/drivers/ram/rockchip/sdram_rv1126b.c b/u-boot/drivers/ram/rockchip/sdram_rv1126b.c new file mode 100644 index 00000000000..5d280a6d0e2 --- /dev/null +++ b/u-boot/drivers/ram/rockchip/sdram_rv1126b.c @@ -0,0 +1,13 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * (C) Copyright 2025 Rockchip Electronics Co., Ltd. + */ + +#include + +#ifdef CONFIG_TPL_BUILD +int sdram_init(void) +{ + return (-1); +} +#endif /* CONFIG_TPL_BUILD */ diff --git a/u-boot/drivers/rkflash/sfc_nand.c b/u-boot/drivers/rkflash/sfc_nand.c index 03a28a7cfd0..3bab0557564 100644 --- a/u-boot/drivers/rkflash/sfc_nand.c +++ b/u-boot/drivers/rkflash/sfc_nand.c @@ -25,6 +25,7 @@ static u32 sfc_nand_get_ecc_status7(void); static u32 sfc_nand_get_ecc_status8(void); static u32 sfc_nand_get_ecc_status9(void); static u32 sfc_nand_get_ecc_status10(void); +static u32 sfc_nand_get_ecc_status11(void); static struct nand_info spi_nand_tbl[] = { /* TC58CVG0S0HxAIx */ @@ -90,7 +91,7 @@ static struct nand_info spi_nand_tbl[] = { /* GD5F1GM7REYIGR */ { 0xC8, 0x81, 0x00, 4, 0x40, 1, 1024, 0x4C, 18, 0x8, 1, { 0x04, 0x08, 0xFF, 0xFF }, &sfc_nand_get_ecc_status3 }, /* GD5F4GM8UEYIGR */ - { 0xC8, 0x95, 0x00, 4, 0x40, 1, 4096, 0x4C, 20, 0x8, 1, { 0x04, 0x08, 0xFF, 0xFF }, &sfc_nand_get_ecc_status3 }, + { 0xC8, 0x95, 0x00, 4, 0x40, 1, 4096, 0x4C, 20, 0x8, 1, { 0x04, 0x08, 0x0C, 0x10 }, &sfc_nand_get_ecc_status3 }, /* W25N01GV */ { 0xEF, 0xAA, 0x21, 4, 0x40, 1, 1024, 0x4C, 18, 0x1, 0, { 0x04, 0x14, 0x24, 0xFF }, &sfc_nand_get_ecc_status1 }, @@ -124,9 +125,9 @@ static struct nand_info spi_nand_tbl[] = { /* HYF4GQ4UAACBE */ { 0xC9, 0xD4, 0x00, 8, 0x40, 1, 2048, 0x4C, 20, 0xE, 1, { 0x20, 0x40, 0x24, 0x44 }, &sfc_nand_get_ecc_status0 }, /* HYF2GQ4IAACAE */ - { 0xC9, 0x82, 0x00, 4, 0x40, 1, 2048, 0x4C, 20, 0xE, 1, { 0x04, 0x24, 0xFF, 0xFF }, &sfc_nand_get_ecc_status0 }, + { 0xC9, 0x82, 0x00, 4, 0x40, 1, 2048, 0x4C, 19, 0xE, 1, { 0x04, 0x24, 0xFF, 0xFF }, &sfc_nand_get_ecc_status0 }, /* HYF1GQ4IDACAE */ - { 0xC9, 0x81, 0x00, 4, 0x40, 1, 1024, 0x4C, 20, 0x4, 1, { 0x04, 0x14, 0xFF, 0xFF }, &sfc_nand_get_ecc_status0 }, + { 0xC9, 0x81, 0x00, 4, 0x40, 1, 1024, 0x4C, 18, 0x4, 1, { 0x04, 0x14, 0xFF, 0xFF }, &sfc_nand_get_ecc_status0 }, /* FS35ND01G-S1 */ { 0xCD, 0xB1, 0x00, 4, 0x40, 1, 1024, 0x0C, 18, 0x4, 1, { 0x10, 0x14, 0xFF, 0xFF }, &sfc_nand_get_ecc_status5 }, @@ -137,7 +138,7 @@ static struct nand_info spi_nand_tbl[] = { /* FS35ND02G-S3Y2 */ { 0xCD, 0xEB, 0x00, 4, 0x40, 1, 2048, 0x4C, 19, 0x4, 0, { 0x04, 0x08, 0xFF, 0xFF }, &sfc_nand_get_ecc_status1 }, /* FS35ND04G-S2Y2 1*4096 */ - { 0xCD, 0xEC, 0x00, 4, 0x40, 2, 2048, 0x4C, 20, 0x4, 0, { 0x04, 0x08, 0xFF, 0xFF }, &sfc_nand_get_ecc_status1 }, + { 0xCD, 0xEC, 0x00, 4, 0x40, 2, 2048, 0x4C, 20, 0x4, 0, { 0x04, 0x08, 0x0C, 0x10 }, &sfc_nand_get_ecc_status1 }, /* F35SQA001G */ { 0xCD, 0x71, 0x00, 4, 0x40, 1, 1024, 0x4C, 18, 0x1, 1, { 0x04, 0x08, 0xFF, 0xFF }, &sfc_nand_get_ecc_status1 }, /* F35SQA002G */ @@ -168,7 +169,7 @@ static struct nand_info spi_nand_tbl[] = { /* DS35Q2GB-IB */ { 0xE5, 0xF2, 0x00, 4, 0x40, 2, 1024, 0x0C, 19, 0x8, 1, { 0x04, 0x14, 0xFF, 0xFF }, &sfc_nand_get_ecc_status6 }, /* DS35Q4GM */ - { 0xE5, 0xF4, 0x00, 4, 0x40, 2, 2048, 0x0C, 20, 0x8, 1, { 0x04, 0x14, 0xFF, 0xFF }, &sfc_nand_get_ecc_status6 }, + { 0xE5, 0xF4, 0x00, 4, 0x40, 2, 2048, 0x0C, 20, 0x8, 1, { 0x04, 0x14, 0x0C, 0x10 }, &sfc_nand_get_ecc_status6 }, /* DS35M1GB-IB */ { 0xE5, 0xA1, 0x00, 4, 0x40, 1, 1024, 0x0C, 18, 0x8, 1, { 0x04, 0x14, 0xFF, 0xFF }, &sfc_nand_get_ecc_status6 }, /* DS35Q12B-IB */ @@ -178,9 +179,9 @@ static struct nand_info spi_nand_tbl[] = { /* DS35Q1GD-IB */ { 0xE5, 0x51, 0x00, 4, 0x40, 1, 1024, 0x4C, 18, 0x8, 1, { 0x04, 0x08, 0xFF, 0xFF }, &sfc_nand_get_ecc_status6 }, /* DS35M4GB-IB */ - { 0xE5, 0x64, 0x00, 4, 0x40, 1, 4096, 0x4C, 20, 0x8, 1, { 0x04, 0x08, 0xFF, 0xFF }, &sfc_nand_get_ecc_status6 }, + { 0xE5, 0x64, 0x00, 4, 0x40, 1, 4096, 0x4C, 20, 0x8, 1, { 0x04, 0x08, 0x0C, 0x10 }, &sfc_nand_get_ecc_status6 }, /* DS35Q4GB-IB */ - { 0xE5, 0xB4, 0x00, 4, 0x40, 1, 4096, 0x4C, 20, 0x8, 1, { 0x04, 0x08, 0xFF, 0xFF }, &sfc_nand_get_ecc_status6 }, + { 0xE5, 0xB4, 0x00, 4, 0x40, 1, 4096, 0x4C, 20, 0x8, 1, { 0x04, 0x08, 0x0C, 0x10 }, &sfc_nand_get_ecc_status6 }, /* DS35M12C-IB */ { 0xE5, 0x25, 0x00, 4, 0x40, 1, 512, 0x4C, 17, 0x8, 1, { 0x04, 0x08, 0xFF, 0xFF }, &sfc_nand_get_ecc_status6 }, /* DS35Q12C-IB */ @@ -196,13 +197,15 @@ static struct nand_info spi_nand_tbl[] = { { 0xD5, 0x03, 0x00, 8, 0x40, 1, 2048, 0x4C, 20, 0x8, 1, { 0x04, 0x28, 0x08, 0x2C }, &sfc_nand_get_ecc_status0 }, /* EM73C044VCF-H */ { 0xD5, 0x25, 0x00, 4, 0x40, 1, 1024, 0x0C, 18, 0x4, 1, { 0x04, 0x14, 0xFF, 0xFF }, &sfc_nand_get_ecc_status0 }, + /* EM73E044VCE-H */ + { 0xD5, 0x3B, 0x00, 4, 0x40, 1, 4096, 0x4C, 20, 0x8, 1, { 0x04, 0x08, 0x0C, 0x10 }, &sfc_nand_get_ecc_status0 }, /* XT26G02A */ { 0x0B, 0xE2, 0x00, 4, 0x40, 1, 2048, 0x4C, 19, 0x8, 1, { 0x08, 0x0C, 0xFF, 0xFF }, &sfc_nand_get_ecc_status4 }, /* XT26G01A */ { 0x0B, 0xE1, 0x00, 4, 0x40, 1, 1024, 0x4C, 18, 0x8, 1, { 0x08, 0x0C, 0xFF, 0xFF }, &sfc_nand_get_ecc_status4 }, /* XT26G04A */ - { 0x0B, 0xE3, 0x00, 4, 0x80, 1, 2048, 0x4C, 20, 0x8, 1, { 0x08, 0x0C, 0xFF, 0xFF }, &sfc_nand_get_ecc_status4 }, + { 0x0B, 0xE3, 0x00, 4, 0x80, 1, 2048, 0x4C, 20, 0x8, 1, { 0x08, 0x0C, 0x0C, 0x10 }, &sfc_nand_get_ecc_status4 }, /* XT26G01B */ { 0x0B, 0xF1, 0x00, 4, 0x40, 1, 1024, 0x4C, 18, 0x8, 1, { 0x08, 0x0C, 0xFF, 0xFF }, &sfc_nand_get_ecc_status4 }, /* XT26G02B */ @@ -273,6 +276,10 @@ static struct nand_info spi_nand_tbl[] = { { 0xB0, 0x0D, 0x00, 4, 0x40, 1, 512, 0x4C, 17, 0x4, 1, { 0x04, 0x08, 0xFF, 0xFF }, &sfc_nand_get_ecc_status0 }, /* UM19A9HISW */ { 0xB0, 0x0C, 0x00, 4, 0x40, 1, 512, 0x4C, 17, 0x4, 1, { 0x04, 0x08, 0xFF, 0xFF }, &sfc_nand_get_ecc_status0 }, + /* UM19A0HISW */ + { 0xB0, 0x14, 0x00, 4, 0x40, 1, 1024, 0x4C, 18, 0x8, 1, { 0x04, 0x08, 0xFF, 0xFF }, &sfc_nand_get_ecc_status11 }, + /* UM19A0LISW */ + { 0xB0, 0x15, 0x00, 4, 0x40, 1, 1024, 0x4C, 18, 0x8, 1, { 0x04, 0x08, 0xFF, 0xFF }, &sfc_nand_get_ecc_status11 }, /* ATO25D1GA */ { 0x9B, 0x12, 0x00, 4, 0x40, 1, 1024, 0x40, 18, 0x1, 1, { 0x14, 0x24, 0xFF, 0xFF }, &sfc_nand_get_ecc_status1 }, @@ -311,7 +318,7 @@ static struct nand_info spi_nand_tbl[] = { /* ZB35Q01BYIG */ { 0x5E, 0xA1, 0x00, 4, 0x40, 1, 1024, 0x4C, 18, 0x8, 0, { 0x04, 0x08, 0xFF, 0xFF }, &sfc_nand_get_ecc_status1 }, /* ZB35Q04BYIG */ - { 0x5E, 0xA3, 0x00, 4, 0x80, 1, 2048, 0x4C, 20, 0x8, 1, { 0x04, 0x08, 0xFF, 0xFF }, &sfc_nand_get_ecc_status1 }, + { 0x5E, 0xA3, 0x00, 4, 0x80, 1, 2048, 0x4C, 20, 0x8, 1, { 0x04, 0x08, 0x0C, 0x10 }, &sfc_nand_get_ecc_status1 }, /* HSESYHDSW2G */ { 0x3C, 0xD2, 0x00, 4, 0x40, 1, 2048, 0x4C, 19, 0x4, 0, { 0x04, 0x08, 0xFF, 0xFF }, &sfc_nand_get_ecc_status1 }, @@ -880,7 +887,7 @@ static u32 sfc_nand_get_ecc_status9(void) } /* - * ecc spectial type8: + * ecc spectial type10: * ecc bits: 0xC0[4,6] * [0b000], No bit errors were detected; * [0b001, 0b101], 3~7 Bit errors were detected and corrected. Not @@ -920,6 +927,47 @@ static u32 sfc_nand_get_ecc_status10(void) return ret; } +/* + * ecc spectial type11: + * ecc bits: 0xC0[4,6] + * [0b000], No bit errors were detected; + * [0b001, 0b101], 3~7 Bit errors were detected and corrected. Not + * reach Flipping Bits; + * [0b110], Bit error count equals the bit flip detection threshold + * [0b111], Bit errors greater than ECC capability(8 bits) and not corrected; + */ +static u32 sfc_nand_get_ecc_status11(void) +{ + u32 ret; + u32 i; + u8 ecc; + u8 status; + u32 timeout = 1000 * 1000; + + for (i = 0; i < timeout; i++) { + ret = sfc_nand_read_feature(0xC0, &status); + + if (ret != SFC_OK) + return SFC_NAND_ECC_ERROR; + + if (!(status & (1 << 0))) + break; + + sfc_delay(1); + } + + ecc = (status >> 4) & 0x07; + + if (ecc <= 1) + ret = SFC_NAND_ECC_OK; + else if (ecc == 3 || ecc == 5) + ret = SFC_NAND_ECC_REFRESH; + else + ret = (u32)SFC_NAND_ECC_ERROR; + + return ret; +} + u32 sfc_nand_erase_block(u8 cs, u32 addr) { int ret; diff --git a/u-boot/drivers/ufs/ufs.c b/u-boot/drivers/ufs/ufs.c index 992f3ff50ee..cddbbfb7cbb 100644 --- a/u-boot/drivers/ufs/ufs.c +++ b/u-boot/drivers/ufs/ufs.c @@ -1940,7 +1940,8 @@ retry: if (hba->dev_desc->w_spec_version == 0x2002) if (hba->dev_desc->w_manufacturer_id == 0x250A || - hba->dev_desc->w_manufacturer_id == 0x9802) + hba->dev_desc->w_manufacturer_id == 0x9802 || + hba->dev_desc->w_manufacturer_id == 0xD60C ) hba->quirks |= UFSDEV_QUIRK_LUN_IN_SCSI_COMMANDS; return ret; diff --git a/u-boot/drivers/usb/host/ohci-hcd.c b/u-boot/drivers/usb/host/ohci-hcd.c index 76b9c8d4f46..1c18bdd48f1 100644 --- a/u-boot/drivers/usb/host/ohci-hcd.c +++ b/u-boot/drivers/usb/host/ohci-hcd.c @@ -961,7 +961,8 @@ static void td_submit_job(ohci_t *ohci, struct usb_device *dev, __u32 info = 0; unsigned int toggle = 0; - flush_dcache_buffer(buffer, data_len); + if (buffer && data_len > 0) + flush_dcache_buffer(buffer, data_len); /* OHCI handles the DATA-toggles itself, we just use the USB-toggle * bits for resetting */ diff --git a/u-boot/drivers/video/drm/analogix_dp.c b/u-boot/drivers/video/drm/analogix_dp.c index f766e15912c..1083efa6131 100644 --- a/u-boot/drivers/video/drm/analogix_dp.c +++ b/u-boot/drivers/video/drm/analogix_dp.c @@ -15,6 +15,7 @@ #include #include #include +#include #include #include #include @@ -35,6 +36,11 @@ * @lcdsel_lit: reg value of selecting vop little for eDP * @chip_type: specific chip type * @ssc: check if SSC is supported by source + * @max_link_rate: max supported link rate + * @max_lane_count: max supported lane count + * @format_yuv: check if yuv color format is supported + * @support_dp_mode: check if dp mode is supported + * @max_bpc: max supported bpc which set to 8 by default */ struct rockchip_dp_chip_data { u32 lcdsel_grf_reg; @@ -45,8 +51,33 @@ struct rockchip_dp_chip_data { u32 max_link_rate; u32 max_lane_count; + bool format_yuv; + bool support_dp_mode; + u8 max_bpc; }; +static const struct analogix_dp_output_format possible_output_fmts[] = { + { MEDIA_BUS_FMT_RGB101010_1X30, DRM_COLOR_FORMAT_RGB444, 10 }, + { MEDIA_BUS_FMT_RGB888_1X24, DRM_COLOR_FORMAT_RGB444, 8 }, + { MEDIA_BUS_FMT_RGB666_1X24_CPADHI, DRM_COLOR_FORMAT_RGB444, 6 }, + { MEDIA_BUS_FMT_YUV10_1X30, DRM_COLOR_FORMAT_YCRCB444, 10 }, + { MEDIA_BUS_FMT_YUV8_1X24, DRM_COLOR_FORMAT_YCRCB444, 8}, + { MEDIA_BUS_FMT_YUYV10_1X20, DRM_COLOR_FORMAT_YCRCB422, 10 }, + { MEDIA_BUS_FMT_YUYV8_1X16, DRM_COLOR_FORMAT_YCRCB422, 8 }, +}; + +static u8 analogix_dp_get_output_bpp(const struct analogix_dp_output_format *fmt) +{ + switch (fmt->color_format) { + case DRM_COLOR_FORMAT_YCRCB422: + return fmt->bpc * 2; + case DRM_COLOR_FORMAT_RGB444: + case DRM_COLOR_FORMAT_YCRCB444: + default: + return fmt->bpc * 3; + } +} + static int analogix_dp_enable_rx_to_enhanced_mode(struct analogix_dp_device *dp, bool enable) @@ -69,37 +100,19 @@ analogix_dp_enable_rx_to_enhanced_mode(struct analogix_dp_device *dp, return ret < 0 ? ret : 0; } -static int analogix_dp_is_enhanced_mode_available(struct analogix_dp_device *dp, - u8 *enhanced_mode_support) -{ - u8 data; - int ret; - - ret = drm_dp_dpcd_readb(&dp->aux, DP_MAX_LANE_COUNT, &data); - if (ret != 1) { - *enhanced_mode_support = 0; - return ret; - } - - *enhanced_mode_support = DPCD_ENHANCED_FRAME_CAP(data); - - return 0; -} - static int analogix_dp_set_enhanced_mode(struct analogix_dp_device *dp) { + bool enhanced_frame_en; u8 data; int ret; - ret = analogix_dp_is_enhanced_mode_available(dp, &data); - if (ret < 0) - return ret; + enhanced_frame_en = drm_dp_enhanced_frame_cap(dp->dpcd); - ret = analogix_dp_enable_rx_to_enhanced_mode(dp, data); + ret = analogix_dp_enable_rx_to_enhanced_mode(dp, enhanced_frame_en); if (ret < 0) return ret; - if (!data) { + if (!enhanced_frame_en) { /* * As the Table 3-4 in eDP v1.2 spec: * DPCD 0000Dh: @@ -118,10 +131,10 @@ static int analogix_dp_set_enhanced_mode(struct analogix_dp_device *dp) if (ret < 0) return ret; - data = !!(data & DP_FRAMING_CHANGE_CAP); + enhanced_frame_en = !!(data & DP_FRAMING_CHANGE_CAP); } - analogix_dp_enable_enhanced_mode(dp, data); + analogix_dp_enable_enhanced_mode(dp, enhanced_frame_en); return 0; } @@ -138,6 +151,41 @@ static int analogix_dp_training_pattern_dis(struct analogix_dp_device *dp) return ret < 0 ? ret : 0; } +static int analogix_dp_enable_sink_to_assr_mode(struct analogix_dp_device *dp, bool enable) +{ + u8 data; + int ret; + + ret = drm_dp_dpcd_readb(&dp->aux, DP_EDP_CONFIGURATION_SET, &data); + if (ret != 1) + return ret; + + if (enable) + ret = drm_dp_dpcd_writeb(&dp->aux, DP_EDP_CONFIGURATION_SET, + data | DP_ALTERNATE_SCRAMBLER_RESET_ENABLE); + else + ret = drm_dp_dpcd_writeb(&dp->aux, DP_EDP_CONFIGURATION_SET, + data & ~DP_ALTERNATE_SCRAMBLER_RESET_ENABLE); + + return ret < 0 ? ret : 0; +} + +static int analogix_dp_set_assr_mode(struct analogix_dp_device *dp) +{ + bool assr_en; + int ret; + + assr_en = drm_dp_alternate_scrambler_reset_cap(dp->dpcd); + + ret = analogix_dp_enable_sink_to_assr_mode(dp, assr_en); + if (ret < 0) + return ret; + + analogix_dp_enable_assr_mode(dp, assr_en); + + return 0; +} + static int analogix_dp_link_start(struct analogix_dp_device *dp) { u8 buf[4]; @@ -175,6 +223,13 @@ static int analogix_dp_link_start(struct analogix_dp_device *dp) if (retval < 0) return retval; + /* set ASSR if available */ + retval = analogix_dp_set_assr_mode(dp); + if (retval < 0) { + dev_err(dp->dev, "failed to set assr mode\n"); + return retval; + } + /* set enhanced mode if available */ retval = analogix_dp_set_enhanced_mode(dp); if (retval < 0) { @@ -465,11 +520,10 @@ static int analogix_dp_process_equalizer_training(struct analogix_dp_device *dp) } static bool analogix_dp_bandwidth_ok(struct analogix_dp_device *dp, - const struct drm_display_mode *mode, + const struct drm_display_mode *mode, u32 bpp, unsigned int rate, unsigned int lanes) { u32 max_bw, req_bw; - u32 bpp = 3 * dp->video_info.bpc; req_bw = mode->clock * bpp / 8; max_bw = lanes * rate; @@ -516,8 +570,9 @@ static int analogix_dp_select_link_rate_from_table(struct analogix_dp_device *dp for (i = 0; i < dp->nr_link_rate_table; i++) { bw_code = drm_dp_link_rate_to_bw_code(dp->link_rate_table[i]); - if (!analogix_dp_bandwidth_ok(dp, &dp->video_info.mode, dp->link_rate_table[i], - dp->link_train.lane_count)) + if (!analogix_dp_bandwidth_ok(dp, &dp->video_info.mode, + analogix_dp_get_output_bpp(dp->output_fmt), + dp->link_rate_table[i], dp->link_train.lane_count)) continue; if (dp->link_rate_table[i] <= max_link_rate && @@ -645,10 +700,6 @@ static int analogix_dp_init_training(struct analogix_dp_device *dp, */ analogix_dp_reset_macro(dp); - /* Initialize by reading RX's DPCD */ - analogix_dp_get_max_rx_bandwidth(dp, &dp->link_train.link_rate); - analogix_dp_get_max_rx_lane_count(dp, &dp->link_train.lane_count); - /* Setup TX lane count */ dp->link_train.lane_count = min_t(u32, dp->link_train.lane_count, max_lane); @@ -832,128 +883,19 @@ static void analogix_dp_init_dp(struct analogix_dp_device *dp) analogix_dp_init_aux(dp); } -static unsigned char analogix_dp_calc_edid_check_sum(unsigned char *edid_data) -{ - int i; - unsigned char sum = 0; - - for (i = 0; i < EDID_BLOCK_LENGTH; i++) - sum = sum + edid_data[i]; - - return sum; -} - -static int analogix_dp_read_edid(struct analogix_dp_device *dp) -{ - unsigned char *edid = dp->edid; - unsigned int extend_block = 0; - unsigned char test_vector; - int retval; - - /* - * EDID device address is 0x50. - * However, if necessary, you must have set upper address - * into E-EDID in I2C device, 0x30. - */ - - /* Read Extension Flag, Number of 128-byte EDID extension blocks */ - retval = analogix_dp_read_byte_from_i2c(dp, I2C_EDID_DEVICE_ADDR, - EDID_EXTENSION_FLAG, - &extend_block); - if (retval) - return retval; - - if (extend_block > 0) { - debug("EDID data includes a single extension!\n"); - - /* Read EDID data */ - retval = analogix_dp_read_bytes_from_i2c(dp, - I2C_EDID_DEVICE_ADDR, - EDID_HEADER_PATTERN, - EDID_BLOCK_LENGTH, - &edid[EDID_HEADER_PATTERN]); - if (retval < 0) - return retval; - - if (analogix_dp_calc_edid_check_sum(edid)) - return -EINVAL; - - /* Read additional EDID data */ - retval = analogix_dp_read_bytes_from_i2c(dp, - I2C_EDID_DEVICE_ADDR, - EDID_BLOCK_LENGTH, - EDID_BLOCK_LENGTH, - &edid[EDID_BLOCK_LENGTH]); - if (retval < 0) - return retval; - - if (analogix_dp_calc_edid_check_sum(&edid[EDID_BLOCK_LENGTH])) - return -EINVAL; - - drm_dp_dpcd_readb(&dp->aux, DP_TEST_REQUEST, &test_vector); - if (test_vector & DP_TEST_LINK_EDID_READ) { - drm_dp_dpcd_writeb(&dp->aux, DP_TEST_EDID_CHECKSUM, - edid[EDID_BLOCK_LENGTH + EDID_CHECKSUM]); - drm_dp_dpcd_writeb(&dp->aux, DP_TEST_RESPONSE, - DP_TEST_EDID_CHECKSUM_WRITE); - } - } else { - dev_info(dp->dev, - "EDID data does not include any extensions.\n"); - - /* Read EDID data */ - retval = analogix_dp_read_bytes_from_i2c(dp, - I2C_EDID_DEVICE_ADDR, EDID_HEADER_PATTERN, - EDID_BLOCK_LENGTH, &edid[EDID_HEADER_PATTERN]); - if (retval < 0) - return retval; - - if (analogix_dp_calc_edid_check_sum(edid)) - return -EINVAL; - - drm_dp_dpcd_readb(&dp->aux, DP_TEST_REQUEST, &test_vector); - if (test_vector & DP_TEST_LINK_EDID_READ) { - drm_dp_dpcd_writeb(&dp->aux, DP_TEST_EDID_CHECKSUM, - edid[EDID_CHECKSUM]); - drm_dp_dpcd_writeb(&dp->aux, DP_TEST_RESPONSE, - DP_TEST_EDID_CHECKSUM_WRITE); - } - } - - return 0; -} - -static int analogix_dp_handle_edid(struct analogix_dp_device *dp) -{ - u8 buf[12]; - int i, try = 5; - int retval; - -retry: - /* Read DPCD DP_DPCD_REV~RECEIVE_PORT1_CAP_1 */ - retval = drm_dp_dpcd_read(&dp->aux, DP_DPCD_REV, buf, 12); - if (retval < 0 && try--) { - mdelay(10); - goto retry; - } - - if (retval) - return retval; - - /* Read EDID */ - for (i = 0; i < 3; i++) { - retval = analogix_dp_read_edid(dp); - if (!retval) - break; - } - - return retval; -} - static int analogix_dp_connector_init(struct rockchip_connector *conn, struct display_state *state) { struct connector_state *conn_state = &state->conn_state; struct analogix_dp_device *dp = dev_get_priv(conn->dev); + int submode = PHY_SUBMODE_EDP; + + if (!conn->panel) + dp->dp_mode = true; + + if (dev_read_bool(conn->dev, "dp-mode")) + dp->dp_mode = true; + else if (dev_read_bool(conn->dev, "edp-mode")) + dp->dp_mode = false; conn_state->output_if |= dp->id ? VOP_OUTPUT_IF_eDP1 : VOP_OUTPUT_IF_eDP0; conn_state->output_mode = ROCKCHIP_OUT_MODE_AAAA; @@ -965,7 +907,9 @@ static int analogix_dp_connector_init(struct rockchip_connector *conn, struct di reset_deassert_bulk(&dp->resets); conn_state->disp_info = rockchip_get_disp_info(conn_state->type, dp->id); - generic_phy_set_mode(&dp->phy, PHY_MODE_DP); + if (dp->plat_data.support_dp_mode && dp->dp_mode) + submode = PHY_SUBMODE_DP; + generic_phy_set_mode_ext(&dp->phy, PHY_MODE_DP, submode); generic_phy_power_on(&dp->phy); analogix_dp_init_dp(dp); @@ -979,15 +923,9 @@ static int analogix_dp_connector_get_edid(struct rockchip_connector *conn, struct analogix_dp_device *dp = dev_get_priv(conn->dev); int ret; - ret = analogix_dp_handle_edid(dp); - if (ret) { - dev_err(dp->dev, "failed to get edid\n"); - return ret; - } - - memcpy(&conn_state->edid, &dp->edid, sizeof(dp->edid)); + ret = drm_do_get_edid(&dp->aux.ddc, conn_state->edid); - return 0; + return ret; } static int analogix_dp_link_power_up(struct analogix_dp_device *dp) @@ -1036,6 +974,52 @@ static int analogix_dp_link_power_down(struct analogix_dp_device *dp) return 0; } +static u32 analogix_dp_get_output_format(struct analogix_dp_device *dp, u32 bus_format) +{ + unsigned int i; + + for (i = 0; i < ARRAY_SIZE(possible_output_fmts); i++) { + const struct analogix_dp_output_format *fmt = &possible_output_fmts[i]; + + if (fmt->bus_format == bus_format) + break; + } + + if (i == ARRAY_SIZE(possible_output_fmts)) + return 1; + + return i; +} + +static u32 analogix_dp_get_output_format_by_edid(struct analogix_dp_device *dp, + struct hdmi_edid_data *edid_data) +{ + unsigned int i; + + for (i = 0; i < ARRAY_SIZE(possible_output_fmts); i++) { + const struct analogix_dp_output_format *fmt = &possible_output_fmts[i]; + + if (fmt->bpc > edid_data->display_info.bpc || fmt->bpc > dp->plat_data.max_bpc) + continue; + + if (!(edid_data->display_info.color_formats & fmt->color_format)) + continue; + + if (!analogix_dp_bandwidth_ok(dp, edid_data->preferred_mode, + analogix_dp_get_output_bpp(fmt), + drm_dp_bw_code_to_link_rate(dp->link_train.link_rate), + dp->link_train.lane_count)) + continue; + + break; + } + + if (i == ARRAY_SIZE(possible_output_fmts)) + return 1; + + return i; +} + static int analogix_dp_connector_enable(struct rockchip_connector *conn, struct display_state *state) { @@ -1046,6 +1030,7 @@ static int analogix_dp_connector_enable(struct rockchip_connector *conn, struct analogix_dp_device *dp = dev_get_priv(conn->dev); struct video_info *video = &dp->video_info; struct drm_display_mode mode; + u32 fmt_id; u32 val; int ret; @@ -1064,8 +1049,12 @@ static int analogix_dp_connector_enable(struct rockchip_connector *conn, regmap_write(dp->grf, dp->id ? RK3588_GRF_VO1_CON1 : RK3588_GRF_VO1_CON0, EDP_MODE << 16 | FIELD_PREP(EDP_MODE, 1)); - video->bpc = conn_state->bpc; - switch (video->bpc) { + if (!dp->output_fmt) { + fmt_id = analogix_dp_get_output_format(dp, conn_state->bus_format); + dp->output_fmt = &possible_output_fmts[fmt_id]; + } + + switch (dp->output_fmt->bpc) { case 12: video->color_depth = COLOR_12; break; @@ -1080,6 +1069,16 @@ static int analogix_dp_connector_enable(struct rockchip_connector *conn, video->color_depth = COLOR_8; break; } + if (dp->output_fmt->color_format == DRM_COLOR_FORMAT_YCRCB444) { + video->color_space = COLOR_YCBCR444; + video->ycbcr_coeff = COLOR_YCBCR709; + } else if (dp->output_fmt->color_format == DRM_COLOR_FORMAT_YCRCB422) { + video->color_space = COLOR_YCBCR422; + video->ycbcr_coeff = COLOR_YCBCR709; + } else { + video->color_space = COLOR_RGB; + video->ycbcr_coeff = COLOR_YCBCR601; + } ret = drm_dp_dpcd_read(&dp->aux, DP_DPCD_REV, dp->dpcd, DP_RECEIVER_CAP_SIZE); if (ret < 0) { @@ -1146,8 +1145,26 @@ static int analogix_dp_connector_detect(struct rockchip_connector *conn, struct display_state *state) { struct analogix_dp_device *dp = dev_get_priv(conn->dev); + int ret; + + if (analogix_dp_detect(dp)) { + /* Initialize by reading RX's DPCD */ + ret = analogix_dp_get_max_rx_bandwidth(dp, &dp->link_train.link_rate); + if (ret) { + dev_err(dp->dev, "failed to read max link rate\n"); + return 0; + } + + ret = analogix_dp_get_max_rx_lane_count(dp, &dp->link_train.lane_count); + if (ret) { + dev_err(dp->dev, "failed to read max lane count\n"); + return 0; + } - return analogix_dp_detect(dp); + return 1; + } else { + return 0; + } } static int analogix_dp_connector_mode_valid(struct rockchip_connector *conn, @@ -1166,6 +1183,123 @@ static int analogix_dp_connector_mode_valid(struct rockchip_connector *conn, return MODE_OK; } +static int analogix_dp_mode_valid(struct analogix_dp_device *dp, struct hdmi_edid_data *edid_data) +{ + struct drm_display_info *di = &edid_data->display_info; + u32 max_link_rate, max_lane_count; + u32 min_bpp; + int i; + + if (di->color_formats & DRM_COLOR_FORMAT_YCRCB422) + min_bpp = 16; + else if (di->color_formats & DRM_COLOR_FORMAT_RGB444) + min_bpp = 18; + else + min_bpp = 24; + + max_link_rate = min_t(u32, dp->video_info.max_link_rate, dp->link_train.link_rate); + max_lane_count = min_t(u32, dp->video_info.max_lane_count, dp->link_train.lane_count); + for (i = 0; i < edid_data->modes; i++) { + if (!analogix_dp_bandwidth_ok(dp, &edid_data->mode_buf[i], min_bpp, + drm_dp_bw_code_to_link_rate(max_link_rate), + max_lane_count)) + edid_data->mode_buf[i].invalid = true; + } + + return 0; +} + +static int analogix_dp_connector_get_timing(struct rockchip_connector *conn, + struct display_state *state) +{ + struct connector_state *conn_state = &state->conn_state; + const struct rockchip_dp_chip_data *pdata = + (const struct rockchip_dp_chip_data *)dev_get_driver_data(conn->dev); + struct analogix_dp_device *dp = dev_get_priv(conn->dev); + struct drm_display_mode *mode = &conn_state->mode; + struct hdmi_edid_data edid_data; + struct drm_display_mode *mode_buf; + struct vop_rect rect; + u32 yuv_fmts_mask = DRM_COLOR_FORMAT_YCRCB444 | DRM_COLOR_FORMAT_YCRCB422; + u32 fmt_id; + int ret, i; + + mode_buf = malloc(MODE_LEN * sizeof(struct drm_display_mode)); + if (!mode_buf) + return -ENOMEM; + + memset(mode_buf, 0, MODE_LEN * sizeof(struct drm_display_mode)); + memset(&edid_data, 0, sizeof(struct hdmi_edid_data)); + edid_data.mode_buf = mode_buf; + + ret = drm_do_get_edid(&dp->aux.ddc, conn_state->edid); + if (!ret) + ret = drm_add_edid_modes(&edid_data, conn_state->edid); + + if (ret < 0) { + printf("failed to get edid\n"); + goto err; + } + + if (!pdata->format_yuv) { + if (edid_data.display_info.color_formats & yuv_fmts_mask) { + printf("Swapping display color format from YUV to RGB\n"); + edid_data.display_info.color_formats &= ~yuv_fmts_mask; + edid_data.display_info.color_formats |= DRM_COLOR_FORMAT_RGB444; + } + } + + if (state->conn_state.secondary) { + rect.width = state->crtc_state.max_output.width / 2; + rect.height = state->crtc_state.max_output.height / 2; + } else { + rect.width = state->crtc_state.max_output.width; + rect.height = state->crtc_state.max_output.height; + } + + drm_mode_max_resolution_filter(&edid_data, &rect); + analogix_dp_mode_valid(dp, &edid_data); + + if (!drm_mode_prune_invalid(&edid_data)) { + printf("can't find valid dp mode\n"); + ret = -EINVAL; + goto err; + } + + for (i = 0; i < edid_data.modes; i++) + edid_data.mode_buf[i].vrefresh = drm_mode_vrefresh(&edid_data.mode_buf[i]); + + drm_mode_sort(&edid_data); + memcpy(mode, edid_data.preferred_mode, sizeof(struct drm_display_mode)); + + fmt_id = analogix_dp_get_output_format_by_edid(dp, &edid_data); + dp->output_fmt = &possible_output_fmts[fmt_id]; + + switch (dp->output_fmt->color_format) { + case DRM_COLOR_FORMAT_YCRCB422: + conn_state->output_mode = ROCKCHIP_OUT_MODE_YUV422; + break; + case DRM_COLOR_FORMAT_RGB444: + case DRM_COLOR_FORMAT_YCRCB444: + default: + conn_state->output_mode = ROCKCHIP_OUT_MODE_AAAA; + break; + } + + conn_state->bus_format = dp->output_fmt->bus_format; + conn_state->bpc = dp->output_fmt->bpc; + conn_state->color_encoding = DRM_COLOR_YCBCR_BT709; + if (dp->output_fmt->color_format == DRM_COLOR_FORMAT_RGB444) + conn_state->color_range = DRM_COLOR_YCBCR_FULL_RANGE; + else + conn_state->color_range = DRM_COLOR_YCBCR_LIMITED_RANGE; + +err: + free(mode_buf); + + return 0; +} + static const struct rockchip_connector_funcs analogix_dp_connector_funcs = { .init = analogix_dp_connector_init, .get_edid = analogix_dp_connector_get_edid, @@ -1173,6 +1307,7 @@ static const struct rockchip_connector_funcs analogix_dp_connector_funcs = { .disable = analogix_dp_connector_disable, .detect = analogix_dp_connector_detect, .mode_valid = analogix_dp_connector_mode_valid, + .get_timing = analogix_dp_connector_get_timing, }; static u32 analogix_dp_parse_link_frequencies(struct analogix_dp_device *dp) @@ -1296,6 +1431,8 @@ static int analogix_dp_probe(struct udevice *dev) dp->plat_data.dev_type = ROCKCHIP_DP; dp->plat_data.subdev_type = pdata->chip_type; dp->plat_data.ssc = pdata->ssc; + dp->plat_data.support_dp_mode = pdata->support_dp_mode; + dp->plat_data.max_bpc = pdata->max_bpc ? pdata->max_bpc : 8; dp->video_info.max_link_rate = pdata->max_link_rate; dp->video_info.max_lane_count = pdata->max_lane_count; @@ -1358,6 +1495,9 @@ static const struct rockchip_dp_chip_data rk3576_edp_platform_data = { .max_link_rate = DP_LINK_BW_5_4, .max_lane_count = 4, + .format_yuv = true, + .support_dp_mode = true, + .max_bpc = 10, }; static const struct rockchip_dp_chip_data rk3588_edp_platform_data = { @@ -1366,6 +1506,9 @@ static const struct rockchip_dp_chip_data rk3588_edp_platform_data = { .max_link_rate = DP_LINK_BW_5_4, .max_lane_count = 4, + .format_yuv = true, + .support_dp_mode = true, + .max_bpc = 10, }; static const struct udevice_id analogix_dp_ids[] = { diff --git a/u-boot/drivers/video/drm/analogix_dp.h b/u-boot/drivers/video/drm/analogix_dp.h index 650a476431d..c6cb113190e 100644 --- a/u-boot/drivers/video/drm/analogix_dp.h +++ b/u-boot/drivers/video/drm/analogix_dp.h @@ -125,6 +125,8 @@ #define ANALOGIX_DP_SOC_GENERAL_CTL 0x800 +#define ANALOGIX_DP_LINK_POLICY 0x9D8 + /* ANALOGIX_DP_TX_SW_RESET */ #define RESET_DP_TX (0x1 << 0) @@ -455,6 +457,9 @@ #define VIDEO_MODE_SLAVE_MODE (0x1 << 0) #define VIDEO_MODE_MASTER_MODE (0x0 << 0) +/* ANALOGIX_DP_LINK_POLICY */ +#define ALTERNATE_SR_ENABLE (0x1 << 7) + #define DP_TIMEOUT_LOOP_COUNT 100 #define MAX_CR_LOOP 5 #define MAX_EQ_LOOP 5 @@ -630,6 +635,8 @@ struct analogix_dp_plat_data { enum analogix_dp_devtype dev_type; enum analogix_dp_sub_devtype subdev_type; bool ssc; + bool support_dp_mode; + u8 max_bpc; }; struct analogix_dp_device { @@ -654,6 +661,14 @@ struct analogix_dp_device { bool video_bist_enable; u32 lane_map[4]; struct drm_dp_aux aux; + const struct analogix_dp_output_format *output_fmt; + bool dp_mode; +}; + +struct analogix_dp_output_format { + u32 bus_format; + u32 color_format; + u8 bpc; }; /* analogix_dp_reg.c */ @@ -726,5 +741,7 @@ void analogix_dp_set_video_format(struct analogix_dp_device *dp, const struct drm_display_mode *mode); void analogix_dp_video_bist_enable(struct analogix_dp_device *dp); ssize_t analogix_dp_aux_transfer(struct drm_dp_aux *aux, struct drm_dp_aux_msg *msg); +void analogix_dp_enable_assr_mode(struct analogix_dp_device *dp, bool enable); +bool analogix_dp_get_assr_mode(struct analogix_dp_device *dp); #endif /* __DRM_ANALOGIX_DP__ */ diff --git a/u-boot/drivers/video/drm/analogix_dp_reg.c b/u-boot/drivers/video/drm/analogix_dp_reg.c index 920a9f8d074..b5cb6b123be 100644 --- a/u-boot/drivers/video/drm/analogix_dp_reg.c +++ b/u-boot/drivers/video/drm/analogix_dp_reg.c @@ -1312,3 +1312,27 @@ aux_error: return -EREMOTEIO; } + +void analogix_dp_enable_assr_mode(struct analogix_dp_device *dp, bool enable) +{ + u32 reg; + + if (enable) { + reg = analogix_dp_read(dp, ANALOGIX_DP_LINK_POLICY); + reg |= ALTERNATE_SR_ENABLE; + analogix_dp_write(dp, ANALOGIX_DP_LINK_POLICY, reg); + } else { + reg = analogix_dp_read(dp, ANALOGIX_DP_LINK_POLICY); + reg &= ~ALTERNATE_SR_ENABLE; + analogix_dp_write(dp, ANALOGIX_DP_LINK_POLICY, reg); + } +} + +bool analogix_dp_get_assr_mode(struct analogix_dp_device *dp) +{ + u32 reg; + + reg = analogix_dp_read(dp, ANALOGIX_DP_LINK_POLICY); + + return !!(reg & ALTERNATE_SR_ENABLE); +} diff --git a/u-boot/drivers/video/drm/display-serdes/core.h b/u-boot/drivers/video/drm/display-serdes/core.h index 71de5c38e75..f4dec11fd50 100644 --- a/u-boot/drivers/video/drm/display-serdes/core.h +++ b/u-boot/drivers/video/drm/display-serdes/core.h @@ -316,6 +316,7 @@ struct serdes { int err_irq_trig; bool sel_mipi; + bool mcu_enable; struct mipi_dsi_device *dsi; bool split_mode_enable; diff --git a/u-boot/drivers/video/drm/display-serdes/serdes-bridge.c b/u-boot/drivers/video/drm/display-serdes/serdes-bridge.c index daa5a4debef..ab8a7528b31 100644 --- a/u-boot/drivers/video/drm/display-serdes/serdes-bridge.c +++ b/u-boot/drivers/video/drm/display-serdes/serdes-bridge.c @@ -106,6 +106,11 @@ static bool serdes_bridge_detect(struct rockchip_bridge *bridge) struct udevice *dev = bridge->dev; struct serdes *serdes = dev_get_priv(dev->parent); + if(serdes->mcu_enable) { + printf("serdes %s detect link status in MCU\n", serdes->dev->name); + return ret; + } + if (serdes->chip_data->bridge_ops->detect) ret = serdes->chip_data->bridge_ops->detect(serdes, SER_LINKA); diff --git a/u-boot/drivers/video/drm/display-serdes/serdes-core.c b/u-boot/drivers/video/drm/display-serdes/serdes-core.c index 5fa7a106d7e..520c19dc657 100644 --- a/u-boot/drivers/video/drm/display-serdes/serdes-core.c +++ b/u-boot/drivers/video/drm/display-serdes/serdes-core.c @@ -189,6 +189,11 @@ int serdes_i2c_set_sequence(struct serdes *serdes) int i, ret = 0; unsigned int def = 0; + if(serdes->mcu_enable) { + printf("serdes %s i2c set sequence in MCU\n", serdes->dev->name); + return 0; + } + for (i = 0; i < serdes->serdes_init_seq->reg_seq_cnt; i++) { if (serdes->serdes_init_seq->reg_sequence[i].reg == 0xffff) { SERDES_DBG_MFD("%s: delay 0x%04x us\n", __func__, diff --git a/u-boot/drivers/video/drm/display-serdes/serdes-i2c.c b/u-boot/drivers/video/drm/display-serdes/serdes-i2c.c index 933bca96f00..5a16d0c62f3 100644 --- a/u-boot/drivers/video/drm/display-serdes/serdes-i2c.c +++ b/u-boot/drivers/video/drm/display-serdes/serdes-i2c.c @@ -118,6 +118,8 @@ static int serdes_i2c_probe(struct udevice *dev) SERDES_DBG_MFD("%s: failed to err gpio: %d\n", __func__, ret); + serdes->mcu_enable = dev_read_bool(dev, "mcu-enable"); + if (serdes->chip_data->serdes_type == TYPE_OTHER) { SERDES_DBG_MFD("TYPE_OTHER just need only init i2c\n"); serdes_i2c_init(serdes); @@ -143,14 +145,17 @@ static int serdes_i2c_probe(struct udevice *dev) serdes->serdes_bridge_split = serdes_bridge_split; } - serdes_pinctrl = calloc(1, sizeof(*serdes_pinctrl)); - if (!serdes_pinctrl) - return -ENOMEM; + if(!serdes->mcu_enable) { + serdes_pinctrl = calloc(1, sizeof(*serdes_pinctrl)); + if (!serdes_pinctrl) + return -ENOMEM; - serdes->serdes_pinctrl = serdes_pinctrl; - ret = serdes_pinctrl_register(dev, serdes); - if (ret) - return ret; + serdes->serdes_pinctrl = serdes_pinctrl; + ret = serdes_pinctrl_register(dev, serdes); + if (ret) + return ret; + } else + printf("serdes %s iomux init in MCU\n", serdes->dev->name); serdes->id_serdes_bridge_split = dev_read_u32_default(dev, "id-serdes-bridge-split", 0); if ((serdes->id_serdes_bridge_split < MAX_NUM_SERDES_SPLIT) && (serdes->type == TYPE_SER)) { diff --git a/u-boot/drivers/video/drm/dw-dp.c b/u-boot/drivers/video/drm/dw-dp.c index 261e8cb7d93..e94370d949e 100644 --- a/u-boot/drivers/video/drm/dw-dp.c +++ b/u-boot/drivers/video/drm/dw-dp.c @@ -1834,7 +1834,6 @@ static int dw_dp_bind(struct udevice *parent) debug("%s: subnode %s\n", __func__, node_name); if (!strcasecmp(node_name, "dp0")) { - printf("%s zyb enter\n", __func__); ret = device_bind_driver_to_node(parent, "dw_dp_port0", node_name, subnode, &child); diff --git a/u-boot/drivers/video/drm/dw_mipi_dsi.c b/u-boot/drivers/video/drm/dw_mipi_dsi.c index 4488710d5c5..f8ca89c1e67 100644 --- a/u-boot/drivers/video/drm/dw_mipi_dsi.c +++ b/u-boot/drivers/video/drm/dw_mipi_dsi.c @@ -1032,9 +1032,9 @@ static void dw_mipi_dsi_command_mode_config(struct dw_mipi_dsi *dsi) /* Get lane byte clock cycles. */ static int dw_mipi_dsi_get_hcomponent_lbcc(struct dw_mipi_dsi *dsi, - u32 hcomponent) + u64 hcomponent) { - u32 lbcc; + u64 lbcc; lbcc = hcomponent * dsi->lane_mbps * 1000 / 8; @@ -1597,6 +1597,20 @@ static const struct dw_mipi_dsi_plat_data rv1126_mipi_dsi_plat_data = { .max_bit_rate_per_lane = 1000000000UL, }; +static const u32 rv1126b_dsi_grf_reg_fields[MAX_FIELDS] = { + [DPIUPDATECFG] = GRF_REG_FIELD(0x8000c, 3, 3), + [DPICOLORM] = GRF_REG_FIELD(0x8000c, 1, 1), + [DPISHUTDN] = GRF_REG_FIELD(0x8000c, 0, 0), + [FORCETXSTOPMODE] = GRF_REG_FIELD(0x80010, 4, 7), + [TURNDISABLE] = GRF_REG_FIELD(0x80010, 2, 2), + [FORCERXMODE] = GRF_REG_FIELD(0x80010, 0, 0), +}; + +static const struct dw_mipi_dsi_plat_data rv1126b_mipi_dsi_plat_data = { + .dsi0_grf_reg_fields = rv1126b_dsi_grf_reg_fields, + .max_bit_rate_per_lane = 1000000000UL, +}; + static const struct udevice_id dw_mipi_dsi_ids[] = { { .compatible = "rockchip,px30-mipi-dsi", @@ -1646,6 +1660,10 @@ static const struct udevice_id dw_mipi_dsi_ids[] = { .compatible = "rockchip,rv1126-mipi-dsi", .data = (ulong)&rv1126_mipi_dsi_plat_data, }, + { + .compatible = "rockchip,rv1126b-mipi-dsi", + .data = (ulong)&rv1126b_mipi_dsi_plat_data, + }, {} }; diff --git a/u-boot/drivers/video/drm/dw_mipi_dsi2.c b/u-boot/drivers/video/drm/dw_mipi_dsi2.c index eaab8935364..ecd086d7d62 100644 --- a/u-boot/drivers/video/drm/dw_mipi_dsi2.c +++ b/u-boot/drivers/video/drm/dw_mipi_dsi2.c @@ -689,12 +689,16 @@ static void dw_mipi_dsi2_enable(struct dw_mipi_dsi2 *dsi2) dw_mipi_dsi2_ipi_set(dsi2); if (dsi2->auto_calc_mode) { + dsi_update_bits(dsi2, DSI2_DSI_GENERAL_CFG, BTA_EN, 0); + dsi_write(dsi2, DSI2_MODE_CTRL, AUTOCALC_MODE); ret = readl_poll_timeout(dsi2->base + DSI2_MODE_STATUS, mode, mode == IDLE_MODE, MODE_STATUS_TIMEOUT_US); if (ret < 0) printf("auto calculation training failed\n"); + + dsi_update_bits(dsi2, DSI2_DSI_GENERAL_CFG, BTA_EN, BTA_EN); } if (dsi2->mode_flags & MIPI_DSI_MODE_VIDEO) diff --git a/u-boot/drivers/video/drm/inno_mipi_phy.c b/u-boot/drivers/video/drm/inno_mipi_phy.c index 382b4a70518..13287465c4b 100644 --- a/u-boot/drivers/video/drm/inno_mipi_phy.c +++ b/u-boot/drivers/video/drm/inno_mipi_phy.c @@ -102,6 +102,8 @@ #define DIGITAL_RESET_MASK BIT(0) #define DIGITAL_NORMAL BIT(0) #define DIGITAL_RESET 0 +#define INNO_PHY_MODE_CTRL 0x038c +#define MIPI_MODE_ENABLE BIT(0) #define INNO_PHY_LVDS_CTRL 0x03ac #define LVDS_BGPD BIT(0) @@ -746,6 +748,11 @@ static int inno_mipi_dphy_init(struct rockchip_phy *phy) inno->regs = dev_read_addr_ptr(inno->dev); +#if defined(CONFIG_ROCKCHIP_RK3506) + /* The following command switches gpio to MIPI */ + inno_write(inno, INNO_PHY_MODE_CTRL, MIPI_MODE_ENABLE); +#endif + return 0; } @@ -764,7 +771,7 @@ static const struct udevice_id inno_mipi_dphy_ids[] = { .compatible = "rockchip,rk1808-mipi-dphy", }, { - .compatible = "rockchip,rv1126-mipi-dphy", + .compatible = "rockchip,rv1126-dsi-dphy", }, { .compatible = "rockchip,rk3506-dsi-dphy", diff --git a/u-boot/drivers/video/drm/rk628/rk628_combtxphy.c b/u-boot/drivers/video/drm/rk628/rk628_combtxphy.c index bc3ed1381c7..fc7a90d79d2 100644 --- a/u-boot/drivers/video/drm/rk628/rk628_combtxphy.c +++ b/u-boot/drivers/video/drm/rk628/rk628_combtxphy.c @@ -37,6 +37,12 @@ static void rk628_combtxphy_dsi_power_on(struct rk628 *rk628) rk628_i2c_update_bits(rk628, COMBTXPHY_CON0, SW_MODULEB_EN_MASK, SW_MODULEB_EN); + rk628_i2c_update_bits(rk628, COMBTXPHY_CON0, SW_PD_PLL, SW_PD_PLL); + + if (combtxphy->frac_div) + rk628_i2c_update_bits(rk628, COMBTXPHY_CON8, SW_SSC_DEPTH_MASK | SW_SSC_EN_MASK, + SW_SSC_DEPTH(0) | SW_SSC_EN(1)); + rk628_i2c_write(rk628, COMBTXPHY_CON5, SW_REF_DIV(combtxphy->ref_div - 1) | SW_PLL_FB_DIV(combtxphy->fb_div) | @@ -209,7 +215,7 @@ void rk628_combtxphy_set_gvi_division_mode(struct rk628 *rk628, bool division) void rk628_combtxphy_set_mode(struct rk628 *rk628, enum rk628_phy_mode mode) { struct rk628_combtxphy *combtxphy = &rk628->combtxphy; - unsigned int fvco, fpfd, frac_rate, fin = 24; + unsigned int fvco, fpfd, fin = 24; switch (mode) { case RK628_PHY_MODE_VIDEO_MIPI: @@ -218,7 +224,14 @@ void rk628_combtxphy_set_mode(struct rk628 *rk628, enum rk628_phy_mode mode) unsigned int fhsc = bus_width >> 8; unsigned int flags = bus_width & 0xff; - fhsc = fin * (fhsc / fin); + combtxphy->flags = flags; + + /* + * the VCO can work from 1.5GHz to 3GHz. + * fhsc: 80 ~ 374, fvco: 640 ~ 2992 + * fhsc: 375 ~ 749, fvco: 1500 ~ 2996 + * fhsc: 750 ~ 1500, fvco: 1500 ~ 3000 + */ if (fhsc < 80 || fhsc > 1500) return; else if (fhsc < 375) @@ -228,22 +241,26 @@ void rk628_combtxphy_set_mode(struct rk628 *rk628, enum rk628_phy_mode mode) else combtxphy->rate_div = 1; - combtxphy->flags = flags; - fvco = fhsc * 2 * combtxphy->rate_div; + + /* + * the reference clock at PFD(FPFD = ref_clk / ref_div) about + * 25MHz is recommende, FPFD must range from 16MHz to 35MHz, + * here to find the best ref_div. + */ combtxphy->ref_div = 1; - combtxphy->fb_div = fvco / 8 / fin; - frac_rate = fvco - (fin * 8 * combtxphy->fb_div); - if (frac_rate) { - frac_rate <<= 10; - frac_rate /= fin * 8; - combtxphy->frac_div = frac_rate; - } else { - combtxphy->frac_div = 0; - } - fvco = fin * (1024 * combtxphy->fb_div + combtxphy->frac_div); - fvco *= 8; + /* + * fvco = fin * (fb_div + frac_div / 1024) * 8 / ref_div + */ + combtxphy->fb_div = fvco * combtxphy->ref_div / 8 / fin; + combtxphy->frac_div = 1024 * fvco * combtxphy->ref_div / 8 / fin; + combtxphy->frac_div -= 1024 * combtxphy->fb_div; + + /* + * get the actually frequency + */ + fvco = fin * (1024 * combtxphy->fb_div + combtxphy->frac_div) * 8; fvco = DIV_ROUND_UP(fvco, 1024 * combtxphy->ref_div); fhsc = fvco / 2 / combtxphy->rate_div; combtxphy->bus_width = fhsc; diff --git a/u-boot/drivers/video/drm/rk628/rk628_combtxphy.h b/u-boot/drivers/video/drm/rk628/rk628_combtxphy.h index 8522cbfbd7e..2ec3d457b0d 100644 --- a/u-boot/drivers/video/drm/rk628/rk628_combtxphy.h +++ b/u-boot/drivers/video/drm/rk628/rk628_combtxphy.h @@ -58,6 +58,10 @@ #define TX_COM_VOLT_ADJ(x) UPDATE(x, 2, 0) #define COMBTXPHY_CON8 REG(0x0020) +#define SW_SSC_DEPTH_MASK GENMASK(7, 4) +#define SW_SSC_DEPTH(x) UPDATE(x, 7, 4) +#define SW_SSC_EN_MASK BIT(0) +#define SW_SSC_EN(x) UPDATE(x, 0, 0) #define COMBTXPHY_CON9 REG(0x0024) #define SW_DSI_FSET_EN_MASK BIT(29) #define SW_DSI_FSET_EN BIT(29) diff --git a/u-boot/drivers/video/drm/rockchip_crtc.h b/u-boot/drivers/video/drm/rockchip_crtc.h index bed396b2e12..93e8730e94a 100644 --- a/u-boot/drivers/video/drm/rockchip_crtc.h +++ b/u-boot/drivers/video/drm/rockchip_crtc.h @@ -14,10 +14,10 @@ struct rockchip_vp { bool xmirror_en; u8 bg_ovl_dly; u8 primary_plane_id; + u8 cursor_plane_id; u8 dclk_div; int output_type; u32 plane_mask; - int cursor_plane; }; struct rockchip_crtc { @@ -39,6 +39,7 @@ struct rockchip_crtc_funcs { int (*set_plane)(struct display_state *state); int (*prepare)(struct display_state *state); int (*enable)(struct display_state *state); + int (*post_enable)(struct display_state *state); int (*disable)(struct display_state *state); void (*unprepare)(struct display_state *state); int (*fixup_dts)(struct display_state *state, void *blob); diff --git a/u-boot/drivers/video/drm/rockchip_display.c b/u-boot/drivers/video/drm/rockchip_display.c index 1748f4e9038..0cb84717672 100644 --- a/u-boot/drivers/video/drm/rockchip_display.c +++ b/u-boot/drivers/video/drm/rockchip_display.c @@ -929,6 +929,9 @@ static int display_enable(struct display_state *state) if (state->enabled_at_spl == false) rockchip_connector_enable(state); + if (crtc_funcs->post_enable) + crtc_funcs->post_enable(state); + #ifdef CONFIG_DRM_ROCKCHIP_RK628 /* * trigger .probe helper of U_BOOT_DRIVER(rk628) in ./rk628/rk628.c @@ -1021,7 +1024,10 @@ static int display_logo(struct display_state *state) { struct crtc_state *crtc_state = &state->crtc_state; struct connector_state *conn_state = &state->conn_state; + struct overscan *overscan = &conn_state->overscan; struct logo_info *logo = &state->logo; + u32 crtc_x, crtc_y, crtc_w, crtc_h; + u32 overscan_w, overscan_h; int hdisplay, vdisplay, ret; ret = display_init(state); @@ -1082,6 +1088,26 @@ static int display_logo(struct display_state *state) } } + /* + * For some platforms, such as RK3576, use the win scale instead + * of the post scale to configure overscan parameters, because the + * sharp/post scale/split functions are mutually exclusice. + */ + if (crtc_state->overscan_by_win_scale) { + overscan_w = crtc_state->crtc_rect.w * (200 - overscan->left_margin * 2) / 200; + overscan_h = crtc_state->crtc_rect.h * (200 - overscan->top_margin * 2) / 200; + + crtc_x = crtc_state->crtc_rect.x + overscan_w / 2; + crtc_y = crtc_state->crtc_rect.y + overscan_h / 2; + crtc_w = crtc_state->crtc_rect.w - overscan_w; + crtc_h = crtc_state->crtc_rect.h - overscan_h; + + crtc_state->crtc_rect.x = crtc_x; + crtc_state->crtc_rect.y = crtc_y; + crtc_state->crtc_rect.w = crtc_w; + crtc_state->crtc_rect.h = crtc_h; + } + display_check(state); ret = display_set_plane(state); if (ret) @@ -2211,28 +2237,31 @@ static int rockchip_display_probe(struct udevice *dev) bool vp_enable = false; ofnode_for_each_subnode(vp_node, np_to_ofnode(port_parent_node)) { - int cursor_plane = -1; - vp_id = ofnode_read_u32_default(vp_node, "reg", 0); s->crtc_state.crtc->vps[vp_id].xmirror_en = ofnode_read_bool(vp_node, "xmirror-enable"); - ret = ofnode_read_u32_default(vp_node, "rockchip,plane-mask", 0); + s->crtc_state.crtc->vps[vp_id].primary_plane_id = -1; + + /* + * Cursor plane can be assigned and then fixed up to DTS + * without the specific plane mask. + */ + s->crtc_state.crtc->vps[vp_id].cursor_plane_id = + ofnode_read_u32_default(vp_node, "cursor-win-id", -1); - cursor_plane = ofnode_read_u32_default(vp_node, "cursor-win-id", -1); - s->crtc_state.crtc->vps[vp_id].cursor_plane = cursor_plane; - if (ret) { - s->crtc_state.crtc->vps[vp_id].plane_mask = ret; + s->crtc_state.crtc->vps[vp_id].plane_mask = + ofnode_read_u32_default(vp_node, "rockchip,plane-mask", 0); + if (s->crtc_state.crtc->vps[vp_id].plane_mask) { s->crtc_state.crtc->assign_plane |= true; s->crtc_state.crtc->vps[vp_id].primary_plane_id = - ofnode_read_u32_default(vp_node, "rockchip,primary-plane", U8_MAX); - printf("get vp%d plane mask:0x%x, primary id:%d, cursor_plane:%d, from dts\n", + ofnode_read_u32_default(vp_node, "rockchip,primary-plane", -1); + printf("get vp%d plane mask:0x%x, primary id:%d, cursor id:%d, from dts\n", vp_id, s->crtc_state.crtc->vps[vp_id].plane_mask, - s->crtc_state.crtc->vps[vp_id].primary_plane_id == U8_MAX ? -1 : - s->crtc_state.crtc->vps[vp_id].primary_plane_id, - cursor_plane); + (int8_t)s->crtc_state.crtc->vps[vp_id].primary_plane_id, + (int8_t)s->crtc_state.crtc->vps[vp_id].cursor_plane_id); } /* To check current vp status */ @@ -2291,16 +2320,26 @@ void rockchip_display_fixup(void *blob) const char *path; const char *cacm_header; u64 aligned_memory_size; + bool is_logo_init = 0; if (fdt_node_offset_by_compatible(blob, 0, "rockchip,drm-logo") >= 0) { list_for_each_entry(s, &rockchip_display_list, head) { - ret = load_bmp_logo(&s->logo, s->klogo_name); - if (ret < 0) { - s->is_klogo_valid = false; - printf("VP%d fail to load kernel logo\n", s->crtc_state.crtc_id); - } else { - s->is_klogo_valid = true; + if (s->is_init) { + ret = load_bmp_logo(&s->logo, s->klogo_name); + if (ret < 0) { + s->is_klogo_valid = false; + printf("VP%d fail to load kernel logo\n", + s->crtc_state.crtc_id); + } else { + s->is_klogo_valid = true; + } } + is_logo_init |= s->is_init; + } + + if (!is_logo_init) { + printf("The display is not initialized, skip display fixup\n"); + return; } if (!get_display_size()) @@ -2391,6 +2430,7 @@ void rockchip_display_fixup(void *blob) FDT_SET_U32("overscan,right_margin", s->conn_state.overscan.right_margin); FDT_SET_U32("overscan,top_margin", s->conn_state.overscan.top_margin); FDT_SET_U32("overscan,bottom_margin", s->conn_state.overscan.bottom_margin); + FDT_SET_U32("overscan,win_scale", s->crtc_state.overscan_by_win_scale); if (s->conn_state.disp_info) { cacm_header = (const char*)&s->conn_state.disp_info->cacm_header; diff --git a/u-boot/drivers/video/drm/rockchip_display.h b/u-boot/drivers/video/drm/rockchip_display.h index 780dab7af1c..cc2fb70cf41 100644 --- a/u-boot/drivers/video/drm/rockchip_display.h +++ b/u-boot/drivers/video/drm/rockchip_display.h @@ -17,6 +17,7 @@ #include #include #include +#include #include #include #include @@ -81,12 +82,17 @@ enum rockchip_mcu_cmd { #define ROCKCHIP_OUT_MODE_BT1120 0 #define ROCKCHIP_OUT_MODE_P666 1 #define ROCKCHIP_OUT_MODE_P565 2 +#define RK3588_EDP_OUTPUT_MODE_YUV422 3 #define ROCKCHIP_OUT_MODE_BT656 5 #define ROCKCHIP_OUT_MODE_S666 9 #define ROCKCHIP_OUT_MODE_S888 8 #define ROCKCHIP_OUT_MODE_YUV422 9 #define ROCKCHIP_OUT_MODE_S565 10 #define ROCKCHIP_OUT_MODE_S888_DUMMY 12 +#define RK3588_DP_OUT_MODE_YUV422 12 +#define RK3576_EDP_OUT_MODE_YUV422 12 +#define RK3588_DP_OUT_MODE_YUV420 13 +#define RK3576_HDMI_OUT_MODE_YUV422 13 #define ROCKCHIP_OUT_MODE_YUV420 14 /* for use special outface */ #define ROCKCHIP_OUT_MODE_AAAA 15 @@ -168,6 +174,7 @@ struct crtc_state { ofnode node; struct device_node *ports_node; /* if (ports_node) it's vop2; */ struct device_node *port_node; + struct reset_ctl dclk_rst; struct clk dclk; int crtc_id; @@ -189,6 +196,7 @@ struct crtc_state { bool bcsh_en; bool splice_mode; bool soft_te; + bool overscan_by_win_scale; u8 splice_crtc_id; u8 dsc_id; u8 dsc_enable; diff --git a/u-boot/drivers/video/drm/rockchip_vop2.c b/u-boot/drivers/video/drm/rockchip_vop2.c index b2f089af484..6dd3e0ddb28 100644 --- a/u-boot/drivers/video/drm/rockchip_vop2.c +++ b/u-boot/drivers/video/drm/rockchip_vop2.c @@ -98,6 +98,7 @@ #define RK3576_SYS_PORT_CTRL 0x028 #define VP_INTR_MERGE_EN_SHIFT 14 +#define RK3576_DSP_VS_T_SEL_SHIFT 4 #define INTERLACE_FRM_REG_DONE_MASK 0x7 #define INTERLACE_FRM_REG_DONE_SHIFT 0 @@ -308,6 +309,7 @@ #define RK3528_OVL_SYS_PORT_SEL 0x504 #define RK3528_OVL_SYS_GATING_EN 0x508 #define RK3528_OVL_SYS_CLUSTER0_CTRL 0x510 +#define CLUSTER_DLY_NUM_SHIFT 0 #define RK3528_OVL_SYS_ESMART0_CTRL 0x520 #define ESMART_DLY_NUM_MASK 0xff #define ESMART_DLY_NUM_SHIFT 0 @@ -377,7 +379,16 @@ #define RK3568_VP1_BG_MIX_CTRL 0x6E4 #define RK3568_VP2_BG_MIX_CTRL 0x6E8 #define RK3568_CLUSTER_DLY_NUM 0x6F0 +#define RK3568_CLUSTER_DLY_NUM1 0x6F4 +#define CLUSTER_DLY_NUM_MASK 0xffff +#define CLUSTER0_DLY_NUM_SHIFT 0 +#define CLUSTER1_DLY_NUM_SHIFT 16 #define RK3568_SMART_DLY_NUM 0x6F8 +#define SMART_DLY_NUM_MASK 0xff +#define ESMART0_DLY_NUM_SHIFT 0 +#define ESMART1_DLY_NUM_SHIFT 8 +#define SMART0_DLY_NUM_SHIFT 16 +#define SMART1_DLY_NUM_SHIFT 24 #define RK3528_OVL_PORT1_CTRL 0x700 #define RK3528_OVL_PORT1_LAYER_SEL 0x704 @@ -1047,8 +1058,10 @@ #define RK3588_GRF_VOP_CON2 0x0008 #define RK3588_GRF_EDP0_ENABLE_SHIFT 0 #define RK3588_GRF_HDMITX0_ENABLE_SHIFT 1 +#define RK3588_GRF_HDMITX0_COMPRESS_MODE_SHIFT 2 #define RK3588_GRF_EDP1_ENABLE_SHIFT 3 #define RK3588_GRF_HDMITX1_ENABLE_SHIFT 4 +#define RK3588_GRF_HDMITX1_COMPRESS_MODE_SHIFT 5 #define RK3588_GRF_VO1_CON0 0x0000 #define HDMI_SYNC_POL_MASK 0x3 @@ -1201,6 +1214,12 @@ enum vop2_layer_type { SMART_LAYER = 2, }; +enum vop2_plane_type { + VOP2_PLANE_TYPE_OVERLAY = 0, + VOP2_PLANE_TYPE_PRIMARY = 1, + VOP2_PLANE_TYPE_CURSOR = 2, +}; + /* This define must same with kernel win phy id */ enum vop2_layer_phy_id { ROCKCHIP_VOP2_CLUSTER0 = 0, @@ -1214,6 +1233,7 @@ enum vop2_layer_phy_id { ROCKCHIP_VOP2_ESMART2, ROCKCHIP_VOP2_ESMART3, ROCKCHIP_VOP2_LAYER_MAX, + ROCKCHIP_VOP2_PHY_ID_INVALID = (u8)-1, }; enum vop2_scale_up_mode { @@ -1249,6 +1269,20 @@ enum vop3_pre_scale_down_mode { VOP3_PRE_SCALE_DOWN_AVG, }; +/* + * the delay number of a window in different mode. + */ +enum vop2_win_dly_mode { + VOP2_DLY_MODE_DEFAULT, /* default mode */ + VOP2_DLY_MODE_HISO_S, /* HDR in SDR out mode, as a SDR window */ + VOP2_DLY_MODE_HIHO_H, /* HDR in HDR out mode, as a HDR window */ + VOP2_DLY_MODE_DOVI_IN_CORE1, /* dovi video input, as dovi core1 */ + VOP2_DLY_MODE_DOVI_IN_CORE2, /* dovi video input, as dovi core2 */ + VOP2_DLY_MODE_NONDOVI_IN_CORE1, /* ndovi video input, as dovi core1 */ + VOP2_DLY_MODE_NONDOVI_IN_CORE2, /* ndovi video input, as dovi core2 */ + VOP2_DLY_MODE_MAX, +}; + enum vop3_esmart_lb_mode { VOP3_ESMART_8K_MODE, VOP3_ESMART_4K_4K_MODE, @@ -1282,6 +1316,7 @@ struct vop2_win_data { char *name; u8 phys_id; enum vop2_layer_type type; + enum vop2_plane_type plane_type; u8 win_sel_port_offset; u8 layer_sel_win_id[VOP2_VP_MAX]; u8 axi_id; @@ -1296,7 +1331,8 @@ struct vop2_win_data { u8 vsd_pre_filter_mode; u8 scale_engine_num; u8 source_win_id; - u8 possible_crtcs; + u8 possible_vp_mask; + u8 dly[VOP2_DLY_MODE_MAX]; u16 pd_id; u32 reg_offset; u32 max_upscale_factor; @@ -1321,17 +1357,12 @@ struct vop2_vp_data { struct vop_urgency *urgency; }; -struct vop2_plane_table { - enum vop2_layer_phy_id plane_id; - enum vop2_layer_type plane_type; -}; - struct vop2_vp_plane_mask { u8 primary_plane_id; /* use this win to show logo */ + u8 cursor_plane_id; u8 attached_layers_nr; /* number layers attach to this vp */ u8 attached_layers[VOP2_LAYER_MAX]; /* the layers attached to this vp */ u32 plane_mask; - int cursor_plane_id; }; struct vop2_dsc_data { @@ -1366,21 +1397,30 @@ struct vop2_esmart_lb_map { u8 lb_map_value; }; +/** +* struct vop2_ops - helper operations for vop2 hardware +* +* These hooks are used by the common part of the vop2 driver to +* implement the proper behaviour of different variants. +*/ +struct vop2_ops { + void (*setup_win_dly)(struct display_state *state, int crtc_id); + void (*setup_overlay)(struct display_state *state); +}; + struct vop2_data { u32 version; u32 esmart_lb_mode; struct vop2_vp_data *vp_data; struct vop2_win_data *win_data; struct vop2_vp_plane_mask *plane_mask; - struct vop2_plane_table *plane_table; struct vop2_power_domain_data *pd; struct vop2_dsc_data *dsc; struct dsc_error_info *dsc_error_ecw; struct dsc_error_info *dsc_error_buffer_flow; struct vop2_dump_regs *dump_regs; const struct vop2_esmart_lb_map *esmart_lb_mode_map; - u8 *vp_primary_plane_order; - u8 *vp_default_primary_plane; + const struct vop2_ops *ops; u8 nr_vps; u8 nr_layers; u8 nr_mixers; @@ -1392,6 +1432,7 @@ struct vop2_data { u8 esmart_lb_mode_num; u32 reg_len; u32 dump_regs_size; + u32 plane_mask_base; }; struct vop2 { @@ -1413,6 +1454,31 @@ struct vop2 { static struct vop2 *rockchip_vop2; +/* vop2_layer_phy_id */ +static const char *const vop2_layer_name_list[] = { + "Cluster0", + "Cluster1", + "Esmart0", + "Esmart1", + "Smart0", + "Smart1", + "Cluster2", + "Cluster3", + "Esmart2", + "Esmart3", +}; + +static inline const char *vop2_plane_phys_id_to_string(u8 phys_id) +{ + if (phys_id == ROCKCHIP_VOP2_PHY_ID_INVALID) + return "INVALID"; + + if (phys_id >= ARRAY_SIZE(vop2_layer_name_list)) + return NULL; + + return vop2_layer_name_list[phys_id]; +} + static inline bool is_vop3(struct vop2 *vop2) { if (vop2->version == VOP_VERSION_RK3568 || vop2->version == VOP_VERSION_RK3588) @@ -1541,16 +1607,27 @@ static inline int interpolate(int x1, int y1, int x2, int y2, int x) return y1 + (y2 - y1) * (x - x1) / (x2 - x1); } -static int vop2_get_primary_plane(struct vop2 *vop2, u32 plane_mask) +static inline bool vop2_win_can_attach_to_vp(struct vop2_win_data *win_data, u8 vp_id) +{ + return win_data->possible_vp_mask & BIT(vp_id); +} + +static int vop2_vp_find_attachable_win(struct display_state *state, u8 vp_id) { + struct crtc_state *cstate = &state->crtc_state; + struct vop2 *vop2 = cstate->private; + u32 plane_mask = cstate->crtc->vps[vp_id].plane_mask; int i = 0; + if (!plane_mask) + return ROCKCHIP_VOP2_PHY_ID_INVALID; + for (i = 0; i < vop2->data->nr_layers; i++) { - if (plane_mask & BIT(vop2->data->vp_primary_plane_order[i])) - return vop2->data->vp_primary_plane_order[i]; + if (vop2_win_can_attach_to_vp(&vop2->data->win_data[i], vp_id)) + break; } - return vop2->data->vp_primary_plane_order[0]; + return vop2->data->win_data[i].phys_id; } static inline u16 scl_cal_scale(int src, int dst, int shift) @@ -1608,44 +1685,6 @@ static inline u32 vop2_grf_readl(struct vop2 *vop, void *grf_base, u32 offset, return (readl(grf_base + offset) >> shift) & mask; } -static char *get_plane_name(int plane_id, char *name) -{ - switch (plane_id) { - case ROCKCHIP_VOP2_CLUSTER0: - strcat(name, "Cluster0"); - break; - case ROCKCHIP_VOP2_CLUSTER1: - strcat(name, "Cluster1"); - break; - case ROCKCHIP_VOP2_ESMART0: - strcat(name, "Esmart0"); - break; - case ROCKCHIP_VOP2_ESMART1: - strcat(name, "Esmart1"); - break; - case ROCKCHIP_VOP2_SMART0: - strcat(name, "Smart0"); - break; - case ROCKCHIP_VOP2_SMART1: - strcat(name, "Smart1"); - break; - case ROCKCHIP_VOP2_CLUSTER2: - strcat(name, "Cluster2"); - break; - case ROCKCHIP_VOP2_CLUSTER3: - strcat(name, "Cluster3"); - break; - case ROCKCHIP_VOP2_ESMART2: - strcat(name, "Esmart2"); - break; - case ROCKCHIP_VOP2_ESMART3: - strcat(name, "Esmart3"); - break; - } - - return name; -} - static bool is_yuv_output(u32 bus_format) { switch (bus_format) { @@ -1899,7 +1938,7 @@ static int rockchip_vop2_gamma_lut_init(struct vop2 *vop2, rk3568_vop2_load_lut(vop2, cstate->crtc_id, lut_regs, cstate->lut_val, lut_len); gamma_lut_en_num++; - } else if (vop2->version == VOP_VERSION_RK3588) { + } else { rk3588_vop2_load_lut(vop2, cstate->crtc_id, lut_regs, cstate->lut_val, lut_len); if (cstate->splice_mode) { @@ -2111,18 +2150,9 @@ static void vop3_setup_pipe_dly(struct display_state *state, struct vop2 *vop2, { struct connector_state *conn_state = &state->conn_state; struct drm_display_mode *mode = &conn_state->mode; - struct crtc_state *cstate = &state->crtc_state; - struct vop2_win_data *win_data; u32 bg_dly, pre_scan_dly; u16 hdisplay = mode->crtc_hdisplay; u16 hsync_len = mode->crtc_hsync_end - mode->crtc_hsync_start; - u8 primary_plane_id = vop2->vp_plane_mask[cstate->crtc_id].primary_plane_id; - u8 win_id; - - win_data = vop2_find_win_by_phys_id(vop2, primary_plane_id); - win_id = atoi(&win_data->name[strlen(win_data->name) - 1]); - vop2_mask_write(vop2, RK3528_OVL_SYS_ESMART0_CTRL + win_id * 4, - ESMART_DLY_NUM_MASK, ESMART_DLY_NUM_SHIFT, 0, false); bg_dly = vop2->data->vp_data[crtc_id].win_dly + vop2->data->vp_data[crtc_id].layer_mix_dly + @@ -2144,31 +2174,45 @@ static void vop2_post_config(struct display_state *state, struct vop2 *vop2) struct connector_state *conn_state = &state->conn_state; struct drm_display_mode *mode = &conn_state->mode; struct crtc_state *cstate = &state->crtc_state; + const struct vop2_data *vop2_data = vop2->data; + const struct vop2_ops *vop2_ops = vop2_data->ops; u32 vp_offset = (cstate->crtc_id * 0x100); u16 vtotal = mode->crtc_vtotal; u16 hact_st = mode->crtc_htotal - mode->crtc_hsync_start; u16 vact_st = mode->crtc_vtotal - mode->crtc_vsync_start; u16 hdisplay = mode->crtc_hdisplay; u16 vdisplay = mode->crtc_vdisplay; - u16 hsize = - hdisplay * (conn_state->overscan.left_margin + - conn_state->overscan.right_margin) / 200; - u16 vsize = - vdisplay * (conn_state->overscan.top_margin + - conn_state->overscan.bottom_margin) / 200; + u16 hsize; + u16 vsize; u16 hact_end, vact_end; u32 val; - hsize = round_down(hsize, 2); - vsize = round_down(vsize, 2); + /* + * For RK3576, use the win scale instead of the post scale to configure + * overscan parameters, because the sharp/post scale/split functions are + * mutually exclusice. + */ + if (vop2->version == VOP_VERSION_RK3576) { + hsize = hdisplay; + vsize = vdisplay; + + cstate->overscan_by_win_scale = true; + } else { + hsize = hdisplay * (conn_state->overscan.left_margin + + conn_state->overscan.right_margin) / 200; + vsize = vdisplay * (conn_state->overscan.top_margin + + conn_state->overscan.bottom_margin) / 200; + hsize = round_down(hsize, 2); + vsize = round_down(vsize, 2); + + hact_st += hdisplay * (100 - conn_state->overscan.left_margin) / 200; + vact_st += vdisplay * (100 - conn_state->overscan.top_margin) / 200; + } - hact_st += hdisplay * (100 - conn_state->overscan.left_margin) / 200; hact_end = hact_st + hsize; val = hact_st << 16; val |= hact_end; - vop2_writel(vop2, RK3568_VP0_POST_DSP_HACT_INFO + vp_offset, val); - vact_st += vdisplay * (100 - conn_state->overscan.top_margin) / 200; vact_end = vact_st + vsize; val = vact_st << 16; val |= vact_end; @@ -2194,8 +2238,11 @@ static void vop2_post_config(struct display_state *state, struct vop2 *vop2) vop3_setup_pipe_dly(state, vop2, cstate->crtc_id); } else { vop2_setup_dly_for_vp(state, vop2, cstate->crtc_id); - if (cstate->splice_mode) + vop2_ops->setup_win_dly(state, cstate->crtc_id); + if (cstate->splice_mode) { vop2_setup_dly_for_vp(state, vop2, cstate->splice_crtc_id); + vop2_ops->setup_win_dly(state, cstate->splice_crtc_id); + } } } @@ -2381,7 +2428,7 @@ static int rk3576_vop2_wait_power_domain_on(struct vop2 *vop2, 50 * 1000); else return readl_poll_timeout(vop2->sys_pmu + RK3576_PMU_PWR_GATE_STS, - val, ((val >> PD_VOP_CLUSTER_DWN_STAT) & 0x1), + val, !((val >> PD_VOP_CLUSTER_DWN_STAT) & 0x1), 50 * 1000); } else { is_bisr_en = vop2_grf_readl(vop2, vop2->sys_pmu, RK3576_PMU_BISR_PDGEN_CON0, @@ -2513,104 +2560,6 @@ static void rk3588_vop2_regsbak(struct vop2 *vop2) vop2->regsbak[i] = base[i]; } -static void vop3_overlay_init(struct vop2 *vop2, struct display_state *state) -{ - struct vop2_win_data *win_data; - int layer_phy_id = 0; - int i, j; - u32 ovl_port_offset = 0; - u32 layer_nr = 0; - u8 shift = 0; - - /* layer sel win id */ - for (i = 0; i < vop2->data->nr_vps; i++) { - shift = 0; - ovl_port_offset = 0x100 * i; - layer_nr = vop2->vp_plane_mask[i].attached_layers_nr; - for (j = 0; j < layer_nr; j++) { - layer_phy_id = vop2->vp_plane_mask[i].attached_layers[j]; - win_data = vop2_find_win_by_phys_id(vop2, layer_phy_id); - vop2_mask_write(vop2, RK3528_OVL_PORT0_LAYER_SEL + ovl_port_offset, LAYER_SEL_MASK, - shift, win_data->layer_sel_win_id[i], false); - shift += 4; - } - } - - if (vop2->version != VOP_VERSION_RK3576) { - /* win sel port */ - for (i = 0; i < vop2->data->nr_vps; i++) { - layer_nr = vop2->vp_plane_mask[i].attached_layers_nr; - for (j = 0; j < layer_nr; j++) { - if (!vop2->vp_plane_mask[i].attached_layers[j]) - continue; - layer_phy_id = vop2->vp_plane_mask[i].attached_layers[j]; - win_data = vop2_find_win_by_phys_id(vop2, layer_phy_id); - shift = win_data->win_sel_port_offset * 2; - vop2_mask_write(vop2, RK3528_OVL_SYS_PORT_SEL, - LAYER_SEL_PORT_MASK, shift, i, false); - } - } - } -} - -static void vop2_overlay_init(struct vop2 *vop2, struct display_state *state) -{ - struct crtc_state *cstate = &state->crtc_state; - struct vop2_win_data *win_data; - int layer_phy_id = 0; - int total_used_layer = 0; - int port_mux = 0; - int i, j; - u32 layer_nr = 0; - u8 shift = 0; - - /* layer sel win id */ - for (i = 0; i < vop2->data->nr_vps; i++) { - layer_nr = vop2->vp_plane_mask[i].attached_layers_nr; - for (j = 0; j < layer_nr; j++) { - layer_phy_id = vop2->vp_plane_mask[i].attached_layers[j]; - win_data = vop2_find_win_by_phys_id(vop2, layer_phy_id); - vop2_mask_write(vop2, RK3568_OVL_LAYER_SEL, LAYER_SEL_MASK, - shift, win_data->layer_sel_win_id[i], false); - shift += 4; - } - } - - /* win sel port */ - for (i = 0; i < vop2->data->nr_vps; i++) { - layer_nr = vop2->vp_plane_mask[i].attached_layers_nr; - for (j = 0; j < layer_nr; j++) { - if (!vop2->vp_plane_mask[i].attached_layers[j]) - continue; - layer_phy_id = vop2->vp_plane_mask[i].attached_layers[j]; - win_data = vop2_find_win_by_phys_id(vop2, layer_phy_id); - shift = win_data->win_sel_port_offset * 2; - vop2_mask_write(vop2, RK3568_OVL_PORT_SEL, LAYER_SEL_PORT_MASK, - LAYER_SEL_PORT_SHIFT + shift, i, false); - } - } - - /** - * port mux config - */ - for (i = 0; i < vop2->data->nr_vps; i++) { - shift = i * 4; - if (vop2->vp_plane_mask[i].attached_layers_nr) { - total_used_layer += vop2->vp_plane_mask[i].attached_layers_nr; - port_mux = total_used_layer - 1; - } else { - port_mux = 8; - } - - if (i == vop2->data->nr_vps - 1) - port_mux = vop2->data->nr_mixers; - - cstate->crtc->vps[i].bg_ovl_dly = (vop2->data->nr_mixers - port_mux) << 1; - vop2_mask_write(vop2, RK3568_OVL_PORT_SEL, PORT_MUX_MASK, - PORT_MUX_SHIFT + shift, port_mux, false); - } -} - static bool vop3_ignore_plane(struct vop2 *vop2, struct vop2_win_data *win) { if (!is_vop3(vop2)) @@ -2668,165 +2617,415 @@ static int vop3_get_esmart_lb_mode(struct vop2 *vop2) return vop2->data->esmart_lb_mode_map[0].lb_map_value; } -static void vop2_global_initial(struct vop2 *vop2, struct display_state *state) +static inline void vop2_plane_mask_to_possible_vp_mask(struct display_state *state) { struct crtc_state *cstate = &state->crtc_state; - struct vop2_vp_plane_mask *plane_mask; - int active_vp_num = 0; - int layer_phy_id = 0; + struct vop2 *vop2 = cstate->private; + const struct vop2_data *vop2_data = vop2->data; + struct vop2_win_data *win_data; + u32 plane_mask; + u32 nr_planes; + u32 phys_id; int i, j; - int ret; - u32 layer_nr = 0; - - if (vop2->global_init) - return; - /* OTP must enable at the first time, otherwise mirror layer register is error */ - if (soc_is_rk3566()) - vop2_mask_write(vop2, RK3568_SYS_OTP_WIN_EN, EN_MASK, - OTP_WIN_EN_SHIFT, 1, false); + for (i = 0; i < vop2_data->nr_layers; i++) { + win_data = &vop2_data->win_data[i]; + win_data->possible_vp_mask = 0; + } - if (cstate->crtc->assign_plane) {/* dts assign plane */ - u32 plane_mask; - int primary_plane_id; + for (i = 0; i < vop2_data->nr_vps; i++) { + plane_mask = cstate->crtc->vps[i].plane_mask; + nr_planes = hweight32(plane_mask); - for (i = 0; i < vop2->data->nr_vps; i++) { - plane_mask = cstate->crtc->vps[i].plane_mask; - vop2->vp_plane_mask[i].plane_mask = plane_mask; - layer_nr = hweight32(plane_mask); /* use bitmap to store plane mask */ - vop2->vp_plane_mask[i].attached_layers_nr = layer_nr; - primary_plane_id = cstate->crtc->vps[i].primary_plane_id; - if (primary_plane_id >= ROCKCHIP_VOP2_LAYER_MAX) - primary_plane_id = vop2_get_primary_plane(vop2, plane_mask); - vop2->vp_plane_mask[i].primary_plane_id = primary_plane_id; - vop2->vp_plane_mask[i].plane_mask = plane_mask; - - /* plane mask[bitmap] convert into layer phy id[enum vop2_layer_phy_id]*/ - for (j = 0; j < layer_nr; j++) { - vop2->vp_plane_mask[i].attached_layers[j] = ffs(plane_mask) - 1; - plane_mask &= ~BIT(vop2->vp_plane_mask[i].attached_layers[j]); - } + for (j = 0; j < nr_planes; j++) { + phys_id = ffs(plane_mask) - 1; + win_data = vop2_find_win_by_phys_id(vop2, phys_id); + win_data->possible_vp_mask |= BIT(i); + plane_mask &= ~BIT(phys_id); } - } else {/* need soft assign plane mask */ - printf("Assign plane mask automatically\n"); - if (vop2->version == VOP_VERSION_RK3576) { - for (i = 0; i < vop2->data->nr_vps; i++) { - if (cstate->crtc->vps[i].enable) { - vop2->vp_plane_mask[i].attached_layers_nr = 1; - vop2->vp_plane_mask[i].primary_plane_id = - vop2->data->vp_default_primary_plane[i]; - vop2->vp_plane_mask[i].attached_layers[0] = - vop2->data->vp_default_primary_plane[i]; - vop2->vp_plane_mask[i].plane_mask |= - BIT(vop2->data->vp_default_primary_plane[i]); - active_vp_num++; - } - } - printf("VOP have %d active VP\n", active_vp_num); - } else { - /* find the first unplug devices and set it as main display */ - int main_vp_index = -1; + } +} - for (i = 0; i < vop2->data->nr_vps; i++) { - if (cstate->crtc->vps[i].enable) - active_vp_num++; - } - printf("VOP have %d active VP\n", active_vp_num); +/* + * The function checks whether the 'rockchip,plane-mask' property assigned + * in DTS is valid. + */ +static bool vop2_plane_mask_check(struct display_state *state) +{ + struct crtc_state *cstate = &state->crtc_state; + struct vop2 *vop2 = cstate->private; + struct vop2_win_data *win_data; + u32 assigned_plane_mask = 0, plane_mask = 0; + u32 phys_id; + u32 nr_planes; + u8 primary_plane_id, cursor_plane_id; + int i, j; - if (soc_is_rk3566() && active_vp_num > 2) - printf("ERROR: rk3566 only support 2 display output!!\n"); - plane_mask = vop2->data->plane_mask; - plane_mask += (active_vp_num - 1) * VOP2_VP_MAX; - /* - * For rk3528, one display policy for hdmi store in plane_mask[0], and - * the other for cvbs store in plane_mask[2]. - */ - if (vop2->version == VOP_VERSION_RK3528 && active_vp_num == 1 && - cstate->crtc->vps[1].output_type == DRM_MODE_CONNECTOR_TV) - plane_mask += 2 * VOP2_VP_MAX; + /* + * If plane mask is assigned in DTS, then every plane need to be assigned to + * one of all the VPs, and no single plane can be assigned to more than one + * VP. + */ + for (i = 0; i < vop2->data->nr_vps; i++) { + plane_mask = cstate->crtc->vps[i].plane_mask; + primary_plane_id = cstate->crtc->vps[i].primary_plane_id; + cursor_plane_id = cstate->crtc->vps[i].cursor_plane_id; + nr_planes = hweight32(plane_mask); - if (vop2->version == VOP_VERSION_RK3528) { - /* - * For rk3528, the plane mask of vp is limited, only esmart2 can - * be selected by both vp0 and vp1. - */ - j = 0; - } else { - for (i = 0; i < vop2->data->nr_vps; i++) { - if (!is_hot_plug_devices(cstate->crtc->vps[i].output_type)) { - /* the first store main display plane mask */ - vop2->vp_plane_mask[i] = plane_mask[0]; - main_vp_index = i; - break; - } - } + /* + * If the plane mask and primary plane both are assigned in DTS, the + * primary plane should be included in the plane mask of VPx. + */ + if (plane_mask && primary_plane_id != ROCKCHIP_VOP2_PHY_ID_INVALID && + !(BIT(primary_plane_id) & plane_mask)) { + printf("Invalid primary plane %s[0x%lx] for VP%d[plane mask: 0x%08x]\n", + vop2_plane_phys_id_to_string(primary_plane_id), + BIT(primary_plane_id), i, plane_mask); + return false; + } - /* if no find unplug devices, use vp0 as main display */ - if (main_vp_index < 0) { - main_vp_index = 0; - vop2->vp_plane_mask[0] = plane_mask[0]; - } + if (cursor_plane_id != ROCKCHIP_VOP2_PHY_ID_INVALID && + cursor_plane_id == primary_plane_id) { + printf("Assigned cursor plane of VP%d [%s] has been assigned as its pirmary plane\n", + i, vop2_plane_phys_id_to_string(cursor_plane_id)); + return false; + } - /* plane_mask[0] store main display, so we from plane_mask[1] */ - j = 1; + /* + * If the plane mask and cursor plane both are assigned in DTS, the + * cursor plane should be included in the plane mask of VPx. + */ + if (plane_mask && cursor_plane_id != ROCKCHIP_VOP2_PHY_ID_INVALID && + !(BIT(cursor_plane_id) & plane_mask)) { + printf("Invalid cursor plane %s[0x%lx] for VP%d[plane mask: 0x%08x]\n", + vop2_plane_phys_id_to_string(cursor_plane_id), + BIT(cursor_plane_id), i, plane_mask); + return false; + } + + /* + * Every plane assigned to the specific VP should follow the constraints + * of default &vop2_win_data.possible_vp_mask. + */ + for (j = 0; j < nr_planes; j++) { + phys_id = ffs(plane_mask) - 1; + win_data = vop2_find_win_by_phys_id(vop2, phys_id); + if (!win_data) { + printf("Invalid plane id %d in VP%d assigned plane mask\n", + phys_id, i); + return false; } - /* init other display except main display */ - for (i = 0; i < vop2->data->nr_vps; i++) { - /* main display or no connect devices */ - if (i == main_vp_index || !cstate->crtc->vps[i].enable) - continue; - vop2->vp_plane_mask[i] = plane_mask[j++]; + if (!(vop2_win_can_attach_to_vp(win_data, i))) { + printf("%s can not attach to VP%d\n", + vop2_plane_phys_id_to_string(phys_id), i); + return false; } + + plane_mask &= ~BIT(phys_id); } - /* store plane mask for vop2_fixup_dts */ - for (i = 0; i < vop2->data->nr_vps; i++) { - layer_nr = vop2->vp_plane_mask[i].attached_layers_nr; - for (j = 0; j < layer_nr; j++) { - layer_phy_id = vop2->vp_plane_mask[i].attached_layers[j]; - vop2->vp_plane_mask[i].plane_mask |= BIT(layer_phy_id); - } + + if (assigned_plane_mask & cstate->crtc->vps[i].plane_mask) { + printf("the same window can't be assigned to two vp\n"); + return false; } + assigned_plane_mask |= cstate->crtc->vps[i].plane_mask; } - if (vop2->version == VOP_VERSION_RK3588) - rk3588_vop2_regsbak(vop2); - else - memcpy(vop2->regsbak, vop2->regs, vop2->reg_len); + if (assigned_plane_mask != vop2->data->plane_mask_base) { + printf("all windows should be assigned, full plane mask: [0x%08x], current plane mask: [0x%08x]\n", + vop2->data->plane_mask_base, assigned_plane_mask); + return false; + } - vop2_mask_write(vop2, RK3568_OVL_CTRL, EN_MASK, - OVL_PORT_MUX_REG_DONE_IMD_SHIFT, 1, false); - vop2_mask_write(vop2, RK3568_DSP_IF_POL, EN_MASK, - IF_CTRL_REG_DONE_IMD_SHIFT, 1, false); + /* + * If plane_mask assigned in DTS is valid, then convert it to &vop2_win_data.possible_vp_mask + * and replace the default one with it. + */ + vop2_plane_mask_to_possible_vp_mask(state); - for (i = 0; i < vop2->data->nr_vps; i++) { - printf("vp%d have layer nr:%d[", i, vop2->vp_plane_mask[i].attached_layers_nr); - for (j = 0; j < vop2->vp_plane_mask[i].attached_layers_nr; j++) - printf("%d ", vop2->vp_plane_mask[i].attached_layers[j]); - printf("], primary plane: %d\n", vop2->vp_plane_mask[i].primary_plane_id); + return true; +} + +static void rockchip_cursor_plane_assign(struct display_state *state, u8 vp_id) +{ + struct crtc_state *cstate = &state->crtc_state; + struct vop2 *vop2 = cstate->private; + struct vop2_win_data *win_data; + int i, j; + + if (cstate->crtc->vps[vp_id].cursor_plane_id != ROCKCHIP_VOP2_PHY_ID_INVALID) { + win_data = vop2_find_win_by_phys_id(vop2, cstate->crtc->vps[vp_id].cursor_plane_id); + if (win_data) { + if (vop2_win_can_attach_to_vp(win_data, vp_id)) + vop2->vp_plane_mask[vp_id].cursor_plane_id = + cstate->crtc->vps[vp_id].cursor_plane_id; + return; + } } - if (is_vop3(vop2)) - vop3_overlay_init(vop2, state); - else - vop2_overlay_init(vop2, state); + for (i = 0; i < vop2->data->nr_layers; i++) { + win_data = &vop2->data->win_data[i]; - if (is_vop3(vop2)) { - /* - * you can rewrite at dts vop node: - * - * VOP3_ESMART_8K_MODE = 0, - * VOP3_ESMART_4K_4K_MODE = 1, - * VOP3_ESMART_4K_2K_2K_MODE = 2, - * VOP3_ESMART_2K_2K_2K_2K_MODE = 3, - * - * &vop { - * esmart_lb_mode = /bits/ 8 <2>; - * }; - */ - ret = ofnode_read_u32(cstate->node, "esmart_lb_mode", &vop2->esmart_lb_mode); - if (ret < 0) - vop2->esmart_lb_mode = vop2->data->esmart_lb_mode; + if (win_data->plane_type != VOP2_PLANE_TYPE_CURSOR) + continue; + + if (!vop2_win_can_attach_to_vp(win_data, vp_id)) + continue; + + for (j = 0; j < vop2->data->nr_vps; j++) { + if (win_data->phys_id == vop2->vp_plane_mask[j].cursor_plane_id) + break; + } + + /* The win has been used as the cursor plane for other VPs */ + if (j < vop2->data->nr_vps) + continue; + + vop2->vp_plane_mask[vp_id].cursor_plane_id = win_data->phys_id; + return; + } + + vop2->vp_plane_mask[vp_id].cursor_plane_id = ROCKCHIP_VOP2_PHY_ID_INVALID; +} + +static void vop2_plane_mask_assign(struct display_state *state) +{ + struct crtc_state *cstate = &state->crtc_state; + struct vop2 *vop2 = cstate->private; + struct vop2_vp_plane_mask *plane_mask; + struct vop2_win_data *win_data; + u32 nr_planes = 0; + int active_vp_num = 0; + int main_vp_index = -1; + int layer_phy_id = 0; + int i, j, k; + + printf("Assign default plane mask\n"); + + /* + * For vop3, &vop2_vp_plane_mask.plane_mask will not be fixup in + * &rockchip_crtc_funcs.fixup_dts(), because planes can be switched + * between different CRTCs flexibly and the userspace do not need + * the plane_mask to restrict the binding between the crtc and plane. + * We just find a expected plane for logo display. + */ + if (is_vop3(vop2)) { + for (i = 0; i < vop2->data->nr_vps; i++) { + /* + * mark the primary plane id of the VP that is + * not enabled to invalid. + */ + vop2->vp_plane_mask[i].primary_plane_id = ROCKCHIP_VOP2_PHY_ID_INVALID; + if (!cstate->crtc->vps[i].enable) + continue; + + rockchip_cursor_plane_assign(state, i); + for (j = 0; j < vop2->data->nr_layers; j++) { + win_data = &vop2->data->win_data[j]; + + if (win_data->plane_type != VOP2_PLANE_TYPE_PRIMARY) + continue; + + if (!vop2_win_can_attach_to_vp(win_data, i)) + continue; + + for (k = 0; k < vop2->data->nr_vps; k++) { + if (win_data->phys_id == vop2->vp_plane_mask[k].primary_plane_id) + break; + } + + /* The win has been used as the primary plane for other VPs */ + if (k < vop2->data->nr_vps) + continue; + + vop2->vp_plane_mask[i].attached_layers_nr = 1; + vop2->vp_plane_mask[i].primary_plane_id = win_data->phys_id; + vop2->vp_plane_mask[i].attached_layers[0] = win_data->phys_id; + vop2->vp_plane_mask[i].plane_mask |= BIT(win_data->phys_id); + active_vp_num++; + break; + } + + if (vop2->vp_plane_mask[i].primary_plane_id == ROCKCHIP_VOP2_PHY_ID_INVALID) + printf("ERROR: No primary plane find for video_port%d\n", i); + } + printf("VOP have %d active VP\n", active_vp_num); + } else { + for (i = 0; i < vop2->data->nr_vps; i++) { + /* + * mark the primary plane id of the VP that is + * not enabled to invalid. + */ + vop2->vp_plane_mask[i].primary_plane_id = ROCKCHIP_VOP2_PHY_ID_INVALID; + if (cstate->crtc->vps[i].enable) { + rockchip_cursor_plane_assign(state, i); + active_vp_num++; + } + } + printf("VOP have %d active VP\n", active_vp_num); + + if (soc_is_rk3566() && active_vp_num > 2) + printf("ERROR: rk3566 only support 2 display output!!\n"); + plane_mask = vop2->data->plane_mask; + plane_mask += (active_vp_num - 1) * VOP2_VP_MAX; + + /* + * For RK3566, the main planes should be enabled before the mirror planes. + * The devices that support hot plug may be disconnected initially, so we + * assign the main planes to the first device that does not support hot + * plug, in order to ensure that the mirror planes are not enabled first. + */ + if (soc_is_rk3566()) { + for (i = 0; i < vop2->data->nr_vps; i++) { + if (!is_hot_plug_devices(cstate->crtc->vps[i].output_type)) { + /* the first store main display plane mask */ + vop2->vp_plane_mask[i] = plane_mask[0]; + main_vp_index = i; + break; + } + } + + /* if no find unplug devices, use vp0 as main display */ + if (main_vp_index < 0) { + main_vp_index = 0; + vop2->vp_plane_mask[0] = plane_mask[0]; + } + + /* plane_mask[0] store main display, so we from plane_mask[1] */ + j = 1; + } else { + /* + * For the platforms except RK3566, we assign the plane mask of + * VPx according to the &vop2_data.plane_mask[active_vp_num][x]. + */ + j = 0; + } + + /* init other display except main display */ + for (i = 0; i < vop2->data->nr_vps; i++) { + /* main display or no connect devices */ + if (i == main_vp_index || !cstate->crtc->vps[i].enable) + continue; + vop2->vp_plane_mask[i] = plane_mask[j++]; + /* + * For rk3588, the main window should attach to the VP0 while + * the splice window should attach to the VP1 when the display + * mode is over 4k. + * If only one VP is enabled and the plane mask is not assigned + * in DTS, all main windows will be assigned to the enabled VPx, + * and all splice windows will be assigned to the VPx+1, in order + * to ensure that the splice mode work well. + */ + if (vop2->version == VOP_VERSION_RK3588 && active_vp_num == 1) + vop2->vp_plane_mask[(i + 1) % vop2->data->nr_vps] = plane_mask[j++]; + } + + /* store plane mask for vop2_fixup_dts */ + for (i = 0; i < vop2->data->nr_vps; i++) { + nr_planes = vop2->vp_plane_mask[i].attached_layers_nr; + for (j = 0; j < nr_planes; j++) { + layer_phy_id = vop2->vp_plane_mask[i].attached_layers[j]; + vop2->vp_plane_mask[i].plane_mask |= BIT(layer_phy_id); + } + } + } +} + +static void vop2_global_initial(struct vop2 *vop2, struct display_state *state) +{ + struct crtc_state *cstate = &state->crtc_state; + const struct vop2_data *vop2_data = vop2->data; + const struct vop2_ops *vop2_ops = vop2_data->ops; + u32 nr_planes = 0; + u32 plane_mask; + u8 primary_plane_id; + const u8 *tmp; + int i, j; + + if (vop2->global_init) + return; + + /* OTP must enable at the first time, otherwise mirror layer register is error */ + if (soc_is_rk3566()) + vop2_mask_write(vop2, RK3568_SYS_OTP_WIN_EN, EN_MASK, + OTP_WIN_EN_SHIFT, 1, false); + + /* The plane mask is assigned in DTS */ + if (cstate->crtc->assign_plane) { + /* check whether plane mask and primary plane are valid */ + if (vop2_plane_mask_check(state)) { + for (i = 0; i < vop2->data->nr_vps; i++) { + plane_mask = cstate->crtc->vps[i].plane_mask; + nr_planes = hweight32(plane_mask); /* use bitmap to store plane mask */ + vop2->vp_plane_mask[i].attached_layers_nr = nr_planes; + primary_plane_id = cstate->crtc->vps[i].primary_plane_id; + /* + * If the primary plane of specific VP is not assigned + * in DTS, find a proper primary plane according to the + * &vop2_win_data.possible_vp_mask. + */ + if (primary_plane_id == ROCKCHIP_VOP2_PHY_ID_INVALID) + primary_plane_id = vop2_vp_find_attachable_win(state, i); + vop2->vp_plane_mask[i].primary_plane_id = primary_plane_id; + vop2->vp_plane_mask[i].plane_mask = plane_mask; + + /* plane mask[bitmap] convert into layer phy id[enum vop2_layer_phy_id] */ + for (j = 0; j < nr_planes; j++) { + vop2->vp_plane_mask[i].attached_layers[j] = ffs(plane_mask) - 1; + plane_mask &= ~BIT(vop2->vp_plane_mask[i].attached_layers[j]); + } + } + } else { + vop2_plane_mask_assign(state); + } + } else { + /* + * If no plane mask assignment, plane mask and primary plane will be + * assigned automatically. + */ + vop2_plane_mask_assign(state); + } + + if (vop2->version == VOP_VERSION_RK3588) + rk3588_vop2_regsbak(vop2); + else + memcpy(vop2->regsbak, vop2->regs, vop2->reg_len); + + vop2_mask_write(vop2, RK3568_OVL_CTRL, EN_MASK, + OVL_PORT_MUX_REG_DONE_IMD_SHIFT, 1, false); + vop2_mask_write(vop2, RK3568_DSP_IF_POL, EN_MASK, + IF_CTRL_REG_DONE_IMD_SHIFT, 1, false); + + for (i = 0; i < vop2->data->nr_vps; i++) { + printf("vp%d have layer nr:%d[", i, vop2->vp_plane_mask[i].attached_layers_nr); + for (j = 0; j < vop2->vp_plane_mask[i].attached_layers_nr; j++) + printf("%s ", + vop2_plane_phys_id_to_string(vop2->vp_plane_mask[i].attached_layers[j])); + printf("], primary plane: %s\n", + vop2_plane_phys_id_to_string(vop2->vp_plane_mask[i].primary_plane_id)); + } + + vop2_ops->setup_overlay(state); + + if (is_vop3(vop2)) { + /* + * you can rewrite at dts vop node: + * + * VOP3_ESMART_8K_MODE = 0, + * VOP3_ESMART_4K_4K_MODE = 1, + * VOP3_ESMART_4K_2K_2K_MODE = 2, + * VOP3_ESMART_2K_2K_2K_2K_MODE = 3, + * + * &vop { + * esmart_lb_mode = /bits/ 8 <2>; + * }; + */ + tmp = dev_read_u8_array_ptr(cstate->dev, "esmart_lb_mode", 1); + if (tmp) + vop2->esmart_lb_mode = *tmp; + else + vop2->esmart_lb_mode = vop2->data->esmart_lb_mode; if (vop2->version == VOP_VERSION_RK3576) vop2_mask_write(vop2, RK3576_SYS_ESMART_PD_CTRL, RK3576_ESMART_LB_MODE_SEL_MASK, @@ -2836,12 +3035,16 @@ static void vop2_global_initial(struct vop2 *vop2, struct display_state *state) vop2_mask_write(vop2, RK3568_SYS_LUT_PORT_SEL, ESMART_LB_MODE_SEL_MASK, ESMART_LB_MODE_SEL_SHIFT, - vop3_get_esmart_lb_mode(vop2), true); + vop3_get_esmart_lb_mode(vop2), false); vop3_init_esmart_scale_engine(vop2); - vop2_mask_write(vop2, RK3568_SYS_AXI_LUT_CTRL, EN_MASK, - DSP_VS_T_SEL_SHIFT, 0, false); + if (vop2->version == VOP_VERSION_RK3576) + vop2_mask_write(vop2, RK3576_SYS_PORT_CTRL, EN_MASK, + RK3576_DSP_VS_T_SEL_SHIFT, 0, true); + else + vop2_mask_write(vop2, RK3568_SYS_AXI_LUT_CTRL, EN_MASK, + DSP_VS_T_SEL_SHIFT, 0, false); /* * This is a workaround for RK3528/RK3562/RK3576: @@ -2866,8 +3069,8 @@ static void vop2_global_initial(struct vop2 *vop2, struct display_state *state) if (vop2->version == VOP_VERSION_RK3576) { vop2->merge_irq = ofnode_read_bool(cstate->node, "rockchip,vop-merge-irq"); - /* Default use rkiommu 1.0 for axi0 */ - vop2_mask_write(vop2, RK3576_SYS_MMU_CTRL, EN_MASK, RKMMU_V2_EN_SHIFT, 0, true); + /* Default use rkiommu 2.0 for axi0 */ + vop2_mask_write(vop2, RK3576_SYS_MMU_CTRL, EN_MASK, RKMMU_V2_EN_SHIFT, 1, true); /* Init frc2.0 config */ vop2_writel(vop2, 0xca0, 0xc8); @@ -3057,6 +3260,8 @@ static int rockchip_vop2_preinit(struct display_state *state) struct crtc_state *cstate = &state->crtc_state; const struct vop2_data *vop2_data = cstate->crtc->data; struct regmap *map; + char dclk_name[16]; + int ret; if (!rockchip_vop2) { rockchip_vop2 = calloc(1, sizeof(struct vop2)); @@ -3106,6 +3311,15 @@ static int rockchip_vop2_preinit(struct display_state *state) } } + snprintf(dclk_name, sizeof(dclk_name), "dclk_vp%d", cstate->crtc_id); + if (dev_read_stringlist_search(cstate->dev, "reset-names", dclk_name) > 0) { + ret = reset_get_by_name(cstate->dev, dclk_name, &cstate->dclk_rst); + if (ret < 0) { + printf("%s: failed to get dclk reset: %d\n", __func__, ret); + cstate->dclk_rst.dev = NULL; + } + } + cstate->private = rockchip_vop2; cstate->max_output = vop2_data->vp_data[cstate->crtc_id].max_output; cstate->feature = vop2_data->vp_data[cstate->crtc_id].feature; @@ -3177,8 +3391,8 @@ static unsigned long vop2_calc_cru_cfg(struct display_state *state, K = 2; } if (cstate->dsc_enable) { - if_pixclk_rate = cstate->dsc_cds_clk_rate << 1; - if_dclk_rate = cstate->dsc_cds_clk_rate; + if_pixclk_rate = cstate->dsc_cds_clk_rate / 1000 << 1; + if_dclk_rate = cstate->dsc_cds_clk_rate / 1000; } else { if_pixclk_rate = (dclk_core_rate << 1) / K; if_dclk_rate = dclk_core_rate / K; @@ -3196,6 +3410,9 @@ static unsigned long vop2_calc_cru_cfg(struct display_state *state, *if_pixclk_div = dclk_rate / if_pixclk_rate; *if_dclk_div = dclk_rate / if_dclk_rate; *dclk_core_div = dclk_rate / dclk_core_rate; + /* For HDMI DSC mode, the dclk_out_div should be the same as dclk_core_div */ + if (cstate->dsc_enable) + *dclk_out_div = *dclk_core_div; printf("dclk:%lu,if_pixclk_div;%d,if_dclk_div:%d\n", dclk_rate, *if_pixclk_div, *if_dclk_div); } else if (output_type == DRM_MODE_CONNECTOR_eDP) { @@ -3255,7 +3472,16 @@ static unsigned long vop2_calc_cru_cfg(struct display_state *state, *if_pixclk_div = ilog2(*if_pixclk_div); *if_dclk_div = ilog2(*if_dclk_div); *dclk_core_div = ilog2(*dclk_core_div); - *dclk_out_div = ilog2(*dclk_out_div); + /* + * For RK3588, dclk_out is designed for DP, MIPI(both DSC and non-DSC mode) + * and HDMI in DSC mode. + */ + if (output_type == DRM_MODE_CONNECTOR_DisplayPort || + output_type == DRM_MODE_CONNECTOR_DSI || + (output_type == DRM_MODE_CONNECTOR_HDMIA && cstate->dsc_enable)) + *dclk_out_div = ilog2(*dclk_out_div); + else + *dclk_out_div = 0; return dclk_rate; } @@ -3484,6 +3710,10 @@ static unsigned long rk3588_vop2_if_cfg(struct display_state *state) vop2_mask_write(vop2, RK3568_DSP_IF_CTRL, 3, HDMI_EDP0_PIXCLK_DIV_SHIFT, if_pixclk_div, false); + if (cstate->dsc_enable) + vop2_grf_writel(vop2, vop2->vop_grf, RK3588_GRF_VOP_CON2, EN_MASK, + RK3588_GRF_HDMITX0_COMPRESS_MODE_SHIFT, 1); + vop2_grf_writel(vop2, vop2->vop_grf, RK3588_GRF_VOP_CON2, EN_MASK, RK3588_GRF_HDMITX0_ENABLE_SHIFT, 1); vop2_grf_writel(vop2, vop2->vo1_grf, RK3588_GRF_VO1_CON0, @@ -3502,6 +3732,10 @@ static unsigned long rk3588_vop2_if_cfg(struct display_state *state) vop2_mask_write(vop2, RK3568_DSP_IF_CTRL, 3, HDMI_EDP1_PIXCLK_DIV_SHIFT, if_pixclk_div, false); + if (cstate->dsc_enable) + vop2_grf_writel(vop2, vop2->vop_grf, RK3588_GRF_VOP_CON2, EN_MASK, + RK3588_GRF_HDMITX1_COMPRESS_MODE_SHIFT, 1); + vop2_grf_writel(vop2, vop2->vop_grf, RK3588_GRF_VOP_CON2, EN_MASK, RK3588_GRF_HDMITX1_ENABLE_SHIFT, 1); vop2_grf_writel(vop2, vop2->vo1_grf, RK3588_GRF_VO1_CON0, @@ -3510,8 +3744,6 @@ static unsigned long rk3588_vop2_if_cfg(struct display_state *state) } if (output_if & VOP_OUTPUT_IF_DP0) { - vop2_mask_write(vop2, RK3568_DSP_IF_EN, EN_MASK, RK3588_DP0_EN_SHIFT, - 1, false); vop2_mask_write(vop2, RK3568_DSP_IF_EN, IF_MUX_MASK, RK3588_DP0_MUX_SHIFT, cstate->crtc_id, false); vop2_mask_write(vop2, RK3568_DSP_IF_POL, RK3588_IF_PIN_POL_MASK, @@ -3519,8 +3751,6 @@ static unsigned long rk3588_vop2_if_cfg(struct display_state *state) } if (output_if & VOP_OUTPUT_IF_DP1) { - vop2_mask_write(vop2, RK3568_DSP_IF_EN, EN_MASK, RK3588_DP1_EN_SHIFT, - 1, false); vop2_mask_write(vop2, RK3568_DSP_IF_EN, IF_MUX_MASK, RK3588_DP1_MUX_SHIFT, cstate->crtc_id, false); vop2_mask_write(vop2, RK3568_DSP_IF_POL, RK3588_IF_PIN_POL_MASK, @@ -3781,8 +4011,6 @@ static unsigned long rk3576_vop2_if_cfg(struct display_state *state) RK3576_IF_REGDONE_IMD_EN_SHIFT, 1, false); vop2_mask_write(vop2, RK3576_DP0_IF_CTRL, EN_MASK, RK3576_IF_CLK_OUT_EN_SHIFT, 1, false); - vop2_mask_write(vop2, RK3576_DP0_IF_CTRL, EN_MASK, - RK3576_IF_OUT_EN_SHIFT, 1, false); vop2_mask_write(vop2, RK3576_DP0_IF_CTRL, RK3576_IF_PORT_SEL_MASK, RK3576_IF_PORT_SEL_SHIFT, cstate->crtc_id, false); vop2_mask_write(vop2, RK3576_DP0_IF_CTRL, RK3576_IF_PIN_POL_MASK, @@ -3800,8 +4028,6 @@ static unsigned long rk3576_vop2_if_cfg(struct display_state *state) RK3576_IF_REGDONE_IMD_EN_SHIFT, 1, false); vop2_mask_write(vop2, RK3576_DP1_IF_CTRL, EN_MASK, RK3576_IF_CLK_OUT_EN_SHIFT, 1, false); - vop2_mask_write(vop2, RK3576_DP1_IF_CTRL, EN_MASK, - RK3576_IF_OUT_EN_SHIFT, 1, false); vop2_mask_write(vop2, RK3576_DP1_IF_CTRL, RK3576_IF_PORT_SEL_MASK, RK3576_IF_PORT_SEL_SHIFT, cstate->crtc_id, false); vop2_mask_write(vop2, RK3576_DP1_IF_CTRL, RK3576_IF_PIN_POL_MASK, @@ -3819,8 +4045,6 @@ static unsigned long rk3576_vop2_if_cfg(struct display_state *state) RK3576_IF_REGDONE_IMD_EN_SHIFT, 1, false); vop2_mask_write(vop2, RK3576_DP2_IF_CTRL, EN_MASK, RK3576_IF_CLK_OUT_EN_SHIFT, 1, false); - vop2_mask_write(vop2, RK3576_DP2_IF_CTRL, EN_MASK, - RK3576_IF_OUT_EN_SHIFT, 1, false); vop2_mask_write(vop2, RK3576_DP2_IF_CTRL, RK3576_IF_PORT_SEL_MASK, RK3576_IF_PORT_SEL_SHIFT, cstate->crtc_id, false); vop2_mask_write(vop2, RK3576_DP2_IF_CTRL, RK3576_IF_PIN_POL_MASK, @@ -4659,6 +4883,24 @@ static int rockchip_vop2_init(struct display_state *state) conn_state->output_if & VOP_OUTPUT_IF_BT656) conn_state->output_mode = ROCKCHIP_OUT_MODE_P888; + if (conn_state->output_mode == ROCKCHIP_OUT_MODE_YUV420) { + if (vop2->version == VOP_VERSION_RK3588 && + conn_state->type == DRM_MODE_CONNECTOR_DisplayPort) + conn_state->output_mode = RK3588_DP_OUT_MODE_YUV420; + } else if (conn_state->output_mode == ROCKCHIP_OUT_MODE_YUV422) { + if (vop2->version == VOP_VERSION_RK3576 && + conn_state->type == DRM_MODE_CONNECTOR_eDP) + conn_state->output_mode = RK3576_EDP_OUT_MODE_YUV422; + else if (vop2->version == VOP_VERSION_RK3588 && + conn_state->type == DRM_MODE_CONNECTOR_eDP) + conn_state->output_mode = RK3588_EDP_OUTPUT_MODE_YUV422; + else if (vop2->version == VOP_VERSION_RK3576 && + conn_state->type == DRM_MODE_CONNECTOR_HDMIA) + conn_state->output_mode = RK3576_HDMI_OUT_MODE_YUV422; + else if (conn_state->type == DRM_MODE_CONNECTOR_DisplayPort) + conn_state->output_mode = RK3588_DP_OUT_MODE_YUV422; + } + vop2_post_color_swap(state); vop2_mask_write(vop2, RK3568_VP0_DSP_CTRL + vp_offset, OUT_MODE_MASK, @@ -5119,6 +5361,8 @@ static int vop2_set_cluster_win(struct display_state *state, struct vop2_win_dat struct connector_state *conn_state = &state->conn_state; struct drm_display_mode *mode = &conn_state->mode; struct vop2 *vop2 = cstate->private; + const struct vop2_data *vop2_data = vop2->data; + const struct vop2_ops *vop2_ops = vop2_data->ops; int src_w = cstate->src_rect.w; int src_h = cstate->src_rect.h; int crtc_x = cstate->crtc_rect.x; @@ -5171,13 +5415,17 @@ static int vop2_set_cluster_win(struct display_state *state, struct vop2_win_dat if (y_mirror) printf("WARN: y mirror is unsupported by cluster window\n"); - if (is_vop3(vop2)) + if (is_vop3(vop2)) { vop2_mask_write(vop2, RK3576_CLUSTER0_PORT_SEL + win_offset, - CLUSTER_PORT_SEL_SHIFT, CLUSTER_PORT_SEL_SHIFT, + CLUSTER_PORT_SEL_MASK, CLUSTER_PORT_SEL_SHIFT, cstate->crtc_id, false); + vop2_ops->setup_win_dly(state, cstate->crtc_id); + } - /* rk3588 should set half_blocK_en to 1 in line and tile mode */ - if (vop2->version == VOP_VERSION_RK3588) + /* + * rk3588 and later platforms should set half_blocK_en to 1 in line and tile mode. + */ + if (vop2->version >= VOP_VERSION_RK3588) vop2_mask_write(vop2, RK3568_CLUSTER0_WIN0_AFBCD_CTRL + win_offset, EN_MASK, CLUSTER_AFBCD_HALF_BLOCK_SHIFT, 1, false); @@ -5219,6 +5467,8 @@ static int vop2_set_smart_win(struct display_state *state, struct vop2_win_data struct connector_state *conn_state = &state->conn_state; struct drm_display_mode *mode = &conn_state->mode; struct vop2 *vop2 = cstate->private; + const struct vop2_data *vop2_data = vop2->data; + const struct vop2_ops *vop2_ops = vop2_data->ops; int src_w = cstate->src_rect.w; int src_h = cstate->src_rect.h; int crtc_x = cstate->crtc_rect.x; @@ -5295,9 +5545,7 @@ static int vop2_set_smart_win(struct display_state *state, struct vop2_win_data vop2_mask_write(vop2, RK3576_ESMART0_PORT_SEL + win_offset, ESMART_PORT_SEL_MASK, ESMART_PORT_SEL_SHIFT, cstate->crtc_id, false); - vop2_mask_write(vop2, RK3576_ESMART0_DLY_NUM + win_offset, - ESMART_DLY_NUM_MASK, ESMART_DLY_NUM_SHIFT, - 0, false); + vop2_ops->setup_win_dly(state, cstate->crtc_id); /* Merge esmart1/3 from vp1 post to vp0 */ if (vop2->version == VOP_VERSION_RK3576 && cstate->crtc_id == 0 && @@ -5407,7 +5655,6 @@ static int rockchip_vop2_set_plane(struct display_state *state) struct vop2_win_data *win_data; struct vop2_win_data *splice_win_data; u8 primary_plane_id = vop2->vp_plane_mask[cstate->crtc_id].primary_plane_id; - char plane_name[10] = {0}; int ret; if (cstate->crtc_rect.w > cstate->max_output.width) { @@ -5446,7 +5693,7 @@ static int rockchip_vop2_set_plane(struct display_state *state) vop2_set_smart_win(state, splice_win_data); } else { printf("ERROR: splice mode is unsupported by plane %s\n", - get_plane_name(primary_plane_id, plane_name)); + vop2_plane_phys_id_to_string(primary_plane_id)); return -EINVAL; } } @@ -5459,7 +5706,7 @@ static int rockchip_vop2_set_plane(struct display_state *state) return ret; printf("VOP VP%d enable %s[%dx%d->%dx%d@%dx%d] fmt[%d] addr[0x%x]\n", - cstate->crtc_id, get_plane_name(primary_plane_id, plane_name), + cstate->crtc_id, vop2_plane_phys_id_to_string(primary_plane_id), cstate->src_rect.w, cstate->src_rect.h, cstate->crtc_rect.w, cstate->crtc_rect.h, cstate->crtc_rect.x, cstate->crtc_rect.y, cstate->format, cstate->dma_addr); @@ -5516,65 +5763,107 @@ static int rockchip_vop2_enable(struct display_state *state) return 0; } -static int rockchip_vop2_disable(struct display_state *state) +static int rk3588_vop2_post_enable(struct display_state *state) { + struct connector_state *conn_state = &state->conn_state; struct crtc_state *cstate = &state->crtc_state; struct vop2 *vop2 = cstate->private; - u32 vp_offset = (cstate->crtc_id * 0x100); + int output_if = conn_state->output_if; u32 cfg_done = CFG_DONE_EN | BIT(cstate->crtc_id) | (BIT(cstate->crtc_id) << 16); + int ret, val; - vop2_mask_write(vop2, RK3568_VP0_DSP_CTRL + vp_offset, EN_MASK, - STANDBY_EN_SHIFT, 1, false); + if (output_if & VOP_OUTPUT_IF_DP0) + vop2_mask_write(vop2, RK3568_DSP_IF_EN, EN_MASK, RK3588_DP0_EN_SHIFT, + 1, false); - if (cstate->splice_mode) - cfg_done |= BIT(cstate->splice_crtc_id) | (BIT(cstate->splice_crtc_id) << 16); + if (output_if & VOP_OUTPUT_IF_DP1) + vop2_mask_write(vop2, RK3568_DSP_IF_EN, EN_MASK, RK3588_DP1_EN_SHIFT, + 1, false); - vop2_writel(vop2, RK3568_REG_CFG_DONE, cfg_done); + if (output_if & (VOP_OUTPUT_IF_DP0 | VOP_OUTPUT_IF_DP1)) { + vop2_writel(vop2, RK3568_REG_CFG_DONE, cfg_done); + ret = readl_poll_timeout(vop2->regs + RK3568_REG_CFG_DONE, val, + val & BIT(cstate->crtc_id), 50 * 1000); + if (ret) + printf("%s wait cfg done timeout\n", __func__); + + if (cstate->dclk_rst.dev) { + reset_assert(&cstate->dclk_rst); + udelay(20); + reset_deassert(&cstate->dclk_rst); + } + } return 0; } -static int rockchip_vop2_get_cursor_plane(struct display_state *state, u32 plane_mask, int cursor_plane) +static int rk3576_vop2_post_enable(struct display_state *state) { + struct connector_state *conn_state = &state->conn_state; struct crtc_state *cstate = &state->crtc_state; struct vop2 *vop2 = cstate->private; - int i = 0; - int correct_cursor_plane = -1; - int plane_type = -1; + int output_if = conn_state->output_if; + u32 cfg_done = CFG_DONE_EN | BIT(cstate->crtc_id) | (BIT(cstate->crtc_id) << 16); + int ret, val; - if (cursor_plane < 0) - return -1; + if (output_if & VOP_OUTPUT_IF_DP0) + vop2_mask_write(vop2, RK3576_DP0_IF_CTRL, EN_MASK, + RK3576_IF_OUT_EN_SHIFT, 1, false); - if (plane_mask & (1 << cursor_plane)) - return cursor_plane; + if (output_if & VOP_OUTPUT_IF_DP1) + vop2_mask_write(vop2, RK3576_DP1_IF_CTRL, EN_MASK, + RK3576_IF_OUT_EN_SHIFT, 1, false); - /* Get current cursor plane type */ - for (i = 0; i < vop2->data->nr_layers; i++) { - if (vop2->data->plane_table[i].plane_id == cursor_plane) { - plane_type = vop2->data->plane_table[i].plane_type; - break; - } - } + if (output_if & VOP_OUTPUT_IF_DP2) + vop2_mask_write(vop2, RK3576_DP2_IF_CTRL, EN_MASK, + RK3576_IF_OUT_EN_SHIFT, 1, false); - /* Get the other same plane type plane id */ - for (i = 0; i < vop2->data->nr_layers; i++) { - if (vop2->data->plane_table[i].plane_type == plane_type && - vop2->data->plane_table[i].plane_id != cursor_plane) { - correct_cursor_plane = vop2->data->plane_table[i].plane_id; - break; + if (output_if & (VOP_OUTPUT_IF_DP0 | VOP_OUTPUT_IF_DP1 | VOP_OUTPUT_IF_DP2)) { + vop2_writel(vop2, RK3568_REG_CFG_DONE, cfg_done); + ret = readl_poll_timeout(vop2->regs + RK3568_REG_CFG_DONE, val, + val & BIT(cstate->crtc_id), 50 * 1000); + if (ret) + printf("%s wait cfg done timeout\n", __func__); + + if (cstate->dclk_rst.dev) { + reset_assert(&cstate->dclk_rst); + udelay(20); + reset_deassert(&cstate->dclk_rst); } } - /* To check whether the new correct_cursor_plane is attach to current vp */ - if (correct_cursor_plane < 0 || !(plane_mask & (1 << correct_cursor_plane))) { - printf("error: faild to find correct plane as cursor plane\n"); - return -1; - } + return 0; +} + +static int rockchip_vop2_post_enable(struct display_state *state) +{ + struct crtc_state *cstate = &state->crtc_state; + struct vop2 *vop2 = cstate->private; + + if (vop2->version == VOP_VERSION_RK3588) + rk3588_vop2_post_enable(state); + else if (vop2->version == VOP_VERSION_RK3576) + rk3576_vop2_post_enable(state); + + return 0; +} + +static int rockchip_vop2_disable(struct display_state *state) +{ + struct crtc_state *cstate = &state->crtc_state; + struct vop2 *vop2 = cstate->private; + u32 vp_offset = (cstate->crtc_id * 0x100); + u32 cfg_done = CFG_DONE_EN | BIT(cstate->crtc_id) | (BIT(cstate->crtc_id) << 16); - printf("vp%d adjust cursor plane from %d to %d\n", - cstate->crtc_id, cursor_plane, correct_cursor_plane); + vop2_mask_write(vop2, RK3568_VP0_DSP_CTRL + vp_offset, EN_MASK, + STANDBY_EN_SHIFT, 1, false); + + if (cstate->splice_mode) + cfg_done |= BIT(cstate->splice_crtc_id) | (BIT(cstate->splice_crtc_id) << 16); + + vop2_writel(vop2, RK3568_REG_CFG_DONE, cfg_done); - return correct_cursor_plane; + return 0; } static int rockchip_vop2_fixup_dts(struct display_state *state, void *blob) @@ -5587,9 +5876,15 @@ static int rockchip_vop2_fixup_dts(struct display_state *state, void *blob) const char *path; u32 plane_mask = 0; int vp_id = 0; - int cursor_plane_id = -1; - if (vop_fix_dts || vop2->version == VOP_VERSION_RK3528) + /* + * For vop3, &vop2_vp_plane_mask.plane_mask will not be fixup in + * &rockchip_crtc_funcs.fixup_dts(), because planes can be switched + * between different CRTCs flexibly and the userspace do not need + * the plane_mask to restrict the binding between the crtc and plane. + * We just find a expected plane for logo display. + */ + if (vop_fix_dts || is_vop3(vop2)) return 0; ofnode_for_each_subnode(vp_node, np_to_ofnode(port_parent_node)) { @@ -5598,20 +5893,19 @@ static int rockchip_vop2_fixup_dts(struct display_state *state, void *blob) if (cstate->crtc->assign_plane) continue; - cursor_plane_id = rockchip_vop2_get_cursor_plane(state, plane_mask, - cstate->crtc->vps[vp_id].cursor_plane); + printf("vp%d, plane_mask:0x%x, primary-id:%d, curser-id:%d\n", vp_id, plane_mask, vop2->vp_plane_mask[vp_id].primary_plane_id, - cursor_plane_id); + vop2->vp_plane_mask[vp_id].cursor_plane_id); do_fixup_by_path_u32(blob, path, "rockchip,plane-mask", plane_mask, 1); do_fixup_by_path_u32(blob, path, "rockchip,primary-plane", vop2->vp_plane_mask[vp_id].primary_plane_id, 1); - if (cursor_plane_id >= 0) + if (vop2->vp_plane_mask[vp_id].cursor_plane_id != ROCKCHIP_VOP2_PHY_ID_INVALID) do_fixup_by_path_u32(blob, path, "cursor-win-id", - cursor_plane_id, 1); + vop2->vp_plane_mask[vp_id].cursor_plane_id, 1); vp_id++; } @@ -5693,14 +5987,26 @@ static int rockchip_vop2_mode_fixup(struct display_state *state) } } - /* - * For RK3576 YUV420 output, hden signal introduce one cycle delay, - * so we need to adjust hfp and hbp to compatible with this design. - */ - if (vop2->version == VOP_VERSION_RK3576 && - conn_state->output_mode == ROCKCHIP_OUT_MODE_YUV420) { - mode->crtc_hsync_start += 2; - mode->crtc_hsync_end += 2; + if (vop2->version == VOP_VERSION_RK3576) { + /* + * For RK3576 YUV420 output, hden signal introduce one cycle delay, + * so we need to adjust hfp and hbp to compatible with this design. + */ + if (conn_state->output_mode == ROCKCHIP_OUT_MODE_YUV420) { + mode->crtc_hsync_start += 2; + mode->crtc_hsync_end += 2; + } + /* + * For RK3576 DP output, vp send 2 pixels 1 cycle. So the hactive, + * hfp, hsync, hbp should be 2-pixel aligned. + */ + if (conn_state->output_if & + (VOP_OUTPUT_IF_DP0 | VOP_OUTPUT_IF_DP1 | VOP_OUTPUT_IF_DP2)) { + mode->crtc_hdisplay += mode->crtc_hdisplay % 2; + mode->crtc_hsync_start += mode->crtc_hsync_start % 2; + mode->crtc_hsync_end += mode->crtc_hsync_end % 2; + mode->crtc_htotal += mode->crtc_htotal % 2; + } } if (mode->flags & DRM_MODE_FLAG_DBLCLK || conn_state->output_if & VOP_OUTPUT_IF_BT656) @@ -5867,10 +6173,241 @@ static int rockchip_vop2_active_regs_dump(struct display_state *state) return 0; } -static struct vop2_dump_regs rk3528_dump_regs[] = { - { RK3568_REG_CFG_DONE, "SYS", 0, 0, 0, 0 }, - { RK3528_OVL_SYS, "OVL_SYS", 0, 0, 0, 0 }, - { RK3528_OVL_PORT0_CTRL, "OVL_VP0", RK3568_VP0_DSP_CTRL, 0x1, 31, 0 }, +static void rk3528_setup_win_dly(struct display_state *state, int crtc_id) +{ + struct crtc_state *cstate = &state->crtc_state; + struct vop2 *vop2 = cstate->private; + struct vop2_vp_plane_mask *plane_mask = &vop2->vp_plane_mask[crtc_id]; + uint32_t dly = 0; /* For vop3, the default window delay is 0 */ + + switch (plane_mask->primary_plane_id) { + case ROCKCHIP_VOP2_CLUSTER0: + vop2_mask_write(vop2, RK3528_OVL_SYS_CLUSTER0_CTRL, CLUSTER_DLY_NUM_MASK, + CLUSTER_DLY_NUM_SHIFT, dly, false); + break; + case ROCKCHIP_VOP2_ESMART0: + vop2_mask_write(vop2, RK3528_OVL_SYS_ESMART0_CTRL, ESMART_DLY_NUM_MASK, + ESMART_DLY_NUM_SHIFT, dly, false); + break; + case ROCKCHIP_VOP2_ESMART1: + vop2_mask_write(vop2, RK3528_OVL_SYS_ESMART1_CTRL, ESMART_DLY_NUM_MASK, + ESMART_DLY_NUM_SHIFT, dly, false); + break; + case ROCKCHIP_VOP2_ESMART2: + vop2_mask_write(vop2, RK3528_OVL_SYS_ESMART2_CTRL, ESMART_DLY_NUM_MASK, + ESMART_DLY_NUM_SHIFT, dly, false); + break; + case ROCKCHIP_VOP2_ESMART3: + vop2_mask_write(vop2, RK3528_OVL_SYS_ESMART3_CTRL, ESMART_DLY_NUM_MASK, + ESMART_DLY_NUM_SHIFT, dly, false); + break; + } +} + +static void rk3528_setup_overlay(struct display_state *state) +{ + struct crtc_state *cstate = &state->crtc_state; + struct vop2 *vop2 = cstate->private; + struct vop2_win_data *win_data; + int i; + u32 offset = 0; + u8 shift = 0; + + /* init the layer sel value to 0xff(Disable layer) */ + for (i = 0; i < vop2->data->nr_vps; i++) { + offset = 0x100 * i; + vop2_writel(vop2, RK3528_OVL_PORT0_LAYER_SEL + offset, 0xffffffff); + } + + /* layer sel win id */ + for (i = 0; i < vop2->data->nr_vps; i++) { + if (vop2->vp_plane_mask[i].primary_plane_id != ROCKCHIP_VOP2_PHY_ID_INVALID) { + offset = 0x100 * i; + win_data = vop2_find_win_by_phys_id(vop2, vop2->vp_plane_mask[i].primary_plane_id); + vop2_mask_write(vop2, RK3528_OVL_PORT0_LAYER_SEL + offset, + LAYER_SEL_MASK, 0, win_data->layer_sel_win_id[i], false); + } + } + + /* win sel port */ + for (i = 0; i < vop2->data->nr_vps; i++) { + if (vop2->vp_plane_mask[i].primary_plane_id != ROCKCHIP_VOP2_PHY_ID_INVALID) { + win_data = vop2_find_win_by_phys_id(vop2, vop2->vp_plane_mask[i].primary_plane_id); + shift = win_data->win_sel_port_offset * 2; + vop2_mask_write(vop2, RK3528_OVL_SYS_PORT_SEL, + LAYER_SEL_PORT_MASK, shift, i, false); + } + } +} + +static void rk3568_setup_win_dly(struct display_state *state, int crtc_id) +{ + struct crtc_state *cstate = &state->crtc_state; + struct vop2 *vop2 = cstate->private; + struct vop2_vp_plane_mask *plane_mask = &vop2->vp_plane_mask[crtc_id]; + struct vop2_win_data *win_data; + uint32_t dly; + + win_data = vop2_find_win_by_phys_id(vop2, plane_mask->primary_plane_id); + dly = win_data->dly[VOP2_DLY_MODE_DEFAULT]; + if (win_data->type == CLUSTER_LAYER) + dly |= dly << 8; + + switch (plane_mask->primary_plane_id) { + case ROCKCHIP_VOP2_CLUSTER0: + vop2_mask_write(vop2, RK3568_CLUSTER_DLY_NUM, CLUSTER_DLY_NUM_MASK, + CLUSTER0_DLY_NUM_SHIFT, dly, false); + break; + case ROCKCHIP_VOP2_CLUSTER1: + vop2_mask_write(vop2, RK3568_CLUSTER_DLY_NUM, CLUSTER_DLY_NUM_MASK, + CLUSTER1_DLY_NUM_SHIFT, dly, false); + break; + case ROCKCHIP_VOP2_CLUSTER2: + vop2_mask_write(vop2, RK3568_CLUSTER_DLY_NUM1, CLUSTER_DLY_NUM_MASK, + CLUSTER0_DLY_NUM_SHIFT, dly, false); + break; + case ROCKCHIP_VOP2_CLUSTER3: + vop2_mask_write(vop2, RK3568_CLUSTER_DLY_NUM1, CLUSTER_DLY_NUM_MASK, + CLUSTER1_DLY_NUM_SHIFT, dly, false); + break; + case ROCKCHIP_VOP2_ESMART0: + vop2_mask_write(vop2, RK3568_SMART_DLY_NUM, SMART_DLY_NUM_MASK, + ESMART0_DLY_NUM_SHIFT, dly, false); + break; + case ROCKCHIP_VOP2_ESMART1: + vop2_mask_write(vop2, RK3568_SMART_DLY_NUM, SMART_DLY_NUM_MASK, + ESMART1_DLY_NUM_SHIFT, dly, false); + break; + case ROCKCHIP_VOP2_SMART0: + case ROCKCHIP_VOP2_ESMART2: + vop2_mask_write(vop2, RK3568_SMART_DLY_NUM, SMART_DLY_NUM_MASK, + SMART0_DLY_NUM_SHIFT, dly, false); + break; + case ROCKCHIP_VOP2_SMART1: + case ROCKCHIP_VOP2_ESMART3: + vop2_mask_write(vop2, RK3568_SMART_DLY_NUM, SMART_DLY_NUM_MASK, + SMART1_DLY_NUM_SHIFT, dly, false); + break; + } +} + +static void rk3568_setup_overlay(struct display_state *state) +{ + struct crtc_state *cstate = &state->crtc_state; + struct vop2 *vop2 = cstate->private; + struct vop2_win_data *win_data; + int layer_phy_id = 0; + int total_used_layer = 0; + int port_mux = 0; + int i, j; + u32 layer_nr = 0; + u8 shift = 0; + + /* layer sel win id */ + for (i = 0; i < vop2->data->nr_vps; i++) { + layer_nr = vop2->vp_plane_mask[i].attached_layers_nr; + for (j = 0; j < layer_nr; j++) { + layer_phy_id = vop2->vp_plane_mask[i].attached_layers[j]; + win_data = vop2_find_win_by_phys_id(vop2, layer_phy_id); + vop2_mask_write(vop2, RK3568_OVL_LAYER_SEL, LAYER_SEL_MASK, + shift, win_data->layer_sel_win_id[i], false); + shift += 4; + } + } + + /* win sel port */ + for (i = 0; i < vop2->data->nr_vps; i++) { + layer_nr = vop2->vp_plane_mask[i].attached_layers_nr; + for (j = 0; j < layer_nr; j++) { + if (!vop2->vp_plane_mask[i].attached_layers[j]) + continue; + layer_phy_id = vop2->vp_plane_mask[i].attached_layers[j]; + win_data = vop2_find_win_by_phys_id(vop2, layer_phy_id); + shift = win_data->win_sel_port_offset * 2; + vop2_mask_write(vop2, RK3568_OVL_PORT_SEL, LAYER_SEL_PORT_MASK, + LAYER_SEL_PORT_SHIFT + shift, i, false); + } + } + + /** + * port mux config + */ + for (i = 0; i < vop2->data->nr_vps; i++) { + shift = i * 4; + if (vop2->vp_plane_mask[i].attached_layers_nr) { + total_used_layer += vop2->vp_plane_mask[i].attached_layers_nr; + port_mux = total_used_layer - 1; + } else { + port_mux = 8; + } + + if (i == vop2->data->nr_vps - 1) + port_mux = vop2->data->nr_mixers; + + cstate->crtc->vps[i].bg_ovl_dly = (vop2->data->nr_mixers - port_mux) << 1; + vop2_mask_write(vop2, RK3568_OVL_PORT_SEL, PORT_MUX_MASK, + PORT_MUX_SHIFT + shift, port_mux, false); + } +} + +static void rk3576_setup_win_dly(struct display_state *state, int crtc_id) +{ + struct crtc_state *cstate = &state->crtc_state; + struct vop2 *vop2 = cstate->private; + struct vop2_vp_plane_mask *plane_mask = &vop2->vp_plane_mask[crtc_id]; + uint32_t dly = 0; /* For vop3, the default window delay is 0 */ + + switch (plane_mask->primary_plane_id) { + case ROCKCHIP_VOP2_CLUSTER0: + vop2_mask_write(vop2, RK3576_CLUSTER0_DLY_NUM, CLUSTER_DLY_NUM_MASK, + CLUSTER_DLY_NUM_SHIFT, dly, false); + break; + case ROCKCHIP_VOP2_CLUSTER1: + vop2_mask_write(vop2, RK3576_CLUSTER1_DLY_NUM, CLUSTER_DLY_NUM_MASK, + CLUSTER_DLY_NUM_SHIFT, dly, false); + break; + case ROCKCHIP_VOP2_ESMART0: + vop2_mask_write(vop2, RK3576_ESMART0_DLY_NUM, ESMART_DLY_NUM_MASK, + ESMART_DLY_NUM_SHIFT, dly, false); + break; + case ROCKCHIP_VOP2_ESMART1: + vop2_mask_write(vop2, RK3576_ESMART1_DLY_NUM, ESMART_DLY_NUM_MASK, + ESMART_DLY_NUM_SHIFT, dly, false); + break; + case ROCKCHIP_VOP2_ESMART2: + vop2_mask_write(vop2, RK3576_ESMART2_DLY_NUM, ESMART_DLY_NUM_MASK, + ESMART_DLY_NUM_SHIFT, dly, false); + break; + case ROCKCHIP_VOP2_ESMART3: + vop2_mask_write(vop2, RK3576_ESMART3_DLY_NUM, ESMART_DLY_NUM_MASK, + ESMART_DLY_NUM_SHIFT, dly, false); + break; + } +} + +static void rk3576_setup_overlay(struct display_state *state) +{ + struct crtc_state *cstate = &state->crtc_state; + struct vop2 *vop2 = cstate->private; + struct vop2_win_data *win_data; + int i; + u32 offset = 0; + + /* layer sel win id */ + for (i = 0; i < vop2->data->nr_vps; i++) { + if (vop2->vp_plane_mask[i].primary_plane_id != ROCKCHIP_VOP2_PHY_ID_INVALID) { + offset = 0x100 * i; + win_data = vop2_find_win_by_phys_id(vop2, vop2->vp_plane_mask[i].primary_plane_id); + vop2_mask_write(vop2, RK3528_OVL_PORT0_LAYER_SEL + offset, LAYER_SEL_MASK, + 0, win_data->layer_sel_win_id[i], false); + } + } +} + +static struct vop2_dump_regs rk3528_dump_regs[] = { + { RK3568_REG_CFG_DONE, "SYS", 0, 0, 0, 0 }, + { RK3528_OVL_SYS, "OVL_SYS", 0, 0, 0, 0 }, + { RK3528_OVL_PORT0_CTRL, "OVL_VP0", RK3568_VP0_DSP_CTRL, 0x1, 31, 0 }, { RK3528_OVL_PORT1_CTRL, "OVL_VP1", RK3568_VP1_DSP_CTRL, 0x1, 31, 0 }, { RK3568_VP0_DSP_CTRL, "VP0", RK3568_VP0_DSP_CTRL, 0x1, 31, 0 }, { RK3568_VP1_DSP_CTRL, "VP1", RK3568_VP1_DSP_CTRL, 0x1, 31, 0 }, @@ -5883,77 +6420,17 @@ static struct vop2_dump_regs rk3528_dump_regs[] = { { RK3528_ACM_CTRL, "ACM", RK3528_ACM_CTRL, 0x1, 0, 1}, }; -static u8 rk3528_vp_primary_plane_order[ROCKCHIP_VOP2_LAYER_MAX] = { - ROCKCHIP_VOP2_ESMART0, - ROCKCHIP_VOP2_ESMART1, - ROCKCHIP_VOP2_ESMART2, - ROCKCHIP_VOP2_ESMART3, -}; - -static struct vop2_plane_table rk3528_plane_table[ROCKCHIP_VOP2_LAYER_MAX] = { - {ROCKCHIP_VOP2_CLUSTER0, CLUSTER_LAYER}, - {ROCKCHIP_VOP2_ESMART0, ESMART_LAYER}, - {ROCKCHIP_VOP2_ESMART1, ESMART_LAYER}, - {ROCKCHIP_VOP2_ESMART2, ESMART_LAYER}, - {ROCKCHIP_VOP2_ESMART3, ESMART_LAYER}, -}; - -static struct vop2_vp_plane_mask rk3528_vp_plane_mask[VOP2_VP_MAX][VOP2_VP_MAX] = { - { /* one display policy for hdmi */ - {/* main display */ - .primary_plane_id = ROCKCHIP_VOP2_ESMART0, - .attached_layers_nr = 4, - .attached_layers = { - ROCKCHIP_VOP2_CLUSTER0, - ROCKCHIP_VOP2_ESMART0, ROCKCHIP_VOP2_ESMART1, ROCKCHIP_VOP2_ESMART2 - }, - }, - {/* second display */}, - {/* third display */}, - {/* fourth display */}, - }, - - { /* two display policy */ - {/* main display */ - .primary_plane_id = ROCKCHIP_VOP2_ESMART0, - .attached_layers_nr = 3, - .attached_layers = { - ROCKCHIP_VOP2_CLUSTER0, ROCKCHIP_VOP2_ESMART0, ROCKCHIP_VOP2_ESMART1 - }, - }, - - {/* second display */ - .primary_plane_id = ROCKCHIP_VOP2_ESMART3, - .attached_layers_nr = 2, - .attached_layers = { - ROCKCHIP_VOP2_ESMART2, ROCKCHIP_VOP2_ESMART3 - }, - }, - {/* third display */}, - {/* fourth display */}, - }, - - { /* one display policy for cvbs */ - {/* main display */ - .primary_plane_id = ROCKCHIP_VOP2_ESMART3, - .attached_layers_nr = 2, - .attached_layers = { - ROCKCHIP_VOP2_ESMART2, ROCKCHIP_VOP2_ESMART3 - }, - }, - {/* second display */}, - {/* third display */}, - {/* fourth display */}, - }, - - {/* reserved */}, -}; +#define RK3528_PLANE_MASK_BASE \ + (BIT(ROCKCHIP_VOP2_CLUSTER0) | \ + BIT(ROCKCHIP_VOP2_ESMART0) | BIT(ROCKCHIP_VOP2_ESMART1) | \ + BIT(ROCKCHIP_VOP2_ESMART2) | BIT(ROCKCHIP_VOP2_ESMART3)) static struct vop2_win_data rk3528_win_data[5] = { { .name = "Esmart0", .phys_id = ROCKCHIP_VOP2_ESMART0, .type = ESMART_LAYER, + .plane_type = VOP2_PLANE_TYPE_PRIMARY, .win_sel_port_offset = 8, .layer_sel_win_id = { 1, 0xff, 0xff, 0xff }, .reg_offset = 0, @@ -5966,6 +6443,7 @@ static struct vop2_win_data rk3528_win_data[5] = { .vsd_filter_mode = VOP2_SCALE_DOWN_BIL, .hsd_pre_filter_mode = VOP3_PRE_SCALE_DOWN_AVG, /* gt or avg */ .vsd_pre_filter_mode = VOP3_PRE_SCALE_DOWN_GT, /* gt only */ + .possible_vp_mask = BIT(VOP2_VP0), .max_upscale_factor = 8, .max_downscale_factor = 8, }, @@ -5974,6 +6452,7 @@ static struct vop2_win_data rk3528_win_data[5] = { .name = "Esmart1", .phys_id = ROCKCHIP_VOP2_ESMART1, .type = ESMART_LAYER, + .plane_type = VOP2_PLANE_TYPE_OVERLAY, .win_sel_port_offset = 10, .layer_sel_win_id = { 2, 0xff, 0xff, 0xff }, .reg_offset = 0x200, @@ -5986,6 +6465,7 @@ static struct vop2_win_data rk3528_win_data[5] = { .vsd_filter_mode = VOP2_SCALE_DOWN_BIL, .hsd_pre_filter_mode = VOP3_PRE_SCALE_DOWN_AVG, /* gt or avg */ .vsd_pre_filter_mode = VOP3_PRE_SCALE_DOWN_GT, /* gt only */ + .possible_vp_mask = BIT(VOP2_VP0), .max_upscale_factor = 8, .max_downscale_factor = 8, }, @@ -5994,6 +6474,7 @@ static struct vop2_win_data rk3528_win_data[5] = { .name = "Esmart2", .phys_id = ROCKCHIP_VOP2_ESMART2, .type = ESMART_LAYER, + .plane_type = VOP2_PLANE_TYPE_CURSOR, .win_sel_port_offset = 12, .layer_sel_win_id = { 3, 0, 0xff, 0xff }, .reg_offset = 0x400, @@ -6006,6 +6487,7 @@ static struct vop2_win_data rk3528_win_data[5] = { .vsd_filter_mode = VOP2_SCALE_DOWN_BIL, .hsd_pre_filter_mode = VOP3_PRE_SCALE_DOWN_AVG, /* gt or avg */ .vsd_pre_filter_mode = VOP3_PRE_SCALE_DOWN_GT, /* gt only */ + .possible_vp_mask = BIT(VOP2_VP0) | BIT(VOP2_VP1), .max_upscale_factor = 8, .max_downscale_factor = 8, }, @@ -6014,6 +6496,7 @@ static struct vop2_win_data rk3528_win_data[5] = { .name = "Esmart3", .phys_id = ROCKCHIP_VOP2_ESMART3, .type = ESMART_LAYER, + .plane_type = VOP2_PLANE_TYPE_PRIMARY, .win_sel_port_offset = 14, .layer_sel_win_id = { 0xff, 1, 0xff, 0xff }, .reg_offset = 0x600, @@ -6026,6 +6509,7 @@ static struct vop2_win_data rk3528_win_data[5] = { .vsd_filter_mode = VOP2_SCALE_DOWN_BIL, .hsd_pre_filter_mode = VOP3_PRE_SCALE_DOWN_AVG, /* gt or avg */ .vsd_pre_filter_mode = VOP3_PRE_SCALE_DOWN_GT, /* gt only */ + .possible_vp_mask = BIT(VOP2_VP1), .max_upscale_factor = 8, .max_downscale_factor = 8, }, @@ -6034,6 +6518,7 @@ static struct vop2_win_data rk3528_win_data[5] = { .name = "Cluster0", .phys_id = ROCKCHIP_VOP2_CLUSTER0, .type = CLUSTER_LAYER, + .plane_type = VOP2_PLANE_TYPE_OVERLAY, .win_sel_port_offset = 0, .layer_sel_win_id = { 0, 0xff, 0xff, 0xff }, .reg_offset = 0, @@ -6046,6 +6531,7 @@ static struct vop2_win_data rk3528_win_data[5] = { .vsd_filter_mode = VOP2_SCALE_DOWN_BIL, .hsd_pre_filter_mode = VOP3_PRE_SCALE_DOWN_AVG, /* gt or avg */ .vsd_pre_filter_mode = VOP3_PRE_SCALE_DOWN_AVG, /* gt or avg */ + .possible_vp_mask = BIT(VOP2_VP0), .max_upscale_factor = 8, .max_downscale_factor = 8, }, @@ -6069,20 +6555,25 @@ static struct vop2_vp_data rk3528_vp_data[2] = { }, }; +static const struct vop2_ops rk3528_vop_ops = { + .setup_win_dly = rk3528_setup_win_dly, + .setup_overlay = rk3528_setup_overlay, +}; + const struct vop2_data rk3528_vop = { .version = VOP_VERSION_RK3528, .nr_vps = 2, .vp_data = rk3528_vp_data, .win_data = rk3528_win_data, - .plane_mask = rk3528_vp_plane_mask[0], - .plane_table = rk3528_plane_table, - .vp_primary_plane_order = rk3528_vp_primary_plane_order, + .plane_mask_base = RK3528_PLANE_MASK_BASE, .nr_layers = 5, .nr_mixers = 3, .nr_gammas = 2, .esmart_lb_mode = VOP3_ESMART_4K_2K_2K_MODE, .dump_regs = rk3528_dump_regs, .dump_regs_size = ARRAY_SIZE(rk3528_dump_regs), + .ops = &rk3528_vop_ops, + }; static struct vop2_dump_regs rk3562_dump_regs[] = { @@ -6098,63 +6589,16 @@ static struct vop2_dump_regs rk3562_dump_regs[] = { { RK3568_SMART1_CTRL0, "Esmart3", RK3568_SMART1_CTRL0, 0x1, 0, 1 }, }; -static u8 rk3562_vp_primary_plane_order[ROCKCHIP_VOP2_LAYER_MAX] = { - ROCKCHIP_VOP2_ESMART0, - ROCKCHIP_VOP2_ESMART1, - ROCKCHIP_VOP2_ESMART2, - ROCKCHIP_VOP2_ESMART3, -}; - -static struct vop2_plane_table rk3562_plane_table[ROCKCHIP_VOP2_LAYER_MAX] = { - {ROCKCHIP_VOP2_ESMART0, ESMART_LAYER}, - {ROCKCHIP_VOP2_ESMART1, ESMART_LAYER}, - {ROCKCHIP_VOP2_ESMART2, ESMART_LAYER}, - {ROCKCHIP_VOP2_ESMART3, ESMART_LAYER}, -}; - -static struct vop2_vp_plane_mask rk3562_vp_plane_mask[VOP2_VP_MAX][VOP2_VP_MAX] = { - { /* one display policy for hdmi */ - {/* main display */ - .primary_plane_id = ROCKCHIP_VOP2_ESMART0, - .attached_layers_nr = 4, - .attached_layers = { - ROCKCHIP_VOP2_ESMART0, ROCKCHIP_VOP2_ESMART1, - ROCKCHIP_VOP2_ESMART2, ROCKCHIP_VOP2_ESMART3 - }, - }, - {/* second display */}, - {/* third display */}, - {/* fourth display */}, - }, - - { /* two display policy */ - {/* main display */ - .primary_plane_id = ROCKCHIP_VOP2_ESMART0, - .attached_layers_nr = 2, - .attached_layers = { - ROCKCHIP_VOP2_ESMART0, ROCKCHIP_VOP2_ESMART1 - }, - }, - - {/* second display */ - .primary_plane_id = ROCKCHIP_VOP2_ESMART2, - .attached_layers_nr = 2, - .attached_layers = { - ROCKCHIP_VOP2_ESMART2, ROCKCHIP_VOP2_ESMART3 - }, - }, - {/* third display */}, - {/* fourth display */}, - }, - - {/* reserved */}, -}; +#define RK3562_PLANE_MASK_BASE \ + (BIT(ROCKCHIP_VOP2_ESMART0) | BIT(ROCKCHIP_VOP2_ESMART1) | \ + BIT(ROCKCHIP_VOP2_ESMART2) | BIT(ROCKCHIP_VOP2_ESMART3)) static struct vop2_win_data rk3562_win_data[4] = { { .name = "Esmart0", .phys_id = ROCKCHIP_VOP2_ESMART0, .type = ESMART_LAYER, + .plane_type = VOP2_PLANE_TYPE_PRIMARY, .win_sel_port_offset = 8, .layer_sel_win_id = { 0, 0, 0xff, 0xff }, .reg_offset = 0, @@ -6165,6 +6609,7 @@ static struct vop2_win_data rk3562_win_data[4] = { .hsd_filter_mode = VOP2_SCALE_DOWN_BIL, .vsu_filter_mode = VOP2_SCALE_UP_BIL, .vsd_filter_mode = VOP2_SCALE_DOWN_BIL, + .possible_vp_mask = BIT(VOP2_VP0), .max_upscale_factor = 8, .max_downscale_factor = 8, }, @@ -6173,6 +6618,7 @@ static struct vop2_win_data rk3562_win_data[4] = { .name = "Esmart1", .phys_id = ROCKCHIP_VOP2_ESMART1, .type = ESMART_LAYER, + .plane_type = VOP2_PLANE_TYPE_OVERLAY, .win_sel_port_offset = 10, .layer_sel_win_id = { 1, 1, 0xff, 0xff }, .reg_offset = 0x200, @@ -6183,6 +6629,7 @@ static struct vop2_win_data rk3562_win_data[4] = { .hsd_filter_mode = VOP2_SCALE_DOWN_BIL, .vsu_filter_mode = VOP2_SCALE_UP_BIL, .vsd_filter_mode = VOP2_SCALE_DOWN_BIL, + .possible_vp_mask = BIT(VOP2_VP0), .max_upscale_factor = 8, .max_downscale_factor = 8, }, @@ -6191,6 +6638,7 @@ static struct vop2_win_data rk3562_win_data[4] = { .name = "Esmart2", .phys_id = ROCKCHIP_VOP2_ESMART2, .type = ESMART_LAYER, + .plane_type = VOP2_PLANE_TYPE_PRIMARY, .win_sel_port_offset = 12, .layer_sel_win_id = { 2, 2, 0xff, 0xff }, .reg_offset = 0x400, @@ -6201,6 +6649,7 @@ static struct vop2_win_data rk3562_win_data[4] = { .hsd_filter_mode = VOP2_SCALE_DOWN_BIL, .vsu_filter_mode = VOP2_SCALE_UP_BIL, .vsd_filter_mode = VOP2_SCALE_DOWN_BIL, + .possible_vp_mask = BIT(VOP2_VP0), .max_upscale_factor = 8, .max_downscale_factor = 8, }, @@ -6209,6 +6658,7 @@ static struct vop2_win_data rk3562_win_data[4] = { .name = "Esmart3", .phys_id = ROCKCHIP_VOP2_ESMART3, .type = ESMART_LAYER, + .plane_type = VOP2_PLANE_TYPE_OVERLAY, .win_sel_port_offset = 14, .layer_sel_win_id = { 3, 3, 0xff, 0xff }, .reg_offset = 0x600, @@ -6219,6 +6669,7 @@ static struct vop2_win_data rk3562_win_data[4] = { .hsd_filter_mode = VOP2_SCALE_DOWN_BIL, .vsu_filter_mode = VOP2_SCALE_UP_BIL, .vsd_filter_mode = VOP2_SCALE_DOWN_BIL, + .possible_vp_mask = BIT(VOP2_VP0), .max_upscale_factor = 8, .max_downscale_factor = 8, }, @@ -6228,7 +6679,7 @@ static struct vop2_vp_data rk3562_vp_data[2] = { { .feature = VOP_FEATURE_ALPHA_SCALE | VOP_FEATURE_OVERSCAN, .max_output = {2048, 4096}, - .win_dly = 8, + .win_dly = 6, .layer_mix_dly = 8, }, { @@ -6239,20 +6690,24 @@ static struct vop2_vp_data rk3562_vp_data[2] = { }, }; +static const struct vop2_ops rk3562_vop_ops = { + .setup_win_dly = rk3528_setup_win_dly, + .setup_overlay = rk3528_setup_overlay, +}; + const struct vop2_data rk3562_vop = { .version = VOP_VERSION_RK3562, .nr_vps = 2, .vp_data = rk3562_vp_data, .win_data = rk3562_win_data, - .plane_mask = rk3562_vp_plane_mask[0], - .plane_table = rk3562_plane_table, - .vp_primary_plane_order = rk3562_vp_primary_plane_order, + .plane_mask_base = RK3562_PLANE_MASK_BASE, .nr_layers = 4, .nr_mixers = 3, .nr_gammas = 2, .esmart_lb_mode = VOP3_ESMART_2K_2K_2K_2K_MODE, .dump_regs = rk3562_dump_regs, .dump_regs_size = ARRAY_SIZE(rk3562_dump_regs), + .ops = &rk3562_vop_ops, }; static struct vop2_dump_regs rk3568_dump_regs[] = { @@ -6270,22 +6725,6 @@ static struct vop2_dump_regs rk3568_dump_regs[] = { { RK3568_HDR_LUT_CTRL, "HDR", 0, 0, 0, 0 }, }; -static u8 rk3568_vp_primary_plane_order[ROCKCHIP_VOP2_LAYER_MAX] = { - ROCKCHIP_VOP2_SMART0, - ROCKCHIP_VOP2_SMART1, - ROCKCHIP_VOP2_ESMART0, - ROCKCHIP_VOP2_ESMART1, -}; - -static struct vop2_plane_table rk356x_plane_table[ROCKCHIP_VOP2_LAYER_MAX] = { - {ROCKCHIP_VOP2_CLUSTER0, CLUSTER_LAYER}, - {ROCKCHIP_VOP2_CLUSTER1, CLUSTER_LAYER}, - {ROCKCHIP_VOP2_ESMART0, ESMART_LAYER}, - {ROCKCHIP_VOP2_ESMART1, ESMART_LAYER}, - {ROCKCHIP_VOP2_SMART0, SMART_LAYER}, - {ROCKCHIP_VOP2_SMART0, SMART_LAYER}, -}; - static struct vop2_vp_plane_mask rk356x_vp_plane_mask[VOP2_VP_MAX][VOP2_VP_MAX] = { { /* one display policy */ {/* main display */ @@ -6350,11 +6789,17 @@ static struct vop2_vp_plane_mask rk356x_vp_plane_mask[VOP2_VP_MAX][VOP2_VP_MAX] {/* reserved for four display policy */}, }; +#define RK3568_PLANE_MASK_BASE \ + (BIT(ROCKCHIP_VOP2_CLUSTER0) | BIT(ROCKCHIP_VOP2_CLUSTER1) | \ + BIT(ROCKCHIP_VOP2_ESMART0) | BIT(ROCKCHIP_VOP2_ESMART1) | \ + BIT(ROCKCHIP_VOP2_SMART0) | BIT(ROCKCHIP_VOP2_SMART1)) + static struct vop2_win_data rk3568_win_data[6] = { { .name = "Cluster0", .phys_id = ROCKCHIP_VOP2_CLUSTER0, .type = CLUSTER_LAYER, + .plane_type = VOP2_PLANE_TYPE_PRIMARY, .win_sel_port_offset = 0, .layer_sel_win_id = { 0, 0, 0, 0xff }, .reg_offset = 0, @@ -6362,14 +6807,17 @@ static struct vop2_win_data rk3568_win_data[6] = { .hsd_filter_mode = VOP2_SCALE_DOWN_BIL, .vsu_filter_mode = VOP2_SCALE_UP_BIL, .vsd_filter_mode = VOP2_SCALE_DOWN_BIL, + .possible_vp_mask = BIT(VOP2_VP0) | BIT(VOP2_VP1) | BIT(VOP2_VP2), .max_upscale_factor = 4, .max_downscale_factor = 4, + .dly = { 0, 27, 21 }, }, { .name = "Cluster1", .phys_id = ROCKCHIP_VOP2_CLUSTER1, .type = CLUSTER_LAYER, + .plane_type = VOP2_PLANE_TYPE_PRIMARY, .win_sel_port_offset = 1, .layer_sel_win_id = { 1, 1, 1, 0xff }, .reg_offset = 0x200, @@ -6377,16 +6825,19 @@ static struct vop2_win_data rk3568_win_data[6] = { .hsd_filter_mode = VOP2_SCALE_DOWN_BIL, .vsu_filter_mode = VOP2_SCALE_UP_BIL, .vsd_filter_mode = VOP2_SCALE_DOWN_BIL, + .possible_vp_mask = BIT(VOP2_VP0) | BIT(VOP2_VP1) | BIT(VOP2_VP2), .max_upscale_factor = 4, .max_downscale_factor = 4, .source_win_id = ROCKCHIP_VOP2_CLUSTER0, .feature = WIN_FEATURE_MIRROR, + .dly = { 0, 27, 21 }, }, { .name = "Esmart0", .phys_id = ROCKCHIP_VOP2_ESMART0, .type = ESMART_LAYER, + .plane_type = VOP2_PLANE_TYPE_PRIMARY, .win_sel_port_offset = 4, .layer_sel_win_id = { 2, 2, 2, 0xff }, .reg_offset = 0, @@ -6394,14 +6845,17 @@ static struct vop2_win_data rk3568_win_data[6] = { .hsd_filter_mode = VOP2_SCALE_DOWN_BIL, .vsu_filter_mode = VOP2_SCALE_UP_BIL, .vsd_filter_mode = VOP2_SCALE_DOWN_BIL, + .possible_vp_mask = BIT(VOP2_VP0) | BIT(VOP2_VP1) | BIT(VOP2_VP2), .max_upscale_factor = 8, .max_downscale_factor = 8, + .dly = { 20, 47, 41 }, }, { .name = "Esmart1", .phys_id = ROCKCHIP_VOP2_ESMART1, .type = ESMART_LAYER, + .plane_type = VOP2_PLANE_TYPE_OVERLAY, .win_sel_port_offset = 5, .layer_sel_win_id = { 6, 6, 6, 0xff }, .reg_offset = 0x200, @@ -6409,8 +6863,10 @@ static struct vop2_win_data rk3568_win_data[6] = { .hsd_filter_mode = VOP2_SCALE_DOWN_BIL, .vsu_filter_mode = VOP2_SCALE_UP_BIL, .vsd_filter_mode = VOP2_SCALE_DOWN_BIL, + .possible_vp_mask = BIT(VOP2_VP0) | BIT(VOP2_VP1) | BIT(VOP2_VP2), .max_upscale_factor = 8, .max_downscale_factor = 8, + .dly = { 20, 47, 41 }, .source_win_id = ROCKCHIP_VOP2_ESMART0, .feature = WIN_FEATURE_MIRROR, }, @@ -6419,6 +6875,7 @@ static struct vop2_win_data rk3568_win_data[6] = { .name = "Smart0", .phys_id = ROCKCHIP_VOP2_SMART0, .type = SMART_LAYER, + .plane_type = VOP2_PLANE_TYPE_OVERLAY, .win_sel_port_offset = 6, .layer_sel_win_id = { 3, 3, 3, 0xff }, .reg_offset = 0x400, @@ -6426,14 +6883,17 @@ static struct vop2_win_data rk3568_win_data[6] = { .hsd_filter_mode = VOP2_SCALE_DOWN_BIL, .vsu_filter_mode = VOP2_SCALE_UP_BIL, .vsd_filter_mode = VOP2_SCALE_DOWN_BIL, + .possible_vp_mask = BIT(VOP2_VP0) | BIT(VOP2_VP1) | BIT(VOP2_VP2), .max_upscale_factor = 8, .max_downscale_factor = 8, + .dly = { 20, 47, 41 }, }, { .name = "Smart1", .phys_id = ROCKCHIP_VOP2_SMART1, .type = SMART_LAYER, + .plane_type = VOP2_PLANE_TYPE_OVERLAY, .win_sel_port_offset = 7, .layer_sel_win_id = { 7, 7, 7, 0xff }, .reg_offset = 0x600, @@ -6441,8 +6901,10 @@ static struct vop2_win_data rk3568_win_data[6] = { .hsd_filter_mode = VOP2_SCALE_DOWN_BIL, .vsu_filter_mode = VOP2_SCALE_UP_BIL, .vsd_filter_mode = VOP2_SCALE_DOWN_BIL, + .possible_vp_mask = BIT(VOP2_VP0) | BIT(VOP2_VP1) | BIT(VOP2_VP2), .max_upscale_factor = 8, .max_downscale_factor = 8, + .dly = { 20, 47, 41 }, .source_win_id = ROCKCHIP_VOP2_SMART0, .feature = WIN_FEATURE_MIRROR, }, @@ -6466,35 +6928,30 @@ static struct vop2_vp_data rk3568_vp_data[3] = { }, }; +static const struct vop2_ops rk3568_vop_ops = { + .setup_win_dly = rk3568_setup_win_dly, + .setup_overlay = rk3568_setup_overlay, +}; + const struct vop2_data rk3568_vop = { .version = VOP_VERSION_RK3568, .nr_vps = 3, .vp_data = rk3568_vp_data, .win_data = rk3568_win_data, .plane_mask = rk356x_vp_plane_mask[0], - .plane_table = rk356x_plane_table, - .vp_primary_plane_order = rk3568_vp_primary_plane_order, + .plane_mask_base = RK3568_PLANE_MASK_BASE, .nr_layers = 6, .nr_mixers = 5, .nr_gammas = 1, .dump_regs = rk3568_dump_regs, .dump_regs_size = ARRAY_SIZE(rk3568_dump_regs), + .ops = &rk3568_vop_ops, }; -static u8 rk3576_vp_default_primary_plane[VOP2_VP_MAX] = { - ROCKCHIP_VOP2_ESMART0, - ROCKCHIP_VOP2_ESMART1, - ROCKCHIP_VOP2_ESMART2, -}; - -static struct vop2_plane_table rk3576_plane_table[ROCKCHIP_VOP2_LAYER_MAX] = { - {ROCKCHIP_VOP2_ESMART0, ESMART_LAYER}, - {ROCKCHIP_VOP2_ESMART1, ESMART_LAYER}, - {ROCKCHIP_VOP2_ESMART2, ESMART_LAYER}, - {ROCKCHIP_VOP2_ESMART3, ESMART_LAYER}, - {ROCKCHIP_VOP2_CLUSTER0, CLUSTER_LAYER}, - {ROCKCHIP_VOP2_CLUSTER1, CLUSTER_LAYER}, -}; +#define RK3576_PLANE_MASK_BASE \ + (BIT(ROCKCHIP_VOP2_CLUSTER0) | BIT(ROCKCHIP_VOP2_CLUSTER1) | \ + BIT(ROCKCHIP_VOP2_ESMART0) | BIT(ROCKCHIP_VOP2_ESMART1) | \ + BIT(ROCKCHIP_VOP2_ESMART2) | BIT(ROCKCHIP_VOP2_ESMART3)) static struct vop2_dump_regs rk3576_dump_regs[] = { { RK3568_REG_CFG_DONE, "SYS", 0, 0, 0, 0, 0x200 }, @@ -6527,22 +6984,42 @@ static struct vop2_dump_regs rk3576_dump_regs[] = { * * Support prescale down: * * H/V: gt2/avg2 or gt4/avg4 * * After prescale down: - * * nearest-neighbor/bilinear/multi-phase filter for scale up - * * nearest-neighbor/bilinear/multi-phase filter for scale down + * * nearest-neighbor/bilinear/multi-phase filter for scale up + * * nearest-neighbor/bilinear/multi-phase filter for scale down * * * Esmart: * * Support prescale down: * * H: gt2/avg2 or gt4/avg4 * * V: gt2 or gt4 * * After prescale down: - * * nearest-neighbor/bilinear/bicubic for scale up - * * nearest-neighbor/bilinear for scale down + * * nearest-neighbor/bilinear/bicubic for scale up + * * nearest-neighbor/bilinear for scale down + * + * AXI config:: + * + * * Cluster0 win0: 0xa, 0xb [AXI0] + * * Cluster0 win1: 0xc, 0xd [AXI0] + * * Cluster1 win0: 0x6, 0x7 [AXI0] + * * Cluster1 win1: 0x8, 0x9 [AXI0] + * * Esmart0: 0x10, 0x11 [AXI0] + * * Esmart1: 0x12, 0x13 [AXI0] + * * Esmart2: 0xa, 0xb [AXI1] + * * Esmart3: 0xc, 0xd [AXI1] + * * Lut dma rid: 0x1, 0x2, 0x3 [AXI0] + * * DCI dma rid: 0x4 [AXI0] + * * Metadata rid: 0x5 [AXI0] + * + * * Limit: + * * (1) 0x0 and 0xf can't be used; + * * (2) cluster and lut/dci/metadata rid must smaller than 0xf, If Cluster rid is bigger than 0xf, + * * VOP will dead at the system bandwidth very terrible scene. */ static struct vop2_win_data rk3576_win_data[6] = { { .name = "Esmart0", .phys_id = ROCKCHIP_VOP2_ESMART0, .type = ESMART_LAYER, + .plane_type = VOP2_PLANE_TYPE_PRIMARY, .layer_sel_win_id = { 2, 0xff, 0, 0xff }, .reg_offset = 0x0, .supported_rotations = DRM_MODE_REFLECT_Y, @@ -6554,9 +7031,9 @@ static struct vop2_win_data rk3576_win_data[6] = { .vsd_pre_filter_mode = VOP3_PRE_SCALE_DOWN_GT,/* gt only */ .pd_id = VOP2_PD_ESMART, .axi_id = 0, - .axi_yrgb_id = 0x0a, - .axi_uv_id = 0x0b, - .possible_crtcs = 0x5,/* vp0 or vp2 */ + .axi_yrgb_id = 0x10, + .axi_uv_id = 0x11, + .possible_vp_mask = BIT(VOP2_VP0) | BIT(VOP2_VP2), .max_upscale_factor = 8, .max_downscale_factor = 8, .feature = WIN_FEATURE_MULTI_AREA | WIN_FEATURE_Y2R_13BIT_DEPTH, @@ -6565,6 +7042,7 @@ static struct vop2_win_data rk3576_win_data[6] = { .name = "Esmart1", .phys_id = ROCKCHIP_VOP2_ESMART1, .type = ESMART_LAYER, + .plane_type = VOP2_PLANE_TYPE_PRIMARY, .layer_sel_win_id = { 0xff, 2, 1, 0xff }, .reg_offset = 0x200, .supported_rotations = DRM_MODE_REFLECT_Y, @@ -6576,9 +7054,9 @@ static struct vop2_win_data rk3576_win_data[6] = { .vsd_pre_filter_mode = VOP3_PRE_SCALE_DOWN_GT,/* gt only */ .pd_id = VOP2_PD_ESMART, .axi_id = 0, - .axi_yrgb_id = 0x0c, - .axi_uv_id = 0x0d, - .possible_crtcs = 0x6,/* vp1 or vp2 */ + .axi_yrgb_id = 0x12, + .axi_uv_id = 0x13, + .possible_vp_mask = BIT(VOP2_VP1) | BIT(VOP2_VP2), .max_upscale_factor = 8, .max_downscale_factor = 8, .feature = WIN_FEATURE_MULTI_AREA, @@ -6588,6 +7066,7 @@ static struct vop2_win_data rk3576_win_data[6] = { .name = "Esmart2", .phys_id = ROCKCHIP_VOP2_ESMART2, .type = ESMART_LAYER, + .plane_type = VOP2_PLANE_TYPE_PRIMARY, .layer_sel_win_id = { 3, 0xff, 2, 0xff }, .reg_offset = 0x400, .supported_rotations = DRM_MODE_REFLECT_Y, @@ -6601,7 +7080,7 @@ static struct vop2_win_data rk3576_win_data[6] = { .axi_id = 1, .axi_yrgb_id = 0x0a, .axi_uv_id = 0x0b, - .possible_crtcs = 0x5,/* vp0 or vp2 */ + .possible_vp_mask = BIT(VOP2_VP0) | BIT(VOP2_VP2), .max_upscale_factor = 8, .max_downscale_factor = 8, .feature = WIN_FEATURE_MULTI_AREA, @@ -6611,6 +7090,7 @@ static struct vop2_win_data rk3576_win_data[6] = { .name = "Esmart3", .phys_id = ROCKCHIP_VOP2_ESMART3, .type = ESMART_LAYER, + .plane_type = VOP2_PLANE_TYPE_OVERLAY, .layer_sel_win_id = { 0xff, 3, 3, 0xff }, .reg_offset = 0x600, .supported_rotations = DRM_MODE_REFLECT_Y, @@ -6624,7 +7104,7 @@ static struct vop2_win_data rk3576_win_data[6] = { .axi_id = 1, .axi_yrgb_id = 0x0c, .axi_uv_id = 0x0d, - .possible_crtcs = 0x6,/* vp1 or vp2 */ + .possible_vp_mask = BIT(VOP2_VP1) | BIT(VOP2_VP2), .max_upscale_factor = 8, .max_downscale_factor = 8, .feature = WIN_FEATURE_MULTI_AREA, @@ -6634,6 +7114,7 @@ static struct vop2_win_data rk3576_win_data[6] = { .name = "Cluster0", .phys_id = ROCKCHIP_VOP2_CLUSTER0, .type = CLUSTER_LAYER, + .plane_type = VOP2_PLANE_TYPE_OVERLAY, .layer_sel_win_id = { 0, 0, 0xff, 0xff }, .reg_offset = 0x0, .supported_rotations = DRM_MODE_REFLECT_X | DRM_MODE_REFLECT_Y, @@ -6644,9 +7125,9 @@ static struct vop2_win_data rk3576_win_data[6] = { .hsd_pre_filter_mode = VOP3_PRE_SCALE_DOWN_AVG,/* gt or avg */ .vsd_pre_filter_mode = VOP3_PRE_SCALE_DOWN_AVG,/* gt or avg */ .pd_id = VOP2_PD_CLUSTER, - .axi_yrgb_id = 0x02, - .axi_uv_id = 0x03, - .possible_crtcs = 0x3,/* vp0 or vp1 */ + .axi_yrgb_id = 0x0a, + .axi_uv_id = 0x0b, + .possible_vp_mask = BIT(VOP2_VP0) | BIT(VOP2_VP1), .max_upscale_factor = 8, .max_downscale_factor = 8, .feature = WIN_FEATURE_AFBDC | WIN_FEATURE_CLUSTER_MAIN | @@ -6657,6 +7138,7 @@ static struct vop2_win_data rk3576_win_data[6] = { .name = "Cluster1", .phys_id = ROCKCHIP_VOP2_CLUSTER1, .type = CLUSTER_LAYER, + .plane_type = VOP2_PLANE_TYPE_OVERLAY, .layer_sel_win_id = { 1, 1, 0xff, 0xff }, .reg_offset = 0x200, .supported_rotations = DRM_MODE_REFLECT_X | DRM_MODE_REFLECT_Y, @@ -6669,7 +7151,7 @@ static struct vop2_win_data rk3576_win_data[6] = { .pd_id = VOP2_PD_CLUSTER, .axi_yrgb_id = 0x06, .axi_uv_id = 0x07, - .possible_crtcs = 0x3,/* vp0 or vp1 */ + .possible_vp_mask = BIT(VOP2_VP0) | BIT(VOP2_VP1), .max_upscale_factor = 8, .max_downscale_factor = 8, .feature = WIN_FEATURE_AFBDC | WIN_FEATURE_CLUSTER_MAIN | @@ -6741,6 +7223,11 @@ static const struct vop2_esmart_lb_map rk3576_esmart_lb_mode_map[] = { {VOP3_ESMART_4K_4K_2K_2K_MODE, 3} }; +static const struct vop2_ops rk3576_vop_ops = { + .setup_win_dly = rk3576_setup_win_dly, + .setup_overlay = rk3576_setup_overlay, +}; + const struct vop2_data rk3576_vop = { .version = VOP_VERSION_RK3576, .nr_vps = 3, @@ -6752,34 +7239,12 @@ const struct vop2_data rk3576_vop = { .esmart_lb_mode_map = rk3576_esmart_lb_mode_map, .vp_data = rk3576_vp_data, .win_data = rk3576_win_data, - .plane_table = rk3576_plane_table, + .plane_mask_base = RK3576_PLANE_MASK_BASE, .pd = rk3576_vop_pd_data, - .vp_default_primary_plane = rk3576_vp_default_primary_plane, .nr_pd = ARRAY_SIZE(rk3576_vop_pd_data), .dump_regs = rk3576_dump_regs, .dump_regs_size = ARRAY_SIZE(rk3576_dump_regs), -}; - -static u8 rk3588_vp_primary_plane_order[ROCKCHIP_VOP2_LAYER_MAX] = { - ROCKCHIP_VOP2_ESMART0, - ROCKCHIP_VOP2_ESMART1, - ROCKCHIP_VOP2_ESMART2, - ROCKCHIP_VOP2_ESMART3, - ROCKCHIP_VOP2_CLUSTER0, - ROCKCHIP_VOP2_CLUSTER1, - ROCKCHIP_VOP2_CLUSTER2, - ROCKCHIP_VOP2_CLUSTER3, -}; - -static struct vop2_plane_table rk3588_plane_table[ROCKCHIP_VOP2_LAYER_MAX] = { - {ROCKCHIP_VOP2_CLUSTER0, CLUSTER_LAYER}, - {ROCKCHIP_VOP2_CLUSTER1, CLUSTER_LAYER}, - {ROCKCHIP_VOP2_CLUSTER2, CLUSTER_LAYER}, - {ROCKCHIP_VOP2_CLUSTER3, CLUSTER_LAYER}, - {ROCKCHIP_VOP2_ESMART0, ESMART_LAYER}, - {ROCKCHIP_VOP2_ESMART1, ESMART_LAYER}, - {ROCKCHIP_VOP2_ESMART2, ESMART_LAYER}, - {ROCKCHIP_VOP2_ESMART3, ESMART_LAYER}, + .ops = &rk3576_vop_ops, }; static struct vop2_dump_regs rk3588_dump_regs[] = { @@ -6804,14 +7269,21 @@ static struct vop2_vp_plane_mask rk3588_vp_plane_mask[VOP2_VP_MAX][VOP2_VP_MAX] { /* one display policy */ {/* main display */ .primary_plane_id = ROCKCHIP_VOP2_ESMART0, - .attached_layers_nr = 8, + .attached_layers_nr = 4, .attached_layers = { - ROCKCHIP_VOP2_CLUSTER0, ROCKCHIP_VOP2_ESMART0, ROCKCHIP_VOP2_ESMART2, - ROCKCHIP_VOP2_CLUSTER1, ROCKCHIP_VOP2_ESMART1, ROCKCHIP_VOP2_ESMART3, - ROCKCHIP_VOP2_CLUSTER2, ROCKCHIP_VOP2_CLUSTER3 + ROCKCHIP_VOP2_CLUSTER0, ROCKCHIP_VOP2_ESMART0, + ROCKCHIP_VOP2_CLUSTER2, ROCKCHIP_VOP2_ESMART2 + }, + }, + + {/* planes for the splice mode */ + .primary_plane_id = ROCKCHIP_VOP2_ESMART1, + .attached_layers_nr = 4, + .attached_layers = { + ROCKCHIP_VOP2_CLUSTER1, ROCKCHIP_VOP2_ESMART1, + ROCKCHIP_VOP2_CLUSTER3, ROCKCHIP_VOP2_ESMART3 }, }, - {/* second display */}, {/* third display */}, {/* fourth display */}, }, @@ -6822,15 +7294,15 @@ static struct vop2_vp_plane_mask rk3588_vp_plane_mask[VOP2_VP_MAX][VOP2_VP_MAX] .attached_layers_nr = 4, .attached_layers = { ROCKCHIP_VOP2_CLUSTER0, ROCKCHIP_VOP2_ESMART0, - ROCKCHIP_VOP2_CLUSTER1, ROCKCHIP_VOP2_ESMART1 + ROCKCHIP_VOP2_CLUSTER2, ROCKCHIP_VOP2_ESMART2 }, }, {/* second display */ - .primary_plane_id = ROCKCHIP_VOP2_ESMART2, + .primary_plane_id = ROCKCHIP_VOP2_ESMART1, .attached_layers_nr = 4, .attached_layers = { - ROCKCHIP_VOP2_CLUSTER2, ROCKCHIP_VOP2_ESMART2, + ROCKCHIP_VOP2_CLUSTER1, ROCKCHIP_VOP2_ESMART1, ROCKCHIP_VOP2_CLUSTER3, ROCKCHIP_VOP2_ESMART3 }, }, @@ -6843,7 +7315,8 @@ static struct vop2_vp_plane_mask rk3588_vp_plane_mask[VOP2_VP_MAX][VOP2_VP_MAX] .primary_plane_id = ROCKCHIP_VOP2_ESMART0, .attached_layers_nr = 3, .attached_layers = { - ROCKCHIP_VOP2_CLUSTER0, ROCKCHIP_VOP2_CLUSTER1, ROCKCHIP_VOP2_ESMART0 + ROCKCHIP_VOP2_CLUSTER0, ROCKCHIP_VOP2_CLUSTER2, + ROCKCHIP_VOP2_ESMART0 }, }, @@ -6851,7 +7324,8 @@ static struct vop2_vp_plane_mask rk3588_vp_plane_mask[VOP2_VP_MAX][VOP2_VP_MAX] .primary_plane_id = ROCKCHIP_VOP2_ESMART1, .attached_layers_nr = 3, .attached_layers = { - ROCKCHIP_VOP2_CLUSTER2, ROCKCHIP_VOP2_CLUSTER3, ROCKCHIP_VOP2_ESMART1 + ROCKCHIP_VOP2_CLUSTER1, ROCKCHIP_VOP2_CLUSTER3, + ROCKCHIP_VOP2_ESMART1 }, }, @@ -6892,12 +7366,19 @@ static struct vop2_vp_plane_mask rk3588_vp_plane_mask[VOP2_VP_MAX][VOP2_VP_MAX] }; +#define RK3588_PLANE_MASK_BASE \ + (BIT(ROCKCHIP_VOP2_CLUSTER0) | BIT(ROCKCHIP_VOP2_CLUSTER1) | \ + BIT(ROCKCHIP_VOP2_CLUSTER2) | BIT(ROCKCHIP_VOP2_CLUSTER3) | \ + BIT(ROCKCHIP_VOP2_ESMART0) | BIT(ROCKCHIP_VOP2_ESMART1) | \ + BIT(ROCKCHIP_VOP2_ESMART2) | BIT(ROCKCHIP_VOP2_ESMART3)) + static struct vop2_win_data rk3588_win_data[8] = { { .name = "Cluster0", .phys_id = ROCKCHIP_VOP2_CLUSTER0, .splice_win_id = ROCKCHIP_VOP2_CLUSTER1, .type = CLUSTER_LAYER, + .plane_type = VOP2_PLANE_TYPE_OVERLAY, .win_sel_port_offset = 0, .layer_sel_win_id = { 0, 0, 0, 0 }, .reg_offset = 0, @@ -6909,14 +7390,17 @@ static struct vop2_win_data rk3588_win_data[8] = { .hsd_filter_mode = VOP2_SCALE_DOWN_BIL, .vsu_filter_mode = VOP2_SCALE_UP_BIL, .vsd_filter_mode = VOP2_SCALE_DOWN_BIL, + .possible_vp_mask = BIT(VOP2_VP0) | BIT(VOP2_VP1) | BIT(VOP2_VP2) | BIT(VOP2_VP3), .max_upscale_factor = 4, .max_downscale_factor = 4, + .dly = { 4, 26, 29, 4, 35, 3, 5 }, }, { .name = "Cluster1", .phys_id = ROCKCHIP_VOP2_CLUSTER1, .type = CLUSTER_LAYER, + .plane_type = VOP2_PLANE_TYPE_OVERLAY, .win_sel_port_offset = 1, .layer_sel_win_id = { 1, 1, 1, 1 }, .reg_offset = 0x200, @@ -6928,8 +7412,10 @@ static struct vop2_win_data rk3588_win_data[8] = { .hsd_filter_mode = VOP2_SCALE_DOWN_BIL, .vsu_filter_mode = VOP2_SCALE_UP_BIL, .vsd_filter_mode = VOP2_SCALE_DOWN_BIL, + .possible_vp_mask = BIT(VOP2_VP0) | BIT(VOP2_VP1) | BIT(VOP2_VP2) | BIT(VOP2_VP3), .max_upscale_factor = 4, .max_downscale_factor = 4, + .dly = { 4, 26, 29, 4, 35, 3, 5 }, }, { @@ -6937,6 +7423,7 @@ static struct vop2_win_data rk3588_win_data[8] = { .phys_id = ROCKCHIP_VOP2_CLUSTER2, .splice_win_id = ROCKCHIP_VOP2_CLUSTER3, .type = CLUSTER_LAYER, + .plane_type = VOP2_PLANE_TYPE_OVERLAY, .win_sel_port_offset = 2, .layer_sel_win_id = { 4, 4, 4, 4 }, .reg_offset = 0x400, @@ -6948,14 +7435,17 @@ static struct vop2_win_data rk3588_win_data[8] = { .hsd_filter_mode = VOP2_SCALE_DOWN_BIL, .vsu_filter_mode = VOP2_SCALE_UP_BIL, .vsd_filter_mode = VOP2_SCALE_DOWN_BIL, + .possible_vp_mask = BIT(VOP2_VP0) | BIT(VOP2_VP1) | BIT(VOP2_VP2) | BIT(VOP2_VP3), .max_upscale_factor = 4, .max_downscale_factor = 4, + .dly = { 4, 26, 29, 4, 35, 3, 5 }, }, { .name = "Cluster3", .phys_id = ROCKCHIP_VOP2_CLUSTER3, .type = CLUSTER_LAYER, + .plane_type = VOP2_PLANE_TYPE_OVERLAY, .win_sel_port_offset = 3, .layer_sel_win_id = { 5, 5, 5, 5 }, .reg_offset = 0x600, @@ -6967,8 +7457,10 @@ static struct vop2_win_data rk3588_win_data[8] = { .hsd_filter_mode = VOP2_SCALE_DOWN_BIL, .vsu_filter_mode = VOP2_SCALE_UP_BIL, .vsd_filter_mode = VOP2_SCALE_DOWN_BIL, + .possible_vp_mask = BIT(VOP2_VP0) | BIT(VOP2_VP1) | BIT(VOP2_VP2) | BIT(VOP2_VP3), .max_upscale_factor = 4, .max_downscale_factor = 4, + .dly = { 4, 26, 29, 4, 35, 3, 5 }, }, { @@ -6976,6 +7468,7 @@ static struct vop2_win_data rk3588_win_data[8] = { .phys_id = ROCKCHIP_VOP2_ESMART0, .splice_win_id = ROCKCHIP_VOP2_ESMART1, .type = ESMART_LAYER, + .plane_type = VOP2_PLANE_TYPE_PRIMARY, .win_sel_port_offset = 4, .layer_sel_win_id = { 2, 2, 2, 2 }, .reg_offset = 0, @@ -6986,14 +7479,17 @@ static struct vop2_win_data rk3588_win_data[8] = { .hsd_filter_mode = VOP2_SCALE_DOWN_BIL, .vsu_filter_mode = VOP2_SCALE_UP_BIL, .vsd_filter_mode = VOP2_SCALE_DOWN_BIL, + .possible_vp_mask = BIT(VOP2_VP0) | BIT(VOP2_VP1) | BIT(VOP2_VP2) | BIT(VOP2_VP3), .max_upscale_factor = 8, .max_downscale_factor = 8, + .dly = { 23, 45, 48, 23, 54, 22, 24 }, }, { .name = "Esmart1", .phys_id = ROCKCHIP_VOP2_ESMART1, .type = ESMART_LAYER, + .plane_type = VOP2_PLANE_TYPE_PRIMARY, .win_sel_port_offset = 5, .layer_sel_win_id = { 3, 3, 3, 3 }, .reg_offset = 0x200, @@ -7005,8 +7501,10 @@ static struct vop2_win_data rk3588_win_data[8] = { .hsd_filter_mode = VOP2_SCALE_DOWN_BIL, .vsu_filter_mode = VOP2_SCALE_UP_BIL, .vsd_filter_mode = VOP2_SCALE_DOWN_BIL, + .possible_vp_mask = BIT(VOP2_VP0) | BIT(VOP2_VP1) | BIT(VOP2_VP2) | BIT(VOP2_VP3), .max_upscale_factor = 8, .max_downscale_factor = 8, + .dly = { 23, 45, 48, 23, 54, 22, 24 }, }, { @@ -7014,6 +7512,7 @@ static struct vop2_win_data rk3588_win_data[8] = { .phys_id = ROCKCHIP_VOP2_ESMART2, .splice_win_id = ROCKCHIP_VOP2_ESMART3, .type = ESMART_LAYER, + .plane_type = VOP2_PLANE_TYPE_PRIMARY, .win_sel_port_offset = 6, .layer_sel_win_id = { 6, 6, 6, 6 }, .reg_offset = 0x400, @@ -7025,14 +7524,17 @@ static struct vop2_win_data rk3588_win_data[8] = { .hsd_filter_mode = VOP2_SCALE_DOWN_BIL, .vsu_filter_mode = VOP2_SCALE_UP_BIL, .vsd_filter_mode = VOP2_SCALE_DOWN_BIL, + .possible_vp_mask = BIT(VOP2_VP0) | BIT(VOP2_VP1) | BIT(VOP2_VP2) | BIT(VOP2_VP3), .max_upscale_factor = 8, .max_downscale_factor = 8, + .dly = { 23, 45, 48, 23, 54, 22, 24 }, }, { .name = "Esmart3", .phys_id = ROCKCHIP_VOP2_ESMART3, .type = ESMART_LAYER, + .plane_type = VOP2_PLANE_TYPE_PRIMARY, .win_sel_port_offset = 7, .layer_sel_win_id = { 7, 7, 7, 7 }, .reg_offset = 0x600, @@ -7044,8 +7546,10 @@ static struct vop2_win_data rk3588_win_data[8] = { .hsd_filter_mode = VOP2_SCALE_DOWN_BIL, .vsu_filter_mode = VOP2_SCALE_UP_BIL, .vsd_filter_mode = VOP2_SCALE_DOWN_BIL, + .possible_vp_mask = BIT(VOP2_VP0) | BIT(VOP2_VP1) | BIT(VOP2_VP2) | BIT(VOP2_VP3), .max_upscale_factor = 8, .max_downscale_factor = 8, + .dly = { 23, 45, 48, 23, 54, 22, 24 }, }, }; @@ -7188,18 +7692,22 @@ static struct vop2_power_domain_data rk3588_vop_pd_data[] = { }, }; +static const struct vop2_ops rk3588_vop_ops = { + .setup_win_dly = rk3568_setup_win_dly, + .setup_overlay = rk3568_setup_overlay, +}; + const struct vop2_data rk3588_vop = { .version = VOP_VERSION_RK3588, .nr_vps = 4, .vp_data = rk3588_vp_data, .win_data = rk3588_win_data, .plane_mask = rk3588_vp_plane_mask[0], - .plane_table = rk3588_plane_table, + .plane_mask_base = RK3588_PLANE_MASK_BASE, .pd = rk3588_vop_pd_data, .dsc = rk3588_dsc_data, .dsc_error_ecw = dsc_ecw, .dsc_error_buffer_flow = dsc_buffer_flow, - .vp_primary_plane_order = rk3588_vp_primary_plane_order, .nr_layers = 8, .nr_mixers = 7, .nr_gammas = 4, @@ -7209,6 +7717,7 @@ const struct vop2_data rk3588_vop = { .nr_dsc_buffer_flow = ARRAY_SIZE(dsc_buffer_flow), .dump_regs = rk3588_dump_regs, .dump_regs_size = ARRAY_SIZE(rk3588_dump_regs), + .ops = &rk3588_vop_ops, }; const struct rockchip_crtc_funcs rockchip_vop2_funcs = { @@ -7217,6 +7726,7 @@ const struct rockchip_crtc_funcs rockchip_vop2_funcs = { .init = rockchip_vop2_init, .set_plane = rockchip_vop2_set_plane, .enable = rockchip_vop2_enable, + .post_enable = rockchip_vop2_post_enable, .disable = rockchip_vop2_disable, .fixup_dts = rockchip_vop2_fixup_dts, .send_mcu_cmd = rockchip_vop2_send_mcu_cmd, diff --git a/u-boot/drivers/video/drm/rockchip_vop_reg.c b/u-boot/drivers/video/drm/rockchip_vop_reg.c index 6309ae7b66a..c71da6d24f6 100644 --- a/u-boot/drivers/video/drm/rockchip_vop_reg.c +++ b/u-boot/drivers/video/drm/rockchip_vop_reg.c @@ -745,7 +745,6 @@ static const struct vop_ctrl rk3506_ctrl_data = { .dsp_interlace = VOP_REG(RK3366_LIT_DSP_CTRL2, 0x1, 0), .dsp_interlace_pol = VOP_REG(RK3366_LIT_DSP_CTRL2, 0x1, 1), .dither_up = VOP_REG(RK3366_LIT_DSP_CTRL2, 0x1, 2), - .overlay_mode = VOP_REG(RK3366_LIT_DSP_CTRL2, 0x1, 4), .dsp_lut_en = VOP_REG(RK3366_LIT_DSP_CTRL2, 0x1, 5), .dither_down = VOP_REG(RK3366_LIT_DSP_CTRL2, 0x1, 8), .dsp_data_swap = VOP_REG(RK3366_LIT_DSP_CTRL2, 0x1f, 9), @@ -1036,11 +1035,8 @@ static const struct vop_ctrl rv1106_ctrl_data = { .vs_st_end_f1 = VOP_REG(RK3366_LIT_DSP_VS_ST_END_F1, 0x0fff0fff, 0), .dsp_interlace = VOP_REG(RK3366_LIT_DSP_CTRL2, 0x1, 0), .auto_gate_en = VOP_REG(RK3366_LIT_SYS_CTRL2, 0x1, 0), - .overlay_mode = VOP_REG(RK3366_LIT_DSP_CTRL2, 0x1, 4), .core_dclk_div = VOP_REG(RK3366_LIT_DSP_CTRL0, 0x1, 13), - .dclk_ddr = VOP_REG(RK3366_LIT_DSP_CTRL0, 0x1, 14), .rgb_en = VOP_REG(RK3366_LIT_DSP_CTRL0, 0x1, 0), - .rgb_dclk_pol = VOP_REG(RK3366_LIT_DSP_CTRL0, 0x1, 1), .rgb_pin_pol = VOP_REG(RK3366_LIT_DSP_CTRL0, 0x7, 2), .dither_down = VOP_REG(RK3366_LIT_DSP_CTRL2, 0x1, 8), .dither_up = VOP_REG(RK3366_LIT_DSP_CTRL2, 0x1, 2), diff --git a/u-boot/drivers/video/drm/samsung_mipi_dcphy.c b/u-boot/drivers/video/drm/samsung_mipi_dcphy.c index e54cf19f422..3cf54c9c715 100644 --- a/u-boot/drivers/video/drm/samsung_mipi_dcphy.c +++ b/u-boot/drivers/video/drm/samsung_mipi_dcphy.c @@ -229,7 +229,7 @@ struct samsung_mipi_dcphy { unsigned long long rate; u8 prediv; u16 fbdiv; - long dsm; + u16 dsm; u8 scaler; bool ssc_en; @@ -1320,19 +1320,7 @@ static void samsung_mipi_dcphy_pll_configure(struct samsung_mipi_dcphy *samsung) { phy_update_bits(samsung, PLL_CON0, S_MASK | P_MASK, S(samsung->pll.scaler) | P(samsung->pll.prediv)); - - if (samsung->pll.dsm < 0) { - u16 dsm_tmp; - - /* Using opposite number subtraction to find complement */ - dsm_tmp = abs(samsung->pll.dsm); - dsm_tmp = dsm_tmp - 1; - dsm_tmp ^= 0xffff; - phy_write(samsung, PLL_CON1, dsm_tmp); - } else { - phy_write(samsung, PLL_CON1, samsung->pll.dsm); - } - + phy_write(samsung, PLL_CON1, samsung->pll.dsm); phy_update_bits(samsung, PLL_CON2, M_MASK, M(samsung->pll.fbdiv)); if (samsung->pll.ssc_en) { @@ -1659,71 +1647,88 @@ static int samsung_mipi_dcphy_power_off(struct rockchip_phy *phy) static int samsung_mipi_dcphy_pll_ssc_modulation_calc(struct samsung_mipi_dcphy *samsung, - u8 *mfr, u8 *mrr) + u16 prediv, u16 fbdiv, u8 *mfr, u8 *mrr) { unsigned long fin = 24000; - u16 prediv = samsung->pll.prediv; - u16 fbdiv = samsung->pll.fbdiv; - u16 min_mfr, max_mfr; + u16 min_mfr, max_mfr, mid_mfr, mfr_end; u16 _mfr, best_mfr = 0; - u16 mr, _mrr, best_mrr = 0; - - /* 20KHz ≤ MF ≤ 150KHz */ - max_mfr = DIV_ROUND_UP(fin, (20 * prediv) << 5); - min_mfr = div64_ul(fin, ((150 * prediv) << 5)); - /*0 ≤ mfr ≤ 255 */ + u16 _mrr, best_mrr = 0; + + /* MF(MHz) = Fref / p / mfr / 32 */ + /* 30MHz ≤ MF ≤ 33MHz, default 31 */ + max_mfr = DIV_ROUND_UP(fin, (30 * prediv) << 5); + min_mfr = div64_ul(fin, ((33 * prediv) << 5)); + mid_mfr = div64_ul(fin, (31 * prediv) << 5); + /* 0 ≤ mfr ≤ 255 */ if (max_mfr > 256) max_mfr = 256; - for (_mfr = min_mfr; _mfr < max_mfr; _mfr++) { - /* 1 ≤ mrr ≤ 31 */ - for (_mrr = 1; _mrr < 32; _mrr++) { - mr = DIV_ROUND_UP(_mfr * _mrr * 100, fbdiv << 6); - /* 0 ≤ MR ≤ 5% */ - if (mr > 5) - continue; - - if (_mfr * _mrr < 513) { + mfr_end = max_mfr; + for (_mfr = mid_mfr; _mfr < mfr_end; _mfr++) { + /* MR(%) = mfr * mrr * 100 / m / 64 */ + /* 0 ≤ MR ≤ 5000ppm(0.5%), default is reduced from 0.25%. */ + _mrr = (25 * fbdiv << 6) / (_mfr * 100 * 100); + for (; _mrr > 0; _mrr--) { + /* 0 ≤ mrr * mfr ≤ 512 */ + if (_mfr * _mrr <= 512) { best_mfr = _mfr; best_mrr = _mrr; break; } } + + if (best_mrr) + break; + + if (_mfr == mfr_end - 1 && _mfr > mid_mfr) { + _mfr = min_mfr - 1; + mfr_end = mid_mfr; + } } if (best_mrr) { *mfr = best_mfr & 0xff; *mrr = best_mrr & 0x3f; - } else { - dev_err(samsung->dev, "failed to calc ssc parameter mfr and mrr\n"); - return -EINVAL; + dev_info(samsung->dev, "mfr=%d, mrr=%d, MF=%llukHz, MR=%lluppm\n", + *mfr, *mrr, div64_ul(fin, (prediv * *mfr) << 5), + div64_ul(*mfr * *mrr * 1000000, fbdiv << 6)); + + return 0; } - return 0; + dev_info(samsung->dev, "%s: failed to calc ssc parameter mfr and mrr\n", __func__); + + return -EINVAL; } static unsigned long samsung_mipi_dcphy_pll_round_rate(struct samsung_mipi_dcphy *samsung, unsigned long prate, unsigned long rate, - u8 *prediv, u16 *fbdiv, int *dsm, u8 *scaler) + u8 *prediv, u16 *fbdiv, u16 *dsm, u8 *scaler, u8 *mfr, u8 *mrr) { u32 max_fout = samsung->c_option ? samsung->pdata->cphy_tx_max_ksps_per_lane : samsung->pdata->dphy_tx_max_kbps_per_lane; - u64 best_freq = 0; + u64 _freq, best_freq = 0; u64 fin, fvco, fout; u8 min_prediv, max_prediv; + u8 _mfr = 0, best_mfr = 0; + u8 _mrr = 0, best_mrr = 0; u8 _prediv, best_prediv = 1; u16 _fbdiv, best_fbdiv = 1; u8 _scaler, best_scaler = 0; - long _dsm, best_dsm = 0; + long long _dsm, best_dsm = 0; u32 min_delta = 0xffffffff; + int ret = 0; if (!prate) { dev_err(samsung->dev, "prate of pll can not be set zero\n"); return 0; } + printf("%s: fin=%lu, req_rate=%lu\n", + __func__, prate, rate); + /* * The PLL output frequency can be calculated using a simple formula: * Fvco = ((m+k/65536) x 2 x Fin) / p @@ -1759,23 +1764,39 @@ samsung_mipi_dcphy_pll_round_rate(struct samsung_mipi_dcphy *samsung, if ((_fbdiv < 64) || (_fbdiv > 1023)) continue; - /* -32767 ≤ K[15:0] ≤ 32767 */ - _dsm = ((_prediv * fvco) - (2 * _fbdiv * fin)); - _dsm = DIV_ROUND_UP(_dsm << 15, fin); - if (abs(_dsm) > 32767) + /* -32768 ≤ K[15:0] ≤ 32767 */ + _dsm = _prediv * fvco - 2 * _fbdiv * fin; + _dsm = _dsm / abs(_dsm) * DIV_ROUND_UP_ULL(abs(_dsm) << 15, fin); + if (_dsm < -32768 || _dsm > 32767) continue; - tmp = DIV_ROUND_CLOSEST((_fbdiv * fin * 2 * 1000), _prediv); - tmp += DIV_ROUND_CLOSEST((_dsm * fin * 1000), _prediv << 15); + tmp = DIV_ROUND_CLOSEST(_fbdiv * fin * 2 * 1000, _prediv); + tmp += (_dsm / abs(_dsm) * + DIV_ROUND_CLOSEST(abs(_dsm) * fin * 1000, + _prediv << 15)); + _freq = (DIV_ROUND_CLOSEST(tmp, 1000) * MSEC_PER_SEC); + + /* + * All DPHY 2.0 compliant Transmitters shall support SSC + * operating above 2.5 Gbps + */ + if ((_freq >> _scaler) > 2500000000LL) + ret = samsung_mipi_dcphy_pll_ssc_modulation_calc(samsung, + _prediv, + _fbdiv, + &_mfr, + &_mrr); delta = abs(fvco * MSEC_PER_SEC - tmp); - if (delta < min_delta) { + if (!ret && delta <= min_delta) { best_prediv = _prediv; best_fbdiv = _fbdiv; best_dsm = _dsm; + best_mfr = _mfr; + best_mrr = _mrr; best_scaler = _scaler; min_delta = delta; - best_freq = DIV_ROUND_CLOSEST(tmp, 1000) * MSEC_PER_SEC; + best_freq = _freq; } } } @@ -1787,8 +1808,10 @@ samsung_mipi_dcphy_pll_round_rate(struct samsung_mipi_dcphy *samsung, *fbdiv = best_fbdiv; *dsm = (int)best_dsm & 0xffff; *scaler = best_scaler; - dev_info(samsung->dev, "p: %d, m: %d, dsm:%ld, scaler: %d\n", - best_prediv, best_fbdiv, best_dsm, best_scaler); + *mfr = best_mfr; + *mrr = best_mrr; + printf("%s: fout=%llu, prediv=%u, fbdiv=%u, dsm=%lld, scaler=%u\n", + __func__, best_freq >> best_scaler, best_prediv, best_fbdiv, best_dsm, best_scaler); return best_freq >> best_scaler; } @@ -1801,30 +1824,20 @@ static unsigned long samsung_mipi_dcphy_set_pll(struct rockchip_phy *phy, u8 scaler = 0, mfr = 0, mrr = 0; u16 fbdiv = 0; u8 prediv = 1; - int dsm = 0; - int ret; + u16 dsm = 0; samsung->c_option = (samsung->mode == PHY_MODE_MIPI_DPHY) ? false : true; fout = samsung_mipi_dcphy_pll_round_rate(samsung, fin, rate, &prediv, - &fbdiv, &dsm, &scaler); + &fbdiv, &dsm, &scaler, &mfr, &mrr); - dev_info(samsung->dev, "fin=%lu, req_rate=%lu\n", fin, rate); - dev_info(samsung->dev, "fout=%lu, prediv=%u, fbdiv=%u\n", fout, prediv, fbdiv); + if (fout != 0) { + samsung->pll.prediv = prediv; + samsung->pll.fbdiv = fbdiv; + samsung->pll.dsm = dsm; + samsung->pll.scaler = scaler; + samsung->pll.rate = fout; - samsung->pll.prediv = prediv; - samsung->pll.fbdiv = fbdiv; - samsung->pll.dsm = dsm; - samsung->pll.scaler = scaler; - samsung->pll.rate = fout; - - /* - * All DPHY 2.0 compliant Transmitters shall support SSC operating above - * 2.5 Gbps - */ - if (fout > 2500000000LL) { - ret = samsung_mipi_dcphy_pll_ssc_modulation_calc(samsung, - &mfr, &mrr); - if (!ret) { + if (fout > 2500000000LL) { samsung->pll.ssc_en = true; samsung->pll.mfr = mfr; samsung->pll.mrr = mrr; @@ -1901,8 +1914,8 @@ static const struct rockchip_phy_funcs samsung_mipi_dcphy_funcs = { static const struct hs_drv_res_cfg rk3576_dphy_hs_drv_res_cfg = { .clk_hs_drv_up_ohm = _52_OHM, .clk_hs_drv_down_ohm = _52_OHM, - .data_hs_drv_up_ohm = _39_OHM, - .data_hs_drv_down_ohm = _39_OHM, + .data_hs_drv_up_ohm = _43_OHM, + .data_hs_drv_down_ohm = _43_OHM, }; static const struct hs_drv_res_cfg rk3588_dphy_hs_drv_res_cfg = { diff --git a/u-boot/drivers/video/rk_eink/epdlut/epd_lut.c b/u-boot/drivers/video/rk_eink/epdlut/epd_lut.c index 1715b752572..5ae87885f3c 100644 --- a/u-boot/drivers/video/rk_eink/epdlut/epd_lut.c +++ b/u-boot/drivers/video/rk_eink/epdlut/epd_lut.c @@ -1,16 +1,19 @@ // SPDX-License-Identifier: GPL-2.0 /* - * Copyright (c) 2020 Rockchip Electronics Co. Ltd. + * Copyright (c) 2020 Rockchip Electronics Co., Ltd. * * Author: Zorro Liu */ + #include #include #include #include "epd_lut.h" -int epd_lut_from_mem_init(void *waveform, struct epd_lut_ops *ops) +static int (*lut_get)(struct epd_lut_data *, enum epd_lut_type, int, int, int); + +int epd_lut_from_mem_init(void *waveform) { int ret = -1; @@ -19,7 +22,7 @@ int epd_lut_from_mem_init(void *waveform, struct epd_lut_ops *ops) printf("[lut]: failed to input RKF waveform\n"); } else { printf("[lut]: RKF waveform\n"); - ops->lut_get = rkf_wf_get_lut; + lut_get = rkf_wf_get_lut; return 0; } @@ -28,7 +31,7 @@ int epd_lut_from_mem_init(void *waveform, struct epd_lut_ops *ops) printf("[lut]: failed to input PVI waveform\n"); } else { printf("[lut]: PVI waveform\n"); - ops->lut_get = pvi_wf_get_lut; + lut_get = pvi_wf_get_lut; return 0; } @@ -43,3 +46,14 @@ const char *epd_lut_get_wf_version(void) return pvi_wf_get_version(); return NULL; } + +int epd_lut_get(struct epd_lut_data *output, enum epd_lut_type lut_type, int temperture, int pic, int regal_pix) +{ + return lut_get(output, lut_type, temperture, pic, regal_pix); +} + +//you can change overlay lut mode here +int epd_overlay_lut(void) +{ + return WF_TYPE_GRAY2; +} diff --git a/u-boot/drivers/video/rk_eink/epdlut/epd_lut.h b/u-boot/drivers/video/rk_eink/epdlut/epd_lut.h index a5dcdc7a761..c991def09cb 100644 --- a/u-boot/drivers/video/rk_eink/epdlut/epd_lut.h +++ b/u-boot/drivers/video/rk_eink/epdlut/epd_lut.h @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0 /* - * Copyright (c) 2020 Rockchip Electronics Co. Ltd. + * Copyright (c) 2020 Rockchip Electronics Co., Ltd. * * Author: Zorro Liu */ @@ -8,98 +8,61 @@ #ifndef EPD_LUT_H #define EPD_LUT_H -#define LUT_SUCCESS (0) -#define LUT_ERROR (-1) +#define MAXFRAME 255 -#define LUT_FROM_GPIO_SPI_FLASH (0) -#define LUT_FROM_RK_SPI_FLASH (1) -#define LUT_FROM_NAND_FLASH (2) -#define LUT_FROM_WAVEFORM_FILE (3) -#define LUT_FROM_MEM_RESERVED (4) +#define WF_4BIT 16 +#define WF_5BIT 32 +// same to pvi_wf_mode enum epd_lut_type { - WF_TYPE_RESET = 1, - WF_TYPE_GRAY16 = 2, - WF_TYPE_GRAY4 = 3, - WF_TYPE_GRAY2 = 4, - WF_TYPE_AUTO = 5, - WF_TYPE_A2 = 6, - WF_TYPE_GC16 = 7, - WF_TYPE_GL16 = 8, - WF_TYPE_GLR16 = 9, - WF_TYPE_GLD16 = 10, - WF_TYPE_GCC16 = 11, - WF_TYPE_GRAY32 = 12, - WF_TYPE_MAX = 13, -}; - -enum waveform_type { - RKF_WAVEFORM = 1, - PVI_WAVEFORM = 2, - OED_WAVEFORM = 3, -}; - -enum pvi_wf_mode { - PVI_WF_RESET = 0, - PVI_WF_DU = 1, - PVI_WF_DU4 = 2, - PVI_WF_GC16 = 3, - PVI_WF_GL16 = 4, - PVI_WF_GLR16 = 5, - PVI_WF_GLD16 = 6, - PVI_WF_A2 = 7, - PVI_WF_GCC16 = 8, + WF_TYPE_RESET = 0, + WF_TYPE_GRAY2, // like DU + WF_TYPE_GRAY4, // like DU4 + WF_TYPE_GC16, + WF_TYPE_GL16, + WF_TYPE_GLR16, + WF_TYPE_GLD16, + WF_TYPE_A2, + WF_TYPE_GCC16, PVI_WF_MAX, -}; -enum oed_wf_mode { - OED_WF_RESET = 0, - OED_WF_DU = 1, - OED_WF_GC16 = 2, - OED_WF_GU16 = 3, - OED_WF_A2 = 4, - OED_WF_GL16 = 5, - OED_WF_A2IN = 6, - OED_WF_A2OUT = 7, - OED_WF_MAX, + WF_TYPE_AUTO, // like GC16, rk define + WF_TYPE_RK_GLR16, // for part regal mode + WF_TYPE_RK_GLD16, // for part regal mode + WF_TYPE_RK_GL16, // for part gl16 mode + WF_TYPE_RK_GC16, // for part gc16 mode + WF_TYPE_MAX, + WF_TYPE_GRAY16, }; struct epd_lut_data { unsigned int frame_num; unsigned int *data; -}; - -struct epd_lut_ops { - int (*lut_get)(struct epd_lut_data *lut, enum epd_lut_type type, - int temp); + u8 *wf_table[2]; }; /* * EPD LUT module export symbols */ -int epd_lut_from_mem_init(void *waveform, struct epd_lut_ops *ops); +int epd_lut_from_mem_init(void *waveform); const char *epd_lut_get_wf_version(void); +int epd_lut_get(struct epd_lut_data *output, enum epd_lut_type lut_type, int temperture, int pic, int regal_pix); -/* - * External functions - */ -int map_gray16_mode(void); -int map_auto_mode(void); +//you can change overlay lut mode here +int epd_overlay_lut(void); /* * PVI Waveform Interfaces */ int pvi_wf_input(void *waveform_file); +int pvi_wf_add_custom_mode_table(u8 *table, int size); const char *pvi_wf_get_version(void); -int pvi_wf_get_lut(struct epd_lut_data *output, enum epd_lut_type lut_type, - int temperature); +int pvi_wf_get_lut(struct epd_lut_data *output, enum epd_lut_type lut_type, int temperture, int pic, int regal_pix); /* * RKF Waveform Interfaces */ int rkf_wf_input(void *waveform_file); const char *rkf_wf_get_version(void); -int rkf_wf_get_lut(struct epd_lut_data *output, enum epd_lut_type lut_type, - int temperature); +int rkf_wf_get_lut(struct epd_lut_data *output, enum epd_lut_type lut_type, int temperture, int pic, int regal_pix); #endif - diff --git a/u-boot/drivers/video/rk_eink/epdlut/pvi_waveform.S b/u-boot/drivers/video/rk_eink/epdlut/pvi_waveform.S index 79b7a2edb84..0fa9fa3c0ca 100644 --- a/u-boot/drivers/video/rk_eink/epdlut/pvi_waveform.S +++ b/u-boot/drivers/video/rk_eink/epdlut/pvi_waveform.S @@ -1,7 +1,8 @@ +// SPDX-License-Identifier: GPL-2.0 /* - * (C) Copyright 2020 Rockchip Electronics Co., Ltd + * Copyright (c) 2020-2024 Rockchip Electronics Co., Ltd. * - * SPDX-License-Identifier: GPL-2.0+ + * Author: Zorro Liu */ .arch armv8-a+nosimd @@ -9,2358 +10,1120 @@ .text .Ltext0: .cfi_sections .debug_frame - .section .text.get_wf_mode_index,"ax",@progbits + .section .text.get_wf_temp_index,"ax",@progbits .align 2 - .type get_wf_mode_index, %function -get_wf_mode_index: -.LFB215: - .file 1 "drivers/video/rk_eink/epdlut/pvi_waveform.c" - .loc 1 285 0 + .type get_wf_temp_index, %function +get_wf_temp_index: +.LFB218: + .file 1 "/home/hzb/sdk/ebc-dev/rk_eink/../epdlut/pvi_waveform.c" + .loc 1 243 0 .cfi_startproc .LVL0: - stp x29, x30, [sp, -32]! - .cfi_def_cfa_offset 32 - .cfi_offset 29, -32 - .cfi_offset 30, -24 - add x29, sp, 0 - .cfi_def_cfa_register 29 - stp x19, x20, [sp, 16] - .cfi_offset 19, -16 - .cfi_offset 20, -8 - .loc 1 285 0 - mov w20, w0 - .loc 1 286 0 + .loc 1 243 0 + mov w4, w0 + .loc 1 244 0 adrp x0, .LANCHOR0 .LVL1: - adrp x19, .LANCHOR1 - ldr x2, [x0, #:lo12:.LANCHOR0] + .loc 1 248 0 + mov x1, 0 + .loc 1 244 0 + ldr x3, [x0, #:lo12:.LANCHOR0] + ldrb w2, [x3, 38] .LVL2: -.LBB42: -.LBB43: - .loc 1 164 0 - ldrb w1, [x2, 16] - cmp w1, 32 - beq .L3 - bhi .L4 - cmp w1, 22 - beq .L5 - bhi .L6 - cmp w1, 9 - beq .L7 - cmp w1, 18 - beq .L8 .L2: - .loc 1 267 0 - add x0, x19, :lo12:.LANCHOR1 - .loc 1 268 0 - mov w3, 1 - .loc 1 273 0 - mov w4, 5 - .loc 1 267 0 - str wzr, [x19, #:lo12:.LANCHOR1] - .loc 1 269 0 - stp w3, w3, [x0, 4] - .loc 1 270 0 - mov w3, 2 - str w3, [x0, 12] - .loc 1 271 0 - mov w3, 3 - .loc 1 273 0 - str w4, [x0, 24] - .loc 1 274 0 - mov w4, 6 - .loc 1 271 0 - str w3, [x0, 16] - .loc 1 272 0 - mov w3, 4 - .loc 1 274 0 - str w4, [x0, 28] - .loc 1 272 0 - str w3, [x0, 20] - .loc 1 275 0 - str w3, [x0, 32] - .loc 1 276 0 - adrp x0, .LC0 - add x0, x0, :lo12:.LC0 - ldrb w2, [x2, 22] + mov w0, w1 .LVL3: - bl printf + .loc 1 248 0 discriminator 1 + cmp w1, w2 + blt .L4 + .loc 1 255 0 + cmp w1, w2 + bne .L5 + .loc 1 256 0 + sub w0, w2, #1 .LVL4: - b .L15 + ret .LVL5: -.L6: - .loc 1 164 0 - cmp w1, 24 - beq .L3 - cmp w1, 25 -.L43: - bne .L2 - .loc 1 223 0 - add x0, x19, :lo12:.LANCHOR1 - .loc 1 224 0 - mov w1, 1 - .loc 1 223 0 - str wzr, [x19, #:lo12:.LANCHOR1] - .loc 1 224 0 - str w1, [x0, 4] - .loc 1 225 0 - mov w1, 7 - b .L49 .L4: - .loc 1 164 0 - cmp w1, 72 - beq .L10 - bhi .L11 - cmp w1, 35 - beq .L12 - cmp w1, 67 - b .L43 -.L11: - cmp w1, 84 - beq .L13 - cmp w1, 114 - bne .L2 - .loc 1 256 0 - add x0, x19, :lo12:.LANCHOR1 - .loc 1 257 0 - mov w1, 1 - .loc 1 256 0 - str wzr, [x19, #:lo12:.LANCHOR1] - .loc 1 258 0 - stp w1, w1, [x0, 4] - .loc 1 259 0 - mov w1, 2 - str w1, [x0, 12] - .loc 1 260 0 - mov w1, 3 - str w1, [x0, 16] - .loc 1 261 0 - mov w1, 4 - str w1, [x0, 20] - .loc 1 262 0 - mov w1, 11 - str w1, [x0, 24] - .loc 1 263 0 - mov w1, 6 - str w1, [x0, 28] - .loc 1 264 0 - mov w1, 10 - b .L45 -.L10: - .loc 1 166 0 - add x0, x19, :lo12:.LANCHOR1 - .loc 1 167 0 - mov w1, 1 - .loc 1 166 0 - str wzr, [x19, #:lo12:.LANCHOR1] - .loc 1 168 0 - stp w1, w1, [x0, 4] - .loc 1 169 0 - mov w1, 2 - str w1, [x0, 12] - .loc 1 170 0 - mov w1, 3 - str w1, [x0, 16] - .loc 1 171 0 - mov w1, 4 - .loc 1 172 0 - stp w1, w1, [x0, 20] -.L46: - .loc 1 195 0 - str w1, [x0, 32] - .loc 1 196 0 - mov w1, 6 - b .L44 -.L7: - .loc 1 177 0 - add x0, x19, :lo12:.LANCHOR1 - .loc 1 178 0 - mov w1, 1 - .loc 1 177 0 - str wzr, [x19, #:lo12:.LANCHOR1] - .loc 1 179 0 - stp w1, w1, [x0, 4] - .loc 1 180 0 - mov w1, 2 - str w1, [x0, 12] - .loc 1 181 0 - mov w1, 3 - .loc 1 182 0 - stp w1, w1, [x0, 16] - .loc 1 183 0 - str w1, [x0, 24] - .loc 1 184 0 - str w1, [x0, 32] - .loc 1 185 0 - mov w1, 4 -.L44: - str w1, [x0, 28] + .loc 1 249 0 + add x5, x3, x1 + add x1, x1, 1 + ldrb w5, [x5, 48] + cmp w5, w4 + blt .L2 .LVL6: -.L15: -.LBE43: -.LBE42: - .loc 1 292 0 - cmp w20, 5 - beq .L29 - .loc 1 295 0 - cmp w20, 2 - beq .L29 - .loc 1 298 0 - sub w20, w20, #1 +.L1: + .loc 1 259 0 + ret .LVL7: - cmp w20, 9 - bhi .L17 - adrp x0, .L19 - add x0, x0, :lo12:.L19 - ldrb w0, [x0,w20,uxtw] - adr x1, .Lrtx19 - add x0, x1, w0, sxtb #2 - br x0 -.Lrtx19: - .section .rodata.get_wf_mode_index,"a",@progbits - .align 0 - .align 2 -.L19: - .byte (.L18 - .Lrtx19) / 4 - .byte (.L17 - .Lrtx19) / 4 - .byte (.L20 - .Lrtx19) / 4 - .byte (.L21 - .Lrtx19) / 4 - .byte (.L17 - .Lrtx19) / 4 - .byte (.L22 - .Lrtx19) / 4 - .byte (.L29 - .Lrtx19) / 4 - .byte (.L23 - .Lrtx19) / 4 - .byte (.L24 - .Lrtx19) / 4 - .byte (.L25 - .Lrtx19) / 4 - .section .text.get_wf_mode_index -.LVL8: .L5: -.LBB45: -.LBB44: - .loc 1 188 0 - add x0, x19, :lo12:.LANCHOR1 - .loc 1 189 0 - mov w1, 1 - .loc 1 188 0 - str wzr, [x19, #:lo12:.LANCHOR1] - .loc 1 190 0 - stp w1, w1, [x0, 4] - .loc 1 191 0 - mov w1, 2 - str w1, [x0, 12] - .loc 1 192 0 - mov w1, 3 - str w1, [x0, 16] - .loc 1 193 0 - mov w1, 4 - .loc 1 194 0 - stp w1, w1, [x0, 20] - .loc 1 195 0 - mov w1, 5 - b .L46 -.L3: - .loc 1 200 0 - add x0, x19, :lo12:.LANCHOR1 - .loc 1 201 0 - mov w1, 1 - .loc 1 200 0 - str wzr, [x19, #:lo12:.LANCHOR1] - .loc 1 201 0 - str w1, [x0, 4] -.L49: - .loc 1 225 0 - str w1, [x0, 8] - .loc 1 226 0 - mov w1, 2 - .loc 1 229 0 - mov w2, 5 + .loc 1 245 0 + mov w0, -1 +.LVL8: + .loc 1 258 0 + b .L1 + .cfi_endproc +.LFE218: + .size get_wf_temp_index, .-get_wf_temp_index + .section .text.get_wf_frm_num,"ax",@progbits + .align 2 + .type get_wf_frm_num, %function +get_wf_frm_num: +.LFB219: + .loc 1 262 0 + .cfi_startproc .LVL9: - .loc 1 226 0 - str w1, [x0, 12] - .loc 1 227 0 - mov w1, 3 - .loc 1 229 0 - str w2, [x0, 24] - .loc 1 227 0 - str w1, [x0, 16] - .loc 1 230 0 - mov w2, 6 - .loc 1 228 0 - mov w1, 4 - str w1, [x0, 20] - b .L48 + stp x29, x30, [sp, -64]! + .cfi_def_cfa_offset 64 + .cfi_offset 29, -64 + .cfi_offset 30, -56 + .loc 1 263 0 + adrp x2, .LANCHOR0 + .loc 1 267 0 + lsl w0, w0, 2 .LVL10: -.L13: - .loc 1 211 0 - add x0, x19, :lo12:.LANCHOR1 - .loc 1 212 0 - mov w1, 1 - .loc 1 211 0 - str wzr, [x19, #:lo12:.LANCHOR1] - .loc 1 218 0 - mov w2, 5 + .loc 1 262 0 + add x29, sp, 0 + .cfi_def_cfa_register 29 + .loc 1 263 0 + ldr x2, [x2, #:lo12:.LANCHOR0] .LVL11: - .loc 1 213 0 - stp w1, w1, [x0, 4] - .loc 1 214 0 - mov w1, 2 - str w1, [x0, 12] - .loc 1 215 0 - mov w1, 3 - str w1, [x0, 16] - .loc 1 216 0 - mov w1, 4 - .loc 1 217 0 - stp w1, w1, [x0, 20] -.L48: - .loc 1 252 0 - str w2, [x0, 28] -.L45: - .loc 1 264 0 - str w1, [x0, 32] - b .L15 + .loc 1 262 0 + stp x19, x20, [sp, 16] .LVL12: -.L8: - .loc 1 234 0 - add x0, x19, :lo12:.LANCHOR1 - .loc 1 235 0 - mov w1, 1 - .loc 1 240 0 - mov w2, 6 + stp x21, x22, [sp, 32] + str x23, [sp, 48] + .cfi_offset 19, -48 + .cfi_offset 20, -40 + .cfi_offset 21, -32 + .cfi_offset 22, -24 + .cfi_offset 23, -16 + .loc 1 267 0 + ldrb w3, [x2, 32] + add x0, x3, x0, sxtw + add x4, x2, x0 .LVL13: - .loc 1 234 0 - str wzr, [x19, #:lo12:.LANCHOR1] - .loc 1 235 0 - str w1, [x0, 4] - .loc 1 236 0 - mov w1, 7 - str w1, [x0, 8] - .loc 1 237 0 - mov w1, 3 - .loc 1 240 0 - str w2, [x0, 24] - .loc 1 238 0 - stp w1, w1, [x0, 12] - .loc 1 239 0 - mov w1, 5 - str w1, [x0, 20] -.L47: - .loc 1 252 0 - mov w2, 4 - b .L48 + .loc 1 268 0 + ldrb w3, [x2, x0] + ldrb w6, [x4, 1] + ldrb w5, [x4, 3] + ldrb w4, [x4, 2] .LVL14: -.L12: - .loc 1 245 0 - add x0, x19, :lo12:.LANCHOR1 - .loc 1 246 0 - mov w1, 1 - .loc 1 245 0 - str wzr, [x19, #:lo12:.LANCHOR1] - .loc 1 246 0 - str w1, [x0, 4] - .loc 1 247 0 - mov w1, 5 - str w1, [x0, 8] - .loc 1 248 0 - mov w1, 2 - str w1, [x0, 12] - .loc 1 249 0 - mov w1, 3 - .loc 1 250 0 - stp w1, w1, [x0, 16] - .loc 1 251 0 - str w1, [x0, 24] - b .L47 + add w3, w3, w6 + add w3, w3, w4 + cmp w5, w3, uxtb + beq .L7 + .loc 1 269 0 + mov w2, 269 .LVL15: -.L18: -.LBE44: -.LBE45: - .loc 1 303 0 - mov w0, 0 +.L41: + .loc 1 276 0 + adrp x1, .LANCHOR1 + adrp x0, .LC0 + add x1, x1, :lo12:.LANCHOR1 + add x0, x0, :lo12:.LC0 + bl printf .LVL16: -.L16: - .loc 1 328 0 - add x19, x19, :lo12:.LANCHOR1 - ldr w0, [x19, w0, sxtw 2] +.L40: +.LBB8: +.LBB9: + .loc 1 69 0 + mov w0, -22 +.L6: +.LBE9: +.LBE8: + .loc 1 283 0 + ldp x19, x20, [sp, 16] + ldp x21, x22, [sp, 32] + ldr x23, [sp, 48] + ldp x29, x30, [sp], 64 + .cfi_remember_state + .cfi_restore 30 + .cfi_restore 29 + .cfi_restore 23 + .cfi_restore 21 + .cfi_restore 22 + .cfi_restore 19 + .cfi_restore 20 + .cfi_def_cfa 31, 0 + ret .LVL17: - b .L1 +.L7: + .cfi_restore_state + .loc 1 272 0 + ldr w0, [x2, x0] .LVL18: -.L23: - .loc 1 309 0 - mov w0, 4 - .loc 1 310 0 - b .L16 + .loc 1 274 0 + lsl w1, w1, 2 .LVL19: -.L24: - .loc 1 312 0 - mov w0, 5 - .loc 1 313 0 - b .L16 + and x0, x0, 16777215 .LVL20: -.L25: - .loc 1 315 0 - mov w0, 6 - .loc 1 316 0 - b .L16 + add x1, x0, x1, sxtw + add x3, x2, x1 .LVL21: -.L20: - .loc 1 318 0 - mov w0, 2 - .loc 1 319 0 - b .L16 + .loc 1 275 0 + ldrb w0, [x2, x1] + ldrb w5, [x3, 1] + ldrb w4, [x3, 3] + ldrb w3, [x3, 2] .LVL22: -.L21: - .loc 1 321 0 - mov w0, 1 - .loc 1 322 0 - b .L16 + add w0, w0, w5 + add w0, w0, w3 + cmp w4, w0, uxtb + beq .L9 + .loc 1 276 0 + mov w2, 276 .LVL23: -.L17: - .loc 1 324 0 + b .L41 +.LVL24: +.L9: +.LBB13: +.LBB10: + .loc 1 67 0 + adrp x20, .LANCHOR2 +.LBE10: +.LBE13: + .loc 1 279 0 + ldr w8, [x2, x1] +.LBB14: +.LBB11: + .loc 1 67 0 + ldr x10, [x20, #:lo12:.LANCHOR2] +.LBE11: +.LBE14: + .loc 1 281 0 + and x8, x8, 16777215 + add x8, x2, x8 +.LVL25: +.LBB15: +.LBB12: + .loc 1 67 0 + cbnz x10, .L10 + .loc 1 68 0 adrp x0, .LC1 add x0, x0, :lo12:.LC1 bl printf -.LVL24: - .loc 1 325 0 - mov w0, -1 -.L1: - .loc 1 329 0 - ldp x19, x20, [sp, 16] - ldp x29, x30, [sp], 32 - .cfi_remember_state - .cfi_restore 30 - .cfi_restore 29 - .cfi_restore 19 - .cfi_restore 20 - .cfi_def_cfa 31, 0 - ret -.LVL25: -.L22: - .cfi_restore_state - .loc 1 300 0 - mov w0, 7 - b .L16 .LVL26: -.L29: - .loc 1 306 0 - mov w0, 3 - b .L16 - .cfi_endproc -.LFE215: - .size get_wf_mode_index, .-get_wf_mode_index - .section .text.get_lut_gray16_data,"ax",@progbits - .align 2 - .type get_lut_gray16_data, %function -get_lut_gray16_data: -.LFB224: - .loc 1 554 0 - .cfi_startproc + b .L40 .LVL27: - stp x29, x30, [sp, -48]! - .cfi_def_cfa_offset 48 - .cfi_offset 29, -48 - .cfi_offset 30, -40 - .loc 1 560 0 - mov x2, 19200 - .loc 1 554 0 - add x29, sp, 0 - .cfi_def_cfa_register 29 - stp x19, x20, [sp, 16] - .cfi_offset 19, -32 - .cfi_offset 20, -24 - .loc 1 560 0 - adrp x19, gray_data - .loc 1 554 0 - stp x21, x22, [sp, 32] - .cfi_offset 21, -16 - .cfi_offset 22, -8 - .loc 1 560 0 - add x21, x19, :lo12:gray_data - .loc 1 554 0 - mov x22, x0 - mov w20, w1 - .loc 1 560 0 - mov x0, x21 +.L10: + .loc 1 72 0 + adrp x21, .LANCHOR3 + ldr w12, [x21, #:lo12:.LANCHOR3] + cmp w12, 16 + bne .L28 + adrp x0, .LANCHOR4 + ldr w0, [x0, #:lo12:.LANCHOR4] + cmp w0, 32 + cset w13, eq +.L11: .LVL28: - mov w1, 0 + add w2, w13, 5 .LVL29: - bl memset + .loc 1 133 0 + mov w0, 0 + mov w1, 0 .LVL30: - adrp x0, waveformdata - add x0, x0, :lo12:waveformdata - mov x4, 0 + mov w14, 1 + mov w11, 0 + mov w19, 0 .LVL31: -.L51: - lsl w8, w4, 1 - .loc 1 554 0 - mov x3, 0 - b .L56 +.L12: + .loc 1 81 0 + ldrb w3, [x8, w11, uxtw] + cmp w3, 255 + beq .L13 + .loc 1 86 0 + cmp w3, 252 + bne .L14 + .loc 1 87 0 + eor w14, w14, 1 .LVL32: -.L52: -.LBB46: -.LBB47: - .loc 1 157 0 - lsl x2, x5, 10 - add x7, x21, x5, lsl 6 - add x5, x5, 1 + .loc 1 88 0 + add w11, w11, 1 .LVL33: -.LBE47: -.LBE46: - .loc 1 565 0 - ldrb w2, [x1, x2] - lsl w6, w2, w8 - ldr w2, [x7, x3] - orr w2, w2, w6 - str w2, [x7, x3] -.L54: +.L14: + uxtw x17, w11 + add w15, w11, 1 + lsl w6, w19, 10 + lsl w7, w0, w13 + add w5, w1, 1 + add w3, w1, 3 + add w4, w1, 2 + add w16, w1, 4 + .loc 1 91 0 + cbz w14, .L15 + .loc 1 93 0 + lsl w1, w1, w2 + add w1, w1, w6 + add w1, w1, w7 + add w6, w6, w7 + .loc 1 92 0 + ldrb w23, [x8, x17] .LVL34: - .loc 1 563 0 discriminator 1 - cmp w20, w5 - bgt .L52 - add x3, x3, 4 - .loc 1 562 0 discriminator 2 - cmp x3, 64 - beq .L53 + .loc 1 94 0 + lsl w5, w5, w2 + add w5, w5, w6 + .loc 1 95 0 + lsl w4, w4, w2 + add w4, w4, w6 + .loc 1 93 0 + and w17, w23, 3 + .loc 1 96 0 + lsl w3, w3, w2 + .loc 1 93 0 + strb w17, [x10, x1] + .loc 1 96 0 + add w6, w3, w6 + .loc 1 94 0 + ubfx x30, x23, 2, 2 + strb w30, [x10, x5] + .loc 1 95 0 + ubfx x22, x23, 4, 2 + strb w22, [x10, x4] + .loc 1 96 0 + lsr w5, w23, 6 + strb w5, [x10, x6] + mov w1, w16 .LVL35: -.L56: - add x1, x4, x3, lsl 3 - .loc 1 554 0 - mov x5, 0 - add x1, x1, x0 - b .L54 + .loc 1 99 0 + cmp w16, w12 + bcc .L16 .LVL36: -.L53: - add x4, x4, 1 + .loc 1 101 0 + add w0, w0, 1 .LVL37: - .loc 1 561 0 discriminator 2 - cmp x4, 16 - bne .L51 - .loc 1 570 0 - lsl w2, w20, 6 - add x1, x19, :lo12:gray_data - mov x0, x22 - sxtw x2, w2 - .loc 1 571 0 - ldp x19, x20, [sp, 16] + cmp w12, w0 + bhi .L29 .LVL38: - ldp x21, x22, [sp, 32] + .loc 1 103 0 + add w19, w19, 1 .LVL39: - ldp x29, x30, [sp], 48 - .cfi_restore 30 - .cfi_restore 29 - .cfi_restore 21 - .cfi_restore 22 - .cfi_restore 19 - .cfi_restore 20 - .cfi_def_cfa 31, 0 - .loc 1 570 0 - b memcpy + .loc 1 102 0 + mov w0, 0 .LVL40: - .cfi_endproc -.LFE224: - .size get_lut_gray16_data, .-get_lut_gray16_data - .section .text.get_lut_gray2_data,"ax",@progbits - .align 2 - .type get_lut_gray2_data, %function -get_lut_gray2_data: -.LFB222: - .loc 1 509 0 - .cfi_startproc +.L29: + .loc 1 100 0 + mov w1, 0 .LVL41: - stp x29, x30, [sp, -48]! - .cfi_def_cfa_offset 48 - .cfi_offset 29, -48 - .cfi_offset 30, -40 - .loc 1 514 0 - mov x2, 2400 - .loc 1 509 0 - add x29, sp, 0 - .cfi_def_cfa_register 29 - stp x19, x20, [sp, 16] - .cfi_offset 19, -32 - .cfi_offset 20, -24 - .loc 1 514 0 - adrp x20, .LANCHOR2 - add x19, x20, :lo12:.LANCHOR2 - .loc 1 509 0 - stp x21, x22, [sp, 32] - .cfi_offset 21, -16 - .cfi_offset 22, -8 - .loc 1 509 0 - mov x22, x0 - mov w21, w1 - .loc 1 514 0 - mov x0, x19 +.L16: + .loc 1 107 0 + ldrb w6, [x8, w15, uxtw] .LVL42: - mov w1, 0 +.L17: + .loc 1 108 0 + cbnz w6, .L19 + .loc 1 122 0 + add w11, w11, 2 .LVL43: - bl memset + b .L20 .LVL44: - adrp x3, waveformdata+15 - add x0, x19, 4 - add x3, x3, :lo12:waveformdata+15 - .loc 1 515 0 - mov w2, 0 +.L28: + .loc 1 72 0 + mov w13, 0 + b .L11 .LVL45: -.L59: - .loc 1 515 0 is_stmt 0 discriminator 1 - cmp w2, w21 - bge .L60 - ldr w1, [x0, -4] -.LBB48: -.LBB49: -.LBB50: - .loc 1 157 0 is_stmt 1 - sub x7, x3, #15 -.LBE50: -.LBE49: -.LBE48: - .loc 1 515 0 - mov x4, 0 -.L61: +.L19: + .loc 1 109 0 + lsl w4, w19, 10 + lsl w7, w1, w2 + add w7, w7, w4 + lsl w3, w0, w13 + add w7, w7, w3 + add w3, w4, w3 + add w4, w1, 1 + .loc 1 110 0 + lsl w4, w4, w2 + add w4, w4, w3 + .loc 1 109 0 + strb w17, [x10, x7] + .loc 1 110 0 + add w7, w1, 2 + strb w30, [x10, x4] + .loc 1 111 0 + add w4, w1, 3 .LVL46: -.LBB53: -.LBB52: -.LBB51: - .loc 1 157 0 - lsl x5, x4, 5 -.LBE51: -.LBE52: - .loc 1 520 0 - lsl w6, w4, 1 - add x4, x4, 1 + lsl w7, w7, w2 + add w7, w7, w3 + .loc 1 112 0 + lsl w4, w4, w2 .LVL47: -.LBE53: - .loc 1 517 0 - cmp x4, 16 -.LBB54: - .loc 1 520 0 - ldrb w5, [x7, x5] - lsl w5, w5, w6 - orr w1, w1, w5 -.LBE54: - .loc 1 517 0 - bne .L61 - ldr w4, [x0] - mov x6, x3 - str w1, [x0, -4] - mov w1, 0 -.L62: -.LBB55: - .loc 1 520 0 - ldrb w5, [x6], 32 - lsl w5, w5, w1 - add w1, w1, 2 - orr w4, w4, w5 -.LBE55: - .loc 1 517 0 - cmp w1, 32 - bne .L62 - str w4, [x0], 8 + add w3, w4, w3 + add w1, w1, 4 .LVL48: - .loc 1 515 0 discriminator 1 - add w2, w2, 1 + .loc 1 111 0 + strb w22, [x10, x7] .LVL49: - add x3, x3, 1024 - b .L59 + .loc 1 113 0 + cmp w12, w1 + .loc 1 112 0 + strb w5, [x10, x3] + .loc 1 113 0 + bhi .L18 .LVL50: -.L60: - .loc 1 525 0 - lsl w2, w21, 3 + .loc 1 115 0 + add w0, w0, 1 .LVL51: - add x1, x20, :lo12:.LANCHOR2 - mov x0, x22 - sxtw x2, w2 - .loc 1 526 0 - ldp x19, x20, [sp, 16] - ldp x21, x22, [sp, 32] + cmp w12, w0 + bhi .L30 .LVL52: - ldp x29, x30, [sp], 48 - .cfi_restore 30 - .cfi_restore 29 - .cfi_restore 21 - .cfi_restore 22 - .cfi_restore 19 - .cfi_restore 20 - .cfi_def_cfa 31, 0 - .loc 1 525 0 - b memcpy + .loc 1 117 0 + add w19, w19, 1 .LVL53: - .cfi_endproc -.LFE222: - .size get_lut_gray2_data, .-get_lut_gray2_data - .section .text.decodewaveform,"ax",@progbits - .align 2 - .global decodewaveform - .type decodewaveform, %function -decodewaveform: -.LFB212: - .loc 1 50 0 - .cfi_startproc + .loc 1 116 0 + mov w0, 0 .LVL54: - .loc 1 58 0 - cmp w1, 32 - ccmp w1, 16, 4, ne - beq .L69 - .loc 1 58 0 is_stmt 0 discriminator 1 - cmp w2, 32 - ccmp w2, 16, 4, ne - bne .L85 -.L69: - .loc 1 50 0 is_stmt 1 - stp x29, x30, [sp, -64]! - .cfi_def_cfa_offset 64 - .cfi_offset 29, -64 - .cfi_offset 30, -56 - add x29, sp, 0 - .cfi_def_cfa_register 29 - stp x21, x22, [sp, 32] - .cfi_offset 21, -32 - .cfi_offset 22, -24 - .loc 1 61 0 - adrp x22, waveformdata - .loc 1 50 0 - stp x23, x24, [sp, 48] - .cfi_offset 23, -16 - .cfi_offset 24, -8 - .loc 1 61 0 - add x24, x22, :lo12:waveformdata - .loc 1 50 0 - stp x19, x20, [sp, 16] - .cfi_offset 19, -48 - .cfi_offset 20, -40 - mov w21, w1 - mov w20, w2 - mov x23, x0 - .loc 1 61 0 - mov x2, 524288 -.LVL55: +.L30: + .loc 1 114 0 mov w1, 0 +.LVL55: +.L18: + .loc 1 108 0 + sub w6, w6, #1 .LVL56: - mov x0, x24 + and w6, w6, 255 .LVL57: - bl memset + b .L17 .LVL58: - .loc 1 118 0 - mov x5, x24 - .loc 1 56 0 - mov w10, 1 - .loc 1 53 0 - mov w0, 0 - .loc 1 52 0 - mov w19, 0 - .loc 1 51 0 - mov w3, 0 - mov w6, 0 +.L15: + .loc 1 126 0 + lsl w1, w1, w2 + add w1, w1, w6 + add w1, w1, w7 + add w6, w6, w7 + .loc 1 125 0 + ldrb w11, [x8, x17] .LVL59: -.L71: - .loc 1 69 0 - ldrb w1, [x23, w0, uxtw] - cmp w1, 255 - beq .L72 - .loc 1 74 0 - cmp w1, 252 - bne .L73 - .loc 1 75 0 - eor w10, w10, 1 + .loc 1 127 0 + lsl w5, w5, w2 + add w5, w5, w6 + .loc 1 128 0 + lsl w4, w4, w2 + add w4, w4, w6 + .loc 1 126 0 + and w17, w11, 3 + .loc 1 129 0 + lsl w3, w3, w2 + .loc 1 126 0 + strb w17, [x10, x1] + .loc 1 129 0 + add w6, w3, w6 + .loc 1 127 0 + ubfx x1, x11, 2, 2 + strb w1, [x10, x5] + .loc 1 128 0 + ubfx x1, x11, 4, 2 + strb w1, [x10, x4] + .loc 1 129 0 + lsr w3, w11, 6 + strb w3, [x10, x6] + mov w1, w16 .LVL60: - .loc 1 76 0 - add w0, w0, 1 + .loc 1 130 0 + mov w11, w15 .LVL61: -.L73: - uxtw x7, w3 - add w2, w3, 1 - add w12, w3, 3 - add w1, w3, 2 - uxtw x13, w0 - add w11, w0, 1 - uxtw x8, w6 - uxtw x4, w19 - add w3, w3, 4 - .loc 1 79 0 - cbz w10, .L74 - .loc 1 82 0 - lsl x4, x4, 5 - .loc 1 80 0 - ldrb w16, [x23, x13] + .loc 1 132 0 + cmp w16, w12 + bcc .L20 .LVL62: - .loc 1 82 0 - add x7, x4, x7 - .loc 1 83 0 - add x2, x4, x2, uxtw - .loc 1 82 0 - add x7, x5, x7, lsl 5 - .loc 1 83 0 - add x2, x5, x2, lsl 5 - .loc 1 82 0 - and w13, w16, 3 - .loc 1 83 0 - ubfx x14, x16, 2, 2 - .loc 1 84 0 - ubfx x15, x16, 4, 2 - .loc 1 89 0 - cmp w3, w21 - .loc 1 82 0 - strb w13, [x7, x8] - .loc 1 83 0 - strb w14, [x2, x8] + .loc 1 134 0 + add w0, w0, 1 .LVL63: - .loc 1 84 0 - add x2, x4, x1, uxtw - add x2, x5, x2, lsl 5 - .loc 1 85 0 - add x4, x4, x12, uxtw - add x4, x5, x4, lsl 5 - lsr w1, w16, 6 - .loc 1 84 0 - strb w15, [x2, x8] + cmp w12, w0 + bhi .L31 .LVL64: - .loc 1 85 0 - strb w1, [x4, x8] + .loc 1 136 0 + add w19, w19, 1 .LVL65: - .loc 1 89 0 - bcc .L75 + .loc 1 135 0 + mov w0, 0 .LVL66: - .loc 1 91 0 - add w6, w6, 1 +.L31: + .loc 1 133 0 + mov w1, 0 .LVL67: - cmp w21, w6 - bhi .L86 +.L20: + .loc 1 76 0 + cmp w19, 254 + bls .L12 + .loc 1 77 0 + adrp x0, .LC2 .LVL68: - .loc 1 93 0 - add w19, w19, 1 + add x0, x0, :lo12:.LC2 + bl printf .LVL69: - .loc 1 90 0 - mov w3, 0 - .loc 1 92 0 - mov w6, 0 +.L13: + .loc 1 142 0 + ldr w0, [x21, #:lo12:.LANCHOR3] + cmp w0, 32 + beq .L21 +.L22: + .loc 1 154 0 + mov w0, w19 + b .L6 +.L21: + .loc 1 142 0 + adrp x0, .LANCHOR4 + ldr w0, [x0, #:lo12:.LANCHOR4] + cmp w0, 16 + bne .L22 + .loc 1 147 0 + ldr x4, [x20, #:lo12:.LANCHOR2] + mov w0, 0 +.L23: .LVL70: -.L75: - .loc 1 97 0 - ldrb w4, [x23, w11, uxtw] + .loc 1 144 0 + cmp w0, w19 + bcs .L22 + .loc 1 147 0 + lsl w5, w0, 10 + mov w2, 0 +.L25: .LVL71: -.L76: - .loc 1 98 0 discriminator 1 - cbnz w4, .L78 - .loc 1 113 0 - add w0, w0, 2 + .loc 1 148 0 + lsr w3, w2, 1 + add w6, w5, w2, lsl 5 + add w3, w5, w3, lsl 5 + mov w1, 0 .LVL72: - b .L79 +.L24: + .loc 1 147 0 + add w7, w6, w1 + ldrb w8, [x4, x7] .LVL73: -.L88: - .loc 1 126 0 - mov w3, 0 + .loc 1 148 0 + add w7, w3, w1, lsr 1 + .loc 1 146 0 + add w1, w1, 2 .LVL74: -.L79: - .loc 1 64 0 - cmp w19, 511 - bls .L71 - .loc 1 65 0 - adrp x0, .LC2 + cmp w1, 32 + .loc 1 148 0 + strb w8, [x4, x7] + .loc 1 146 0 + bne .L24 + .loc 1 145 0 + add w2, w2, 2 .LVL75: - add x0, x0, :lo12:.LC2 - bl printf + cmp w2, 32 + bne .L25 + .loc 1 144 0 + add w0, w0, 1 .LVL76: -.L72: - .loc 1 135 0 - cmp w21, 32 - ccmp w20, 16, 0, eq - bne .L80 - add x22, x22, :lo12:waveformdata - mov w0, 0 -.L81: + and w0, w0, 255 .LVL77: - .loc 1 137 0 discriminator 1 - cmp w0, w19 - bcc .L89 + b .L23 +.LBE12: +.LBE15: + .cfi_endproc +.LFE219: + .size get_wf_frm_num, .-get_wf_frm_num + .section .text.get_wf_mode_index,"ax",@progbits + .align 2 + .type get_wf_mode_index, %function +get_wf_mode_index: +.LFB217: + .loc 1 217 0 + .cfi_startproc .LVL78: -.L80: - .loc 1 152 0 - mov w0, w19 - .loc 1 153 0 - ldp x19, x20, [sp, 16] + .loc 1 221 0 + cmp w0, 14 + bls .L43 + .loc 1 217 0 + stp x29, x30, [sp, -16]! + .cfi_def_cfa_offset 16 + .cfi_offset 29, -16 + .cfi_offset 30, -8 + .loc 1 222 0 + adrp x0, .LC3 .LVL79: - ldp x21, x22, [sp, 32] + add x0, x0, :lo12:.LC3 + .loc 1 217 0 + add x29, sp, 0 + .cfi_def_cfa_register 29 + .loc 1 222 0 + bl printf .LVL80: - ldp x23, x24, [sp, 48] -.LVL81: - ldp x29, x30, [sp], 64 - .cfi_remember_state + .loc 1 223 0 + mov w0, 255 + .loc 1 240 0 + ldp x29, x30, [sp], 16 .cfi_restore 30 .cfi_restore 29 - .cfi_restore 23 - .cfi_restore 24 - .cfi_restore 21 - .cfi_restore 22 - .cfi_restore 19 - .cfi_restore 20 .cfi_def_cfa 31, 0 ret +.LVL81: +.L43: +.LBB20: +.LBB21: + .loc 1 224 0 + cmp w0, 10 + beq .L59 + .loc 1 226 0 + cmp w0, 12 + beq .L60 + .loc 1 228 0 + cmp w0, 11 + beq .L61 + .loc 1 230 0 + cmp w0, 13 + beq .L62 + .loc 1 235 0 + cmp w0, 14 + mov w1, 3 + csel w0, w0, w1, ne .LVL82: -.L86: - .cfi_restore_state - .loc 1 90 0 - mov w3, 0 - b .L75 +.L45: + .loc 1 237 0 + adrp x1, .LANCHOR0 + ldr x1, [x1, #:lo12:.LANCHOR0] + ldrb w2, [x1, 16] .LVL83: -.L78: - .loc 1 99 0 - ubfiz x11, x19, 5, 32 - .loc 1 100 0 - add w8, w3, 1 - .loc 1 99 0 - add x7, x11, x3, uxtw - uxtw x2, w6 - add x7, x5, x7, lsl 5 - .loc 1 100 0 - add x8, x11, x8 - add x8, x5, x8, lsl 5 - .loc 1 99 0 - strb w13, [x7, x2] - .loc 1 101 0 - add w7, w3, 3 +.LBB22: +.LBB23: + .loc 1 195 0 + cmp w2, 32 + beq .L83 + bhi .L48 + cmp w2, 22 + beq .L49 + bhi .L50 + cmp w2, 9 + beq .L64 + cmp w2, 18 + beq .L52 +.L46: + .loc 1 206 0 + adrp x1, .LANCHOR6 .LVL84: - .loc 1 100 0 - strb w14, [x8, x2] - .loc 1 101 0 - add w8, w3, 2 - add x8, x11, x8 - .loc 1 102 0 - add x7, x11, x7, uxtw + add x1, x1, :lo12:.LANCHOR6 + ldrb w3, [x1, 9] + cmp w3, w2 + beq .L51 +.L83: + .loc 1 209 0 + adrp x1, .LANCHOR5 + add x1, x1, :lo12:.LANCHOR5 + add x1, x1, 72 + b .L51 .LVL85: - .loc 1 101 0 - add x8, x5, x8, lsl 5 - .loc 1 102 0 - add x7, x5, x7, lsl 5 - add w3, w3, 4 +.L59: +.LBE23: +.LBE22: + .loc 1 225 0 + mov w0, 3 .LVL86: - .loc 1 104 0 - cmp w21, w3 - .loc 1 101 0 - strb w15, [x8, x2] + b .L45 .LVL87: - .loc 1 102 0 - strb w1, [x7, x2] - .loc 1 104 0 - bhi .L77 +.L60: + .loc 1 227 0 + mov w0, 6 .LVL88: - .loc 1 106 0 - add w6, w6, 1 + b .L45 .LVL89: - cmp w21, w6 - bhi .L87 +.L61: + .loc 1 229 0 + mov w0, 5 .LVL90: - .loc 1 108 0 - add w19, w19, 1 + b .L45 .LVL91: - .loc 1 105 0 - mov w3, 0 - .loc 1 107 0 - mov w6, 0 +.L62: + .loc 1 231 0 + mov w0, 4 .LVL92: -.L77: - .loc 1 98 0 - sub w4, w4, #1 + b .L45 .LVL93: - and w4, w4, 255 +.L50: +.LBB26: +.LBB24: + .loc 1 195 0 + cmp w2, 24 + beq .L83 + cmp w2, 25 +.L82: + bne .L46 .LVL94: - b .L76 + .loc 1 199 0 + adrp x1, .LANCHOR5 .LVL95: -.L87: - .loc 1 105 0 - mov w3, 0 - b .L77 + add x1, x1, :lo12:.LANCHOR5 + add x1, x1, 27 + b .L51 .LVL96: -.L74: - .loc 1 118 0 - lsl x4, x4, 5 - .loc 1 116 0 - ldrb w0, [x23, x13] +.L48: + .loc 1 195 0 + cmp w2, 72 + beq .L54 + bhi .L55 + cmp w2, 35 + beq .L56 + cmp w2, 67 + b .L82 +.L55: + cmp w2, 84 + beq .L57 + cmp w2, 114 + bne .L46 .LVL97: - .loc 1 118 0 - add x7, x4, x7 - .loc 1 119 0 - add x2, x4, x2, uxtw - .loc 1 118 0 - add x7, x5, x7, lsl 5 - .loc 1 119 0 - add x2, x5, x2, lsl 5 - .loc 1 120 0 - add x1, x4, x1, uxtw - .loc 1 121 0 - add x4, x4, x12, uxtw - .loc 1 120 0 - add x1, x5, x1, lsl 5 - .loc 1 118 0 - and w13, w0, 3 - .loc 1 121 0 - add x4, x5, x4, lsl 5 - .loc 1 118 0 - strb w13, [x7, x8] - .loc 1 119 0 - ubfx x7, x0, 2, 2 - strb w7, [x2, x8] + .loc 1 203 0 + adrp x1, .LANCHOR5 .LVL98: - .loc 1 120 0 - ubfx x2, x0, 4, 2 - strb w2, [x1, x8] + add x1, x1, :lo12:.LANCHOR5 + add x1, x1, 63 + b .L51 .LVL99: - .loc 1 121 0 - lsr w0, w0, 6 +.L52: + .loc 1 197 0 + adrp x1, .LANCHOR5 .LVL100: - strb w0, [x4, x8] - .loc 1 125 0 - cmp w3, w21 - .loc 1 123 0 - mov w0, w11 + add x1, x1, :lo12:.LANCHOR5 + add x1, x1, 9 .LVL101: - .loc 1 125 0 - bcc .L79 +.L51: +.LBE24: +.LBE26: + .loc 1 239 0 + ldrb w0, [x1, w0, sxtw] .LVL102: - .loc 1 127 0 - add w6, w6, 1 + ret .LVL103: - cmp w21, w6 - bhi .L88 +.L49: +.LBB27: +.LBB25: + .loc 1 198 0 + adrp x1, .LANCHOR5 .LVL104: - .loc 1 129 0 - add w19, w19, 1 + add x1, x1, :lo12:.LANCHOR5 + add x1, x1, 18 + b .L51 .LVL105: - .loc 1 126 0 - mov w3, 0 - .loc 1 128 0 - mov w6, 0 - b .L79 +.L56: + .loc 1 200 0 + adrp x1, .LANCHOR5 .LVL106: -.L89: - .loc 1 145 0 - sbfiz x5, x0, 5, 32 - mov x2, 0 -.L84: + add x1, x1, :lo12:.LANCHOR5 + add x1, x1, 36 + b .L51 .LVL107: - and x1, x2, 2147483647 - add x4, x2, x0, uxtw 4 - add x1, x5, x1 - add x4, x22, x4, lsl 6 - add x1, x22, x1, lsl 5 - mov x3, 0 +.L54: + .loc 1 201 0 + adrp x1, .LANCHOR5 .LVL108: -.L82: - .loc 1 144 0 discriminator 3 - lsl x6, x3, 1 - ldrb w7, [x4, x6] + add x1, x1, :lo12:.LANCHOR5 + add x1, x1, 45 + b .L51 .LVL109: - .loc 1 145 0 discriminator 3 - and x6, x3, 2147483647 - add x3, x3, 1 +.L57: + .loc 1 202 0 + adrp x1, .LANCHOR5 .LVL110: - .loc 1 139 0 discriminator 3 - cmp x3, 16 - .loc 1 145 0 discriminator 3 - strb w7, [x1, x6] - .loc 1 139 0 discriminator 3 - bne .L82 + add x1, x1, :lo12:.LANCHOR5 + add x1, x1, 54 + b .L51 .LVL111: - add x2, x2, 1 +.L64: + .loc 1 196 0 + adrp x1, .LANCHOR5 .LVL112: - .loc 1 138 0 discriminator 2 - cmp x2, 16 - bne .L84 - .loc 1 137 0 discriminator 2 - add w0, w0, 1 -.LVL113: - and w0, w0, 255 -.LVL114: - b .L81 -.LVL115: -.L85: - .cfi_def_cfa 31, 0 - .cfi_restore 19 - .cfi_restore 20 - .cfi_restore 21 - .cfi_restore 22 - .cfi_restore 23 - .cfi_restore 24 - .cfi_restore 29 - .cfi_restore 30 - .loc 1 59 0 - mov w0, -22 -.LVL116: - ret + add x1, x1, :lo12:.LANCHOR5 + b .L51 +.LBE25: +.LBE27: +.LBE21: +.LBE20: .cfi_endproc -.LFE212: - .size decodewaveform, .-decodewaveform - .section .text.get_wf_frm_num,"ax",@progbits +.LFE217: + .size get_wf_mode_index, .-get_wf_mode_index + .section .text.pvi_wf_add_custom_mode_table,"ax",@progbits .align 2 - .type get_wf_frm_num, %function -get_wf_frm_num: -.LFB217: - .loc 1 352 0 + .global pvi_wf_add_custom_mode_table + .type pvi_wf_add_custom_mode_table, %function +pvi_wf_add_custom_mode_table: +.LFB215: + .loc 1 177 0 .cfi_startproc +.LVL113: + .loc 1 178 0 + cmp w1, 11 + bne .L88 +.LBB28: + .loc 1 182 0 discriminator 3 + adrp x1, .LANCHOR6 +.LVL114: + add x1, x1, :lo12:.LANCHOR6 +.LBE28: + mov x2, 0 +.L86: +.LVL115: +.LBB29: + add x3, x0, x2 + ldrb w3, [x3, 2] + strb w3, [x2, x1] +.LVL116: + add x2, x2, 1 .LVL117: - stp x29, x30, [sp, -16]! - .cfi_def_cfa_offset 16 - .cfi_offset 29, -16 - .cfi_offset 30, -8 - .loc 1 353 0 - adrp x3, .LANCHOR0 - .loc 1 352 0 - add x29, sp, 0 - .cfi_def_cfa_register 29 - .loc 1 353 0 - ldr x4, [x3, #:lo12:.LANCHOR0] + .loc 1 181 0 discriminator 3 + cmp x2, 9 + bne .L86 +.LBE29: + .loc 1 183 0 + ldrb w2, [x0] + strb w2, [x1, 9] + .loc 1 184 0 + ldrb w0, [x0, 1] .LVL118: - .loc 1 358 0 - ldrb w3, [x4, 32] - add w0, w3, w0, lsl 2 + cmp w0, 4 + bne .L87 + .loc 1 185 0 + mov w0, 16 +.L91: + .loc 1 187 0 + str w0, [x1, 12] +.L89: + .loc 1 189 0 + mov w0, 0 + .loc 1 190 0 + ret +.L87: + .loc 1 186 0 + cmp w0, 5 + bne .L89 + .loc 1 187 0 + mov w0, 32 + b .L91 .LVL119: - .loc 1 360 0 - sxtw x0, w0 - ldrb w7, [x4, x0] +.L88: + .loc 1 179 0 + mov w0, -1 .LVL120: - .loc 1 361 0 - add x0, x4, x0 + ret + .cfi_endproc +.LFE215: + .size pvi_wf_add_custom_mode_table, .-pvi_wf_add_custom_mode_table + .section .text.pvi_wf_get_lut,"ax",@progbits + .align 2 + .global pvi_wf_get_lut + .type pvi_wf_get_lut, %function +pvi_wf_get_lut: +.LFB226: + .loc 1 444 0 + .cfi_startproc .LVL121: - ldrb w5, [x0, 1] + .loc 1 453 0 + adrp x5, .LANCHOR0 + ldr x5, [x5, #:lo12:.LANCHOR0] + cbz x5, .L106 + .loc 1 456 0 + cbnz x0, .L94 + .loc 1 456 0 is_stmt 0 discriminator 1 + ldr x5, [x0, 16] + cbz x5, .L107 +.L94: + .loc 1 462 0 is_stmt 1 + adrp x5, .LANCHOR7 + mov w6, 3 + sdiv w7, w2, w6 + ldr w5, [x5, #:lo12:.LANCHOR7] + sdiv w5, w5, w6 + cmp w7, w5 + bne .L95 + .loc 1 462 0 is_stmt 0 discriminator 1 + adrp x5, .LANCHOR8 + ldr w5, [x5, #:lo12:.LANCHOR8] + cmp w5, w1 + bne .L95 + .loc 1 462 0 discriminator 2 + adrp x5, .LANCHOR9 + ldr w5, [x5, #:lo12:.LANCHOR9] + cmp w5, w4 + bne .L95 + .loc 1 463 0 is_stmt 1 + mov w0, 0 .LVL122: - .loc 1 362 0 - ldrb w6, [x0, 2] + .loc 1 529 0 + ret .LVL123: - .loc 1 363 0 - ldrb w3, [x0, 3] - .loc 1 364 0 - add w0, w5, w6 - add w0, w0, w7 - cmp w3, w0, uxtb - beq .L105 - .loc 1 365 0 - mov w2, 365 +.L95: + .loc 1 444 0 + stp x29, x30, [sp, -80]! + .cfi_def_cfa_offset 80 + .cfi_offset 29, -80 + .cfi_offset 30, -72 + .loc 1 468 0 + cmp w1, 10 + .loc 1 444 0 + add x29, sp, 0 + .cfi_def_cfa_register 29 + stp x23, x24, [sp, 48] + .cfi_offset 23, -32 + .cfi_offset 24, -24 + .loc 1 466 0 + adrp x24, .LANCHOR4 + .loc 1 444 0 + stp x19, x20, [sp, 16] + stp x21, x22, [sp, 32] + stp x25, x26, [sp, 64] + .cfi_offset 19, -64 + .cfi_offset 20, -56 + .cfi_offset 21, -48 + .cfi_offset 22, -40 + .cfi_offset 25, -16 + .cfi_offset 26, -8 + .loc 1 466 0 + str w3, [x24, #:lo12:.LANCHOR4] + .loc 1 468 0 + beq .L119 + .loc 1 470 0 + adrp x25, .LANCHOR2 + mov x19, x0 + ldr x0, [x0, 16] .LVL124: -.L129: - .loc 1 379 0 - adrp x1, .LANCHOR3 - adrp x0, .LC3 - add x1, x1, :lo12:.LANCHOR3 - add x0, x0, :lo12:.LC3 - bl printf + mov w21, w1 + mov w22, w4 + str x0, [x25, #:lo12:.LANCHOR2] + .loc 1 471 0 + mov w0, w2 + bl get_wf_temp_index .LVL125: -.L104: - .loc 1 403 0 - mov w0, -22 - ldp x29, x30, [sp], 16 - .cfi_remember_state - .cfi_restore 30 - .cfi_restore 29 - .cfi_def_cfa 31, 0 - ret + mov w20, w0 .LVL126: -.L105: - .cfi_restore_state - .loc 1 369 0 - lsl w3, w6, 16 - orr w3, w3, w5, lsl 8 - orr w3, w3, w7 + .loc 1 472 0 + mov w0, w21 .LVL127: - .loc 1 371 0 - add w3, w3, w1, lsl 2 + bl get_wf_mode_index .LVL128: - .loc 1 373 0 - sxtw x3, w3 - ldrb w6, [x4, x3] + .loc 1 473 0 + and w0, w0, 255 + mov w1, w20 + bl get_wf_frm_num .LVL129: - .loc 1 374 0 - add x3, x4, x3 + mov w23, w0 .LVL130: - ldrb w1, [x3, 1] + .loc 1 474 0 + tbz w0, #31, .L97 + .loc 1 475 0 + adrp x0, .LC4 .LVL131: - .loc 1 375 0 - ldrb w5, [x3, 2] + add x0, x0, :lo12:.LC4 + bl printf .LVL132: - .loc 1 376 0 - ldrb w0, [x3, 3] - .loc 1 378 0 - add w3, w1, w5 - add w3, w3, w6 - cmp w0, w3, uxtb - beq .L107 - .loc 1 379 0 - mov w2, 379 + .loc 1 476 0 + mov w0, -5 .LVL133: - b .L129 -.LVL134: -.L107: - .loc 1 383 0 - lsl w0, w5, 16 - orr w0, w0, w1, lsl 8 - .loc 1 385 0 - ldrb w1, [x4, 16] -.LVL135: - .loc 1 383 0 - orr w0, w0, w6 -.LVL136: - .loc 1 385 0 - cmp w1, 32 - beq .L109 - bhi .L110 - cmp w1, 22 - beq .L109 - bcc .L108 - sub w1, w1, #24 - cmp w1, 1 - bhi .L108 -.L109: - .loc 1 393 0 - mov w1, 32 -.LVL137: -.L130: - .loc 1 403 0 - ldp x29, x30, [sp], 16 +.L92: + .loc 1 529 0 + ldp x19, x20, [sp, 16] + ldp x21, x22, [sp, 32] + ldp x23, x24, [sp, 48] + ldp x25, x26, [sp, 64] + ldp x29, x30, [sp], 80 .cfi_remember_state .cfi_restore 30 .cfi_restore 29 + .cfi_restore 25 + .cfi_restore 26 + .cfi_restore 23 + .cfi_restore 24 + .cfi_restore 21 + .cfi_restore 22 + .cfi_restore 19 + .cfi_restore 20 .cfi_def_cfa 31, 0 - .loc 1 398 0 - add x0, x4, x0 + ret +.LVL134: +.L97: + .cfi_restore_state + .loc 1 491 0 + ldr x0, [x19, 8] +.LVL135: + cbz x0, .L98 +.LVL136: +.LBB49: +.LBB50: + .file 2 "include/linux/compat.h" + .loc 2 81 0 + bl free +.LVL137: +.LBE50: +.LBE49: + .loc 1 493 0 + str xzr, [x19, 8] +.L98: + .loc 1 495 0 + add w20, w23, 15 .LVL138: - b decodewaveform +.LBB51: +.LBB52: + .loc 2 58 0 + mov w1, 32768 +.LBE52: +.LBE51: + .loc 1 495 0 + asr w20, w20, 4 + lsl w20, w20, 10 + sxtw x20, w20 .LVL139: -.L110: - .cfi_restore_state - .loc 1 385 0 - cmp w1, 72 - beq .L109 - cmp w1, 114 - beq .L109 - cmp w1, 67 - beq .L109 -.L108: - .loc 1 396 0 - cmp w2, 32 - beq .L104 - .loc 1 398 0 - mov w2, 16 +.LBB55: +.LBB53: + .loc 2 58 0 + mov x0, x20 + bl kmalloc .LVL140: - mov w1, w2 - b .L130 - .cfi_endproc -.LFE217: - .size get_wf_frm_num, .-get_wf_frm_num - .section .text.parse_wf_gray16_with_lut_type,"ax",@progbits - .align 2 - .type parse_wf_gray16_with_lut_type, %function -parse_wf_gray16_with_lut_type: -.LFB229: - .loc 1 662 0 - .cfi_startproc +.LBE53: +.LBE55: + .loc 1 495 0 + str x0, [x19, 8] +.LBB56: +.LBB54: + .loc 2 58 0 + mov x26, x0 .LVL141: - stp x29, x30, [sp, -32]! - .cfi_def_cfa_offset 32 - .cfi_offset 29, -32 - .cfi_offset 30, -24 - add x29, sp, 0 - .cfi_def_cfa_register 29 - stp x19, x20, [sp, 16] - .cfi_offset 19, -16 - .cfi_offset 20, -8 - .loc 1 662 0 - mov x20, x0 - mov w19, w1 - .loc 1 666 0 - mov w0, w2 +.LBE54: +.LBE56: + .loc 1 496 0 + cbnz x0, .L99 + .loc 1 497 0 + adrp x0, .LC5 + add x0, x0, :lo12:.LC5 + bl printf .LVL142: - bl get_wf_mode_index + .loc 1 498 0 + mov w0, -12 + b .L92 +.L99: + .loc 1 500 0 + ldr x25, [x25, #:lo12:.LANCHOR2] .LVL143: - .loc 1 667 0 - mov w1, w19 - mov w2, 16 - bl get_wf_frm_num +.LBB57: +.LBB58: + .loc 1 421 0 + ldr w1, [x24, #:lo12:.LANCHOR4] + cmp w1, 16 + cset w24, ne .LVL144: - .loc 1 669 0 - str w0, [x20] - .loc 1 667 0 - mov w19, w0 + .loc 1 423 0 + cbnz x25, .L100 + .loc 1 424 0 + adrp x0, .LC6 .LVL145: - .loc 1 670 0 - lsl w0, w0, 6 + add x0, x0, :lo12:.LC6 + bl printf .LVL146: -.LBB56: -.LBB57: - .file 2 "include/linux/compat.h" - .loc 2 58 0 - mov w1, 32768 - sxtw x0, w0 +.L101: +.LBE58: +.LBE57: + .loc 1 503 0 + ldr w0, [x19] + and w0, w0, 65280 + .loc 1 504 0 + orr w23, w0, w23 .LVL147: - bl kmalloc + .loc 1 505 0 + adrp x0, .LANCHOR8 + .loc 1 504 0 + str w23, [x19] + .loc 1 505 0 + str w21, [x0, #:lo12:.LANCHOR8] + .loc 1 506 0 + adrp x0, .LANCHOR9 + str w22, [x0, #:lo12:.LANCHOR9] .LVL148: -.LBE57: -.LBE56: - .loc 1 670 0 - str x0, [x20, 8] - .loc 1 671 0 - cbz x0, .L133 - .loc 1 674 0 - mov w1, w19 - bl get_lut_gray16_data -.LVL149: - .loc 1 676 0 +.L119: + .loc 1 510 0 mov w0, 0 -.L131: - .loc 1 677 0 - ldp x19, x20, [sp, 16] + b .L92 +.LVL149: +.L100: +.LBB66: +.LBB65: + .loc 1 428 0 + mov x2, x20 + mov w1, 0 + bl memset .LVL150: - ldp x29, x30, [sp], 32 - .cfi_remember_state - .cfi_restore 30 - .cfi_restore 29 - .cfi_restore 19 - .cfi_restore 20 - .cfi_def_cfa 31, 0 - ret + mov w10, 32 + mov w11, 1 + lsl w10, w10, w24 +.LBB59: + .loc 1 430 0 + mov w2, 0 + lsl w11, w11, w24 +.LBB60: +.LBB61: + .loc 1 434 0 + mov w13, 16 .LVL151: -.L133: - .cfi_restore_state - .loc 1 672 0 - mov w0, -12 - b .L131 - .cfi_endproc -.LFE229: - .size parse_wf_gray16_with_lut_type, .-parse_wf_gray16_with_lut_type - .section .text.parse_wf_gray2,"ax",@progbits - .align 2 - .type parse_wf_gray2, %function -parse_wf_gray2: -.LFB226: - .loc 1 600 0 - .cfi_startproc +.L102: +.LBE61: +.LBE60: + .loc 1 430 0 + cmp w23, w2 + beq .L101 +.LBB64: +.LBB62: + .loc 1 434 0 + lsl w1, w2, 8 + .loc 1 433 0 + lsl w8, w2, 10 + sxtw x8, w8 + .loc 1 434 0 + mov w5, 0 + mov w7, 0 + sdiv w1, w1, w13 + sxtw x1, w1 + b .L105 +.L103: .LVL152: - stp x29, x30, [sp, -48]! - .cfi_def_cfa_offset 48 - .cfi_offset 29, -48 - .cfi_offset 30, -40 - add x29, sp, 0 - .cfi_def_cfa_register 29 - str x21, [sp, 32] - .cfi_offset 21, -16 - mov x21, x0 - stp x19, x20, [sp, 16] - .cfi_offset 19, -32 - .cfi_offset 20, -24 - .loc 1 605 0 - mov w0, 4 + .loc 1 433 0 + ldrb w4, [x3, w12, sxtw] + .loc 1 435 0 + and w14, w6, 30 + add w6, w6, 2 + add w12, w12, w11 .LVL153: - .loc 1 600 0 - mov w19, w1 - .loc 1 605 0 - bl get_wf_mode_index + and w4, w4, 3 + .loc 1 432 0 + cmp w6, 32 + .loc 1 435 0 + lsl w4, w4, w14 + ldr w14, [x0] + orr w4, w14, w4 + str w4, [x0] .LVL154: - .loc 1 606 0 - mov w1, w19 - mov w2, 16 - bl get_wf_frm_num + .loc 1 432 0 + bne .L103 .LVL155: - .loc 1 608 0 - str w0, [x21] - .loc 1 606 0 - mov w19, w0 + add w5, w5, 16 .LVL156: - .loc 1 609 0 - lsl w0, w0, 3 + add w7, w7, w10 +.LBE62: + .loc 1 431 0 + cmp w5, 256 + beq .L104 .LVL157: -.LBB66: -.LBB67: - .loc 2 58 0 - mov w1, 32768 - sxtw x0, w0 +.L105: +.LBB63: + .loc 1 434 0 + asr w0, w5, 4 + .loc 1 433 0 + add x3, x8, x7, sxtw + .loc 1 434 0 + add x0, x1, x0, sxtw + mov w6, 0 + add x0, x26, x0, lsl 2 + mov w12, 0 + .loc 1 433 0 + add x3, x25, x3 + b .L103 .LVL158: - bl kmalloc +.L104: +.LBE63: +.LBE64: + .loc 1 430 0 + add w2, w2, 1 .LVL159: -.LBE67: -.LBE66: - .loc 1 610 0 - cbz x0, .L141 - mov x20, x0 - .loc 1 613 0 - mov w1, w19 - bl get_lut_gray2_data + b .L102 .LVL160: - .loc 1 617 0 - str w19, [x21] -.LVL161: -.LBB68: -.LBB69: -.LBB70: -.LBB71: - .loc 2 58 0 - mov w1, 32768 - lsl w0, w19, 6 -.LVL162: - bl kmalloc -.LVL163: -.LBE71: -.LBE70: - .loc 1 450 0 - cbz x0, .L142 - mov x5, x0 - mov x4, x20 - mov w3, 0 -.LVL164: -.L138: - .loc 1 453 0 - cmp w19, w3 - bgt .L140 -.LVL165: -.L137: -.LBE69: -.LBE68: - .loc 1 618 0 - str x0, [x21, 8] -.LVL166: -.LBB73: -.LBB74: - .loc 2 81 0 - mov x0, x20 - bl free -.LVL167: -.LBE74: -.LBE73: - .loc 1 622 0 - mov w0, 0 -.L135: - .loc 1 623 0 - ldp x19, x20, [sp, 16] -.LVL168: - ldr x21, [sp, 32] -.LVL169: - ldp x29, x30, [sp], 48 - .cfi_remember_state - .cfi_restore 30 - .cfi_restore 29 - .cfi_restore 21 - .cfi_restore 19 - .cfi_restore 20 - .cfi_def_cfa 31, 0 - ret -.LVL170: -.L140: - .cfi_restore_state -.LBB75: -.LBB72: - .loc 1 454 0 - ldr w8, [x4], 8 -.LVL171: - .loc 1 455 0 - mov x2, 0 - ldr w7, [x4, -4] -.LVL172: -.L139: - lsl w1, w2, 1 -.LVL173: - .loc 1 458 0 - asr w6, w8, w1 - and w6, w6, 3 - .loc 1 459 0 - asr w1, w7, w1 -.LVL174: - .loc 1 460 0 - orr w1, w6, w1, lsl 30 - .loc 1 461 0 - str w1, [x5, x2, lsl 2] -.LVL175: - add x2, x2, 1 -.LVL176: - .loc 1 457 0 - cmp x2, 16 - bne .L139 - .loc 1 453 0 - add w3, w3, 1 -.LVL177: - add x5, x5, 64 - b .L138 -.LVL178: -.L142: - .loc 1 451 0 - mov x0, 0 - b .L137 -.LVL179: -.L141: -.LBE72: -.LBE75: - .loc 1 611 0 - mov w0, -12 - b .L135 - .cfi_endproc -.LFE226: - .size parse_wf_gray2, .-parse_wf_gray2 - .section .text.pvi_wf_get_lut,"ax",@progbits - .align 2 - .global pvi_wf_get_lut - .type pvi_wf_get_lut, %function -pvi_wf_get_lut: -.LFB232: - .loc 1 739 0 - .cfi_startproc -.LVL180: - .loc 1 745 0 - adrp x3, .LANCHOR0 - ldr x4, [x3, #:lo12:.LANCHOR0] - cbz x4, .L189 - .loc 1 748 0 - cbz x0, .L190 - .loc 1 752 0 - adrp x3, .LANCHOR4 - ldr w5, [x3, #:lo12:.LANCHOR4] - cmp w5, w2 - adrp x5, .LANCHOR5 - bne .L147 - .loc 1 752 0 is_stmt 0 discriminator 1 - ldr w6, [x5, #:lo12:.LANCHOR5] - cmp w6, w1 - beq .L191 -.L147: - .loc 1 739 0 is_stmt 1 - stp x29, x30, [sp, -80]! - .cfi_def_cfa_offset 80 - .cfi_offset 29, -80 - .cfi_offset 30, -72 - add x29, sp, 0 - .cfi_def_cfa_register 29 - stp x19, x20, [sp, 16] - stp x21, x22, [sp, 32] - stp x23, x24, [sp, 48] - str x25, [sp, 64] - .cfi_offset 19, -64 - .cfi_offset 20, -56 - .cfi_offset 21, -48 - .cfi_offset 22, -40 - .cfi_offset 23, -32 - .cfi_offset 24, -24 - .cfi_offset 25, -16 - .loc 1 755 0 - str w2, [x3, #:lo12:.LANCHOR4] -.LBB121: -.LBB122: - .loc 1 334 0 - mov x3, 0 - ldrb w20, [x4, 38] -.LBE122: -.LBE121: - .loc 1 756 0 - str w1, [x5, #:lo12:.LANCHOR5] -.LVL181: -.L148: - mov w5, w3 -.LVL182: -.LBB125: -.LBB123: - .loc 1 338 0 - cmp w20, w3 - bgt .L150 - .loc 1 345 0 - cmp w20, w3 - bne .L192 - .loc 1 346 0 - sub w20, w20, #1 -.LVL183: - b .L149 -.LVL184: -.L150: - .loc 1 339 0 - add x6, x4, x3 - add x3, x3, 1 -.LVL185: - ldrb w6, [x6, 48] - cmp w2, w6 - bge .L148 - .loc 1 340 0 - sub w20, w5, #1 -.LVL186: -.L149: - mov x19, x0 -.LVL187: -.LBE123: -.LBE125: - .loc 1 761 0 - ldr x0, [x0, 8] -.LVL188: - mov w21, w1 - cbz x0, .L151 -.LVL189: -.LBB126: -.LBB127: - .loc 2 81 0 - bl free -.LVL190: -.LBE127: -.LBE126: - .loc 1 763 0 - str xzr, [x19, 8] -.L151: - .loc 1 767 0 - sub w1, w21, #1 - cmp w1, 11 - bhi .L175 - adrp x0, .L153 - add x0, x0, :lo12:.L153 - ldrh w0, [x0,w1,uxtw #1] - adr x1, .Lrtx153 - add x0, x1, w0, sxth #2 - br x0 -.Lrtx153: - .section .rodata.pvi_wf_get_lut,"a",@progbits - .align 0 - .align 2 -.L153: - .2byte (.L152 - .Lrtx153) / 4 - .2byte (.L154 - .Lrtx153) / 4 - .2byte (.L155 - .Lrtx153) / 4 - .2byte (.L219 - .Lrtx153) / 4 - .2byte (.L157 - .Lrtx153) / 4 - .2byte (.L158 - .Lrtx153) / 4 - .2byte (.L159 - .Lrtx153) / 4 - .2byte (.L160 - .Lrtx153) / 4 - .2byte (.L161 - .Lrtx153) / 4 - .2byte (.L162 - .Lrtx153) / 4 - .2byte (.L163 - .Lrtx153) / 4 - .2byte (.L164 - .Lrtx153) / 4 - .section .text.pvi_wf_get_lut -.LVL191: -.L192: -.LBB128: -.LBB124: - .loc 1 335 0 - mov w20, -1 -.LVL192: - b .L149 -.LVL193: -.L152: -.LBE124: -.LBE128: -.LBB129: -.LBB130: - .loc 1 579 0 - mov w0, 1 - bl get_wf_mode_index -.LVL194: - .loc 1 580 0 - mov w1, w20 - mov w2, 16 - bl get_wf_frm_num -.LVL195: - .loc 1 582 0 - add w21, w0, 3 -.LVL196: - mov w20, 4 -.LVL197: - .loc 1 580 0 - mov w22, w0 -.LVL198: -.LBB131: -.LBB132: - .loc 2 58 0 - mov w1, 32768 -.LBE132: -.LBE131: - .loc 1 582 0 - sdiv w20, w21, w20 - sxtw x20, w20 -.LVL199: -.LBB134: -.LBB133: - .loc 2 58 0 - mov x0, x20 -.LVL200: - bl kmalloc -.LVL201: - mov x24, x0 -.LVL202: -.LBE133: -.LBE134: - .loc 1 583 0 - cbz x0, .L175 -.LVL203: -.LBB135: -.LBB136: - .loc 1 499 0 - adrp x25, .LANCHOR6 - add x23, x25, :lo12:.LANCHOR6 - mov x2, 1200 - mov w1, 0 - mov x0, x23 -.LVL204: - bl memset -.LVL205: -.LBB137: -.LBB138: - .loc 1 157 0 - adrp x4, waveformdata - add x4, x4, :lo12:waveformdata -.LBE138: -.LBE137: - .loc 1 499 0 - mov x3, 0 - .loc 1 502 0 - mov w5, 16 -.LVL206: -.L166: - mov w2, w3 -.LVL207: - .loc 1 500 0 - cmp w22, w3 - bgt .L167 - .loc 1 505 0 - mov x2, x20 -.LVL208: - add x1, x25, :lo12:.LANCHOR6 - mov x0, x24 - bl memcpy -.LVL209: -.LBE136: -.LBE135: - .loc 1 590 0 - str w22, [x19] -.LVL210: -.LBB142: -.LBB143: - .loc 1 413 0 - lsr w21, w21, 2 -.LVL211: -.LBB144: -.LBB145: - .loc 2 58 0 - mov w1, 32768 - lsl w0, w22, 10 - bl kmalloc -.LVL212: -.LBE145: -.LBE144: - .loc 1 417 0 - cbz x0, .L194 - mov x2, 0 -.LVL213: -.L169: - .loc 1 420 0 - cmp w21, w2 - bgt .L173 -.LVL214: -.L168: -.LBE143: -.LBE142: - .loc 1 592 0 - str x0, [x19, 8] -.LVL215: -.LBB148: -.LBB149: - .loc 2 81 0 - mov x0, x24 -.LVL216: -.L222: -.LBE149: -.LBE148: -.LBE130: -.LBE129: -.LBB153: -.LBB154: -.LBB155: -.LBB156: - bl free -.LVL217: - b .L218 -.LVL218: -.L167: -.LBE156: -.LBE155: -.LBE154: -.LBE153: -.LBB176: -.LBB152: -.LBB150: -.LBB141: - .loc 1 502 0 - sdiv w1, w3, w5 -.LBB140: -.LBB139: - .loc 1 157 0 - lsl x0, x3, 10 -.LBE139: -.LBE140: - .loc 1 502 0 - negs w2, w2 -.LVL219: - and w6, w3, 15 - and w2, w2, 15 - add x3, x3, 1 -.LVL220: - ldrb w0, [x0, x4] - csneg w2, w6, w2, mi - sxtw x1, w1 - lsl w2, w2, 1 - lsl w2, w0, w2 - ldr w0, [x23, x1, lsl 2] - orr w2, w2, w0 - str w2, [x23, x1, lsl 2] - b .L166 -.LVL221: -.L173: -.LBE141: -.LBE150: -.LBB151: -.LBB147: - .loc 1 421 0 - ldr w6, [x24, x2, lsl 2] -.LVL222: - lsl x7, x2, 8 - mov x3, 0 -.LVL223: -.L172: -.LBB146: - .loc 1 423 0 - lsl w1, w3, 1 - mov w4, 0 - asr w1, w6, w1 - and w1, w1, 3 -.LVL224: - .loc 1 424 0 - mov w5, w1 -.LVL225: -.L170: - .loc 1 427 0 - lsl w8, w1, w4 - add w4, w4, 2 - orr w5, w5, w8 -.LVL226: - .loc 1 426 0 - cmp w4, 32 - bne .L170 - add x4, x7, x3, lsl 4 - mov x1, 0 -.LVL227: - add x4, x0, x4, lsl 2 -.LVL228: -.L171: - .loc 1 430 0 - str w5, [x4, x1, lsl 2] -.LVL229: - add x1, x1, 1 -.LVL230: - .loc 1 429 0 - cmp x1, 16 - bne .L171 -.LVL231: - add x3, x3, 1 -.LVL232: -.LBE146: - .loc 1 422 0 - cmp x3, 16 - bne .L172 -.LVL233: - add x2, x2, 1 -.LVL234: - b .L169 -.LVL235: -.L194: - .loc 1 418 0 - mov x0, 0 - b .L168 -.LVL236: -.L154: -.LBE147: -.LBE151: -.LBE152: -.LBE176: -.LBB177: -.LBB178: - .loc 1 648 0 - mov w0, 2 - bl get_wf_mode_index -.LVL237: - .loc 1 649 0 - mov w1, w20 - mov w2, 16 - bl get_wf_frm_num -.LVL238: - mov w20, w0 -.LVL239: - .loc 1 651 0 - str w20, [x19] -.LVL240: - .loc 1 652 0 - lsl w0, w0, 6 -.LVL241: -.LBB179: -.LBB180: - .loc 2 58 0 - mov w1, 32768 - sxtw x0, w0 -.LVL242: - bl kmalloc -.LVL243: -.LBE180: -.LBE179: - .loc 1 652 0 - str x0, [x19, 8] - .loc 1 653 0 - cbnz x0, .L174 -.LVL244: -.L175: -.LBE178: -.LBE177: - .loc 1 823 0 - mov w0, -1 - b .L145 -.LVL245: -.L174: -.LBB182: -.LBB181: - .loc 1 656 0 - mov w1, w20 -.LVL246: -.L223: -.LBE181: -.LBE182: -.LBB183: -.LBB184: - .loc 1 695 0 - bl get_lut_gray16_data -.LVL247: - b .L218 -.LVL248: -.L159: -.LBE184: -.LBE183: - .loc 1 781 0 - mov w2, 7 -.L221: - .loc 1 805 0 - mov w1, w20 - mov x0, x19 - bl parse_wf_gray16_with_lut_type -.LVL249: -.L220: - .loc 1 828 0 - cmp w0, 0 - csetm w0, ne -.LVL250: -.L145: - .loc 1 841 0 - ldp x19, x20, [sp, 16] - ldp x21, x22, [sp, 32] - ldp x23, x24, [sp, 48] - ldr x25, [sp, 64] - ldp x29, x30, [sp], 80 - .cfi_remember_state - .cfi_restore 30 - .cfi_restore 29 - .cfi_restore 25 - .cfi_restore 23 - .cfi_restore 24 - .cfi_restore 21 - .cfi_restore 22 - .cfi_restore 19 - .cfi_restore 20 - .cfi_def_cfa 31, 0 - ret -.LVL251: -.L160: - .cfi_restore_state - .loc 1 787 0 - mov w2, 8 - b .L221 -.L161: - .loc 1 793 0 - mov w2, 9 - b .L221 -.L162: - .loc 1 799 0 - mov w2, 10 - b .L221 -.L163: - .loc 1 805 0 - mov w2, 11 - b .L221 -.L155: - .loc 1 811 0 - adrp x0, .LC4 - add x0, x0, :lo12:.LC4 - bl printf -.LVL252: -.L218: - .loc 1 840 0 - mov w0, 0 - b .L145 -.LVL253: -.L157: -.LBB188: -.LBB173: - .loc 1 707 0 - mov w0, 5 - bl get_wf_mode_index -.LVL254: - .loc 1 708 0 - mov w2, 16 - mov w1, w20 - bl get_wf_frm_num -.LVL255: - mov w21, w0 -.LVL256: - .loc 1 710 0 - str w21, [x19] -.LVL257: - .loc 1 711 0 - lsl w0, w0, 6 -.LVL258: -.LBB158: -.LBB159: - .loc 2 58 0 - mov w1, 32768 - sxtw x0, w0 -.LVL259: - bl kmalloc -.LVL260: -.LBE159: -.LBE158: - .loc 1 711 0 - str x0, [x19, 8] - .loc 1 712 0 - cbz x0, .L175 - .loc 1 715 0 - mov w1, w21 - bl get_lut_gray16_data -.LVL261: - .loc 1 718 0 - mov w0, 4 - bl get_wf_mode_index -.LVL262: - .loc 1 719 0 - mov w1, w20 - mov w2, 16 - bl get_wf_frm_num -.LVL263: - mov w20, w0 -.LVL264: - .loc 1 722 0 - ldr w0, [x19] -.LVL265: -.LBB160: -.LBB161: - .loc 2 58 0 - mov w1, 32768 -.LBE161: -.LBE160: - .loc 1 722 0 - orr w0, w0, w20, lsl 8 - str w0, [x19] -.LVL266: - .loc 1 724 0 - lsl w0, w20, 3 -.LBB163: -.LBB162: - .loc 2 58 0 - sxtw x0, w0 -.LVL267: - bl kmalloc -.LVL268: - mov x21, x0 -.LVL269: -.LBE162: -.LBE163: - .loc 1 725 0 - cbz x0, .L175 - .loc 1 728 0 - mov w1, w20 - bl get_lut_gray2_data -.LVL270: - mov x0, 4 - ldr x3, [x19, 8] -.LVL271: - add x20, x0, x20, uxtw 3 -.LVL272: - add x2, x21, 4 - add x20, x21, x20 -.LVL273: -.L176: -.LBB164: -.LBB165: - .loc 1 480 0 - cmp x2, x20 - bne .L178 -.LVL274: -.LBE165: -.LBE164: -.LBB169: -.LBB157: - .loc 2 81 0 - mov x0, x21 - b .L222 -.LVL275: -.L178: -.LBE157: -.LBE169: -.LBB170: -.LBB166: - .loc 1 482 0 - ldp w7, w6, [x2, -4] -.LVL276: - mov x1, 0 -.LVL277: -.L177: - .loc 1 484 0 - ldr w0, [x3, x1, lsl 2] -.LVL278: - .loc 1 485 0 - and w4, w0, 1073741820 -.LVL279: - lsl w0, w1, 1 -.LVL280: - .loc 1 486 0 - asr w5, w7, w0 - and w5, w5, 3 - .loc 1 487 0 - asr w0, w6, w0 -.LVL281: - .loc 1 486 0 - orr w0, w5, w0, lsl 30 - orr w0, w0, w4 - .loc 1 488 0 - str w0, [x3, x1, lsl 2] -.LVL282: - add x1, x1, 1 -.LVL283: - .loc 1 483 0 - cmp x1, 16 - bne .L177 - add x3, x3, 64 -.LVL284: - add x2, x2, 8 -.LVL285: - b .L176 -.LVL286: -.L158: -.LBE166: -.LBE170: -.LBE173: -.LBE188: -.LBB189: -.LBB187: - .loc 1 684 0 - mov w0, 6 - bl get_wf_mode_index -.LVL287: - .loc 1 685 0 - mov w2, 16 - mov w1, w20 - bl get_wf_frm_num -.LVL288: - mov w21, w0 -.LVL289: - .loc 1 687 0 - cmp w0, 0 - bgt .L179 -.LVL290: -.L219: - .loc 1 688 0 - mov w1, w20 - mov x0, x19 - bl parse_wf_gray2 -.LVL291: - b .L220 -.LVL292: -.L179: - .loc 1 690 0 - str w21, [x19] -.LVL293: - .loc 1 691 0 - lsl w0, w0, 6 -.LVL294: -.LBB185: -.LBB186: - .loc 2 58 0 - mov w1, 32768 - sxtw x0, w0 - bl kmalloc -.LVL295: -.LBE186: -.LBE185: - .loc 1 691 0 - str x0, [x19, 8] - .loc 1 692 0 - cbz x0, .L175 - .loc 1 695 0 - mov w1, w21 - b .L223 -.LVL296: -.L164: -.LBE187: -.LBE189: -.LBB190: -.LBB191: - .loc 1 630 0 - mov w0, 7 - bl get_wf_mode_index -.LVL297: - .loc 1 631 0 - mov w1, w20 - mov w2, 32 - bl get_wf_frm_num -.LVL298: - mov w23, w0 -.LVL299: - .loc 1 634 0 - lsl w20, w0, 8 -.LVL300: - .loc 1 633 0 - str w23, [x19] - .loc 1 634 0 - sxtw x20, w20 -.LVL301: -.LBB192: -.LBB193: - .loc 2 58 0 - mov w1, 32768 - mov x0, x20 -.LVL302: - bl kmalloc -.LVL303: -.LBE193: -.LBE192: - .loc 1 634 0 - str x0, [x19, 8] -.LBB195: -.LBB194: - .loc 2 58 0 - mov x22, x0 -.LVL304: -.LBE194: -.LBE195: - .loc 1 635 0 - cbz x0, .L175 -.LVL305: -.LBB196: -.LBB197: - .loc 1 535 0 - adrp x21, gray32_data -.LVL306: - mov x2, 11264 - add x19, x21, :lo12:gray32_data -.LVL307: - mov w1, 0 - movk x2, 0x1, lsl 16 - mov x0, x19 -.LVL308: - bl memset -.LVL309: - adrp x5, waveformdata - add x5, x5, :lo12:waveformdata - mov w1, -32 - mov x3, 0 -.LVL310: -.L181: - lsl w12, w3, 1 -.LBE197: -.LBE196: -.LBE191: -.LBE190: -.LBB208: -.LBB174: -.LBB171: -.LBB167: - .loc 1 482 0 - mov x2, 0 - b .L188 -.LVL311: -.L184: -.LBE167: -.LBE171: -.LBE174: -.LBE208: -.LBB209: -.LBB206: -.LBB204: -.LBB202: -.LBB198: -.LBB199: - .loc 1 157 0 - lsl x4, x0, 2 - add x11, x0, x19 -.LBE199: -.LBE198: - .loc 1 540 0 - cmp x3, 15 -.LBB201: -.LBB200: - .loc 1 157 0 - ldrb w4, [x7, x4] -.LVL312: -.LBE200: -.LBE201: - .loc 1 540 0 - bhi .L182 - .loc 1 541 0 - ldr w8, [x11, x2] - lsl w4, w4, w12 - orr w4, w8, w4 - str w4, [x11, x2] -.L183: - .loc 1 538 0 - add w6, w6, 1 -.LVL313: - add x0, x0, 256 -.LVL314: -.L186: - cmp w23, w6 - bgt .L184 - add x2, x2, 8 - .loc 1 537 0 - cmp x2, 256 - beq .L185 -.LVL315: -.L188: - add x7, x3, x2, lsl 2 -.LBE202: -.LBE204: -.LBE206: -.LBE209: -.LBB210: -.LBB175: -.LBB172: -.LBB168: - .loc 1 482 0 - mov x0, 0 - add x7, x7, x5 - mov w6, 0 - add x10, x2, 4 - b .L186 -.LVL316: -.L182: -.LBE168: -.LBE172: -.LBE175: -.LBE210: -.LBB211: -.LBB207: -.LBB205: -.LBB203: - .loc 1 544 0 - ldr w8, [x11, x10] - lsl w4, w4, w1 - orr w4, w8, w4 - str w4, [x11, x10] - b .L183 -.L185: -.LVL317: - add x3, x3, 1 -.LVL318: - add w1, w1, 2 - .loc 1 536 0 - cmp x3, 32 - bne .L181 - .loc 1 550 0 - mov x2, x20 - add x1, x21, :lo12:gray32_data - mov x0, x22 - bl memcpy -.LVL319: - b .L218 -.LVL320: -.L189: +.L106: .cfi_def_cfa 31, 0 .cfi_restore 19 .cfi_restore 20 @@ -2369,158 +1132,203 @@ pvi_wf_get_lut: .cfi_restore 23 .cfi_restore 24 .cfi_restore 25 + .cfi_restore 26 .cfi_restore 29 .cfi_restore 30 -.LBE203: -.LBE205: -.LBE207: -.LBE211: - .loc 1 746 0 +.LBE59: +.LBE65: +.LBE66: + .loc 1 454 0 mov w0, -19 -.LVL321: +.LVL161: ret -.LVL322: -.L190: - .loc 1 749 0 +.LVL162: +.L107: + .loc 1 457 0 mov w0, -22 -.LVL323: - ret -.LVL324: -.L191: - .loc 1 753 0 - mov w0, 0 -.LVL325: +.LVL163: ret .cfi_endproc -.LFE232: +.LFE226: .size pvi_wf_get_lut, .-pvi_wf_get_lut .section .text.pvi_wf_input,"ax",@progbits .align 2 .global pvi_wf_input .type pvi_wf_input, %function pvi_wf_input: -.LFB233: - .loc 1 851 0 +.LFB227: + .loc 1 538 0 .cfi_startproc -.LVL326: - .loc 1 854 0 +.LVL164: + .loc 1 541 0 adrp x1, .LANCHOR0 - ldr x3, [x1, #:lo12:.LANCHOR0] - cbnz x3, .L231 - mov x2, x1 - .loc 1 858 0 + ldr x2, [x1, #:lo12:.LANCHOR0] + cbnz x2, .L129 + .loc 1 538 0 + stp x29, x30, [sp, -32]! + .cfi_def_cfa_offset 32 + .cfi_offset 29, -32 + .cfi_offset 30, -24 + add x29, sp, 0 + .cfi_def_cfa_register 29 + stp x19, x20, [sp, 16] + .cfi_offset 19, -16 + .cfi_offset 20, -8 + mov x20, x1 + mov x19, x0 + .loc 1 544 0 ldrb w1, [x0, 16] + adrp x0, .LC7 +.LVL165: + add x0, x0, :lo12:.LC7 + bl printf +.LVL166: + .loc 1 547 0 + ldrb w1, [x19, 16] cmp w1, 32 - beq .L227 - bhi .L228 + beq .L123 + bhi .L124 cmp w1, 22 - beq .L227 - bhi .L229 + beq .L123 + bhi .L125 cmp w1, 9 - beq .L227 + beq .L126 cmp w1, 18 -.L263: - bne .L226 -.L227: - .loc 1 877 0 - str x0, [x2, #:lo12:.LANCHOR0] - .loc 1 879 0 + beq .L126 +.L122: + .loc 1 563 0 + adrp x0, .LANCHOR6 + add x0, x0, :lo12:.LANCHOR6 + ldrb w2, [x0, 9] + cmp w2, w1 + bne .L128 + .loc 1 564 0 + ldr w1, [x0, 12] + b .L163 +.L125: + .loc 1 547 0 + sub w0, w1, #24 + cmp w0, 1 + bhi .L122 +.L123: + .loc 1 555 0 + mov w1, 32 +.L163: + .loc 1 564 0 + adrp x0, .LANCHOR3 + str w1, [x0, #:lo12:.LANCHOR3] +.L126: + .loc 1 573 0 + str x19, [x20, #:lo12:.LANCHOR0] + .loc 1 575 0 mov w0, 0 -.LVL327: - ret -.LVL328: -.L229: - .loc 1 858 0 - sub w3, w1, #24 - cmp w3, 1 - bls .L227 -.L226: - .loc 1 851 0 - stp x29, x30, [sp, -16]! - .cfi_def_cfa_offset 16 - .cfi_offset 29, -16 - .cfi_offset 30, -8 - add x29, sp, 0 - .cfi_def_cfa_register 29 - .loc 1 872 0 - ldrb w2, [x0, 22] - adrp x0, .LC5 -.LVL329: - add x0, x0, :lo12:.LC5 + b .L120 +.L124: + .loc 1 547 0 + cmp w1, 72 + beq .L123 + bhi .L127 + cmp w1, 35 + beq .L126 + cmp w1, 67 +.L162: + bne .L122 + b .L123 +.L127: + cmp w1, 84 + beq .L126 + cmp w1, 114 + b .L162 +.L128: + .loc 1 566 0 + ldrb w2, [x19, 22] + adrp x0, .LC8 + add x0, x0, :lo12:.LC8 bl printf -.LVL330: - .loc 1 874 0 +.LVL167: + .loc 1 568 0 mov w0, -8 - .loc 1 880 0 - ldp x29, x30, [sp], 16 +.L120: + .loc 1 576 0 + ldp x19, x20, [sp, 16] +.LVL168: + ldp x29, x30, [sp], 32 .cfi_restore 30 .cfi_restore 29 + .cfi_restore 19 + .cfi_restore 20 .cfi_def_cfa 31, 0 ret -.LVL331: -.L228: - .loc 1 858 0 - cmp w1, 72 - beq .L227 - bhi .L230 - cmp w1, 35 - beq .L227 - cmp w1, 67 - b .L263 -.L230: - cmp w1, 84 - beq .L227 - cmp w1, 114 - b .L263 -.L231: - .loc 1 855 0 +.LVL169: +.L129: + .loc 1 542 0 mov w0, -16 -.LVL332: +.LVL170: ret .cfi_endproc -.LFE233: +.LFE227: .size pvi_wf_input, .-pvi_wf_input .section .text.pvi_wf_get_version,"ax",@progbits .align 2 .global pvi_wf_get_version .type pvi_wf_get_version, %function pvi_wf_get_version: -.LFB234: - .loc 1 890 0 +.LFB228: + .loc 1 585 0 .cfi_startproc - .loc 1 891 0 + .loc 1 586 0 adrp x0, .LANCHOR0 ldr x2, [x0, #:lo12:.LANCHOR0] -.LVL333: - .loc 1 895 0 - cbz x2, .L268 - .loc 1 899 0 discriminator 3 - adrp x0, .LANCHOR7 - add x0, x0, :lo12:.LANCHOR7 +.LVL171: + .loc 1 589 0 + cbz x2, .L167 +.LBB67: + .loc 1 593 0 discriminator 3 + adrp x0, .LANCHOR10 + add x0, x0, :lo12:.LANCHOR10 +.LBE67: mov x1, 0 -.L267: -.LVL334: +.L166: +.LVL172: +.LBB68: add x3, x2, x1 ldrb w3, [x3, 65] strb w3, [x1, x0] -.LVL335: +.LVL173: add x1, x1, 1 -.LVL336: - .loc 1 898 0 discriminator 3 +.LVL174: + .loc 1 592 0 discriminator 3 cmp x1, 31 - bne .L267 - .loc 1 901 0 + bne .L166 +.LBE68: + .loc 1 595 0 strb wzr, [x0, 31] - .loc 1 903 0 + .loc 1 597 0 ret -.L268: - .loc 1 896 0 - mov x0, 0 - .loc 1 904 0 +.L167: + .loc 1 590 0 + mov x0, 0 + .loc 1 598 0 ret .cfi_endproc -.LFE234: +.LFE228: .size pvi_wf_get_version, .-pvi_wf_get_version + .global custom_mode_table + .global pvi_mode_table + .section .bss.custom_mode_table,"aw",@nobits + .align 3 + .set .LANCHOR6,. + 0 + .type custom_mode_table, %object + .size custom_mode_table, 16 +custom_mode_table: + .zero 16 + .section .bss.fix.6288,"aw",@nobits + .align 2 + .set .LANCHOR9,. + 0 + .type fix.6288, %object + .size fix.6288, 4 +fix.6288: + .zero 4 .section .bss.global_waveform,"aw",@nobits .align 3 .set .LANCHOR0,. + 0 @@ -2528,95 +1336,169 @@ pvi_wf_get_version: .size global_waveform, 8 global_waveform: .zero 8 - .section .bss.gray32_data,"aw",@nobits - .align 3 - .type gray32_data, %object - .size gray32_data, 76800 -gray32_data: - .zero 76800 - .section .bss.gray_2_data,"aw",@nobits - .align 3 - .set .LANCHOR2,. + 0 - .type gray_2_data, %object - .size gray_2_data, 2400 -gray_2_data: - .zero 2400 - .section .bss.gray_data,"aw",@nobits - .align 3 - .type gray_data, %object - .size gray_data, 19200 -gray_data: - .zero 19200 - .section .bss.pvi_modes.6055,"aw",@nobits - .align 3 - .set .LANCHOR1,. + 0 - .type pvi_modes.6055, %object - .size pvi_modes.6055, 36 -pvi_modes.6055: - .zero 36 - .section .bss.reset_data,"aw",@nobits + .section .bss.spi_id_buffer.6314,"aw",@nobits .align 3 - .set .LANCHOR6,. + 0 - .type reset_data, %object - .size reset_data, 1200 -reset_data: - .zero 1200 - .section .bss.spi_id_buffer.6330,"aw",@nobits - .align 3 - .set .LANCHOR7,. + 0 - .type spi_id_buffer.6330, %object - .size spi_id_buffer.6330, 32 -spi_id_buffer.6330: + .set .LANCHOR10,. + 0 + .type spi_id_buffer.6314, %object + .size spi_id_buffer.6314, 32 +spi_id_buffer.6314: .zero 32 .section .bss.waveformdata,"aw",@nobits .align 3 + .set .LANCHOR2,. + 0 .type waveformdata, %object - .size waveformdata, 524288 + .size waveformdata, 8 waveformdata: - .zero 524288 - .section .data.sftemp.6292,"aw",@progbits + .zero 8 + .section .data.maxpic,"aw",@progbits + .align 2 + .set .LANCHOR3,. + 0 + .type maxpic, %object + .size maxpic, 4 +maxpic: + .word 16 + .section .data.need_pic,"aw",@progbits .align 2 .set .LANCHOR4,. + 0 - .type sftemp.6292, %object - .size sftemp.6292, 4 -sftemp.6292: + .type need_pic, %object + .size need_pic, 4 +need_pic: + .word 16 + .section .data.sftemp.6287,"aw",@progbits + .align 2 + .set .LANCHOR7,. + 0 + .type sftemp.6287, %object + .size sftemp.6287, 4 +sftemp.6287: .word -1 - .section .data.stype.6291,"aw",@progbits + .section .data.stype.6286,"aw",@progbits .align 2 - .set .LANCHOR5,. + 0 - .type stype.6291, %object - .size stype.6291, 4 -stype.6291: - .word 13 - .section .rodata.__func__.6107,"a",@progbits + .set .LANCHOR8,. + 0 + .type stype.6286, %object + .size stype.6286, 4 +stype.6286: + .word 15 + .section .rodata.__func__.6207,"a",@progbits .align 3 - .set .LANCHOR3,. + 0 - .type __func__.6107, %object - .size __func__.6107, 15 -__func__.6107: + .set .LANCHOR1,. + 0 + .type __func__.6207, %object + .size __func__.6207, 15 +__func__.6207: .string "get_wf_frm_num" - .section .rodata.decodewaveform.str1.1,"aMS",@progbits,1 -.LC2: - .string "pvi: decodec waveform 19 error\n" .section .rodata.get_wf_frm_num.str1.1,"aMS",@progbits,1 -.LC3: - .string "pvi: %s %d check error\n" - .section .rodata.get_wf_mode_index.str1.1,"aMS",@progbits,1 .LC0: - .string "pvi : Unknow waveform version %x,%x\n" + .string "pvi: %s %d check error\n" .LC1: + .string "waveformdata is NULL\n" +.LC2: + .string "pvi: decodec waveform error, framenum err\n" + .section .rodata.get_wf_mode_index.str1.1,"aMS",@progbits,1 +.LC3: .string "pvi: unspport PVI waveform type" + .section .rodata.pvi_mode_table,"a",@progbits + .align 3 + .set .LANCHOR5,. + 0 + .type pvi_mode_table, %object + .size pvi_mode_table, 81 +pvi_mode_table: + .byte 0 + .byte 1 + .byte 1 + .byte 2 + .byte 3 + .byte 3 + .byte 3 + .byte 4 + .byte 3 + .byte 0 + .byte 1 + .byte 7 + .byte 3 + .byte 3 + .byte 5 + .byte 6 + .byte 4 + .byte 5 + .byte 0 + .byte 1 + .byte 1 + .byte 2 + .byte 3 + .byte 4 + .byte 4 + .byte 6 + .byte 5 + .byte 0 + .byte 1 + .byte 7 + .byte 2 + .byte 3 + .byte 4 + .byte 5 + .byte 6 + .byte 4 + .byte 0 + .byte 1 + .byte 5 + .byte 2 + .byte 3 + .byte 3 + .byte 3 + .byte 4 + .byte 3 + .byte 0 + .byte 1 + .byte 1 + .byte 2 + .byte 3 + .byte 4 + .byte 4 + .byte 6 + .byte 4 + .byte 0 + .byte 1 + .byte 1 + .byte 2 + .byte 3 + .byte 4 + .byte 4 + .byte 5 + .byte 4 + .byte 0 + .byte 1 + .byte 1 + .byte 2 + .byte 3 + .byte 4 + .byte 11 + .byte 6 + .byte 10 + .byte 0 + .byte 1 + .byte 1 + .byte 2 + .byte 3 + .byte 4 + .byte 5 + .byte 6 + .byte 4 .section .rodata.pvi_wf_get_lut.str1.1,"aMS",@progbits,1 .LC4: - .string "pvi: unsupport WF GRAY4n" - .section .rodata.pvi_wf_input.str1.1,"aMS",@progbits,1 + .string "pvi waveform get frame number failed\n" .LC5: - .string "pvi : Unknow waveform version %x,%x, may be wrong waveform file\n" + .string "kzalloc output->data failed\n" +.LC6: + .string "wf_table or lut_data is NULL\n" + .section .rodata.pvi_wf_input.str1.1,"aMS",@progbits,1 +.LC7: + .string "pvi : input waveform version 0x%x\n" +.LC8: + .string "pvi : Unknow waveform version 0x%x, 0x%x, may be wrong waveform file\n" .text .Letext0: .file 3 "include/common.h" - .file 4 "./arch/arm/include/asm/types.h" - .file 5 "./arch/arm/include/asm/posix_types.h" + .file 4 "/home/hzb/sdk/u-boot/arch/arm/include/asm/types.h" + .file 5 "/home/hzb/sdk/u-boot/arch/arm/include/asm/posix_types.h" .file 6 "include/linux/types.h" .file 7 "include/errno.h" .file 8 "include/linux/string.h" @@ -2626,29 +1508,27 @@ __func__.6107: .file 12 "include/flash.h" .file 13 "include/lmb.h" .file 14 "include/asm-generic/u-boot.h" - .file 15 "./arch/arm/include/asm/u-boot-arm.h" + .file 15 "/home/hzb/sdk/u-boot/arch/arm/include/asm/u-boot-arm.h" .file 16 "include/linux/libfdt_env.h" .file 17 "include/linux/../../scripts/dtc/libfdt/fdt.h" .file 18 "include/linux/libfdt.h" .file 19 "include/image.h" .file 20 "include/net.h" - .file 21 "include/dm/uclass-id.h" - .file 22 "include/malloc.h" - .file 23 "drivers/video/rk_eink/epdlut/epd_lut.h" - .file 24 "include/stdio.h" - .file 25 "include/log.h" + .file 21 "include/malloc.h" + .file 22 "/home/hzb/sdk/ebc-dev/rk_eink/../epdlut/epd_lut.h" + .file 23 "include/stdio.h" .section .debug_info,"",@progbits .Ldebug_info0: - .4byte 0x2756 + .4byte 0x1792 .2byte 0x4 .4byte .Ldebug_abbrev0 .byte 0x8 .uleb128 0x1 - .4byte .LASF413 + .4byte .LASF284 .byte 0xc - .4byte .LASF414 - .4byte .LASF415 - .4byte .Ldebug_ranges0+0x450 + .4byte .LASF285 + .4byte .LASF286 + .4byte .Ldebug_ranges0+0x1d0 .8byte 0 .4byte .Ldebug_line0 .uleb128 0x2 @@ -2677,8 +1557,6 @@ __func__.6107: .byte 0x4 .byte 0x5 .string "int" - .uleb128 0x6 - .4byte 0x54 .uleb128 0x3 .byte 0x1 .byte 0x6 @@ -2696,7 +1574,7 @@ __func__.6107: .4byte .LASF7 .byte 0x4 .byte 0x12 - .4byte 0x84 + .4byte 0x7f .uleb128 0x3 .byte 0x4 .byte 0x7 @@ -2709,51 +1587,51 @@ __func__.6107: .byte 0x8 .byte 0x7 .4byte .LASF10 - .uleb128 0x7 + .uleb128 0x6 .string "u8" .byte 0x4 .byte 0x1f .4byte 0x34 - .uleb128 0x6 - .4byte 0x99 .uleb128 0x7 + .4byte 0x94 + .uleb128 0x6 .string "u16" .byte 0x4 .byte 0x22 .4byte 0x42 - .uleb128 0x7 + .uleb128 0x6 .string "u32" .byte 0x4 .byte 0x25 - .4byte 0x84 - .uleb128 0x7 + .4byte 0x7f + .uleb128 0x6 .string "u64" .byte 0x4 .byte 0x28 - .4byte 0x92 + .4byte 0x8d .uleb128 0x2 .4byte .LASF11 .byte 0x4 .byte 0x31 - .4byte 0x92 + .4byte 0x8d .uleb128 0x2 .4byte .LASF12 .byte 0x4 .byte 0x32 - .4byte 0x92 + .4byte 0x8d .uleb128 0x3 .byte 0x8 .byte 0x7 .4byte .LASF13 .uleb128 0x8 .byte 0x8 - .4byte 0xf3 + .4byte 0xee .uleb128 0x3 .byte 0x1 .byte 0x8 .4byte .LASF14 - .uleb128 0x6 - .4byte 0xec + .uleb128 0x7 + .4byte 0xe7 .uleb128 0x3 .byte 0x8 .byte 0x5 @@ -2765,12 +1643,12 @@ __func__.6107: .4byte 0x3b .uleb128 0x8 .byte 0x8 - .4byte 0xec + .4byte 0xe7 .uleb128 0x2 .4byte .LASF17 .byte 0x6 .byte 0x35 - .4byte 0xff + .4byte 0xfa .uleb128 0x2 .4byte .LASF18 .byte 0x6 @@ -2785,67 +1663,67 @@ __func__.6107: .4byte .LASF20 .byte 0x6 .byte 0x69 - .4byte 0x67 + .4byte 0x62 .uleb128 0x2 .4byte .LASF21 .byte 0x6 .byte 0x97 - .4byte 0x79 + .4byte 0x74 .uleb128 0x2 .4byte .LASF22 .byte 0x6 .byte 0x9f - .4byte 0x84 + .4byte 0x7f .uleb128 0x9 .byte 0x8 .uleb128 0x4 .4byte .LASF24 .byte 0x8 .byte 0xb - .4byte 0x10a + .4byte 0x105 .uleb128 0x3 .byte 0x1 .byte 0x2 .4byte .LASF25 .uleb128 0xa - .4byte 0xec - .4byte 0x171 + .4byte 0xe7 + .4byte 0x16c .uleb128 0xb .byte 0 .uleb128 0xc .4byte .LASF26 .byte 0x9 .2byte 0x140 - .4byte 0x166 + .4byte 0x161 .uleb128 0xc .4byte .LASF27 .byte 0x9 .2byte 0x143 - .4byte 0x166 + .4byte 0x161 .uleb128 0xc .4byte .LASF28 .byte 0x9 .2byte 0x143 - .4byte 0x166 + .4byte 0x161 .uleb128 0x8 .byte 0x8 - .4byte 0x19b + .4byte 0x196 .uleb128 0xd .uleb128 0xa - .4byte 0x126 - .4byte 0x1a7 + .4byte 0x121 + .4byte 0x1a2 .uleb128 0xb .byte 0 .uleb128 0x4 .4byte .LASF29 .byte 0xa .byte 0x10 - .4byte 0x19c + .4byte 0x197 .uleb128 0xa .4byte 0x34 - .4byte 0x1c2 + .4byte 0x1bd .uleb128 0xe - .4byte 0xdf + .4byte 0xda .byte 0x5 .byte 0 .uleb128 0xf @@ -2853,25 +1731,25 @@ __func__.6107: .byte 0x10 .byte 0xb .byte 0xf - .4byte 0x1e7 + .4byte 0x1e2 .uleb128 0x10 .4byte .LASF30 .byte 0xb .byte 0x10 - .4byte 0x10a + .4byte 0x105 .byte 0 .uleb128 0x10 .4byte .LASF31 .byte 0xb .byte 0x11 - .4byte 0x200 + .4byte 0x1fb .byte 0x8 .byte 0 - .uleb128 0x6 - .4byte 0x1c2 + .uleb128 0x7 + .4byte 0x1bd .uleb128 0x11 .4byte 0x54 - .4byte 0x200 + .4byte 0x1fb .uleb128 0x12 .4byte 0x54 .uleb128 0x12 @@ -2879,95 +1757,95 @@ __func__.6107: .byte 0 .uleb128 0x8 .byte 0x8 - .4byte 0x1ec - .uleb128 0xa .4byte 0x1e7 - .4byte 0x211 + .uleb128 0xa + .4byte 0x1e2 + .4byte 0x20c .uleb128 0xb .byte 0 - .uleb128 0x6 - .4byte 0x206 + .uleb128 0x7 + .4byte 0x201 .uleb128 0x4 .4byte .LASF32 .byte 0xb .byte 0xe1 - .4byte 0x211 + .4byte 0x20c .uleb128 0x13 .2byte 0x1220 .byte 0xc .byte 0x13 - .4byte 0x275 + .4byte 0x270 .uleb128 0x10 .4byte .LASF33 .byte 0xc .byte 0x14 - .4byte 0x126 + .4byte 0x121 .byte 0 .uleb128 0x10 .4byte .LASF34 .byte 0xc .byte 0x15 - .4byte 0x11b + .4byte 0x116 .byte 0x8 .uleb128 0x10 .4byte .LASF35 .byte 0xc .byte 0x16 - .4byte 0x126 + .4byte 0x121 .byte 0x10 .uleb128 0x10 .4byte .LASF36 .byte 0xc .byte 0x17 - .4byte 0x275 + .4byte 0x270 .byte 0x18 .uleb128 0x14 .4byte .LASF37 .byte 0xc .byte 0x18 - .4byte 0x286 + .4byte 0x281 .2byte 0x1018 .uleb128 0x15 .string "mtd" .byte 0xc .byte 0x31 - .4byte 0x29c + .4byte 0x297 .2byte 0x1218 .byte 0 .uleb128 0xa - .4byte 0x126 - .4byte 0x286 + .4byte 0x121 + .4byte 0x281 .uleb128 0x16 - .4byte 0xdf + .4byte 0xda .2byte 0x1ff .byte 0 .uleb128 0xa .4byte 0x29 - .4byte 0x297 + .4byte 0x292 .uleb128 0x16 - .4byte 0xdf + .4byte 0xda .2byte 0x1ff .byte 0 .uleb128 0x17 - .4byte .LASF416 + .4byte .LASF287 .uleb128 0x8 .byte 0x8 - .4byte 0x297 + .4byte 0x292 .uleb128 0x2 .4byte .LASF38 .byte 0xc .byte 0x37 - .4byte 0x221 + .4byte 0x21c .uleb128 0xa - .4byte 0x2a2 - .4byte 0x2b8 + .4byte 0x29d + .4byte 0x2b3 .uleb128 0xb .byte 0 .uleb128 0x4 .4byte .LASF39 .byte 0xc .byte 0x39 - .4byte 0x2ad + .4byte 0x2a8 .uleb128 0x3 .byte 0x10 .byte 0x4 @@ -2977,18 +1855,18 @@ __func__.6107: .byte 0x10 .byte 0xd .byte 0x10 - .4byte 0x2ef + .4byte 0x2ea .uleb128 0x10 .4byte .LASF42 .byte 0xd .byte 0x11 - .4byte 0xc9 + .4byte 0xc4 .byte 0 .uleb128 0x10 .4byte .LASF33 .byte 0xd .byte 0x12 - .4byte 0xd4 + .4byte 0xcf .byte 0x8 .byte 0 .uleb128 0x18 @@ -2996,7 +1874,7 @@ __func__.6107: .2byte 0x120 .byte 0xd .byte 0x15 - .4byte 0x321 + .4byte 0x31c .uleb128 0x19 .string "cnt" .byte 0xd @@ -3007,20 +1885,20 @@ __func__.6107: .4byte .LASF33 .byte 0xd .byte 0x17 - .4byte 0xd4 + .4byte 0xcf .byte 0x8 .uleb128 0x10 .4byte .LASF44 .byte 0xd .byte 0x18 - .4byte 0x321 + .4byte 0x31c .byte 0x10 .byte 0 .uleb128 0xa - .4byte 0x2ca - .4byte 0x331 + .4byte 0x2c5 + .4byte 0x32c .uleb128 0xe - .4byte 0xdf + .4byte 0xda .byte 0x10 .byte 0 .uleb128 0x1a @@ -3028,49 +1906,49 @@ __func__.6107: .2byte 0x240 .byte 0xd .byte 0x1b - .4byte 0x358 + .4byte 0x353 .uleb128 0x10 .4byte .LASF45 .byte 0xd .byte 0x1c - .4byte 0x2ef + .4byte 0x2ea .byte 0 .uleb128 0x14 .4byte .LASF46 .byte 0xd .byte 0x1d - .4byte 0x2ef + .4byte 0x2ea .2byte 0x120 .byte 0 .uleb128 0x1b .string "lmb" .byte 0xd .byte 0x20 - .4byte 0x331 + .4byte 0x32c .uleb128 0x1c .byte 0x10 .byte 0xe - .byte 0x5d - .4byte 0x384 + .byte 0x5b + .4byte 0x37f .uleb128 0x10 .4byte .LASF36 .byte 0xe - .byte 0x5e - .4byte 0xbe + .byte 0x5c + .4byte 0xb9 .byte 0 .uleb128 0x10 .4byte .LASF33 .byte 0xe - .byte 0x5f - .4byte 0xbe + .byte 0x5d + .4byte 0xb9 .byte 0x8 .byte 0 .uleb128 0x18 .4byte .LASF47 - .2byte 0x150 + .2byte 0x148 .byte 0xe .byte 0x1b - .4byte 0x482 + .4byte 0x471 .uleb128 0x10 .4byte .LASF48 .byte 0xe @@ -3081,7 +1959,7 @@ __func__.6107: .4byte .LASF49 .byte 0xe .byte 0x1d - .4byte 0xd4 + .4byte 0xcf .byte 0x8 .uleb128 0x10 .4byte .LASF50 @@ -3147,7 +2025,7 @@ __func__.6107: .4byte .LASF60 .byte 0xe .byte 0x33 - .4byte 0x1b2 + .4byte 0x1ad .byte 0x60 .uleb128 0x10 .4byte .LASF61 @@ -3171,412 +2049,406 @@ __func__.6107: .4byte .LASF64 .byte 0xe .byte 0x57 - .4byte 0x126 + .4byte 0x121 .byte 0x78 .uleb128 0x10 .4byte .LASF65 .byte 0xe .byte 0x58 - .4byte 0x126 + .4byte 0x121 .byte 0x80 .uleb128 0x10 .4byte .LASF66 .byte 0xe - .byte 0x5b - .4byte 0x84 + .byte 0x5e + .4byte 0x471 .byte 0x88 - .uleb128 0x10 - .4byte .LASF67 - .byte 0xe - .byte 0x60 - .4byte 0x482 - .byte 0x90 .byte 0 .uleb128 0xa - .4byte 0x363 - .4byte 0x492 + .4byte 0x35e + .4byte 0x481 .uleb128 0xe - .4byte 0xdf + .4byte 0xda .byte 0xb .byte 0 .uleb128 0x2 - .4byte .LASF68 + .4byte .LASF67 .byte 0xe - .byte 0x62 - .4byte 0x384 + .byte 0x60 + .4byte 0x37f .uleb128 0x4 - .4byte .LASF69 + .4byte .LASF68 .byte 0xf .byte 0x13 - .4byte 0x126 + .4byte 0x121 .uleb128 0x4 - .4byte .LASF70 + .4byte .LASF69 .byte 0xf .byte 0x14 - .4byte 0x126 + .4byte 0x121 .uleb128 0x4 - .4byte .LASF71 + .4byte .LASF70 .byte 0xf .byte 0x15 - .4byte 0x126 + .4byte 0x121 .uleb128 0x4 - .4byte .LASF72 + .4byte .LASF71 .byte 0xf .byte 0x16 - .4byte 0x126 + .4byte 0x121 .uleb128 0x4 - .4byte .LASF73 + .4byte .LASF72 .byte 0xf .byte 0x17 - .4byte 0x126 + .4byte 0x121 .uleb128 0x4 - .4byte .LASF74 + .4byte .LASF73 .byte 0xf .byte 0x18 - .4byte 0x126 + .4byte 0x121 .uleb128 0x4 - .4byte .LASF75 + .4byte .LASF74 .byte 0xf .byte 0x19 - .4byte 0x126 + .4byte 0x121 .uleb128 0x8 .byte 0x8 .4byte 0x34 .uleb128 0x2 - .4byte .LASF76 + .4byte .LASF75 .byte 0x10 .byte 0x11 - .4byte 0x13c + .4byte 0x137 .uleb128 0xf - .4byte .LASF77 + .4byte .LASF76 .byte 0x28 .byte 0x11 .byte 0x39 - .4byte 0x580 + .4byte 0x56f .uleb128 0x10 - .4byte .LASF78 + .4byte .LASF77 .byte 0x11 .byte 0x3a - .4byte 0x4f0 + .4byte 0x4df .byte 0 .uleb128 0x10 - .4byte .LASF79 + .4byte .LASF78 .byte 0x11 .byte 0x3b - .4byte 0x4f0 + .4byte 0x4df .byte 0x4 .uleb128 0x10 - .4byte .LASF80 + .4byte .LASF79 .byte 0x11 .byte 0x3c - .4byte 0x4f0 + .4byte 0x4df .byte 0x8 .uleb128 0x10 - .4byte .LASF81 + .4byte .LASF80 .byte 0x11 .byte 0x3d - .4byte 0x4f0 + .4byte 0x4df .byte 0xc .uleb128 0x10 - .4byte .LASF82 + .4byte .LASF81 .byte 0x11 .byte 0x3e - .4byte 0x4f0 + .4byte 0x4df .byte 0x10 .uleb128 0x10 - .4byte .LASF83 + .4byte .LASF82 .byte 0x11 .byte 0x3f - .4byte 0x4f0 + .4byte 0x4df .byte 0x14 .uleb128 0x10 - .4byte .LASF84 + .4byte .LASF83 .byte 0x11 .byte 0x40 - .4byte 0x4f0 + .4byte 0x4df .byte 0x18 .uleb128 0x10 - .4byte .LASF85 + .4byte .LASF84 .byte 0x11 .byte 0x43 - .4byte 0x4f0 + .4byte 0x4df .byte 0x1c .uleb128 0x10 - .4byte .LASF86 + .4byte .LASF85 .byte 0x11 .byte 0x46 - .4byte 0x4f0 + .4byte 0x4df .byte 0x20 .uleb128 0x10 - .4byte .LASF87 + .4byte .LASF86 .byte 0x11 .byte 0x49 - .4byte 0x4f0 + .4byte 0x4df .byte 0x24 .byte 0 .uleb128 0xc - .4byte .LASF88 + .4byte .LASF87 .byte 0x12 .2byte 0x136 - .4byte 0x58c + .4byte 0x57b .uleb128 0x8 .byte 0x8 - .4byte 0x4fb + .4byte 0x4ea .uleb128 0x1d - .4byte .LASF89 + .4byte .LASF88 .byte 0x40 .byte 0x13 .2byte 0x137 - .4byte 0x63c + .4byte 0x62b .uleb128 0x1e - .4byte .LASF90 + .4byte .LASF89 .byte 0x13 .2byte 0x138 - .4byte 0x13c + .4byte 0x137 .byte 0 .uleb128 0x1e - .4byte .LASF91 + .4byte .LASF90 .byte 0x13 .2byte 0x139 - .4byte 0x13c + .4byte 0x137 .byte 0x4 .uleb128 0x1e - .4byte .LASF92 + .4byte .LASF91 .byte 0x13 .2byte 0x13a - .4byte 0x13c + .4byte 0x137 .byte 0x8 .uleb128 0x1e - .4byte .LASF93 + .4byte .LASF92 .byte 0x13 .2byte 0x13b - .4byte 0x13c + .4byte 0x137 .byte 0xc .uleb128 0x1e - .4byte .LASF94 + .4byte .LASF93 .byte 0x13 .2byte 0x13c - .4byte 0x13c + .4byte 0x137 .byte 0x10 .uleb128 0x1e - .4byte .LASF95 + .4byte .LASF94 .byte 0x13 .2byte 0x13d - .4byte 0x13c + .4byte 0x137 .byte 0x14 .uleb128 0x1e - .4byte .LASF96 + .4byte .LASF95 .byte 0x13 .2byte 0x13e - .4byte 0x13c + .4byte 0x137 .byte 0x18 .uleb128 0x1e - .4byte .LASF97 + .4byte .LASF96 .byte 0x13 .2byte 0x13f - .4byte 0x131 + .4byte 0x12c .byte 0x1c .uleb128 0x1e - .4byte .LASF98 + .4byte .LASF97 .byte 0x13 .2byte 0x140 - .4byte 0x131 + .4byte 0x12c .byte 0x1d .uleb128 0x1e - .4byte .LASF99 + .4byte .LASF98 .byte 0x13 .2byte 0x141 - .4byte 0x131 + .4byte 0x12c .byte 0x1e .uleb128 0x1e - .4byte .LASF100 + .4byte .LASF99 .byte 0x13 .2byte 0x142 - .4byte 0x131 + .4byte 0x12c .byte 0x1f .uleb128 0x1e - .4byte .LASF101 + .4byte .LASF100 .byte 0x13 .2byte 0x143 - .4byte 0x63c + .4byte 0x62b .byte 0x20 .byte 0 .uleb128 0xa - .4byte 0x131 - .4byte 0x64c + .4byte 0x12c + .4byte 0x63b .uleb128 0xe - .4byte 0xdf + .4byte 0xda .byte 0x1f .byte 0 .uleb128 0x1f - .4byte .LASF102 + .4byte .LASF101 .byte 0x13 .2byte 0x144 - .4byte 0x592 + .4byte 0x581 .uleb128 0x1d - .4byte .LASF103 + .4byte .LASF102 .byte 0x30 .byte 0x13 .2byte 0x146 - .4byte 0x6da + .4byte 0x6c9 .uleb128 0x1e .4byte .LASF36 .byte 0x13 .2byte 0x147 - .4byte 0x126 + .4byte 0x121 .byte 0 .uleb128 0x20 .string "end" .byte 0x13 .2byte 0x147 - .4byte 0x126 + .4byte 0x121 .byte 0x8 .uleb128 0x1e - .4byte .LASF104 + .4byte .LASF103 .byte 0x13 .2byte 0x148 - .4byte 0x126 + .4byte 0x121 .byte 0x10 .uleb128 0x1e - .4byte .LASF105 + .4byte .LASF104 .byte 0x13 .2byte 0x148 - .4byte 0x126 + .4byte 0x121 .byte 0x18 .uleb128 0x1e - .4byte .LASF106 + .4byte .LASF105 .byte 0x13 .2byte 0x149 - .4byte 0x126 + .4byte 0x121 .byte 0x20 .uleb128 0x1e - .4byte .LASF107 + .4byte .LASF106 .byte 0x13 .2byte 0x14a - .4byte 0x131 + .4byte 0x12c .byte 0x28 .uleb128 0x1e - .4byte .LASF108 + .4byte .LASF107 .byte 0x13 .2byte 0x14a - .4byte 0x131 + .4byte 0x12c .byte 0x29 .uleb128 0x20 .string "os" .byte 0x13 .2byte 0x14a - .4byte 0x131 + .4byte 0x12c .byte 0x2a .uleb128 0x1e - .4byte .LASF109 + .4byte .LASF108 .byte 0x13 .2byte 0x14b - .4byte 0x131 + .4byte 0x12c .byte 0x2b .byte 0 .uleb128 0x1f - .4byte .LASF110 + .4byte .LASF109 .byte 0x13 .2byte 0x14c - .4byte 0x658 + .4byte 0x647 .uleb128 0x21 - .4byte .LASF111 + .4byte .LASF110 .2byte 0x380 .byte 0x13 .2byte 0x152 - .4byte 0x883 + .4byte 0x872 .uleb128 0x1e - .4byte .LASF112 + .4byte .LASF111 .byte 0x13 .2byte 0x158 - .4byte 0x883 + .4byte 0x872 .byte 0 .uleb128 0x1e - .4byte .LASF113 + .4byte .LASF112 .byte 0x13 .2byte 0x159 - .4byte 0x64c + .4byte 0x63b .byte 0x8 .uleb128 0x1e - .4byte .LASF114 + .4byte .LASF113 .byte 0x13 .2byte 0x15a - .4byte 0x126 + .4byte 0x121 .byte 0x48 .uleb128 0x1e - .4byte .LASF115 + .4byte .LASF114 .byte 0x13 .2byte 0x15d - .4byte 0xe6 + .4byte 0xe1 .byte 0x50 .uleb128 0x1e - .4byte .LASF116 + .4byte .LASF115 .byte 0x13 .2byte 0x15f - .4byte 0x152 + .4byte 0x14d .byte 0x58 .uleb128 0x1e - .4byte .LASF117 + .4byte .LASF116 .byte 0x13 .2byte 0x160 - .4byte 0xe6 + .4byte 0xe1 .byte 0x60 .uleb128 0x1e - .4byte .LASF118 + .4byte .LASF117 .byte 0x13 .2byte 0x161 .4byte 0x54 .byte 0x68 .uleb128 0x1e - .4byte .LASF119 + .4byte .LASF118 .byte 0x13 .2byte 0x163 - .4byte 0x152 + .4byte 0x14d .byte 0x70 .uleb128 0x1e - .4byte .LASF120 + .4byte .LASF119 .byte 0x13 .2byte 0x164 - .4byte 0xe6 + .4byte 0xe1 .byte 0x78 .uleb128 0x1e - .4byte .LASF121 + .4byte .LASF120 .byte 0x13 .2byte 0x165 .4byte 0x54 .byte 0x80 .uleb128 0x1e - .4byte .LASF122 + .4byte .LASF121 .byte 0x13 .2byte 0x167 - .4byte 0x152 + .4byte 0x14d .byte 0x88 .uleb128 0x1e - .4byte .LASF123 + .4byte .LASF122 .byte 0x13 .2byte 0x168 - .4byte 0xe6 + .4byte 0xe1 .byte 0x90 .uleb128 0x1e - .4byte .LASF124 + .4byte .LASF123 .byte 0x13 .2byte 0x169 .4byte 0x54 .byte 0x98 .uleb128 0x1e - .4byte .LASF125 + .4byte .LASF124 .byte 0x13 .2byte 0x16b - .4byte 0x152 + .4byte 0x14d .byte 0xa0 .uleb128 0x1e - .4byte .LASF126 + .4byte .LASF125 .byte 0x13 .2byte 0x16c - .4byte 0xe6 + .4byte 0xe1 .byte 0xa8 .uleb128 0x1e - .4byte .LASF127 + .4byte .LASF126 .byte 0x13 .2byte 0x16d .4byte 0x54 @@ -3585,76 +2457,76 @@ __func__.6107: .string "os" .byte 0x13 .2byte 0x171 - .4byte 0x6da + .4byte 0x6c9 .byte 0xb8 .uleb128 0x20 .string "ep" .byte 0x13 .2byte 0x172 - .4byte 0x126 + .4byte 0x121 .byte 0xe8 .uleb128 0x1e - .4byte .LASF128 + .4byte .LASF127 .byte 0x13 .2byte 0x174 - .4byte 0x126 + .4byte 0x121 .byte 0xf0 .uleb128 0x1e - .4byte .LASF129 + .4byte .LASF128 .byte 0x13 .2byte 0x174 - .4byte 0x126 + .4byte 0x121 .byte 0xf8 .uleb128 0x22 - .4byte .LASF130 + .4byte .LASF129 .byte 0x13 .2byte 0x176 - .4byte 0x10a + .4byte 0x105 .2byte 0x100 .uleb128 0x22 - .4byte .LASF131 + .4byte .LASF130 .byte 0x13 .2byte 0x177 - .4byte 0x126 + .4byte 0x121 .2byte 0x108 .uleb128 0x22 - .4byte .LASF132 + .4byte .LASF131 .byte 0x13 .2byte 0x179 - .4byte 0x126 + .4byte 0x121 .2byte 0x110 .uleb128 0x22 - .4byte .LASF133 + .4byte .LASF132 .byte 0x13 .2byte 0x17a - .4byte 0x126 + .4byte 0x121 .2byte 0x118 .uleb128 0x22 - .4byte .LASF134 + .4byte .LASF133 .byte 0x13 .2byte 0x17b - .4byte 0x126 + .4byte 0x121 .2byte 0x120 .uleb128 0x22 - .4byte .LASF135 + .4byte .LASF134 .byte 0x13 .2byte 0x17c - .4byte 0x126 + .4byte 0x121 .2byte 0x128 .uleb128 0x23 .string "kbd" .byte 0x13 .2byte 0x17d - .4byte 0x889 + .4byte 0x878 .2byte 0x130 .uleb128 0x22 - .4byte .LASF136 + .4byte .LASF135 .byte 0x13 .2byte 0x180 .4byte 0x54 .2byte 0x138 .uleb128 0x22 - .4byte .LASF137 + .4byte .LASF136 .byte 0x13 .2byte 0x18d .4byte 0x54 @@ -3663,1187 +2535,863 @@ __func__.6107: .string "lmb" .byte 0x13 .2byte 0x190 - .4byte 0x331 + .4byte 0x32c .2byte 0x140 .byte 0 .uleb128 0x8 .byte 0x8 - .4byte 0x64c + .4byte 0x63b .uleb128 0x8 .byte 0x8 - .4byte 0x492 + .4byte 0x481 .uleb128 0x1f - .4byte .LASF138 + .4byte .LASF137 .byte 0x13 .2byte 0x196 - .4byte 0x6e6 + .4byte 0x6d5 .uleb128 0xc - .4byte .LASF139 + .4byte .LASF138 .byte 0x13 .2byte 0x198 - .4byte 0x88f - .uleb128 0x24 - .4byte .LASF271 - .byte 0x4 - .4byte 0x54 - .byte 0x15 - .byte 0xe - .4byte 0xb0a - .uleb128 0x25 - .4byte .LASF140 + .4byte 0x87e + .uleb128 0xa + .4byte 0xe7 + .4byte 0x8a7 + .uleb128 0x16 + .4byte 0xda + .2byte 0x3ff .byte 0 - .uleb128 0x25 + .uleb128 0xa + .4byte 0xe7 + .4byte 0x8b7 + .uleb128 0xe + .4byte 0xda + .byte 0x1f + .byte 0 + .uleb128 0x4 + .4byte .LASF139 + .byte 0x3 + .byte 0xad + .4byte 0x121 + .uleb128 0xa + .4byte 0x94 + .4byte 0x8cd + .uleb128 0xb + .byte 0 + .uleb128 0x4 + .4byte .LASF140 + .byte 0x3 + .byte 0xaf + .4byte 0x8c2 + .uleb128 0x4 .4byte .LASF141 - .byte 0x1 - .uleb128 0x25 - .4byte .LASF142 - .byte 0x2 - .uleb128 0x25 - .4byte .LASF143 .byte 0x3 - .uleb128 0x25 + .byte 0xb0 + .4byte 0x8c2 + .uleb128 0x4 + .4byte .LASF142 + .byte 0x3 + .byte 0xfe + .4byte 0x121 + .uleb128 0x4 + .4byte .LASF143 + .byte 0x3 + .byte 0xff + .4byte 0x121 + .uleb128 0xc .4byte .LASF144 - .byte 0x4 - .uleb128 0x25 + .byte 0x3 + .2byte 0x100 + .4byte 0x121 + .uleb128 0xf .4byte .LASF145 - .byte 0x5 - .uleb128 0x25 + .byte 0x4 + .byte 0x14 + .byte 0x2e + .4byte 0x91e + .uleb128 0x10 .4byte .LASF146 - .byte 0x6 - .uleb128 0x25 + .byte 0x14 + .byte 0x2f + .4byte 0x137 + .byte 0 + .byte 0 + .uleb128 0x8 + .byte 0x8 + .4byte 0x29 + .uleb128 0xa + .4byte 0x94 + .4byte 0x934 + .uleb128 0xe + .4byte 0xda + .byte 0x5 + .byte 0 + .uleb128 0xc .4byte .LASF147 - .byte 0x7 - .uleb128 0x25 + .byte 0x14 + .2byte 0x1fd + .4byte 0x905 + .uleb128 0xc .4byte .LASF148 - .byte 0x8 - .uleb128 0x25 + .byte 0x14 + .2byte 0x1fe + .4byte 0x905 + .uleb128 0xc .4byte .LASF149 - .byte 0x9 - .uleb128 0x25 + .byte 0x14 + .2byte 0x200 + .4byte 0x905 + .uleb128 0xc .4byte .LASF150 - .byte 0xa - .uleb128 0x25 + .byte 0x14 + .2byte 0x205 + .4byte 0x8a7 + .uleb128 0xc .4byte .LASF151 - .byte 0xb - .uleb128 0x25 + .byte 0x14 + .2byte 0x206 + .4byte 0x8a7 + .uleb128 0xa + .4byte 0xe7 + .4byte 0x980 + .uleb128 0xe + .4byte 0xda + .byte 0x3f + .byte 0 + .uleb128 0xc .4byte .LASF152 - .byte 0xc - .uleb128 0x25 + .byte 0x14 + .2byte 0x207 + .4byte 0x970 + .uleb128 0xc .4byte .LASF153 - .byte 0xd - .uleb128 0x25 + .byte 0x14 + .2byte 0x209 + .4byte 0x924 + .uleb128 0xc .4byte .LASF154 - .byte 0xe - .uleb128 0x25 + .byte 0x14 + .2byte 0x20a + .4byte 0x924 + .uleb128 0xc .4byte .LASF155 - .byte 0xf - .uleb128 0x25 + .byte 0x14 + .2byte 0x20b + .4byte 0x905 + .uleb128 0xc .4byte .LASF156 - .byte 0x10 - .uleb128 0x25 + .byte 0x14 + .2byte 0x20c + .4byte 0x905 + .uleb128 0xc .4byte .LASF157 - .byte 0x11 - .uleb128 0x25 + .byte 0x14 + .2byte 0x20d + .4byte 0x91e + .uleb128 0xa + .4byte 0x91e + .4byte 0x9d8 + .uleb128 0xe + .4byte 0xda + .byte 0x3 + .byte 0 + .uleb128 0xc .4byte .LASF158 - .byte 0x12 - .uleb128 0x25 + .byte 0x14 + .2byte 0x20e + .4byte 0x9c8 + .uleb128 0xc .4byte .LASF159 - .byte 0x13 - .uleb128 0x25 + .byte 0x14 + .2byte 0x20f + .4byte 0x91e + .uleb128 0xc .4byte .LASF160 .byte 0x14 - .uleb128 0x25 + .2byte 0x210 + .4byte 0x54 + .uleb128 0xa + .4byte 0x9e + .4byte 0xa0c + .uleb128 0xe + .4byte 0xda + .byte 0x5 + .byte 0 + .uleb128 0x7 + .4byte 0x9fc + .uleb128 0xc .4byte .LASF161 - .byte 0x15 - .uleb128 0x25 + .byte 0x14 + .2byte 0x211 + .4byte 0xa0c + .uleb128 0xc .4byte .LASF162 - .byte 0x16 - .uleb128 0x25 + .byte 0x14 + .2byte 0x212 + .4byte 0xa0c + .uleb128 0xc .4byte .LASF163 - .byte 0x17 - .uleb128 0x25 + .byte 0x14 + .2byte 0x216 + .4byte 0x116 + .uleb128 0xc .4byte .LASF164 - .byte 0x18 - .uleb128 0x25 + .byte 0x14 + .2byte 0x217 + .4byte 0x116 + .uleb128 0xc .4byte .LASF165 - .byte 0x19 - .uleb128 0x25 + .byte 0x14 + .2byte 0x219 + .4byte 0x54 + .uleb128 0xc .4byte .LASF166 - .byte 0x1a - .uleb128 0x25 + .byte 0x14 + .2byte 0x220 + .4byte 0x896 + .uleb128 0xc .4byte .LASF167 - .byte 0x1b - .uleb128 0x25 + .byte 0x14 + .2byte 0x222 + .4byte 0xae + .uleb128 0xc .4byte .LASF168 - .byte 0x1c - .uleb128 0x25 + .byte 0x14 + .2byte 0x224 + .4byte 0xae + .uleb128 0xc .4byte .LASF169 - .byte 0x1d + .byte 0x14 + .2byte 0x230 + .4byte 0x905 + .uleb128 0x24 + .4byte .LASF180 + .byte 0x4 + .4byte 0x7f + .byte 0x14 + .2byte 0x286 + .4byte 0xaa7 .uleb128 0x25 .4byte .LASF170 - .byte 0x1e + .byte 0 .uleb128 0x25 .4byte .LASF171 - .byte 0x1f + .byte 0x1 .uleb128 0x25 .4byte .LASF172 - .byte 0x20 + .byte 0x2 .uleb128 0x25 .4byte .LASF173 - .byte 0x21 - .uleb128 0x25 + .byte 0x3 + .byte 0 + .uleb128 0xc .4byte .LASF174 - .byte 0x22 - .uleb128 0x25 + .byte 0x14 + .2byte 0x28c + .4byte 0xa7d + .uleb128 0xc .4byte .LASF175 - .byte 0x23 - .uleb128 0x25 + .byte 0x15 + .2byte 0x3ba + .4byte 0x121 + .uleb128 0xc .4byte .LASF176 - .byte 0x24 - .uleb128 0x25 + .byte 0x15 + .2byte 0x3bb + .4byte 0x121 + .uleb128 0xc .4byte .LASF177 - .byte 0x25 - .uleb128 0x25 + .byte 0x15 + .2byte 0x3bc + .4byte 0x121 + .uleb128 0xf .4byte .LASF178 - .byte 0x26 - .uleb128 0x25 + .byte 0x4 + .byte 0x2 + .byte 0xd + .4byte 0xaf0 + .uleb128 0x19 + .string "pid" + .byte 0x2 + .byte 0xe + .4byte 0x54 + .byte 0 + .byte 0 + .uleb128 0x4 .4byte .LASF179 - .byte 0x27 - .uleb128 0x25 - .4byte .LASF180 - .byte 0x28 - .uleb128 0x25 + .byte 0x2 + .byte 0x11 + .4byte 0xafb + .uleb128 0x8 + .byte 0x8 + .4byte 0xad7 + .uleb128 0x26 .4byte .LASF181 - .byte 0x29 + .byte 0x4 + .4byte 0x7f + .byte 0x16 + .byte 0x11 + .4byte 0xb78 .uleb128 0x25 .4byte .LASF182 - .byte 0x2a + .byte 0 .uleb128 0x25 .4byte .LASF183 - .byte 0x2b + .byte 0x1 .uleb128 0x25 .4byte .LASF184 - .byte 0x2c + .byte 0x2 .uleb128 0x25 .4byte .LASF185 - .byte 0x2d + .byte 0x3 .uleb128 0x25 .4byte .LASF186 - .byte 0x2e + .byte 0x4 .uleb128 0x25 .4byte .LASF187 - .byte 0x2f + .byte 0x5 .uleb128 0x25 .4byte .LASF188 - .byte 0x30 + .byte 0x6 .uleb128 0x25 .4byte .LASF189 - .byte 0x31 + .byte 0x7 .uleb128 0x25 .4byte .LASF190 - .byte 0x32 + .byte 0x8 .uleb128 0x25 .4byte .LASF191 - .byte 0x33 + .byte 0x9 .uleb128 0x25 .4byte .LASF192 - .byte 0x34 + .byte 0xa .uleb128 0x25 .4byte .LASF193 - .byte 0x35 + .byte 0xb .uleb128 0x25 .4byte .LASF194 - .byte 0x36 + .byte 0xc .uleb128 0x25 .4byte .LASF195 - .byte 0x37 + .byte 0xd .uleb128 0x25 .4byte .LASF196 - .byte 0x38 + .byte 0xe .uleb128 0x25 .4byte .LASF197 - .byte 0x39 + .byte 0xf .uleb128 0x25 .4byte .LASF198 - .byte 0x3a - .uleb128 0x25 + .byte 0x10 + .byte 0 + .uleb128 0xf .4byte .LASF199 - .byte 0x3b - .uleb128 0x25 + .byte 0x20 + .byte 0x16 + .byte 0x26 + .4byte 0xba9 + .uleb128 0x10 .4byte .LASF200 - .byte 0x3c - .uleb128 0x25 + .byte 0x16 + .byte 0x27 + .4byte 0x7f + .byte 0 + .uleb128 0x10 .4byte .LASF201 - .byte 0x3d - .uleb128 0x25 + .byte 0x16 + .byte 0x28 + .4byte 0xba9 + .byte 0x8 + .uleb128 0x10 .4byte .LASF202 - .byte 0x3e - .uleb128 0x25 + .byte 0x16 + .byte 0x29 + .4byte 0xbaf + .byte 0x10 + .byte 0 + .uleb128 0x8 + .byte 0x8 + .4byte 0x7f + .uleb128 0xa + .4byte 0xbbf + .4byte 0xbbf + .uleb128 0xe + .4byte 0xda + .byte 0x1 + .byte 0 + .uleb128 0x8 + .byte 0x8 + .4byte 0x94 + .uleb128 0x27 + .4byte .LASF249 + .byte 0x1 + .byte 0x15 + .4byte 0x15a + .uleb128 0xf .4byte .LASF203 - .byte 0x3f - .uleb128 0x25 + .byte 0x34 + .byte 0x1 + .byte 0x1a + .4byte 0xcf1 + .uleb128 0x10 .4byte .LASF204 - .byte 0x40 - .uleb128 0x25 + .byte 0x1 + .byte 0x1b + .4byte 0xae + .byte 0 + .uleb128 0x10 .4byte .LASF205 - .byte 0x41 - .uleb128 0x25 + .byte 0x1 + .byte 0x1c + .4byte 0xae + .byte 0x4 + .uleb128 0x10 .4byte .LASF206 - .byte 0x42 - .uleb128 0x25 + .byte 0x1 + .byte 0x1d + .4byte 0xae + .byte 0x8 + .uleb128 0x10 .4byte .LASF207 - .byte 0x43 - .uleb128 0x25 + .byte 0x1 + .byte 0x1e + .4byte 0x94 + .byte 0xc + .uleb128 0x10 .4byte .LASF208 - .byte 0x44 - .uleb128 0x25 + .byte 0x1 + .byte 0x1f + .4byte 0x94 + .byte 0xd + .uleb128 0x10 .4byte .LASF209 - .byte 0x45 - .uleb128 0x25 + .byte 0x1 + .byte 0x20 + .4byte 0xa3 + .byte 0xe + .uleb128 0x10 .4byte .LASF210 - .byte 0x46 - .uleb128 0x25 + .byte 0x1 + .byte 0x21 + .4byte 0x94 + .byte 0x10 + .uleb128 0x10 .4byte .LASF211 - .byte 0x47 - .uleb128 0x25 + .byte 0x1 + .byte 0x22 + .4byte 0x94 + .byte 0x11 + .uleb128 0x10 .4byte .LASF212 - .byte 0x48 - .uleb128 0x25 + .byte 0x1 + .byte 0x23 + .4byte 0x94 + .byte 0x12 + .uleb128 0x10 .4byte .LASF213 - .byte 0x49 - .uleb128 0x25 + .byte 0x1 + .byte 0x24 + .4byte 0x94 + .byte 0x13 + .uleb128 0x10 .4byte .LASF214 - .byte 0x4a - .uleb128 0x25 + .byte 0x1 + .byte 0x25 + .4byte 0x94 + .byte 0x14 + .uleb128 0x10 .4byte .LASF215 - .byte 0x4b - .uleb128 0x25 + .byte 0x1 + .byte 0x26 + .4byte 0x94 + .byte 0x15 + .uleb128 0x10 .4byte .LASF216 - .byte 0x4c - .uleb128 0x25 + .byte 0x1 + .byte 0x27 + .4byte 0x94 + .byte 0x16 + .uleb128 0x10 .4byte .LASF217 - .byte 0x4d - .uleb128 0x25 + .byte 0x1 + .byte 0x28 + .4byte 0x94 + .byte 0x17 + .uleb128 0x10 + .4byte .LASF46 + .byte 0x1 + .byte 0x29 + .4byte 0xae + .byte 0x18 + .uleb128 0x10 .4byte .LASF218 - .byte 0x4e - .uleb128 0x25 + .byte 0x1 + .byte 0x2a + .4byte 0x94 + .byte 0x1c + .uleb128 0x10 .4byte .LASF219 - .byte 0x4f - .uleb128 0x25 + .byte 0x1 + .byte 0x2b + .4byte 0xcf1 + .byte 0x1d + .uleb128 0x19 + .string "sc1" + .byte 0x1 + .byte 0x2c + .4byte 0x94 + .byte 0x20 + .uleb128 0x10 .4byte .LASF220 - .byte 0x50 - .uleb128 0x25 + .byte 0x1 + .byte 0x2d + .4byte 0xd01 + .byte 0x21 + .uleb128 0x10 .4byte .LASF221 - .byte 0x51 - .uleb128 0x25 + .byte 0x1 + .byte 0x2e + .4byte 0x94 + .byte 0x25 + .uleb128 0x10 .4byte .LASF222 - .byte 0x52 - .uleb128 0x25 + .byte 0x1 + .byte 0x2f + .4byte 0x94 + .byte 0x26 + .uleb128 0x10 .4byte .LASF223 - .byte 0x53 - .uleb128 0x25 + .byte 0x1 + .byte 0x30 + .4byte 0xd11 + .byte 0x27 + .uleb128 0x10 .4byte .LASF224 - .byte 0x54 - .uleb128 0x25 - .4byte .LASF225 - .byte 0x55 - .uleb128 0x25 - .4byte .LASF226 - .byte 0x56 - .uleb128 0x25 - .4byte .LASF227 - .byte 0x57 - .uleb128 0x25 - .4byte .LASF228 - .byte 0x58 - .uleb128 0x25 - .4byte .LASF229 - .byte 0x59 - .uleb128 0x25 - .4byte .LASF230 - .byte 0x5a - .uleb128 0x25 - .4byte .LASF231 - .byte 0x5b - .uleb128 0x25 - .4byte .LASF232 - .byte 0x5c - .uleb128 0x25 - .4byte .LASF233 - .byte 0x5d - .uleb128 0x25 - .4byte .LASF234 - .byte 0x5e - .uleb128 0x25 - .4byte .LASF235 - .byte 0x5f - .uleb128 0x25 - .4byte .LASF236 - .byte 0x60 - .uleb128 0x25 - .4byte .LASF237 - .byte 0x61 - .uleb128 0x26 - .4byte .LASF238 - .sleb128 -1 - .byte 0 - .uleb128 0x27 - .byte 0x4 - .4byte 0x84 - .byte 0x19 - .byte 0xf6 - .4byte 0xb1d - .uleb128 0x25 - .4byte .LASF239 - .byte 0x5 + .byte 0x1 + .byte 0x31 + .4byte 0xd21 + .byte 0x30 .byte 0 .uleb128 0xa - .4byte 0xec - .4byte 0xb2d + .4byte 0x94 + .4byte 0xd01 .uleb128 0xe - .4byte 0xdf - .byte 0x1f + .4byte 0xda + .byte 0x2 .byte 0 - .uleb128 0x4 - .4byte .LASF240 + .uleb128 0xa + .4byte 0x94 + .4byte 0xd11 + .uleb128 0xe + .4byte 0xda .byte 0x3 - .byte 0xad - .4byte 0x126 + .byte 0 .uleb128 0xa - .4byte 0x99 - .4byte 0xb43 - .uleb128 0xb + .4byte 0x94 + .4byte 0xd21 + .uleb128 0xe + .4byte 0xda + .byte 0x8 .byte 0 - .uleb128 0x4 - .4byte .LASF241 + .uleb128 0xa + .4byte 0x94 + .4byte 0xd31 + .uleb128 0xe + .4byte 0xda + .byte 0 + .byte 0 + .uleb128 0x28 + .4byte .LASF225 + .byte 0x1 + .byte 0x34 + .4byte 0xbbf + .uleb128 0x9 .byte 0x3 - .byte 0xaf - .4byte 0xb38 - .uleb128 0x4 - .4byte .LASF242 + .8byte waveformdata + .uleb128 0x28 + .4byte .LASF226 + .byte 0x1 + .byte 0x35 + .4byte 0x54 + .uleb128 0x9 .byte 0x3 - .byte 0xb0 - .4byte 0xb38 - .uleb128 0x4 - .4byte .LASF243 - .byte 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0xb7b - .uleb128 0xc - .4byte .LASF251 - .byte 0x14 - .2byte 0x205 - .4byte 0xb1d - .uleb128 0xc - .4byte .LASF252 - .byte 0x14 - .2byte 0x206 - .4byte 0xb1d - .uleb128 0xa - .4byte 0xec - .4byte 0xbf6 + .4byte 0xda + .byte 0x8 .uleb128 0xe - .4byte 0xdf - .byte 0x3f + .4byte 0xda + .byte 0x8 .byte 0 - .uleb128 0xc - .4byte .LASF253 - .byte 0x14 - .2byte 0x207 - .4byte 0xbe6 - .uleb128 0xc - .4byte .LASF254 - .byte 0x14 - .2byte 0x209 - .4byte 0xb9a - .uleb128 0xc - .4byte .LASF255 - .byte 0x14 - .2byte 0x20a - .4byte 0xb9a - .uleb128 0xc - .4byte .LASF256 - .byte 0x14 - .2byte 0x20b - .4byte 0xb7b - .uleb128 0xc - .4byte .LASF257 - .byte 0x14 - .2byte 0x20c - .4byte 0xb7b - .uleb128 0xc - .4byte .LASF258 - .byte 0x14 - .2byte 0x20d - .4byte 0xb94 - .uleb128 0xa - .4byte 0xb94 - .4byte 0xc4e - .uleb128 0xe - .4byte 0xdf + .uleb128 0x7 + .4byte 0xd8b + .uleb128 0x29 + .4byte .LASF229 + .byte 0x1 + .byte 0x9e + .4byte 0xda1 + .uleb128 0x9 .byte 0x3 + .8byte pvi_mode_table + .uleb128 0xf + .4byte .LASF230 + .byte 0x10 + .byte 0x1 + .byte 0xaa + .4byte 0xdec + .uleb128 0x10 + .4byte .LASF231 + .byte 0x1 + .byte 0xab + .4byte 0xd11 .byte 0 - .uleb128 0xc - .4byte .LASF259 - .byte 0x14 - .2byte 0x20e - .4byte 0xc3e - .uleb128 0xc - .4byte .LASF260 - .byte 0x14 - .2byte 0x20f - .4byte 0xb94 - .uleb128 0xc - .4byte .LASF261 - .byte 0x14 - .2byte 0x210 - .4byte 0x54 - .uleb128 0xa - .4byte 0xa3 - .4byte 0xc82 - .uleb128 0xe - .4byte 0xdf - .byte 0x5 - .byte 0 - .uleb128 0x6 - .4byte 0xc72 - .uleb128 0xc - .4byte .LASF262 - .byte 0x14 - .2byte 0x211 - .4byte 0xc82 - .uleb128 0xc - .4byte .LASF263 - .byte 0x14 - .2byte 0x212 - .4byte 0xc82 - .uleb128 0xc - .4byte .LASF264 - .byte 0x14 - .2byte 0x216 - .4byte 0x11b - .uleb128 0xc - .4byte .LASF265 - .byte 0x14 - .2byte 0x217 - .4byte 0x11b - .uleb128 0xc - .4byte .LASF266 - .byte 0x14 - .2byte 0x219 + .uleb128 0x10 + .4byte .LASF82 + .byte 0x1 + .byte 0xac + .4byte 0x94 + .byte 0x9 + .uleb128 0x10 + .4byte .LASF226 + .byte 0x1 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0x16 - .2byte 0x3bb - .4byte 0x126 - .uleb128 0xc - .4byte .LASF280 - .byte 0x16 - .2byte 0x3bc - .4byte 0x126 - .uleb128 0xf - .4byte .LASF281 - .byte 0x4 - .byte 0x2 - .byte 0xd - .4byte 0xd77 - .uleb128 0x19 - .string "pid" - .byte 0x2 - .byte 0xe + .8byte custom_mode_table + .uleb128 0x2a + .4byte .LASF235 + .byte 0x1 + .2byte 0x248 + .4byte 0xe1 + .8byte .LFB228 + .8byte .LFE228-.LFB228 + .uleb128 0x1 + .byte 0x9c + .4byte 0xe5c + .uleb128 0x2b + .4byte .LASF233 + .byte 0x1 + .2byte 0x24a + .4byte 0xe1 + .uleb128 0x1 + .byte 0x52 + .uleb128 0x2b + .4byte .LASF234 + .byte 0x1 + .2byte 0x24b + .4byte 0x8a7 + .uleb128 0x9 + .byte 0x3 + .8byte spi_id_buffer.6314 + .uleb128 0x2c + .4byte .Ldebug_ranges0+0x1a0 + .uleb128 0x2d + .string "i" + .byte 0x1 + .2byte 0x250 .4byte 0x54 + .4byte .LLST47 .byte 0 .byte 0 - .uleb128 0x4 - .4byte .LASF282 - .byte 0x2 - .byte 0x11 - .4byte 0xd82 - .uleb128 0x8 - .byte 0x8 - .4byte 0xd5e - .uleb128 0x24 - .4byte .LASF283 - .byte 0x4 - .4byte 0x84 - .byte 0x17 - .byte 0x14 - .4byte 0xde7 - .uleb128 0x25 - .4byte .LASF284 + .uleb128 0x2a + .4byte .LASF236 .byte 0x1 - .uleb128 0x25 - .4byte .LASF285 - .byte 0x2 - .uleb128 0x25 - .4byte .LASF286 - .byte 0x3 - .uleb128 0x25 - .4byte .LASF287 - .byte 0x4 - .uleb128 0x25 - .4byte .LASF288 - .byte 0x5 - .uleb128 0x25 - .4byte .LASF289 - .byte 0x6 - .uleb128 0x25 - .4byte .LASF290 - .byte 0x7 - .uleb128 0x25 - .4byte .LASF291 - .byte 0x8 - .uleb128 0x25 - .4byte .LASF292 - .byte 0x9 - .uleb128 0x25 - .4byte .LASF293 - .byte 0xa - .uleb128 0x25 - .4byte .LASF294 - .byte 0xb - .uleb128 0x25 - .4byte .LASF295 - .byte 0xc - .uleb128 0x25 - .4byte .LASF296 - .byte 0xd - .byte 0 - .uleb128 0x24 - .4byte .LASF297 - .byte 0x4 - .4byte 0x84 - .byte 0x17 - .byte 0x2a - .4byte 0xe34 - .uleb128 0x25 - .4byte .LASF298 - .byte 0 - .uleb128 0x25 - .4byte .LASF299 + .2byte 0x219 + .4byte 0x54 + .8byte .LFB227 + .8byte .LFE227-.LFB227 + .uleb128 0x1 + .byte 0x9c + .4byte 0xed9 + .uleb128 0x2e + .4byte .LASF239 .byte 0x1 - .uleb128 0x25 - .4byte .LASF300 - .byte 0x2 - .uleb128 0x25 - .4byte .LASF301 + .2byte 0x219 + .4byte 0x14d + .4byte .LLST45 + .uleb128 0x2f + .4byte .LASF237 + .byte 0x1 + .2byte 0x21b + .4byte 0xd70 + .4byte .LLST46 + .uleb128 0x30 + .8byte .LVL166 + .4byte 0x1767 + .4byte 0xebd + .uleb128 0x31 + .uleb128 0x1 + .byte 0x50 + .uleb128 0x9 .byte 0x3 - .uleb128 0x25 - .4byte .LASF302 - .byte 0x4 - .uleb128 0x25 - .4byte .LASF303 - .byte 0x5 - .uleb128 0x25 - .4byte .LASF304 - .byte 0x6 - .uleb128 0x25 - .4byte .LASF305 - .byte 0x7 - .uleb128 0x25 - .4byte .LASF306 - .byte 0x8 - .uleb128 0x25 - .4byte .LASF307 - .byte 0x9 - .byte 0 - .uleb128 0xf - .4byte .LASF308 - .byte 0x10 - .byte 0x17 - .byte 0x43 - .4byte 0xe59 - .uleb128 0x10 - .4byte .LASF309 - .byte 0x17 - .byte 0x44 - .4byte 0x84 + .8byte .LC7 .byte 0 - .uleb128 0x10 - .4byte .LASF310 - .byte 0x17 - .byte 0x45 - .4byte 0xe59 - .byte 0x8 + .uleb128 0x32 + .8byte .LVL167 + .4byte 0x1767 + .uleb128 0x31 + .uleb128 0x1 + .byte 0x50 + .uleb128 0x9 + .byte 0x3 + .8byte .LC8 .byte 0 - .uleb128 0x8 - .byte 0x8 - .4byte 0x84 - .uleb128 0x8 - .byte 0x8 - .4byte 0xe34 - .uleb128 0xf - .4byte .LASF311 - .byte 0x30 - .byte 0x1 - .byte 0xc - .4byte 0xf7a - .uleb128 0x10 - .4byte .LASF312 - .byte 0x1 - .byte 0xd - .4byte 0xb3 .byte 0 - .uleb128 0x10 - .4byte .LASF313 - .byte 0x1 - .byte 0xe - .4byte 0xb3 - .byte 0x4 - .uleb128 0x10 - .4byte .LASF314 - .byte 0x1 - .byte 0xf - .4byte 0xb3 - .byte 0x8 - .uleb128 0x10 - .4byte .LASF315 - .byte 0x1 - .byte 0x10 - .4byte 0x99 - .byte 0xc - .uleb128 0x10 - .4byte .LASF316 - .byte 0x1 - .byte 0x11 - .4byte 0x99 - .byte 0xd - .uleb128 0x10 - .4byte .LASF317 - .byte 0x1 - .byte 0x12 - .4byte 0xa8 - .byte 0xe - .uleb128 0x10 - .4byte .LASF318 - .byte 0x1 - .byte 0x13 - .4byte 0x99 - .byte 0x10 - .uleb128 0x10 - .4byte .LASF319 - .byte 0x1 - .byte 0x14 - .4byte 0x99 - .byte 0x11 - .uleb128 0x10 - .4byte .LASF320 - .byte 0x1 - .byte 0x15 - .4byte 0x99 - .byte 0x12 - .uleb128 0x10 - .4byte .LASF321 - .byte 0x1 - .byte 0x16 - .4byte 0x99 - .byte 0x13 - .uleb128 0x10 - .4byte .LASF322 - .byte 0x1 - .byte 0x17 - .4byte 0x99 - .byte 0x14 - .uleb128 0x10 - .4byte .LASF323 - .byte 0x1 - .byte 0x18 - .4byte 0x99 - .byte 0x15 - .uleb128 0x10 - .4byte .LASF324 - .byte 0x1 - .byte 0x19 - .4byte 0x99 - .byte 0x16 - .uleb128 0x10 - .4byte .LASF325 - .byte 0x1 - .byte 0x1a - .4byte 0x99 - .byte 0x17 - .uleb128 0x10 - .4byte .LASF46 - .byte 0x1 - .byte 0x1b - .4byte 0xb3 - .byte 0x18 - .uleb128 0x10 - .4byte .LASF326 - .byte 0x1 - .byte 0x1c - .4byte 0x99 - .byte 0x1c - .uleb128 0x10 - .4byte .LASF327 + .uleb128 0x2a + .4byte .LASF238 .byte 0x1 - .byte 0x1d - .4byte 0xf7a - .byte 0x1d - .uleb128 0x19 - .string "sc1" + .2byte 0x1bb + .4byte 0x54 + .8byte .LFB226 + .8byte .LFE226-.LFB226 + .uleb128 0x1 + .byte 0x9c + .4byte 0x1196 + .uleb128 0x2e + .4byte .LASF240 .byte 0x1 - .byte 0x1e - .4byte 0x99 - .byte 0x20 - .uleb128 0x10 - .4byte .LASF328 + .2byte 0x1bb + .4byte 0x1196 + .4byte .LLST25 + .uleb128 0x2e + .4byte .LASF241 .byte 0x1 - .byte 0x1f - .4byte 0xf8a - .byte 0x21 - .uleb128 0x10 - .4byte .LASF329 + .2byte 0x1bb + .4byte 0xb01 + .4byte .LLST26 + .uleb128 0x2e + .4byte .LASF224 .byte 0x1 - .byte 0x20 - .4byte 0x99 - .byte 0x25 - .uleb128 0x10 - .4byte .LASF330 + .2byte 0x1bb + .4byte 0x54 + .4byte .LLST27 + .uleb128 0x33 + .string "pic" .byte 0x1 - .byte 0x21 - .4byte 0x99 - .byte 0x26 - .uleb128 0x10 - .4byte .LASF331 + .2byte 0x1bb + .4byte 0x54 + .4byte .LLST28 + .uleb128 0x2e + .4byte .LASF242 .byte 0x1 - .byte 0x22 - .4byte 0xf9a - .byte 0x27 - .byte 0 - .uleb128 0xa - .4byte 0x99 - .4byte 0xf8a - .uleb128 0xe - .4byte 0xdf - .byte 0x2 - .byte 0 - .uleb128 0xa - .4byte 0x99 - .4byte 0xf9a - .uleb128 0xe - .4byte 0xdf - .byte 0x3 - .byte 0 - .uleb128 0xa - .4byte 0x99 - .4byte 0xfaa - .uleb128 0xe - .4byte 0xdf - .byte 0x8 - .byte 0 - .uleb128 0xa - .4byte 0x34 - .4byte 0xfc7 - .uleb128 0x16 - .4byte 0xdf - .2byte 0x1ff - .uleb128 0xe - .4byte 0xdf - .byte 0x1f - .uleb128 0xe - .4byte 0xdf - .byte 0x1f - .byte 0 - .uleb128 0x29 - .4byte .LASF332 + .2byte 0x1bb + .4byte 0x54 + .4byte .LLST29 + .uleb128 0x2b + .4byte .LASF243 .byte 0x1 - .byte 0x2a - .4byte 0xfaa + .2byte 0x1bd + .4byte 0xb01 .uleb128 0x9 .byte 0x3 - .8byte waveformdata - .uleb128 0xa - .4byte 0x84 - .4byte 0xff3 - .uleb128 0x16 - .4byte 0xdf - .2byte 0x12b - .uleb128 0xe - .4byte 0xdf - .byte 0xf - .byte 0 - .uleb128 0x29 - .4byte .LASF333 + .8byte stype.6286 + .uleb128 0x2b + .4byte .LASF244 .byte 0x1 - .byte 0x2b - .4byte 0xfdc + .2byte 0x1be + .4byte 0x54 .uleb128 0x9 .byte 0x3 - .8byte gray_data - .uleb128 0xa - .4byte 0x84 - .4byte 0x1019 - .uleb128 0x16 - .4byte 0xdf - .2byte 0x12b - .byte 0 - .uleb128 0x29 - .4byte .LASF334 + .8byte sftemp.6287 + .uleb128 0x34 + .string "fix" .byte 0x1 - .byte 0x2c - .4byte 0x1008 + .2byte 0x1bf + .4byte 0x54 .uleb128 0x9 .byte 0x3 - .8byte reset_data - .uleb128 0xa - .4byte 0x84 - .4byte 0x1045 - .uleb128 0x16 - .4byte 0xdf - .2byte 0x12b - .uleb128 0xe - .4byte 0xdf + .8byte fix.6288 + .uleb128 0x2f + .4byte .LASF245 .byte 0x1 - .byte 0 - .uleb128 0x29 - .4byte .LASF335 + .2byte 0x1c0 + .4byte 0x54 + .4byte .LLST30 + .uleb128 0x2f + .4byte .LASF246 .byte 0x1 - .byte 0x2d - .4byte 0x102e - .uleb128 0x9 - .byte 0x3 - .8byte gray_2_data - .uleb128 0xa - .4byte 0x84 - .4byte 0x1071 - .uleb128 0x16 - .4byte 0xdf - .2byte 0x12b - .uleb128 0xe - .4byte 0xdf - .byte 0x3f - .byte 0 - .uleb128 0x29 - .4byte .LASF336 - .byte 0x1 - .byte 0x2e - .4byte 0x105a - .uleb128 0x9 - .byte 0x3 - .8byte gray32_data - .uleb128 0x29 - .4byte .LASF337 - .byte 0x1 - .byte 0x2f - .4byte 0x109b - .uleb128 0x9 - .byte 0x3 - .8byte global_waveform - .uleb128 0x8 - .byte 0x8 - .4byte 0xe65 - .uleb128 0x2a - .4byte .LASF340 - .byte 0x1 - .2byte 0x379 - .4byte 0xe6 - .8byte .LFB234 - .8byte .LFE234-.LFB234 - .uleb128 0x1 - .byte 0x9c - .4byte 0x10f6 - .uleb128 0x2b - .4byte .LASF338 - .byte 0x1 - .2byte 0x37b - .4byte 0xe6 - .uleb128 0x1 - .byte 0x52 - .uleb128 0x2b - .4byte .LASF339 - .byte 0x1 - .2byte 0x37c - .4byte 0xb1d - .uleb128 0x9 - .byte 0x3 - .8byte spi_id_buffer.6330 - .uleb128 0x2c - .string "i" - .byte 0x1 - .2byte 0x37d - .4byte 0x54 - .4byte .LLST135 - .byte 0 - .uleb128 0x2a - .4byte .LASF341 - .byte 0x1 - .2byte 0x352 + .2byte 0x1c1 .4byte 0x54 - .8byte .LFB233 - .8byte .LFE233-.LFB233 - .uleb128 0x1 - .byte 0x9c - .4byte 0x1154 - .uleb128 0x2d - .4byte .LASF344 - .byte 0x1 - .2byte 0x352 - .4byte 0x152 - .4byte .LLST133 - .uleb128 0x2e - .4byte .LASF342 - .byte 0x1 - .2byte 0x354 - .4byte 0x109b - .4byte .LLST134 + .4byte .LLST31 .uleb128 0x2f - .8byte .LVL330 - .4byte 0x271f - .uleb128 0x30 - .uleb128 0x1 - .byte 0x50 - .uleb128 0x9 - .byte 0x3 - .8byte .LC5 - .byte 0 - .byte 0 - .uleb128 0x2a - .4byte .LASF343 - .byte 0x1 - .2byte 0x2e2 - .4byte 0x54 - .8byte .LFB232 - .8byte .LFE232-.LFB232 - .uleb128 0x1 - .byte 0x9c - .4byte 0x1a73 - .uleb128 0x2d - .4byte .LASF345 - .byte 0x1 - .2byte 0x2e2 - .4byte 0xe5f - .4byte .LLST60 - .uleb128 0x2d - .4byte .LASF346 - .byte 0x1 - .2byte 0x2e2 - .4byte 0xd88 - .4byte .LLST61 - .uleb128 0x2d - .4byte .LASF347 - .byte 0x1 - .2byte 0x2e2 - .4byte 0x54 - .4byte .LLST62 - .uleb128 0x2b - .4byte .LASF348 - .byte 0x1 - .2byte 0x2e4 - .4byte 0xd88 - .uleb128 0x9 - .byte 0x3 - .8byte stype.6291 - .uleb128 0x2b - .4byte .LASF349 - .byte 0x1 - .2byte 0x2e5 - .4byte 0x54 - .uleb128 0x9 - .byte 0x3 - .8byte sftemp.6292 - .uleb128 0x31 - .4byte .LASF350 - .byte 0x1 - .2byte 0x2e6 - .4byte 0x54 - .uleb128 0x32 - .string "ret" + .4byte .LASF200 .byte 0x1 - .2byte 0x2e7 + .2byte 0x1c2 .4byte 0x54 - .uleb128 0x33 - .4byte 0x245a - .8byte .LBB121 - .4byte .Ldebug_ranges0+0xe0 - .byte 0x1 - .2byte 0x2f6 - .4byte 0x1236 - .uleb128 0x34 - .4byte 0x246b - .4byte .LLST63 + .4byte .LLST32 .uleb128 0x35 - .4byte .Ldebug_ranges0+0xe0 - .uleb128 0x36 - .4byte 0x2477 - .4byte .LLST64 - .uleb128 0x36 - .4byte 0x2483 - .4byte .LLST65 - .uleb128 0x36 - .4byte 0x248f - .4byte .LLST66 + .4byte .LASF247 + .byte 0x1 + .2byte 0x1c3 + .4byte 0xb01 + .sleb128 -1 .uleb128 0x36 - .4byte 0x249b - .4byte .LLST67 - .byte 0 - .byte 0 - .uleb128 0x37 - .4byte 0x26e0 - .8byte .LBB126 - .8byte .LBE126-.LBB126 + .4byte 0x1673 + .8byte .LBB49 + .8byte .LBE49-.LBB49 .byte 0x1 - .2byte 0x2fa - .4byte 0x1269 - .uleb128 0x34 - .4byte 0x26ec - .4byte .LLST68 + .2byte 0x1ec + .4byte 0xffd + .uleb128 0x37 + .4byte 0x167f + .4byte .LLST33 .uleb128 0x38 - .8byte .LVL190 - .4byte 0x272a + .8byte .LVL137 + .4byte 0x1772 .byte 0 - .uleb128 0x33 - .4byte 0x1eb4 - .8byte .LBB129 - .4byte .Ldebug_ranges0+0x120 - .byte 0x1 - .2byte 0x301 - .4byte 0x14e6 - .uleb128 0x34 - .4byte 0x1ed1 - .4byte .LLST69 - .uleb128 0x34 - .4byte 0x1ec5 - .4byte .LLST70 - .uleb128 0x35 - .4byte .Ldebug_ranges0+0x120 .uleb128 0x39 - .4byte 0x1edd - .uleb128 0x36 - .4byte 0x1ee9 - .4byte .LLST71 - .uleb128 0x36 - .4byte 0x1ef5 - .4byte .LLST72 - .uleb128 0x33 - .4byte 0x26f8 - .8byte .LBB131 - .4byte .Ldebug_ranges0+0x150 + .4byte 0x168b + .8byte .LBB51 + .4byte .Ldebug_ranges0+0xc0 .byte 0x1 - .2byte 0x246 - .4byte 0x12f5 - .uleb128 0x34 - .4byte 0x2713 - .4byte .LLST73 - .uleb128 0x34 - .4byte 0x2708 - .4byte .LLST74 - .uleb128 0x2f - .8byte .LVL201 - .4byte 0x2736 - .uleb128 0x30 + .2byte 0x1ef + .4byte 0x1043 + .uleb128 0x37 + .4byte 0x16a6 + .4byte .LLST34 + .uleb128 0x37 + .4byte 0x169b + .4byte .LLST35 + .uleb128 0x32 + .8byte .LVL140 + .4byte 0x177e + .uleb128 0x31 .uleb128 0x1 .byte 0x50 .uleb128 0x2 .byte 0x84 .sleb128 0 - .uleb128 0x30 + .uleb128 0x31 .uleb128 0x1 .byte 0x51 .uleb128 0x3 @@ -4851,78 +3399,75 @@ __func__.6107: .2byte 0x8000 .byte 0 .byte 0 - .uleb128 0x33 - .4byte 0x214c - .8byte .LBB135 - .4byte .Ldebug_ranges0+0x180 - .byte 0x1 - .2byte 0x24a - .4byte 0x13a7 - .uleb128 0x34 - .4byte 0x2165 - .4byte .LLST75 - .uleb128 0x34 - .4byte 0x2159 - .4byte .LLST76 - .uleb128 0x35 - .4byte .Ldebug_ranges0+0x180 .uleb128 0x39 - .4byte 0x2171 - .uleb128 0x36 - .4byte 0x217d - .4byte .LLST77 - .uleb128 0x33 - .4byte 0x25b9 - .8byte .LBB137 - .4byte .Ldebug_ranges0+0x1b0 + .4byte 0x119c + .8byte .LBB57 + .4byte .Ldebug_ranges0+0x100 .byte 0x1 - .2byte 0x1f5 - .4byte 0x135a + .2byte 0x1f4 + .4byte 0x1112 + .uleb128 0x37 + .4byte 0x11d1 + .4byte .LLST36 + .uleb128 0x37 + .4byte 0x11c5 + .4byte .LLST37 + .uleb128 0x37 + .4byte 0x11b9 + .4byte .LLST38 + .uleb128 0x37 + .4byte 0x11ad + .4byte .LLST39 + .uleb128 0x2c + .4byte .Ldebug_ranges0+0x100 .uleb128 0x3a - .4byte 0x25df + .4byte 0x11dd + .4byte .LLST40 .uleb128 0x3a - .4byte 0x25d4 + .4byte 0x11e9 + .4byte .LLST41 .uleb128 0x3a - .4byte 0x25c9 - .byte 0 + .4byte 0x11f5 + .4byte .LLST42 .uleb128 0x3b - .8byte .LVL205 - .4byte 0x2741 - .4byte 0x137e + .8byte .LBB59 + .8byte .LBE59-.LBB59 + .4byte 0x10d8 + .uleb128 0x3a + .4byte 0x1202 + .4byte .LLST43 + .uleb128 0x2c + .4byte .Ldebug_ranges0+0x130 + .uleb128 0x3c + .4byte 0x120d + .uleb128 0x2c + .4byte .Ldebug_ranges0+0x160 + .uleb128 0x3a + .4byte 0x121a + .4byte .LLST44 + .byte 0 + .byte 0 + .byte 0 .uleb128 0x30 + .8byte .LVL146 + .4byte 0x1767 + .4byte 0x10f7 + .uleb128 0x31 .uleb128 0x1 .byte 0x50 - .uleb128 0x2 - .byte 0x87 - .sleb128 0 - .uleb128 0x30 + .uleb128 0x9 + .byte 0x3 + .8byte .LC6 + .byte 0 + .uleb128 0x32 + .8byte .LVL150 + .4byte 0x1789 + .uleb128 0x31 .uleb128 0x1 .byte 0x51 .uleb128 0x1 .byte 0x30 - .uleb128 0x30 - .uleb128 0x1 - .byte 0x52 - .uleb128 0x3 - .byte 0xa - .2byte 0x4b0 - .byte 0 - .uleb128 0x2f - .8byte .LVL209 - .4byte 0x274d - .uleb128 0x30 - .uleb128 0x1 - .byte 0x50 - .uleb128 0x2 - .byte 0x88 - .sleb128 0 - .uleb128 0x30 - .uleb128 0x1 - .byte 0x51 - .uleb128 0x9 - .byte 0x3 - .8byte .LANCHOR6 - .uleb128 0x30 + .uleb128 0x31 .uleb128 0x1 .byte 0x52 .uleb128 0x2 @@ -4931,2161 +3476,904 @@ __func__.6107: .byte 0 .byte 0 .byte 0 - .uleb128 0x33 - .4byte 0x229e - .8byte .LBB142 - .4byte .Ldebug_ranges0+0x1e0 - .byte 0x1 - .2byte 0x250 - .4byte 0x148e - .uleb128 0x34 - .4byte 0x22af - .4byte .LLST78 - .uleb128 0x35 - .4byte .Ldebug_ranges0+0x1e0 - .uleb128 0x36 - .4byte 0x22bb - .4byte .LLST79 - .uleb128 0x39 - .4byte 0x22c7 - .uleb128 0x36 - .4byte 0x22d3 - .4byte .LLST80 - .uleb128 0x36 - .4byte 0x22dd - .4byte .LLST81 - .uleb128 0x36 - .4byte 0x22e7 - .4byte .LLST82 - .uleb128 0x36 - .4byte 0x22f1 - .4byte .LLST83 - .uleb128 0x36 - .4byte 0x22fb - .4byte .LLST84 - .uleb128 0x36 - .4byte 0x2307 - .4byte .LLST85 - .uleb128 0x36 - .4byte 0x2313 - .4byte .LLST86 - .uleb128 0x37 - .4byte 0x26f8 - .8byte .LBB144 - .8byte .LBE144-.LBB144 - .byte 0x1 - .2byte 0x1a0 - .4byte 0x1468 - .uleb128 0x34 - .4byte 0x2713 - .4byte .LLST87 - .uleb128 0x3a - .4byte 0x2708 - .uleb128 0x2f - .8byte .LVL212 - .4byte 0x2736 .uleb128 0x30 + .8byte .LVL125 + .4byte 0x14f5 + .4byte 0x112b + .uleb128 0x31 .uleb128 0x1 .byte 0x50 - .uleb128 0xa - .byte 0x86 - .sleb128 0 - .byte 0x3a - .byte 0x24 - .byte 0xc - .4byte 0xffffffff - .byte 0x1a - .uleb128 0x30 - .uleb128 0x1 - .byte 0x51 .uleb128 0x3 - .byte 0xa - .2byte 0x8000 - .byte 0 - .byte 0 - .uleb128 0x3c - .8byte .LBB146 - .8byte .LBE146-.LBB146 - .uleb128 0x36 - .4byte 0x2320 - .4byte .LLST88 - .uleb128 0x36 - .4byte 0x232c - .4byte .LLST89 - .byte 0 - .byte 0 - .byte 0 - .uleb128 0x37 - .4byte 0x26e0 - .8byte .LBB148 - .8byte .LBE148-.LBB148 - .byte 0x1 - .2byte 0x252 - .4byte 0x14b4 - .uleb128 0x34 - .4byte 0x26ec - .4byte .LLST90 + .byte 0xf3 + .uleb128 0x1 + .byte 0x52 .byte 0 - .uleb128 0x3b - .8byte .LVL194 - .4byte 0x24a6 - .4byte 0x14cb .uleb128 0x30 + .8byte .LVL128 + .4byte 0x154f + .4byte 0x1143 + .uleb128 0x31 .uleb128 0x1 .byte 0x50 - .uleb128 0x1 - .byte 0x31 + .uleb128 0x2 + .byte 0x85 + .sleb128 0 .byte 0 - .uleb128 0x2f - .8byte .LVL195 - .4byte 0x233a .uleb128 0x30 + .8byte .LVL129 + .4byte 0x1388 + .4byte 0x115b + .uleb128 0x31 .uleb128 0x1 .byte 0x51 .uleb128 0x2 .byte 0x84 .sleb128 0 + .byte 0 .uleb128 0x30 + .8byte .LVL132 + .4byte 0x1767 + .4byte 0x117a + .uleb128 0x31 .uleb128 0x1 - .byte 0x52 + .byte 0x50 + .uleb128 0x9 + .byte 0x3 + .8byte .LC4 + .byte 0 + .uleb128 0x32 + .8byte .LVL142 + .4byte 0x1767 + .uleb128 0x31 .uleb128 0x1 - .byte 0x40 + .byte 0x50 + .uleb128 0x9 + .byte 0x3 + .8byte .LC5 .byte 0 .byte 0 - .byte 0 - .uleb128 0x33 - .4byte 0x1a73 - .8byte .LBB153 - .4byte .Ldebug_ranges0+0x210 + .uleb128 0x8 + .byte 0x8 + .4byte 0xb78 + .uleb128 0x3d + .4byte .LASF251 .byte 0x1 - .2byte 0x335 - .4byte 0x1705 - .uleb128 0x34 - .4byte 0x1a90 - .4byte .LLST91 - .uleb128 0x34 - .4byte 0x1a84 - .4byte .LLST92 - .uleb128 0x35 - .4byte .Ldebug_ranges0+0x210 - .uleb128 0x39 - .4byte 0x1a9c - .uleb128 0x36 - .4byte 0x1aa8 - .4byte .LLST93 - .uleb128 0x36 - .4byte 0x1ab4 - .4byte .LLST94 - .uleb128 0x33 - .4byte 0x26e0 - .8byte .LBB155 - .4byte .Ldebug_ranges0+0x260 + .2byte 0x1a3 + .4byte 0x54 .byte 0x1 - .2byte 0x2dd - .4byte 0x155b - .uleb128 0x34 - .4byte 0x26ec - .4byte .LLST95 - .uleb128 0x38 - .8byte .LVL217 - .4byte 0x272a - .byte 0 - .uleb128 0x37 - .4byte 0x26f8 - .8byte .LBB158 - .8byte .LBE158-.LBB158 + .4byte 0x122a + .uleb128 0x3e + .4byte .LASF248 .byte 0x1 - .2byte 0x2c7 - .4byte 0x15ad - .uleb128 0x34 - .4byte 0x2713 - .4byte .LLST96 - .uleb128 0x34 - .4byte 0x2708 - .4byte .LLST97 - .uleb128 0x2f - .8byte .LVL260 - .4byte 0x2736 - .uleb128 0x30 - .uleb128 0x1 - .byte 0x50 - .uleb128 0xa - .byte 0x85 - .sleb128 0 - .byte 0x36 - .byte 0x24 - .byte 0x8 - .byte 0x20 - .byte 0x24 - .byte 0x8 - .byte 0x20 - .byte 0x26 - .uleb128 0x30 - .uleb128 0x1 - .byte 0x51 - .uleb128 0x3 - .byte 0xa - .2byte 0x8000 - .byte 0 - .byte 0 - .uleb128 0x33 - .4byte 0x26f8 - .8byte .LBB160 - .4byte .Ldebug_ranges0+0x290 + .2byte 0x1a3 + .4byte 0x122a + .uleb128 0x3e + .4byte .LASF202 .byte 0x1 - .2byte 0x2d4 - .4byte 0x15fb - .uleb128 0x34 - .4byte 0x2713 - .4byte .LLST98 - .uleb128 0x34 - .4byte 0x2708 - .4byte .LLST99 - .uleb128 0x2f - .8byte .LVL268 - .4byte 0x2736 - .uleb128 0x30 - .uleb128 0x1 - .byte 0x50 - .uleb128 0xa - .byte 0x84 - .sleb128 0 - .byte 0x33 - .byte 0x24 - .byte 0x8 - .byte 0x20 - .byte 0x24 - .byte 0x8 - .byte 0x20 - .byte 0x26 - .uleb128 0x30 - .uleb128 0x1 - .byte 0x51 - .uleb128 0x3 - .byte 0xa - .2byte 0x8000 - .byte 0 - .byte 0 - .uleb128 0x33 - .4byte 0x2188 - .8byte .LBB164 - .4byte .Ldebug_ranges0+0x2c0 + .2byte 0x1a3 + .4byte 0xbbf + .uleb128 0x3e + .4byte .LASF200 .byte 0x1 - .2byte 0x2db - .4byte 0x1669 - .uleb128 0x34 - .4byte 0x21a1 - .4byte .LLST100 - .uleb128 0x34 - .4byte 0x2195 - .4byte .LLST101 - .uleb128 0x35 - .4byte .Ldebug_ranges0+0x2c0 - .uleb128 0x36 - .4byte 0x21ad - .4byte .LLST102 - .uleb128 0x3d - .4byte 0x21b9 - .uleb128 0x1 - .byte 0x57 - .uleb128 0x36 - .4byte 0x21c5 - .4byte .LLST103 - .uleb128 0x36 - .4byte 0x21d1 - .4byte .LLST104 - .uleb128 0x36 - .4byte 0x21dd - .4byte .LLST105 - .uleb128 0x36 - .4byte 0x21e9 - .4byte .LLST106 - .uleb128 0x36 - .4byte 0x21f5 - .4byte .LLST107 - .byte 0 - .byte 0 - .uleb128 0x3b - .8byte .LVL254 - .4byte 0x24a6 - .4byte 0x1680 - .uleb128 0x30 - .uleb128 0x1 - .byte 0x50 - .uleb128 0x1 - .byte 0x35 - .byte 0 - .uleb128 0x3b - .8byte .LVL255 - .4byte 0x233a - .4byte 0x169d - .uleb128 0x30 - .uleb128 0x1 - .byte 0x51 - .uleb128 0x2 - .byte 0x84 - .sleb128 0 - .uleb128 0x30 - .uleb128 0x1 - .byte 0x52 - .uleb128 0x1 - .byte 0x40 + .2byte 0x1a3 + .4byte 0x54 + .uleb128 0x3f + .string "pic" + .byte 0x1 + .2byte 0x1a3 + .4byte 0x54 + .uleb128 0x40 + .string "lut" + .byte 0x1 + .2byte 0x1a4 + .4byte 0x122a + .uleb128 0x41 + .4byte .LASF201 + .byte 0x1 + .2byte 0x1a5 + .4byte 0x94 + .uleb128 0x41 + .4byte .LASF250 + .byte 0x1 + .2byte 0x1a5 + .4byte 0x94 + .uleb128 0x42 + .uleb128 0x40 + .string "f" + .byte 0x1 + .2byte 0x1ae + .4byte 0x54 + .uleb128 0x42 + .uleb128 0x40 + .string "old" + .byte 0x1 + .2byte 0x1af + .4byte 0x94 + .uleb128 0x42 + .uleb128 0x40 + .string "new" + .byte 0x1 + .2byte 0x1b0 + .4byte 0x94 .byte 0 - .uleb128 0x3b - .8byte .LVL261 - .4byte 0x1f02 - .4byte 0x16b5 - .uleb128 0x30 - .uleb128 0x1 - .byte 0x51 - .uleb128 0x2 - .byte 0x85 - .sleb128 0 .byte 0 - .uleb128 0x3b - .8byte .LVL262 - .4byte 0x24a6 - .4byte 0x16cc - .uleb128 0x30 - .uleb128 0x1 - .byte 0x50 - .uleb128 0x1 - .byte 0x34 .byte 0 - .uleb128 0x3b - .8byte .LVL263 - .4byte 0x233a - .4byte 0x16e9 - .uleb128 0x30 - .uleb128 0x1 - .byte 0x51 - .uleb128 0x2 - .byte 0x84 - .sleb128 0 - .uleb128 0x30 - .uleb128 0x1 - .byte 0x52 - .uleb128 0x1 - .byte 0x40 .byte 0 - .uleb128 0x2f - .8byte .LVL270 - .4byte 0x2050 - .uleb128 0x30 - .uleb128 0x1 - .byte 0x50 - .uleb128 0x2 - .byte 0x85 - .sleb128 0 - .uleb128 0x30 - .uleb128 0x1 - .byte 0x51 - .uleb128 0x2 - .byte 0x84 - .sleb128 0 + .uleb128 0x8 + .byte 0x8 + .4byte 0xae + .uleb128 0x3d + .4byte .LASF252 + .byte 0x1 + .2byte 0x17c + .4byte 0x54 + .byte 0x1 + .4byte 0x127c + .uleb128 0x3e + .4byte .LASF202 + .byte 0x1 + .2byte 0x17c + .4byte 0xbbf + .uleb128 0x3e + .4byte .LASF200 + .byte 0x1 + .2byte 0x17c + .4byte 0x54 + .uleb128 0x3f + .string "fix" + .byte 0x1 + .2byte 0x17c + .4byte 0x54 + .uleb128 0x40 + .string "f" + .byte 0x1 + .2byte 0x17e + .4byte 0x54 + .uleb128 0x41 + .4byte .LASF231 + .byte 0x1 + .2byte 0x17f + .4byte 0xbbf .byte 0 + .uleb128 0x3d + .4byte .LASF253 + .byte 0x1 + .2byte 0x165 + .4byte 0x54 + .byte 0x1 + .4byte 0x12c8 + .uleb128 0x3e + .4byte .LASF202 + .byte 0x1 + .2byte 0x165 + .4byte 0xbbf + .uleb128 0x3e + .4byte .LASF200 + .byte 0x1 + .2byte 0x165 + .4byte 0x54 + .uleb128 0x3e + .4byte .LASF254 + .byte 0x1 + .2byte 0x165 + .4byte 0x54 + .uleb128 0x40 + .string "f" + .byte 0x1 + .2byte 0x167 + .4byte 0x54 + .uleb128 0x41 + .4byte .LASF231 + .byte 0x1 + .2byte 0x168 + .4byte 0xbbf .byte 0 + .uleb128 0x3d + .4byte .LASF255 + .byte 0x1 + .2byte 0x156 + .4byte 0x54 + .byte 0x1 + .4byte 0x1308 + .uleb128 0x3e + .4byte .LASF202 + .byte 0x1 + .2byte 0x156 + .4byte 0xbbf + .uleb128 0x3e + .4byte .LASF200 + .byte 0x1 + .2byte 0x156 + .4byte 0x54 + .uleb128 0x40 + .string "f" + .byte 0x1 + .2byte 0x158 + .4byte 0x54 + .uleb128 0x41 + .4byte .LASF231 + .byte 0x1 + .2byte 0x159 + .4byte 0xbbf .byte 0 - .uleb128 0x33 - .4byte 0x1c12 - .8byte .LBB177 - .4byte .Ldebug_ranges0+0x310 + .uleb128 0x3d + .4byte .LASF256 .byte 0x1 - .2byte 0x307 - .4byte 0x17ca - .uleb128 0x34 - .4byte 0x1c2f - .4byte .LLST108 - .uleb128 0x34 - .4byte 0x1c23 - .4byte .LLST109 - .uleb128 0x35 - .4byte .Ldebug_ranges0+0x310 - .uleb128 0x36 - .4byte 0x1c3b - .4byte .LLST110 - .uleb128 0x36 - .4byte 0x1c47 - .4byte .LLST111 - .uleb128 0x37 - .4byte 0x26f8 - .8byte .LBB179 - .8byte .LBE179-.LBB179 + .2byte 0x13a + .4byte 0x54 .byte 0x1 - .2byte 0x28c - .4byte 0x1798 - .uleb128 0x34 - .4byte 0x2713 - .4byte .LLST112 - .uleb128 0x34 - .4byte 0x2708 - .4byte .LLST113 - .uleb128 0x2f - .8byte .LVL243 - .4byte 0x2736 - .uleb128 0x30 - .uleb128 0x1 - .byte 0x50 - .uleb128 0xa - .byte 0x84 - .sleb128 0 - .byte 0x36 - .byte 0x24 - .byte 0x8 - .byte 0x20 - .byte 0x24 - .byte 0x8 - .byte 0x20 - .byte 0x26 - .uleb128 0x30 - .uleb128 0x1 - .byte 0x51 - .uleb128 0x3 - .byte 0xa - .2byte 0x8000 + .4byte 0x1348 + .uleb128 0x3e + .4byte .LASF202 + .byte 0x1 + .2byte 0x13a + .4byte 0xbbf + .uleb128 0x3e + .4byte .LASF200 + .byte 0x1 + .2byte 0x13a + .4byte 0x54 + .uleb128 0x40 + .string "f" + .byte 0x1 + .2byte 0x13c + .4byte 0x54 + .uleb128 0x41 + .4byte .LASF231 + .byte 0x1 + .2byte 0x13d + .4byte 0xbbf .byte 0 + .uleb128 0x3d + .4byte .LASF257 + .byte 0x1 + .2byte 0x11d + .4byte 0x54 + .byte 0x1 + .4byte 0x1388 + .uleb128 0x3e + .4byte .LASF202 + .byte 0x1 + .2byte 0x11d + .4byte 0xbbf + .uleb128 0x3e + .4byte .LASF200 + .byte 0x1 + .2byte 0x11d + .4byte 0x54 + .uleb128 0x40 + .string "f" + .byte 0x1 + .2byte 0x11f + .4byte 0x54 + .uleb128 0x41 + .4byte .LASF231 + .byte 0x1 + .2byte 0x120 + .4byte 0xbbf .byte 0 - .uleb128 0x3b - .8byte .LVL237 - .4byte 0x24a6 - .4byte 0x17af - .uleb128 0x30 - .uleb128 0x1 - .byte 0x50 + .uleb128 0x43 + .4byte .LASF262 + .byte 0x1 + .2byte 0x105 + .4byte 0x54 + .8byte .LFB219 + .8byte .LFE219-.LFB219 .uleb128 0x1 - .byte 0x32 - .byte 0 + .byte 0x9c + .4byte 0x14e0 + .uleb128 0x2e + .4byte .LASF258 + .byte 0x1 + .2byte 0x105 + .4byte 0x54 + .4byte .LLST3 + .uleb128 0x2e + .4byte .LASF245 + .byte 0x1 + .2byte 0x105 + .4byte 0x54 + .4byte .LLST4 .uleb128 0x2f - .8byte .LVL238 - .4byte 0x233a - .uleb128 0x30 - .uleb128 0x1 - .byte 0x51 - .uleb128 0x2 - .byte 0x84 - .sleb128 0 - .uleb128 0x30 - .uleb128 0x1 - .byte 0x52 - .uleb128 0x1 - .byte 0x40 - .byte 0 - .byte 0 - .byte 0 - .uleb128 0x33 - .4byte 0x1ac1 - .8byte .LBB183 - .4byte .Ldebug_ranges0+0x340 + .4byte .LASF233 .byte 0x1 - .2byte 0x33b - .4byte 0x18ba - .uleb128 0x34 - .4byte 0x1ade - .4byte .LLST114 - .uleb128 0x34 - .4byte 0x1ad2 - .4byte .LLST115 - .uleb128 0x35 - .4byte .Ldebug_ranges0+0x340 - .uleb128 0x36 - .4byte 0x1aea - .4byte .LLST116 - .uleb128 0x36 - .4byte 0x1af6 - .4byte .LLST117 - .uleb128 0x37 - .4byte 0x26f8 - .8byte .LBB185 - .8byte .LBE185-.LBB185 + .2byte 0x107 + .4byte 0x4d9 + .4byte .LLST5 + .uleb128 0x2f + .4byte .LASF259 .byte 0x1 - .2byte 0x2b3 - .4byte 0x185d - .uleb128 0x34 - .4byte 0x2713 - .4byte .LLST118 - .uleb128 0x34 - .4byte 0x2708 - .4byte .LLST119 + .2byte 0x108 + .4byte 0x4d9 + .4byte .LLST6 .uleb128 0x2f - .8byte .LVL295 - .4byte 0x2736 + .4byte .LASF260 + .byte 0x1 + .2byte 0x109 + .4byte 0x54 + .4byte .LLST7 + .uleb128 0x44 + .4byte .LASF261 + .4byte 0x14f0 + .uleb128 0x9 + .byte 0x3 + .8byte __func__.6207 + .uleb128 0x39 + .4byte 0x1601 + .8byte .LBB8 + .4byte .Ldebug_ranges0+0 + .byte 0x1 + .2byte 0x11a + .4byte 0x14b7 + .uleb128 0x37 + .4byte 0x1611 + .4byte .LLST8 + .uleb128 0x2c + .4byte .Ldebug_ranges0+0 + .uleb128 0x3a + .4byte 0x161c + .4byte .LLST9 + .uleb128 0x3a + .4byte 0x1627 + .4byte .LLST10 + .uleb128 0x3a + .4byte 0x1632 + .4byte .LLST11 + .uleb128 0x3a + .4byte 0x163d + .4byte .LLST12 + .uleb128 0x3a + .4byte 0x1648 + .4byte .LLST13 + .uleb128 0x3a + .4byte 0x1653 + .4byte .LLST14 + .uleb128 0x3a + .4byte 0x165c + .4byte .LLST15 + .uleb128 0x3a + .4byte 0x1667 + .4byte .LLST16 .uleb128 0x30 + .8byte .LVL26 + .4byte 0x1767 + .4byte 0x149a + .uleb128 0x31 .uleb128 0x1 .byte 0x50 - .uleb128 0xa - .byte 0x85 - .sleb128 0 - .byte 0x36 - .byte 0x24 - .byte 0x8 - .byte 0x20 - .byte 0x24 - .byte 0x8 - .byte 0x20 - .byte 0x26 - .uleb128 0x30 - .uleb128 0x1 - .byte 0x51 - .uleb128 0x3 - .byte 0xa - .2byte 0x8000 - .byte 0 + .uleb128 0x9 + .byte 0x3 + .8byte .LC1 .byte 0 - .uleb128 0x38 - .8byte .LVL247 - .4byte 0x1f02 - .uleb128 0x3b - .8byte .LVL287 - .4byte 0x24a6 - .4byte 0x1881 - .uleb128 0x30 + .uleb128 0x32 + .8byte .LVL69 + .4byte 0x1767 + .uleb128 0x31 .uleb128 0x1 .byte 0x50 - .uleb128 0x1 - .byte 0x36 + .uleb128 0x9 + .byte 0x3 + .8byte .LC2 .byte 0 - .uleb128 0x3b - .8byte .LVL288 - .4byte 0x233a - .4byte 0x189e - .uleb128 0x30 - .uleb128 0x1 - .byte 0x51 - .uleb128 0x2 - .byte 0x84 - .sleb128 0 - .uleb128 0x30 - .uleb128 0x1 - .byte 0x52 - .uleb128 0x1 - .byte 0x40 .byte 0 - .uleb128 0x2f - .8byte .LVL291 - .4byte 0x1c96 - .uleb128 0x30 + .byte 0 + .uleb128 0x32 + .8byte .LVL16 + .4byte 0x1767 + .uleb128 0x31 .uleb128 0x1 .byte 0x50 - .uleb128 0x2 - .byte 0x83 - .sleb128 0 - .uleb128 0x30 + .uleb128 0x9 + .byte 0x3 + .8byte .LC0 + .uleb128 0x31 .uleb128 0x1 .byte 0x51 - .uleb128 0x2 - .byte 0x84 - .sleb128 0 + .uleb128 0x9 + .byte 0x3 + .8byte .LANCHOR1 .byte 0 .byte 0 + .uleb128 0xa + .4byte 0xee + .4byte 0x14f0 + .uleb128 0xe + .4byte 0xda + .byte 0xe .byte 0 - .uleb128 0x33 - .4byte 0x1c54 - .8byte .LBB190 - .4byte .Ldebug_ranges0+0x370 - .byte 0x1 - .2byte 0x340 - .4byte 0x1a39 - .uleb128 0x34 - .4byte 0x1c71 - .4byte .LLST120 - .uleb128 0x34 - .4byte 0x1c65 - .4byte .LLST121 - .uleb128 0x35 - .4byte .Ldebug_ranges0+0x370 - .uleb128 0x36 - .4byte 0x1c7d - .4byte .LLST122 - .uleb128 0x36 - .4byte 0x1c89 - .4byte .LLST123 - .uleb128 0x33 - .4byte 0x26f8 - .8byte .LBB192 - .4byte .Ldebug_ranges0+0x3b0 + .uleb128 0x7 + .4byte 0x14e0 + .uleb128 0x45 + .4byte .LASF263 .byte 0x1 - .2byte 0x27a - .4byte 0x1941 - .uleb128 0x34 - .4byte 0x2713 - .4byte .LLST124 - .uleb128 0x34 - .4byte 0x2708 - .4byte .LLST125 - .uleb128 0x2f - .8byte .LVL303 - .4byte 0x2736 - .uleb128 0x30 - .uleb128 0x1 - .byte 0x50 - .uleb128 0x2 - .byte 0x84 - .sleb128 0 - .uleb128 0x30 + .byte 0xf2 + .4byte 0x54 + .8byte .LFB218 + .8byte .LFE218-.LFB218 .uleb128 0x1 - .byte 0x51 - .uleb128 0x3 - .byte 0xa - .2byte 0x8000 - .byte 0 - .byte 0 - .uleb128 0x33 - .4byte 0x1ffc - .8byte .LBB196 - .4byte .Ldebug_ranges0+0x3e0 + .byte 0x9c + .4byte 0x154f + .uleb128 0x46 + .4byte .LASF224 .byte 0x1 - .2byte 0x27e - .4byte 0x1a06 - .uleb128 0x34 - .4byte 0x2015 - .4byte .LLST126 - .uleb128 0x34 - .4byte 0x2009 - .4byte .LLST127 - .uleb128 0x35 - .4byte .Ldebug_ranges0+0x3e0 - .uleb128 0x39 - .4byte 0x2021 - .uleb128 0x36 - .4byte 0x202d - .4byte .LLST128 - .uleb128 0x36 - .4byte 0x2039 - .4byte .LLST129 - .uleb128 0x36 - .4byte 0x2045 - .4byte .LLST130 - .uleb128 0x33 - .4byte 0x25b9 - .8byte .LBB198 - .4byte .Ldebug_ranges0+0x420 + .byte 0xf2 + .4byte 0x54 + .4byte .LLST0 + .uleb128 0x28 + .4byte .LASF264 .byte 0x1 - .2byte 0x21b - .4byte 0x19c0 - .uleb128 0x34 - .4byte 0x25df - .4byte .LLST131 - .uleb128 0x3a - .4byte 0x25d4 - .uleb128 0x34 - .4byte 0x25c9 - .4byte .LLST132 - .byte 0 - .uleb128 0x3b - .8byte .LVL309 - .4byte 0x2741 - .4byte 0x19dd - .uleb128 0x30 - .uleb128 0x1 - .byte 0x50 - .uleb128 0x2 - .byte 0x83 - .sleb128 0 - .uleb128 0x30 - .uleb128 0x1 - .byte 0x51 - .uleb128 0x1 - .byte 0x30 - .byte 0 - .uleb128 0x2f - .8byte .LVL319 - .4byte 0x274d - .uleb128 0x30 - .uleb128 0x1 - .byte 0x50 - .uleb128 0x2 - .byte 0x86 - .sleb128 0 - .uleb128 0x30 - .uleb128 0x1 - .byte 0x51 - .uleb128 0x9 - .byte 0x3 - .8byte gray32_data - .uleb128 0x30 - .uleb128 0x1 - .byte 0x52 - .uleb128 0x2 - .byte 0x84 - .sleb128 0 - .byte 0 - .byte 0 - .byte 0 - .uleb128 0x3b - .8byte .LVL297 - .4byte 0x24a6 - .4byte 0x1a1d - .uleb128 0x30 - .uleb128 0x1 - .byte 0x50 - .uleb128 0x1 - .byte 0x37 - .byte 0 - .uleb128 0x2f - .8byte .LVL298 - .4byte 0x233a - .uleb128 0x30 - .uleb128 0x1 - .byte 0x51 - .uleb128 0x2 - .byte 0x84 - .sleb128 0 - .uleb128 0x30 + .byte 0xf4 + .4byte 0x54 .uleb128 0x1 .byte 0x52 - .uleb128 0x2 - .byte 0x8 - .byte 0x20 - .byte 0 - .byte 0 - .byte 0 - .uleb128 0x3b - .8byte .LVL249 - .4byte 0x1b03 - .4byte 0x1a57 - .uleb128 0x30 - .uleb128 0x1 - .byte 0x50 - .uleb128 0x2 - .byte 0x83 - .sleb128 0 - .uleb128 0x30 - .uleb128 0x1 - .byte 0x51 - .uleb128 0x2 - .byte 0x84 - .sleb128 0 - .byte 0 - .uleb128 0x2f - .8byte .LVL252 - .4byte 0x271f - .uleb128 0x30 - .uleb128 0x1 - .byte 0x50 - .uleb128 0x9 - .byte 0x3 - .8byte .LC4 - .byte 0 - .byte 0 - .uleb128 0x3e - .4byte .LASF353 + .uleb128 0x47 + .4byte .LASF265 .byte 0x1 - .2byte 0x2bc + .byte 0xf5 .4byte 0x54 + .4byte .LLST1 + .uleb128 0x48 + .string "i" .byte 0x1 - .4byte 0x1ac1 - .uleb128 0x3f - .4byte .LASF345 + .byte 0xf6 + .4byte 0x54 + .4byte .LLST2 + .byte 0 + .uleb128 0x49 + .4byte .LASF266 .byte 0x1 - .2byte 0x2bc - .4byte 0xe5f - .uleb128 0x3f - .4byte .LASF350 + .byte 0xd8 + .4byte 0x94 .byte 0x1 - .2byte 0x2bc - .4byte 0x54 - .uleb128 0x31 - .4byte .LASF351 + .4byte 0x1581 + .uleb128 0x4a + .4byte .LASF241 .byte 0x1 - .2byte 0x2be - .4byte 0xe34 - .uleb128 0x31 - .4byte .LASF352 + .byte 0xd8 + .4byte 0xb01 + .uleb128 0x27 + .4byte .LASF267 .byte 0x1 - .2byte 0x2bf - .4byte 0x54 - .uleb128 0x31 - .4byte .LASF309 + .byte 0xda + .4byte 0x1581 + .uleb128 0x27 + .4byte .LASF258 .byte 0x1 - .2byte 0x2c0 + .byte 0xdb .4byte 0x54 .byte 0 - .uleb128 0x3e - .4byte .LASF354 - .byte 0x1 - .2byte 0x2a7 - .4byte 0x54 - .byte 0x1 - .4byte 0x1b03 - .uleb128 0x3f - .4byte .LASF345 + .uleb128 0x8 + .byte 0x8 + .4byte 0x9e + .uleb128 0x49 + .4byte .LASF268 .byte 0x1 - .2byte 0x2a7 - .4byte 0xe5f - .uleb128 0x3f - .4byte .LASF350 + .byte 0xc0 + .4byte 0x1581 .byte 0x1 - .2byte 0x2a7 - .4byte 0x54 - .uleb128 0x31 - .4byte .LASF352 + .4byte 0x15ae + .uleb128 0x4a + .4byte .LASF233 .byte 0x1 - .2byte 0x2a9 - .4byte 0x54 - .uleb128 0x31 - .4byte .LASF309 + .byte 0xc0 + .4byte 0xd70 + .uleb128 0x27 + .4byte .LASF267 .byte 0x1 - .2byte 0x2aa - .4byte 0x54 + .byte 0xc2 + .4byte 0x1581 .byte 0 - .uleb128 0x40 - .4byte .LASF357 + .uleb128 0x4b + .4byte .LASF269 .byte 0x1 - .2byte 0x295 + .byte 0xb0 .4byte 0x54 - .8byte .LFB229 - .8byte .LFE229-.LFB229 + .8byte .LFB215 + .8byte .LFE215-.LFB215 .uleb128 0x1 .byte 0x9c - .4byte 0x1c12 - .uleb128 0x2d - .4byte .LASF345 - .byte 0x1 - .2byte 0x295 - .4byte 0xe5f - .4byte .LLST33 - .uleb128 0x2d - .4byte .LASF350 - .byte 0x1 - .2byte 0x295 - .4byte 0x54 - .4byte .LLST34 - .uleb128 0x2d - .4byte .LASF346 + .4byte 0x1601 + .uleb128 0x46 + .4byte .LASF231 .byte 0x1 - .2byte 0x295 - .4byte 0xd88 - .4byte .LLST35 - .uleb128 0x2e - .4byte .LASF352 + .byte 0xb0 + .4byte 0xbbf + .4byte .LLST22 + .uleb128 0x46 + .4byte .LASF33 .byte 0x1 - .2byte 0x297 + .byte 0xb0 .4byte 0x54 - .4byte .LLST36 - .uleb128 0x2e - .4byte .LASF309 + .4byte .LLST23 + .uleb128 0x2c + .4byte .Ldebug_ranges0+0x90 + .uleb128 0x48 + .string "i" .byte 0x1 - .2byte 0x298 + .byte 0xb5 .4byte 0x54 - .4byte .LLST37 - .uleb128 0x37 - .4byte 0x26f8 - .8byte .LBB56 - .8byte .LBE56-.LBB56 - .byte 0x1 - .2byte 0x29e - .4byte 0x1bc7 - .uleb128 0x34 - .4byte 0x2713 - .4byte .LLST38 - .uleb128 0x34 - .4byte 0x2708 - .4byte .LLST39 - .uleb128 0x2f - .8byte .LVL148 - .4byte 0x2736 - .uleb128 0x30 - .uleb128 0x1 - .byte 0x50 - .uleb128 0xa - .byte 0x83 - .sleb128 0 - .byte 0x36 - .byte 0x24 - .byte 0x8 - .byte 0x20 - .byte 0x24 - .byte 0x8 - .byte 0x20 - .byte 0x26 - .uleb128 0x30 - .uleb128 0x1 - .byte 0x51 - .uleb128 0x3 - .byte 0xa - .2byte 0x8000 - .byte 0 - .byte 0 - .uleb128 0x3b - .8byte .LVL143 - .4byte 0x24a6 - .4byte 0x1be0 - .uleb128 0x30 - .uleb128 0x1 - .byte 0x50 - .uleb128 0x3 - .byte 0xf3 - .uleb128 0x1 - .byte 0x52 - .byte 0 - .uleb128 0x3b - .8byte .LVL144 - .4byte 0x233a - .4byte 0x1bfd - .uleb128 0x30 - .uleb128 0x1 - .byte 0x51 - .uleb128 0x2 - .byte 0x83 - .sleb128 0 - .uleb128 0x30 - .uleb128 0x1 - .byte 0x52 - .uleb128 0x1 - .byte 0x40 - .byte 0 - .uleb128 0x2f - .8byte .LVL149 - .4byte 0x1f02 - .uleb128 0x30 - .uleb128 0x1 - .byte 0x51 - .uleb128 0x2 - .byte 0x83 - .sleb128 0 + .4byte .LLST24 .byte 0 .byte 0 - .uleb128 0x3e - .4byte .LASF355 + .uleb128 0x49 + .4byte .LASF270 .byte 0x1 - .2byte 0x283 + .byte 0x39 .4byte 0x54 .byte 0x1 - .4byte 0x1c54 - .uleb128 0x3f - .4byte .LASF345 + .4byte 0x1673 + .uleb128 0x4a + .4byte .LASF201 .byte 0x1 - .2byte 0x283 - .4byte 0xe5f - .uleb128 0x3f - .4byte .LASF350 + .byte 0x39 + .4byte 0x4d9 + .uleb128 0x27 + .4byte .LASF271 .byte 0x1 - .2byte 0x283 - .4byte 0x54 - .uleb128 0x31 - .4byte .LASF352 + .byte 0x3b + .4byte 0x7f + .uleb128 0x27 + .4byte .LASF272 .byte 0x1 - .2byte 0x285 - .4byte 0x54 - .uleb128 0x31 - .4byte .LASF309 + .byte 0x3b + .4byte 0x7f + .uleb128 0x27 + .4byte .LASF273 .byte 0x1 - .2byte 0x286 - .4byte 0x54 - .byte 0 - .uleb128 0x3e - .4byte .LASF356 + .byte 0x3c + .4byte 0x7f + .uleb128 0x27 + .4byte .LASF260 .byte 0x1 - .2byte 0x271 - .4byte 0x54 + .byte 0x3d + .4byte 0x7f + .uleb128 0x27 + .4byte .LASF274 .byte 0x1 - .4byte 0x1c96 - .uleb128 0x3f - .4byte .LASF345 + .byte 0x3e + .4byte 0x34 + .uleb128 0x4c + .string "i" .byte 0x1 - .2byte 0x271 - .4byte 0xe5f - .uleb128 0x3f - .4byte .LASF350 + .byte 0x3f + .4byte 0x34 + .uleb128 0x27 + .4byte .LASF275 .byte 0x1 - .2byte 0x271 - .4byte 0x54 - .uleb128 0x31 - .4byte .LASF352 - .byte 0x1 - .2byte 0x273 - .4byte 0x54 - .uleb128 0x31 - .4byte .LASF309 + .byte 0x40 + .4byte 0x15a + .uleb128 0x27 + .4byte .LASF276 .byte 0x1 - .2byte 0x274 + .byte 0x41 .4byte 0x54 .byte 0 - .uleb128 0x40 - .4byte .LASF358 - .byte 0x1 - .2byte 0x257 - .4byte 0x54 - .8byte .LFB226 - .8byte .LFE226-.LFB226 + .uleb128 0x4d + .4byte .LASF288 + .byte 0x2 + .byte 0x4f + .byte 0x3 + .4byte 0x168b + .uleb128 0x4a + .4byte .LASF277 + .byte 0x2 + .byte 0x4f + .4byte 0x190 + .byte 0 + .uleb128 0x49 + .4byte .LASF278 + .byte 0x2 + .byte 0x38 + .4byte 0x14d + .byte 0x3 + .4byte 0x16b2 + .uleb128 0x4a + .4byte .LASF33 + .byte 0x2 + .byte 0x38 + .4byte 0x10b + .uleb128 0x4a + .4byte .LASF279 + .byte 0x2 + .byte 0x38 + .4byte 0x142 + .byte 0 + .uleb128 0x4e + .4byte 0x154f + .8byte .LFB217 + .8byte .LFE217-.LFB217 .uleb128 0x1 .byte 0x9c - .4byte 0x1eb4 - .uleb128 0x2d - .4byte .LASF345 - .byte 0x1 - .2byte 0x257 - .4byte 0xe5f - .4byte .LLST40 - .uleb128 0x2d - .4byte .LASF350 - .byte 0x1 - .2byte 0x257 - .4byte 0x54 - .4byte .LLST41 - .uleb128 0x31 - .4byte .LASF351 - .byte 0x1 - .2byte 0x259 - .4byte 0xe34 - .uleb128 0x2e - .4byte .LASF352 - .byte 0x1 - .2byte 0x25a - .4byte 0x54 - .4byte .LLST42 - .uleb128 0x2e - .4byte .LASF309 - .byte 0x1 - .2byte 0x25b - .4byte 0x54 - .4byte .LLST43 + .4byte 0x1767 .uleb128 0x37 - .4byte 0x26f8 - .8byte .LBB66 - .8byte .LBE66-.LBB66 + .4byte 0x155f + .4byte .LLST17 + .uleb128 0x3c + .4byte 0x156a + .uleb128 0x3c + .4byte 0x1575 + .uleb128 0x3b + .8byte .LBB20 + .8byte .LBE20-.LBB20 + .4byte 0x174b + .uleb128 0x37 + .4byte 0x155f + .4byte .LLST18 + .uleb128 0x4f + .8byte .LBB21 + .8byte .LBE21-.LBB21 + .uleb128 0x3c + .4byte 0x16d6 + .uleb128 0x3a + .4byte 0x16db + .4byte .LLST19 + .uleb128 0x50 + .4byte 0x1587 + .8byte .LBB22 + .4byte .Ldebug_ranges0+0x50 .byte 0x1 - .2byte 0x261 - .4byte 0x1d56 - .uleb128 0x34 - .4byte 0x2713 - .4byte .LLST44 - .uleb128 0x34 - .4byte 0x2708 - .4byte .LLST45 - .uleb128 0x2f - .8byte .LVL159 - .4byte 0x2736 - .uleb128 0x30 - .uleb128 0x1 - .byte 0x50 - .uleb128 0xa - .byte 0x83 - .sleb128 0 - .byte 0x33 - .byte 0x24 - .byte 0x8 - .byte 0x20 - .byte 0x24 - .byte 0x8 - .byte 0x20 - .byte 0x26 - .uleb128 0x30 - .uleb128 0x1 - .byte 0x51 - .uleb128 0x3 - .byte 0xa - .2byte 0x8000 + .byte 0xed + .uleb128 0x37 + .4byte 0x1597 + .4byte .LLST20 + .uleb128 0x2c + .4byte .Ldebug_ranges0+0x50 + .uleb128 0x3a + .4byte 0x15a2 + .4byte .LLST21 .byte 0 .byte 0 - .uleb128 0x33 - .4byte 0x2200 - .8byte .LBB68 - .4byte .Ldebug_ranges0+0xb0 - .byte 0x1 - .2byte 0x26a - .4byte 0x1e2b - .uleb128 0x34 - .4byte 0x2211 - .4byte .LLST46 - .uleb128 0x35 - .4byte .Ldebug_ranges0+0xb0 - .uleb128 0x36 - .4byte 0x221d - .4byte .LLST47 - .uleb128 0x39 - .4byte 0x2229 - .uleb128 0x36 - .4byte 0x2235 - .4byte .LLST48 - .uleb128 0x36 - .4byte 0x2241 - .4byte .LLST49 - .uleb128 0x36 - .4byte 0x224d - .4byte .LLST50 - .uleb128 0x36 - .4byte 0x2259 - .4byte .LLST51 - .uleb128 0x36 - .4byte 0x2265 - .4byte .LLST52 - .uleb128 0x36 - .4byte 0x2271 - .4byte .LLST53 - .uleb128 0x36 - .4byte 0x227d - .4byte .LLST54 - .uleb128 0x36 - .4byte 0x2287 - .4byte .LLST55 - .uleb128 0x36 - .4byte 0x2291 - .4byte .LLST56 - .uleb128 0x41 - .4byte 0x26f8 - .8byte .LBB70 - .8byte .LBE70-.LBB70 - .byte 0x1 - .2byte 0x1c1 - .uleb128 0x34 - .4byte 0x2713 - .4byte .LLST57 - .uleb128 0x34 - .4byte 0x2708 - .4byte .LLST58 - .uleb128 0x2f - .8byte .LVL163 - .4byte 0x2736 - .uleb128 0x30 + .byte 0 + .byte 0 + .uleb128 0x32 + .8byte .LVL80 + .4byte 0x1767 + .uleb128 0x31 .uleb128 0x1 .byte 0x50 - .uleb128 0xa - .byte 0x83 - .sleb128 0 - .byte 0x36 - .byte 0x24 - .byte 0xc - .4byte 0xffffffff - .byte 0x1a - .uleb128 0x30 - .uleb128 0x1 - .byte 0x51 - .uleb128 0x3 - .byte 0xa - .2byte 0x8000 - .byte 0 + .uleb128 0x9 + .byte 0x3 + .8byte .LC3 .byte 0 .byte 0 + .uleb128 0x51 + .4byte .LASF280 + .4byte .LASF280 + .byte 0x17 + .byte 0x13 + .uleb128 0x52 + .4byte .LASF281 + .4byte .LASF281 + .byte 0x15 + .2byte 0x399 + .uleb128 0x51 + .4byte .LASF282 + .4byte .LASF282 + .byte 0x2 + .byte 0x36 + .uleb128 0x52 + .4byte .LASF283 + .4byte .LASF283 + .byte 0x15 + .2byte 0x16c .byte 0 - .uleb128 0x37 - .4byte 0x26e0 - .8byte .LBB73 - .8byte .LBE73-.LBB73 + .section .debug_abbrev,"",@progbits +.Ldebug_abbrev0: + .uleb128 0x1 + .uleb128 0x11 .byte 0x1 - .2byte 0x26c - .4byte 0x1e65 - .uleb128 0x34 - .4byte 0x26ec - .4byte .LLST59 - .uleb128 0x2f - .8byte .LVL167 - .4byte 0x272a - .uleb128 0x30 + .uleb128 0x25 + .uleb128 0xe + .uleb128 0x13 + .uleb128 0xb + .uleb128 0x3 + .uleb128 0xe + .uleb128 0x1b + .uleb128 0xe + .uleb128 0x55 + .uleb128 0x17 + .uleb128 0x11 .uleb128 0x1 - .byte 0x50 - .uleb128 0x2 - .byte 0x84 - .sleb128 0 + .uleb128 0x10 + .uleb128 0x17 .byte 0 .byte 0 - .uleb128 0x3b - .8byte .LVL154 - .4byte 0x24a6 - .4byte 0x1e7c - .uleb128 0x30 - .uleb128 0x1 - .byte 0x50 - .uleb128 0x1 - .byte 0x34 + .uleb128 0x2 + .uleb128 0x16 .byte 0 + .uleb128 0x3 + .uleb128 0xe + .uleb128 0x3a + .uleb128 0xb .uleb128 0x3b - .8byte .LVL155 - .4byte 0x233a - .4byte 0x1e99 - .uleb128 0x30 - .uleb128 0x1 - .byte 0x51 - .uleb128 0x2 - .byte 0x83 - .sleb128 0 - .uleb128 0x30 - .uleb128 0x1 - .byte 0x52 - .uleb128 0x1 - .byte 0x40 + .uleb128 0xb + .uleb128 0x49 + .uleb128 0x13 .byte 0 - .uleb128 0x2f - .8byte .LVL160 - .4byte 0x2050 - .uleb128 0x30 - .uleb128 0x1 - .byte 0x50 - .uleb128 0x2 - .byte 0x84 - .sleb128 0 - .uleb128 0x30 - .uleb128 0x1 - .byte 0x51 - .uleb128 0x2 - .byte 0x83 - .sleb128 0 .byte 0 + .uleb128 0x3 + .uleb128 0x24 .byte 0 + .uleb128 0xb + .uleb128 0xb .uleb128 0x3e - .4byte .LASF359 - .byte 0x1 - .2byte 0x23d - .4byte 0x54 - .byte 0x1 - .4byte 0x1f02 - .uleb128 0x3f - .4byte .LASF345 - .byte 0x1 - .2byte 0x23d - .4byte 0xe5f - .uleb128 0x3f - .4byte .LASF350 - .byte 0x1 - .2byte 0x23d - .4byte 0x54 - .uleb128 0x31 - .4byte .LASF351 - .byte 0x1 - .2byte 0x23f - .4byte 0xe34 - .uleb128 0x31 - .4byte .LASF352 - .byte 0x1 - .2byte 0x240 - .4byte 0x54 - .uleb128 0x31 - .4byte .LASF309 - .byte 0x1 - .2byte 0x241 - .4byte 0x54 + .uleb128 0xb + .uleb128 0x3 + .uleb128 0xe .byte 0 - .uleb128 0x42 - .4byte .LASF362 - .byte 0x1 - .2byte 0x229 - .8byte .LFB224 - .8byte .LFE224-.LFB224 - .uleb128 0x1 - .byte 0x9c - .4byte 0x1ffc - .uleb128 0x43 - .string "dst" - .byte 0x1 - .2byte 0x229 - .4byte 0xe59 - .4byte .LLST4 - .uleb128 0x2d - .4byte .LASF309 - .byte 0x1 - .2byte 0x229 - .4byte 0x54 - .4byte .LLST5 - .uleb128 0x31 - .4byte .LASF310 - .byte 0x1 - .2byte 0x22b - .4byte 0x34 - .uleb128 0x2e - .4byte .LASF360 - .byte 0x1 - .2byte 0x22c - .4byte 0x54 - .4byte .LLST6 - .uleb128 0x2e - .4byte .LASF361 - .byte 0x1 - .2byte 0x22d - .4byte 0x54 - .4byte .LLST7 - .uleb128 0x2c - .string "j" - .byte 0x1 - .2byte 0x22e - .4byte 0x54 - .4byte .LLST8 - .uleb128 0x37 - .4byte 0x25b9 - .8byte .LBB46 - .8byte .LBE46-.LBB46 - .byte 0x1 - .2byte 0x234 - .4byte 0x1fa6 - .uleb128 0x3a - .4byte 0x25df - .uleb128 0x3a - .4byte 0x25d4 - .uleb128 0x3a - .4byte 0x25c9 .byte 0 + .uleb128 0x4 + .uleb128 0x34 + .byte 0 + .uleb128 0x3 + .uleb128 0xe + .uleb128 0x3a + .uleb128 0xb .uleb128 0x3b - .8byte .LVL30 - .4byte 0x2741 - .4byte 0x1fca - .uleb128 0x30 - .uleb128 0x1 - .byte 0x50 - .uleb128 0x2 - .byte 0x85 - .sleb128 0 - .uleb128 0x30 - .uleb128 0x1 - .byte 0x51 - .uleb128 0x1 - .byte 0x30 - .uleb128 0x30 - .uleb128 0x1 - .byte 0x52 + .uleb128 0xb + .uleb128 0x49 + .uleb128 0x13 + .uleb128 0x3f + .uleb128 0x19 + .uleb128 0x3c + .uleb128 0x19 + .byte 0 + .byte 0 + .uleb128 0x5 + .uleb128 0x24 + .byte 0 + .uleb128 0xb + .uleb128 0xb + .uleb128 0x3e + .uleb128 0xb .uleb128 0x3 - .byte 0xa - .2byte 0x4b00 + .uleb128 0x8 + .byte 0 + .byte 0 + .uleb128 0x6 + .uleb128 0x16 .byte 0 - .uleb128 0x44 - .8byte .LVL40 - .4byte 0x274d - .uleb128 0x30 - .uleb128 0x1 - .byte 0x50 .uleb128 0x3 - .byte 0xf3 - .uleb128 0x1 - .byte 0x50 - .uleb128 0x30 - .uleb128 0x1 - .byte 0x51 - .uleb128 0x9 - .byte 0x3 - .8byte gray_data - .uleb128 0x30 - .uleb128 0x1 - .byte 0x52 + .uleb128 0x8 + .uleb128 0x3a .uleb128 0xb - .byte 0xf3 - .uleb128 0x1 - .byte 0x51 - .byte 0x36 - .byte 0x24 - .byte 0x8 - .byte 0x20 - .byte 0x24 - .byte 0x8 - .byte 0x20 - .byte 0x26 + .uleb128 0x3b + .uleb128 0xb + .uleb128 0x49 + .uleb128 0x13 .byte 0 .byte 0 - .uleb128 0x45 - .4byte .LASF364 - .byte 0x1 - .2byte 0x210 - .byte 0x1 - .4byte 0x2050 - .uleb128 0x46 - .string "dst" - .byte 0x1 - .2byte 0x210 - .4byte 0xe59 - .uleb128 0x3f - .4byte .LASF309 - .byte 0x1 - .2byte 0x210 - .4byte 0x54 - .uleb128 0x31 - .4byte .LASF310 - .byte 0x1 - .2byte 0x212 - .4byte 0x34 - .uleb128 0x31 - .4byte .LASF360 - .byte 0x1 - .2byte 0x213 - .4byte 0x54 - .uleb128 0x31 - .4byte .LASF361 - .byte 0x1 - .2byte 0x214 - .4byte 0x54 - .uleb128 0x32 - .string "j" - .byte 0x1 - .2byte 0x215 - .4byte 0x54 + .uleb128 0x7 + .uleb128 0x26 .byte 0 - .uleb128 0x42 - .4byte .LASF363 - .byte 0x1 - .2byte 0x1fc - .8byte .LFB222 - .8byte .LFE222-.LFB222 - .uleb128 0x1 - .byte 0x9c - .4byte 0x214c - .uleb128 0x43 - .string "dst" - .byte 0x1 - .2byte 0x1fc - .4byte 0xe59 - .4byte .LLST9 - .uleb128 0x2d - .4byte .LASF309 - .byte 0x1 - .2byte 0x1fc - .4byte 0x54 - .4byte .LLST10 - .uleb128 0x2e - .4byte .LASF360 - .byte 0x1 - .2byte 0x1fe - .4byte 0x54 - .4byte .LLST11 - .uleb128 0x2e - .4byte .LASF361 - .byte 0x1 - .2byte 0x1ff - .4byte 0x54 - .4byte .LLST12 - .uleb128 0x2c - .string "j" - .byte 0x1 - .2byte 0x200 - .4byte 0x54 - .4byte .LLST13 - .uleb128 0x47 - .4byte .Ldebug_ranges0+0x30 - .4byte 0x20f6 - .uleb128 0x31 - .4byte .LASF310 - .byte 0x1 - .2byte 0x206 - .4byte 0x34 - .uleb128 0x48 - .4byte 0x25b9 - .8byte .LBB49 - .4byte .Ldebug_ranges0+0x80 - .byte 0x1 - .2byte 0x207 - .uleb128 0x3a - .4byte 0x25df - .uleb128 0x3a - .4byte 0x25d4 - .uleb128 0x3a - .4byte 0x25c9 + .uleb128 0x49 + .uleb128 0x13 .byte 0 .byte 0 - .uleb128 0x3b - .8byte .LVL44 - .4byte 0x2741 - .4byte 0x211a - .uleb128 0x30 - .uleb128 0x1 - .byte 0x50 - .uleb128 0x2 - .byte 0x83 - .sleb128 0 - .uleb128 0x30 - .uleb128 0x1 - .byte 0x51 - .uleb128 0x1 - .byte 0x30 - .uleb128 0x30 - .uleb128 0x1 - .byte 0x52 - .uleb128 0x3 - .byte 0xa - .2byte 0x960 + .uleb128 0x8 + .uleb128 0xf + .byte 0 + .uleb128 0xb + .uleb128 0xb + .uleb128 0x49 + .uleb128 0x13 + .byte 0 .byte 0 - .uleb128 0x44 - .8byte .LVL53 - .4byte 0x274d - .uleb128 0x30 - .uleb128 0x1 - .byte 0x50 - .uleb128 0x3 - .byte 0xf3 - .uleb128 0x1 - .byte 0x50 - .uleb128 0x30 - .uleb128 0x1 - .byte 0x51 .uleb128 0x9 - .byte 0x3 - .8byte .LANCHOR2 - .uleb128 0x30 - .uleb128 0x1 - .byte 0x52 + .uleb128 0xf + .byte 0 + .uleb128 0xb .uleb128 0xb - .byte 0xf3 - .uleb128 0x1 - .byte 0x51 - .byte 0x33 - .byte 0x24 - .byte 0x8 - .byte 0x20 - .byte 0x24 - .byte 0x8 - .byte 0x20 - .byte 0x26 .byte 0 .byte 0 - .uleb128 0x45 - .4byte .LASF365 - .byte 0x1 - .2byte 0x1ee - .byte 0x1 - .4byte 0x2188 - .uleb128 0x46 - .string "dst" - .byte 0x1 - .2byte 0x1ee - .4byte 0xe59 - .uleb128 0x3f - .4byte .LASF309 - .byte 0x1 - .2byte 0x1ee - .4byte 0x54 - .uleb128 0x31 - .4byte .LASF310 - .byte 0x1 - .2byte 0x1f0 - .4byte 0x34 - .uleb128 0x32 - .string "j" + .uleb128 0xa + .uleb128 0x1 .byte 0x1 - .2byte 0x1f1 - .4byte 0x54 + .uleb128 0x49 + .uleb128 0x13 + .uleb128 0x1 + .uleb128 0x13 .byte 0 - .uleb128 0x45 - .4byte .LASF366 - .byte 0x1 - .2byte 0x1d5 - .byte 0x1 - .4byte 0x2200 - .uleb128 0x3f - .4byte .LASF351 - .byte 0x1 - .2byte 0x1d5 - .4byte 0xe5f - .uleb128 0x3f - .4byte .LASF345 - .byte 0x1 - .2byte 0x1d6 - .4byte 0xe5f - .uleb128 0x31 - .4byte .LASF367 - .byte 0x1 - .2byte 0x1d8 - .4byte 0x54 - .uleb128 0x31 - .4byte .LASF368 - .byte 0x1 - .2byte 0x1d8 - .4byte 0x54 - .uleb128 0x31 - .4byte .LASF369 - .byte 0x1 - .2byte 0x1d8 - .4byte 0x54 - .uleb128 0x31 - .4byte .LASF370 - .byte 0x1 - .2byte 0x1d9 - .4byte 0xe59 - .uleb128 0x31 - .4byte .LASF371 - .byte 0x1 - .2byte 0x1d9 - .4byte 0xe59 - .uleb128 0x31 - .4byte .LASF372 - .byte 0x1 - .2byte 0x1da - .4byte 0x54 - .uleb128 0x32 - .string "i" - .byte 0x1 - .2byte 0x1db - .4byte 0x54 .byte 0 - .uleb128 0x3e - .4byte .LASF373 - .byte 0x1 - .2byte 0x1b5 - .4byte 0xe59 - .byte 0x1 - .4byte 0x229e - .uleb128 0x3f - .4byte .LASF351 - .byte 0x1 - .2byte 0x1b5 - .4byte 0xe5f - .uleb128 0x31 - .4byte .LASF370 - .byte 0x1 - .2byte 0x1b7 - .4byte 0xe59 - .uleb128 0x31 - .4byte .LASF371 - .byte 0x1 - .2byte 0x1b7 - .4byte 0xe59 - .uleb128 0x31 - .4byte .LASF368 - .byte 0x1 - .2byte 0x1b8 - .4byte 0x54 - .uleb128 0x31 - .4byte .LASF369 - .byte 0x1 - .2byte 0x1b8 - .4byte 0x54 - .uleb128 0x31 - .4byte .LASF374 - .byte 0x1 - .2byte 0x1b8 - .4byte 0x54 - .uleb128 0x31 - .4byte .LASF375 - .byte 0x1 - .2byte 0x1b9 - .4byte 0x54 - .uleb128 0x31 - .4byte .LASF376 - .byte 0x1 - .2byte 0x1b9 - .4byte 0x54 - .uleb128 0x32 - .string "num" - .byte 0x1 - .2byte 0x1ba - .4byte 0x54 - .uleb128 0x32 - .string "i" - .byte 0x1 - .2byte 0x1bb - .4byte 0x54 - .uleb128 0x32 - .string "j" - .byte 0x1 - .2byte 0x1bb - .4byte 0x54 - .uleb128 0x32 - .string "len" - .byte 0x1 - .2byte 0x1bc - .4byte 0x54 + .uleb128 0xb + .uleb128 0x21 .byte 0 - .uleb128 0x3e - .4byte .LASF377 - .byte 0x1 - .2byte 0x195 - .4byte 0xe59 - .byte 0x1 - .4byte 0x233a + .byte 0 + .byte 0 + .uleb128 0xc + .uleb128 0x34 + .byte 0 + .uleb128 0x3 + .uleb128 0xe + .uleb128 0x3a + .uleb128 0xb + .uleb128 0x3b + .uleb128 0x5 + .uleb128 0x49 + .uleb128 0x13 .uleb128 0x3f - .4byte .LASF351 - .byte 0x1 - .2byte 0x195 - .4byte 0xe5f - .uleb128 0x31 - .4byte .LASF370 - .byte 0x1 - .2byte 0x197 - .4byte 0xe59 - .uleb128 0x31 - .4byte .LASF371 - .byte 0x1 - .2byte 0x197 - .4byte 0xe59 - .uleb128 0x32 - .string "i" - .byte 0x1 - .2byte 0x198 - .4byte 0x54 - .uleb128 0x32 - .string "j" - .byte 0x1 - .2byte 0x198 - .4byte 0x54 - .uleb128 0x32 - .string "k" - .byte 0x1 - .2byte 0x198 - .4byte 0x54 - .uleb128 0x32 - .string "h" - .byte 0x1 - .2byte 0x198 - .4byte 0x54 - .uleb128 0x31 - .4byte .LASF378 - .byte 0x1 - .2byte 0x199 - .4byte 0x54 - .uleb128 0x32 - .string "num" - .byte 0x1 - .2byte 0x19a - .4byte 0x54 - .uleb128 0x32 - .string "len" - .byte 0x1 - .2byte 0x19b - .4byte 0x54 + .uleb128 0x19 + .uleb128 0x3c + .uleb128 0x19 + .byte 0 + .byte 0 + .uleb128 0xd + .uleb128 0x26 + .byte 0 + .byte 0 + .byte 0 + .uleb128 0xe + .uleb128 0x21 + .byte 0 .uleb128 0x49 - .uleb128 0x31 - .4byte .LASF372 - .byte 0x1 - .2byte 0x1a7 - .4byte 0x54 - .uleb128 0x31 - .4byte .LASF379 - .byte 0x1 - .2byte 0x1a8 - .4byte 0x54 + .uleb128 0x13 + .uleb128 0x2f + .uleb128 0xb .byte 0 .byte 0 - .uleb128 0x40 - .4byte .LASF380 - .byte 0x1 - .2byte 0x15f - .4byte 0x54 - .8byte .LFB217 - .8byte .LFE217-.LFB217 - .uleb128 0x1 - .byte 0x9c - .4byte 0x2445 - .uleb128 0x2d - .4byte .LASF381 - .byte 0x1 - .2byte 0x15f - .4byte 0x54 - .4byte .LLST24 - .uleb128 0x2d - .4byte .LASF350 - .byte 0x1 - .2byte 0x15f - .4byte 0x54 - .4byte .LLST25 - .uleb128 0x2d - .4byte .LASF382 - .byte 0x1 - .2byte 0x15f - .4byte 0x54 - .4byte .LLST26 - .uleb128 0x2e - .4byte .LASF338 - .byte 0x1 - .2byte 0x161 - .4byte 0x4ea - .4byte .LLST27 - .uleb128 0x2e - .4byte .LASF379 - .byte 0x1 - .2byte 0x162 - .4byte 0x84 - .4byte .LLST28 - .uleb128 0x2e - .4byte .LASF383 - .byte 0x1 - .2byte 0x162 - .4byte 0x84 - .4byte .LLST29 - .uleb128 0x2e - .4byte .LASF384 - .byte 0x1 - .2byte 0x162 - .4byte 0x84 - .4byte .LLST30 - .uleb128 0x2e - .4byte .LASF385 - .byte 0x1 - .2byte 0x162 - .4byte 0x84 - .4byte .LLST31 - .uleb128 0x31 - .4byte .LASF386 - .byte 0x1 - .2byte 0x163 - .4byte 0x84 - .uleb128 0x2e - .4byte .LASF387 + .uleb128 0xf + .uleb128 0x13 .byte 0x1 - .2byte 0x164 - .4byte 0x54 - .4byte .LLST32 - .uleb128 0x4a - .4byte .LASF388 - .4byte 0x2455 - .uleb128 0x9 - .byte 0x3 - .8byte __func__.6107 + .uleb128 0x3 + .uleb128 0xe + .uleb128 0xb + .uleb128 0xb + .uleb128 0x3a + .uleb128 0xb .uleb128 0x3b - .8byte .LVL125 - .4byte 0x271f - .4byte 0x2437 - .uleb128 0x30 - .uleb128 0x1 - .byte 0x50 - .uleb128 0x9 - .byte 0x3 - .8byte .LC3 - .uleb128 0x30 + .uleb128 0xb .uleb128 0x1 - .byte 0x51 - .uleb128 0x9 - .byte 0x3 - .8byte .LANCHOR3 + .uleb128 0x13 .byte 0 - .uleb128 0x4b - .8byte .LVL139 - .4byte 0x25eb .byte 0 - .uleb128 0xa - .4byte 0xf3 - .4byte 0x2455 + .uleb128 0x10 + .uleb128 0xd + .byte 0 + .uleb128 0x3 .uleb128 0xe - .4byte 0xdf - .byte 0xe + .uleb128 0x3a + .uleb128 0xb + .uleb128 0x3b + .uleb128 0xb + .uleb128 0x49 + .uleb128 0x13 + .uleb128 0x38 + .uleb128 0xb .byte 0 - .uleb128 0x6 - .4byte 0x2445 - .uleb128 0x3e - .4byte .LASF389 - .byte 0x1 - .2byte 0x14b - .4byte 0x54 - .byte 0x1 - .4byte 0x24a6 - .uleb128 0x3f - .4byte .LASF347 - .byte 0x1 - .2byte 0x14b - .4byte 0x54 - .uleb128 0x31 - .4byte .LASF338 - .byte 0x1 - .2byte 0x14d - .4byte 0x4ea - .uleb128 0x31 - .4byte .LASF390 - .byte 0x1 - .2byte 0x14e - .4byte 0x54 - .uleb128 0x31 - .4byte .LASF391 - .byte 0x1 - .2byte 0x14f - .4byte 0x54 - .uleb128 0x32 - .string "i" - .byte 0x1 - .2byte 0x150 - .4byte 0x54 .byte 0 - .uleb128 0x40 - .4byte .LASF392 + .uleb128 0x11 + .uleb128 0x15 .byte 0x1 - .2byte 0x11c - .4byte 0x54 - .8byte .LFB215 - .8byte .LFE215-.LFB215 + .uleb128 0x27 + .uleb128 0x19 + .uleb128 0x49 + .uleb128 0x13 .uleb128 0x1 - .byte 0x9c - .4byte 0x2572 - .uleb128 0x2d - .4byte .LASF346 - .byte 0x1 - .2byte 0x11c - .4byte 0xd88 - .4byte .LLST0 - .uleb128 0x2e - .4byte .LASF338 - .byte 0x1 - .2byte 0x11e - .4byte 0x109b - .4byte .LLST1 - .uleb128 0x31 - .4byte .LASF393 - .byte 0x1 - .2byte 0x11f - .4byte 0x2572 - .uleb128 0x2e - .4byte .LASF381 - .byte 0x1 - .2byte 0x120 - .4byte 0x54 - .4byte .LLST2 - .uleb128 0x33 - .4byte 0x2578 - .8byte .LBB42 - .4byte .Ldebug_ranges0+0 - .byte 0x1 - .2byte 0x122 - .4byte 0x2556 - .uleb128 0x34 - .4byte 0x2588 - .4byte .LLST1 - .uleb128 0x35 - .4byte .Ldebug_ranges0+0 - .uleb128 0x3d - .4byte 0x2593 - .uleb128 0x9 - .byte 0x3 - .8byte pvi_modes.6055 - .uleb128 0x2f - .8byte .LVL4 - .4byte 0x271f - .uleb128 0x30 - .uleb128 0x1 - .byte 0x50 - .uleb128 0x9 - .byte 0x3 - .8byte .LC0 - .byte 0 - .byte 0 - .byte 0 - .uleb128 0x2f - .8byte .LVL24 - .4byte 0x271f - .uleb128 0x30 - .uleb128 0x1 - .byte 0x50 - .uleb128 0x9 - .byte 0x3 - .8byte .LC1 + .uleb128 0x13 .byte 0 .byte 0 - .uleb128 0x8 - .byte 0x8 - .4byte 0x5b - .uleb128 0x4c - .4byte .LASF394 - .byte 0x1 - .byte 0xa0 - .4byte 0x2572 - .byte 0x1 - .4byte 0x25a9 - .uleb128 0x4d - .4byte .LASF338 - .byte 0x1 - .byte 0xa0 - .4byte 0x109b - .uleb128 0x29 - .4byte .LASF393 - .byte 0x1 - .byte 0xa2 - .4byte 0x25a9 - .uleb128 0x9 - .byte 0x3 - .8byte pvi_modes.6055 + .uleb128 0x12 + .uleb128 0x5 .byte 0 - .uleb128 0xa - .4byte 0x54 - .4byte 0x25b9 - .uleb128 0xe - .4byte 0xdf - .byte 0x8 + .uleb128 0x49 + .uleb128 0x13 .byte 0 - .uleb128 0x4c - .4byte .LASF395 - .byte 0x1 - .byte 0x9b - .4byte 0x34 - .byte 0x1 - .4byte 0x25eb - .uleb128 0x4d - .4byte .LASF396 - .byte 0x1 - .byte 0x9b - .4byte 0x54 - .uleb128 0x4d - .4byte .LASF360 - .byte 0x1 - .byte 0x9b - .4byte 0x54 - .uleb128 0x4d - .4byte .LASF361 - .byte 0x1 - .byte 0x9b - .4byte 0x54 .byte 0 - .uleb128 0x4e - .4byte .LASF397 - .byte 0x1 - .byte 0x31 - .4byte 0x54 - .8byte .LFB212 - .8byte .LFE212-.LFB212 - .uleb128 0x1 - .byte 0x9c - .4byte 0x26e0 - .uleb128 0x4f - .4byte .LASF310 - .byte 0x1 - .byte 0x31 - .4byte 0x4ea - .4byte .LLST14 - .uleb128 0x4f - .4byte .LASF398 - .byte 0x1 - .byte 0x31 - .4byte 0x54 - .4byte .LLST15 - .uleb128 0x4f - .4byte .LASF382 - .byte 0x1 - .byte 0x31 - .4byte 0x54 - .4byte .LLST16 - .uleb128 0x50 - .4byte .LASF399 - .byte 0x1 - .byte 0x33 - .4byte 0x84 - .4byte .LLST17 - .uleb128 0x50 - .4byte .LASF400 - .byte 0x1 - .byte 0x33 - .4byte 0x84 - .4byte .LLST18 - .uleb128 0x50 - .4byte .LASF401 - .byte 0x1 - .byte 0x34 - .4byte 0x84 - .4byte .LLST19 - .uleb128 0x50 - .4byte .LASF387 - .byte 0x1 - .byte 0x35 - .4byte 0x84 - .4byte .LLST20 - .uleb128 0x50 - .4byte .LASF402 - .byte 0x1 - .byte 0x36 - .4byte 0x34 - .4byte .LLST21 - .uleb128 0x51 - .string "i" - .byte 0x1 - .byte 0x37 - .4byte 0x34 - .4byte .LLST22 - .uleb128 0x50 - .4byte .LASF403 + .uleb128 0x13 + .uleb128 0x13 .byte 0x1 - .byte 0x38 - .4byte 0x15f - .4byte .LLST23 + .uleb128 0xb + .uleb128 0x5 + .uleb128 0x3a + .uleb128 0xb .uleb128 0x3b - .8byte .LVL58 - .4byte 0x2741 - .4byte 0x26c4 - .uleb128 0x30 - .uleb128 0x1 - .byte 0x50 - .uleb128 0x2 - .byte 0x88 - .sleb128 0 - .uleb128 0x30 - .uleb128 0x1 - .byte 0x51 - .uleb128 0x1 - .byte 0x30 - .uleb128 0x30 - .uleb128 0x1 - .byte 0x52 - .uleb128 0x3 - .byte 0x40 - .byte 0x3f - .byte 0x24 - .byte 0 - .uleb128 0x2f - .8byte .LVL76 - .4byte 0x271f - .uleb128 0x30 - .uleb128 0x1 - .byte 0x50 - .uleb128 0x9 - .byte 0x3 - .8byte .LC2 - .byte 0 - .byte 0 - .uleb128 0x52 - .4byte .LASF404 - .byte 0x2 - .byte 0x4f - .byte 0x3 - .4byte 0x26f8 - .uleb128 0x4d - .4byte .LASF405 - .byte 0x2 - .byte 0x4f - .4byte 0x195 - .byte 0 - .uleb128 0x4c - .4byte .LASF406 - .byte 0x2 - .byte 0x38 - .4byte 0x152 - .byte 0x3 - .4byte 0x271f - .uleb128 0x4d - .4byte .LASF33 - .byte 0x2 - .byte 0x38 - .4byte 0x110 - .uleb128 0x4d - .4byte .LASF407 - .byte 0x2 - .byte 0x38 - .4byte 0x147 - .byte 0 - .uleb128 0x53 - .4byte .LASF408 - .4byte .LASF408 - .byte 0x18 - .byte 0x13 - .uleb128 0x54 - .4byte .LASF409 - .4byte .LASF409 - .byte 0x16 - .2byte 0x399 - .uleb128 0x53 - .4byte .LASF410 - .4byte .LASF410 - .byte 0x2 - .byte 0x36 - .uleb128 0x54 - .4byte .LASF411 - .4byte .LASF411 - .byte 0x16 - .2byte 0x16c - .uleb128 0x54 - .4byte .LASF412 - .4byte .LASF412 - .byte 0x16 - .2byte 0x16d - .byte 0 - .section .debug_abbrev,"",@progbits -.Ldebug_abbrev0: - .uleb128 0x1 - .uleb128 0x11 - .byte 0x1 - .uleb128 0x25 - .uleb128 0xe - .uleb128 0x13 .uleb128 0xb - .uleb128 0x3 - .uleb128 0xe - .uleb128 0x1b - .uleb128 0xe - .uleb128 0x55 - .uleb128 0x17 - .uleb128 0x11 .uleb128 0x1 - .uleb128 0x10 - .uleb128 0x17 + .uleb128 0x13 .byte 0 .byte 0 - .uleb128 0x2 - .uleb128 0x16 + .uleb128 0x14 + .uleb128 0xd .byte 0 .uleb128 0x3 .uleb128 0xe @@ -7095,230 +4383,36 @@ __func__.6107: .uleb128 0xb .uleb128 0x49 .uleb128 0x13 + .uleb128 0x38 + .uleb128 0x5 .byte 0 .byte 0 - .uleb128 0x3 - .uleb128 0x24 - .byte 0 - .uleb128 0xb - .uleb128 0xb - .uleb128 0x3e - .uleb128 0xb - .uleb128 0x3 - .uleb128 0xe - .byte 0 - .byte 0 - .uleb128 0x4 - .uleb128 0x34 + .uleb128 0x15 + .uleb128 0xd .byte 0 .uleb128 0x3 - .uleb128 0xe + .uleb128 0x8 .uleb128 0x3a .uleb128 0xb .uleb128 0x3b .uleb128 0xb .uleb128 0x49 .uleb128 0x13 - .uleb128 0x3f - .uleb128 0x19 - .uleb128 0x3c - .uleb128 0x19 - .byte 0 - .byte 0 + .uleb128 0x38 .uleb128 0x5 - .uleb128 0x24 - .byte 0 - .uleb128 0xb - .uleb128 0xb - .uleb128 0x3e - .uleb128 0xb - .uleb128 0x3 - .uleb128 0x8 .byte 0 .byte 0 - .uleb128 0x6 - .uleb128 0x26 + .uleb128 0x16 + .uleb128 0x21 .byte 0 .uleb128 0x49 .uleb128 0x13 + .uleb128 0x2f + .uleb128 0x5 .byte 0 .byte 0 - .uleb128 0x7 - .uleb128 0x16 - .byte 0 - .uleb128 0x3 - .uleb128 0x8 - .uleb128 0x3a - .uleb128 0xb - .uleb128 0x3b - .uleb128 0xb - .uleb128 0x49 - .uleb128 0x13 - .byte 0 - .byte 0 - .uleb128 0x8 - .uleb128 0xf - .byte 0 - .uleb128 0xb - .uleb128 0xb - .uleb128 0x49 - .uleb128 0x13 - .byte 0 - .byte 0 - .uleb128 0x9 - .uleb128 0xf - .byte 0 - .uleb128 0xb - .uleb128 0xb - .byte 0 - .byte 0 - .uleb128 0xa - .uleb128 0x1 - .byte 0x1 - .uleb128 0x49 - .uleb128 0x13 - .uleb128 0x1 - .uleb128 0x13 - .byte 0 - .byte 0 - .uleb128 0xb - .uleb128 0x21 - .byte 0 - .byte 0 - .byte 0 - .uleb128 0xc - .uleb128 0x34 - .byte 0 - .uleb128 0x3 - .uleb128 0xe - .uleb128 0x3a - .uleb128 0xb - .uleb128 0x3b - .uleb128 0x5 - .uleb128 0x49 - .uleb128 0x13 - .uleb128 0x3f - .uleb128 0x19 - .uleb128 0x3c - .uleb128 0x19 - .byte 0 - .byte 0 - .uleb128 0xd - .uleb128 0x26 - .byte 0 - .byte 0 - .byte 0 - .uleb128 0xe - .uleb128 0x21 - .byte 0 - .uleb128 0x49 - .uleb128 0x13 - .uleb128 0x2f - .uleb128 0xb - .byte 0 - .byte 0 - .uleb128 0xf - .uleb128 0x13 - .byte 0x1 - .uleb128 0x3 - .uleb128 0xe - .uleb128 0xb - .uleb128 0xb - .uleb128 0x3a - .uleb128 0xb - .uleb128 0x3b - .uleb128 0xb - .uleb128 0x1 - .uleb128 0x13 - .byte 0 - .byte 0 - .uleb128 0x10 - .uleb128 0xd - .byte 0 - .uleb128 0x3 - .uleb128 0xe - .uleb128 0x3a - .uleb128 0xb - .uleb128 0x3b - .uleb128 0xb - .uleb128 0x49 - .uleb128 0x13 - .uleb128 0x38 - .uleb128 0xb - .byte 0 - .byte 0 - .uleb128 0x11 - .uleb128 0x15 - .byte 0x1 - .uleb128 0x27 - .uleb128 0x19 - .uleb128 0x49 - .uleb128 0x13 - .uleb128 0x1 - .uleb128 0x13 - .byte 0 - .byte 0 - .uleb128 0x12 - .uleb128 0x5 - .byte 0 - .uleb128 0x49 - .uleb128 0x13 - .byte 0 - .byte 0 - .uleb128 0x13 - .uleb128 0x13 - .byte 0x1 - .uleb128 0xb - .uleb128 0x5 - .uleb128 0x3a - .uleb128 0xb - .uleb128 0x3b - .uleb128 0xb - .uleb128 0x1 - .uleb128 0x13 - .byte 0 - .byte 0 - .uleb128 0x14 - .uleb128 0xd - .byte 0 - .uleb128 0x3 - .uleb128 0xe - .uleb128 0x3a - .uleb128 0xb - .uleb128 0x3b - .uleb128 0xb - .uleb128 0x49 - .uleb128 0x13 - .uleb128 0x38 - .uleb128 0x5 - .byte 0 - .byte 0 - .uleb128 0x15 - .uleb128 0xd - .byte 0 - .uleb128 0x3 - .uleb128 0x8 - .uleb128 0x3a - .uleb128 0xb - .uleb128 0x3b - .uleb128 0xb - .uleb128 0x49 - .uleb128 0x13 - .uleb128 0x38 - .uleb128 0x5 - .byte 0 - .byte 0 - .uleb128 0x16 - .uleb128 0x21 - .byte 0 - .uleb128 0x49 - .uleb128 0x13 - .uleb128 0x2f - .uleb128 0x5 - .byte 0 - .byte 0 - .uleb128 0x17 - .uleb128 0x13 + .uleb128 0x17 + .uleb128 0x13 .byte 0 .uleb128 0x3 .uleb128 0xe @@ -7516,7 +4610,7 @@ __func__.6107: .uleb128 0x3a .uleb128 0xb .uleb128 0x3b - .uleb128 0xb + .uleb128 0x5 .uleb128 0x1 .uleb128 0x13 .byte 0 @@ -7531,17 +4625,10 @@ __func__.6107: .byte 0 .byte 0 .uleb128 0x26 - .uleb128 0x28 - .byte 0 - .uleb128 0x3 - .uleb128 0xe - .uleb128 0x1c - .uleb128 0xd - .byte 0 - .byte 0 - .uleb128 0x27 .uleb128 0x4 .byte 0x1 + .uleb128 0x3 + .uleb128 0xe .uleb128 0xb .uleb128 0xb .uleb128 0x49 @@ -7554,21 +4641,32 @@ __func__.6107: .uleb128 0x13 .byte 0 .byte 0 - .uleb128 0x28 - .uleb128 0x4 - .byte 0x1 + .uleb128 0x27 + .uleb128 0x34 + .byte 0 .uleb128 0x3 .uleb128 0xe + .uleb128 0x3a .uleb128 0xb + .uleb128 0x3b .uleb128 0xb .uleb128 0x49 .uleb128 0x13 + .byte 0 + .byte 0 + .uleb128 0x28 + .uleb128 0x34 + .byte 0 + .uleb128 0x3 + .uleb128 0xe .uleb128 0x3a .uleb128 0xb .uleb128 0x3b - .uleb128 0x5 - .uleb128 0x1 + .uleb128 0xb + .uleb128 0x49 .uleb128 0x13 + .uleb128 0x2 + .uleb128 0x18 .byte 0 .byte 0 .uleb128 0x29 @@ -7582,6 +4680,8 @@ __func__.6107: .uleb128 0xb .uleb128 0x49 .uleb128 0x13 + .uleb128 0x3f + .uleb128 0x19 .uleb128 0x2 .uleb128 0x18 .byte 0 @@ -7629,6 +4729,13 @@ __func__.6107: .byte 0 .byte 0 .uleb128 0x2c + .uleb128 0xb + .byte 0x1 + .uleb128 0x55 + .uleb128 0x17 + .byte 0 + .byte 0 + .uleb128 0x2d .uleb128 0x34 .byte 0 .uleb128 0x3 @@ -7643,7 +4750,7 @@ __func__.6107: .uleb128 0x17 .byte 0 .byte 0 - .uleb128 0x2d + .uleb128 0x2e .uleb128 0x5 .byte 0 .uleb128 0x3 @@ -7658,7 +4765,7 @@ __func__.6107: .uleb128 0x17 .byte 0 .byte 0 - .uleb128 0x2e + .uleb128 0x2f .uleb128 0x34 .byte 0 .uleb128 0x3 @@ -7673,16 +4780,18 @@ __func__.6107: .uleb128 0x17 .byte 0 .byte 0 - .uleb128 0x2f + .uleb128 0x30 .uleb128 0x4109 .byte 0x1 .uleb128 0x11 .uleb128 0x1 .uleb128 0x31 .uleb128 0x13 + .uleb128 0x1 + .uleb128 0x13 .byte 0 .byte 0 - .uleb128 0x30 + .uleb128 0x31 .uleb128 0x410a .byte 0 .uleb128 0x2 @@ -7691,20 +4800,31 @@ __func__.6107: .uleb128 0x18 .byte 0 .byte 0 + .uleb128 0x32 + .uleb128 0x4109 + .byte 0x1 + .uleb128 0x11 + .uleb128 0x1 .uleb128 0x31 - .uleb128 0x34 + .uleb128 0x13 + .byte 0 + .byte 0 + .uleb128 0x33 + .uleb128 0x5 .byte 0 .uleb128 0x3 - .uleb128 0xe + .uleb128 0x8 .uleb128 0x3a .uleb128 0xb .uleb128 0x3b .uleb128 0x5 .uleb128 0x49 .uleb128 0x13 + .uleb128 0x2 + .uleb128 0x17 .byte 0 .byte 0 - .uleb128 0x32 + .uleb128 0x34 .uleb128 0x34 .byte 0 .uleb128 0x3 @@ -7715,17 +4835,34 @@ __func__.6107: .uleb128 0x5 .uleb128 0x49 .uleb128 0x13 + .uleb128 0x2 + .uleb128 0x18 .byte 0 .byte 0 - .uleb128 0x33 - .uleb128 0x1d - .byte 0x1 - .uleb128 0x31 + .uleb128 0x35 + .uleb128 0x34 + .byte 0 + .uleb128 0x3 + .uleb128 0xe + .uleb128 0x3a + .uleb128 0xb + .uleb128 0x3b + .uleb128 0x5 + .uleb128 0x49 .uleb128 0x13 - .uleb128 0x52 + .uleb128 0x1c + .uleb128 0xd + .byte 0 + .byte 0 + .uleb128 0x36 + .uleb128 0x1d + .byte 0x1 + .uleb128 0x31 + .uleb128 0x13 + .uleb128 0x11 .uleb128 0x1 - .uleb128 0x55 - .uleb128 0x17 + .uleb128 0x12 + .uleb128 0x7 .uleb128 0x58 .uleb128 0xb .uleb128 0x59 @@ -7734,7 +4871,7 @@ __func__.6107: .uleb128 0x13 .byte 0 .byte 0 - .uleb128 0x34 + .uleb128 0x37 .uleb128 0x5 .byte 0 .uleb128 0x31 @@ -7743,31 +4880,24 @@ __func__.6107: .uleb128 0x17 .byte 0 .byte 0 - .uleb128 0x35 - .uleb128 0xb - .byte 0x1 - .uleb128 0x55 - .uleb128 0x17 - .byte 0 - .byte 0 - .uleb128 0x36 - .uleb128 0x34 + .uleb128 0x38 + .uleb128 0x4109 .byte 0 + .uleb128 0x11 + .uleb128 0x1 .uleb128 0x31 .uleb128 0x13 - .uleb128 0x2 - .uleb128 0x17 .byte 0 .byte 0 - .uleb128 0x37 + .uleb128 0x39 .uleb128 0x1d .byte 0x1 .uleb128 0x31 .uleb128 0x13 - .uleb128 0x11 + .uleb128 0x52 .uleb128 0x1 - .uleb128 0x12 - .uleb128 0x7 + .uleb128 0x55 + .uleb128 0x17 .uleb128 0x58 .uleb128 0xb .uleb128 0x59 @@ -7776,59 +4906,34 @@ __func__.6107: .uleb128 0x13 .byte 0 .byte 0 - .uleb128 0x38 - .uleb128 0x4109 - .byte 0 - .uleb128 0x11 - .uleb128 0x1 - .uleb128 0x31 - .uleb128 0x13 - .byte 0 - .byte 0 - .uleb128 0x39 - .uleb128 0x34 - .byte 0 - .uleb128 0x31 - .uleb128 0x13 - .byte 0 - .byte 0 .uleb128 0x3a - .uleb128 0x5 + .uleb128 0x34 .byte 0 .uleb128 0x31 .uleb128 0x13 + .uleb128 0x2 + .uleb128 0x17 .byte 0 .byte 0 .uleb128 0x3b - .uleb128 0x4109 - .byte 0x1 - .uleb128 0x11 - .uleb128 0x1 - .uleb128 0x31 - .uleb128 0x13 - .uleb128 0x1 - .uleb128 0x13 - .byte 0 - .byte 0 - .uleb128 0x3c .uleb128 0xb .byte 0x1 .uleb128 0x11 .uleb128 0x1 .uleb128 0x12 .uleb128 0x7 + .uleb128 0x1 + .uleb128 0x13 .byte 0 .byte 0 - .uleb128 0x3d + .uleb128 0x3c .uleb128 0x34 .byte 0 .uleb128 0x31 .uleb128 0x13 - .uleb128 0x2 - .uleb128 0x18 .byte 0 .byte 0 - .uleb128 0x3e + .uleb128 0x3d .uleb128 0x2e .byte 0x1 .uleb128 0x3 @@ -7847,7 +4952,7 @@ __func__.6107: .uleb128 0x13 .byte 0 .byte 0 - .uleb128 0x3f + .uleb128 0x3e .uleb128 0x5 .byte 0 .uleb128 0x3 @@ -7860,47 +4965,51 @@ __func__.6107: .uleb128 0x13 .byte 0 .byte 0 - .uleb128 0x40 - .uleb128 0x2e - .byte 0x1 + .uleb128 0x3f + .uleb128 0x5 + .byte 0 .uleb128 0x3 - .uleb128 0xe + .uleb128 0x8 .uleb128 0x3a .uleb128 0xb .uleb128 0x3b .uleb128 0x5 - .uleb128 0x27 - .uleb128 0x19 .uleb128 0x49 .uleb128 0x13 - .uleb128 0x11 - .uleb128 0x1 - .uleb128 0x12 - .uleb128 0x7 + .byte 0 + .byte 0 .uleb128 0x40 - .uleb128 0x18 - .uleb128 0x2117 - .uleb128 0x19 - .uleb128 0x1 + .uleb128 0x34 + .byte 0 + .uleb128 0x3 + .uleb128 0x8 + .uleb128 0x3a + .uleb128 0xb + .uleb128 0x3b + .uleb128 0x5 + .uleb128 0x49 .uleb128 0x13 .byte 0 .byte 0 .uleb128 0x41 - .uleb128 0x1d - .byte 0x1 - .uleb128 0x31 - .uleb128 0x13 - .uleb128 0x11 - .uleb128 0x1 - .uleb128 0x12 - .uleb128 0x7 - .uleb128 0x58 + .uleb128 0x34 + .byte 0 + .uleb128 0x3 + .uleb128 0xe + .uleb128 0x3a .uleb128 0xb - .uleb128 0x59 + .uleb128 0x3b .uleb128 0x5 + .uleb128 0x49 + .uleb128 0x13 .byte 0 .byte 0 .uleb128 0x42 + .uleb128 0xb + .byte 0x1 + .byte 0 + .byte 0 + .uleb128 0x43 .uleb128 0x2e .byte 0x1 .uleb128 0x3 @@ -7911,6 +5020,8 @@ __func__.6107: .uleb128 0x5 .uleb128 0x27 .uleb128 0x19 + .uleb128 0x49 + .uleb128 0x13 .uleb128 0x11 .uleb128 0x1 .uleb128 0x12 @@ -7923,30 +5034,17 @@ __func__.6107: .uleb128 0x13 .byte 0 .byte 0 - .uleb128 0x43 - .uleb128 0x5 + .uleb128 0x44 + .uleb128 0x34 .byte 0 .uleb128 0x3 - .uleb128 0x8 - .uleb128 0x3a - .uleb128 0xb - .uleb128 0x3b - .uleb128 0x5 + .uleb128 0xe .uleb128 0x49 .uleb128 0x13 - .uleb128 0x2 - .uleb128 0x17 - .byte 0 - .byte 0 - .uleb128 0x44 - .uleb128 0x4109 - .byte 0x1 - .uleb128 0x11 - .uleb128 0x1 - .uleb128 0x2115 + .uleb128 0x34 .uleb128 0x19 - .uleb128 0x31 - .uleb128 0x13 + .uleb128 0x2 + .uleb128 0x18 .byte 0 .byte 0 .uleb128 0x45 @@ -7957,11 +5055,19 @@ __func__.6107: .uleb128 0x3a .uleb128 0xb .uleb128 0x3b - .uleb128 0x5 + .uleb128 0xb .uleb128 0x27 .uleb128 0x19 - .uleb128 0x20 - .uleb128 0xb + .uleb128 0x49 + .uleb128 0x13 + .uleb128 0x11 + .uleb128 0x1 + .uleb128 0x12 + .uleb128 0x7 + .uleb128 0x40 + .uleb128 0x18 + .uleb128 0x2117 + .uleb128 0x19 .uleb128 0x1 .uleb128 0x13 .byte 0 @@ -7970,69 +5076,48 @@ __func__.6107: .uleb128 0x5 .byte 0 .uleb128 0x3 - .uleb128 0x8 + .uleb128 0xe .uleb128 0x3a .uleb128 0xb .uleb128 0x3b - .uleb128 0x5 - .uleb128 0x49 - .uleb128 0x13 - .byte 0 - .byte 0 - .uleb128 0x47 .uleb128 0xb - .byte 0x1 - .uleb128 0x55 - .uleb128 0x17 - .uleb128 0x1 - .uleb128 0x13 - .byte 0 - .byte 0 - .uleb128 0x48 - .uleb128 0x1d - .byte 0x1 - .uleb128 0x31 + .uleb128 0x49 .uleb128 0x13 - .uleb128 0x52 - .uleb128 0x1 - .uleb128 0x55 + .uleb128 0x2 .uleb128 0x17 - .uleb128 0x58 - .uleb128 0xb - .uleb128 0x59 - .uleb128 0x5 - .byte 0 - .byte 0 - .uleb128 0x49 - .uleb128 0xb - .byte 0x1 .byte 0 .byte 0 - .uleb128 0x4a + .uleb128 0x47 .uleb128 0x34 .byte 0 .uleb128 0x3 .uleb128 0xe + .uleb128 0x3a + .uleb128 0xb + .uleb128 0x3b + .uleb128 0xb .uleb128 0x49 .uleb128 0x13 - .uleb128 0x34 - .uleb128 0x19 .uleb128 0x2 - .uleb128 0x18 + .uleb128 0x17 .byte 0 .byte 0 - .uleb128 0x4b - .uleb128 0x4109 + .uleb128 0x48 + .uleb128 0x34 .byte 0 - .uleb128 0x11 - .uleb128 0x1 - .uleb128 0x2115 - .uleb128 0x19 - .uleb128 0x31 + .uleb128 0x3 + .uleb128 0x8 + .uleb128 0x3a + .uleb128 0xb + .uleb128 0x3b + .uleb128 0xb + .uleb128 0x49 .uleb128 0x13 + .uleb128 0x2 + .uleb128 0x17 .byte 0 .byte 0 - .uleb128 0x4c + .uleb128 0x49 .uleb128 0x2e .byte 0x1 .uleb128 0x3 @@ -8051,7 +5136,7 @@ __func__.6107: .uleb128 0x13 .byte 0 .byte 0 - .uleb128 0x4d + .uleb128 0x4a .uleb128 0x5 .byte 0 .uleb128 0x3 @@ -8064,7 +5149,7 @@ __func__.6107: .uleb128 0x13 .byte 0 .byte 0 - .uleb128 0x4e + .uleb128 0x4b .uleb128 0x2e .byte 0x1 .uleb128 0x3f @@ -8091,2096 +5176,149 @@ __func__.6107: .uleb128 0x13 .byte 0 .byte 0 - .uleb128 0x4f - .uleb128 0x5 + .uleb128 0x4c + .uleb128 0x34 .byte 0 .uleb128 0x3 - .uleb128 0xe + .uleb128 0x8 .uleb128 0x3a .uleb128 0xb .uleb128 0x3b .uleb128 0xb .uleb128 0x49 .uleb128 0x13 - .uleb128 0x2 - .uleb128 0x17 - .byte 0 .byte 0 - .uleb128 0x50 - .uleb128 0x34 .byte 0 + .uleb128 0x4d + .uleb128 0x2e + .byte 0x1 .uleb128 0x3 .uleb128 0xe .uleb128 0x3a .uleb128 0xb .uleb128 0x3b .uleb128 0xb - .uleb128 0x49 - .uleb128 0x13 - .uleb128 0x2 - .uleb128 0x17 - .byte 0 - .byte 0 - .uleb128 0x51 - .uleb128 0x34 - .byte 0 - .uleb128 0x3 - .uleb128 0x8 - .uleb128 0x3a - .uleb128 0xb - .uleb128 0x3b + .uleb128 0x27 + .uleb128 0x19 + .uleb128 0x20 .uleb128 0xb - .uleb128 0x49 + .uleb128 0x1 .uleb128 0x13 - .uleb128 0x2 - .uleb128 0x17 .byte 0 .byte 0 - .uleb128 0x52 + .uleb128 0x4e .uleb128 0x2e .byte 0x1 - .uleb128 0x3 - .uleb128 0xe - .uleb128 0x3a - .uleb128 0xb - .uleb128 0x3b - .uleb128 0xb - .uleb128 0x27 + .uleb128 0x31 + .uleb128 0x13 + .uleb128 0x11 + .uleb128 0x1 + .uleb128 0x12 + .uleb128 0x7 + .uleb128 0x40 + .uleb128 0x18 + .uleb128 0x2117 .uleb128 0x19 - .uleb128 0x20 - .uleb128 0xb .uleb128 0x1 .uleb128 0x13 .byte 0 .byte 0 - .uleb128 0x53 - .uleb128 0x2e - .byte 0 - .uleb128 0x3f - .uleb128 0x19 - .uleb128 0x3c - .uleb128 0x19 - .uleb128 0x6e - .uleb128 0xe - .uleb128 0x3 - .uleb128 0xe - .uleb128 0x3a - .uleb128 0xb - .uleb128 0x3b + .uleb128 0x4f .uleb128 0xb + .byte 0x1 + .uleb128 0x11 + .uleb128 0x1 + .uleb128 0x12 + .uleb128 0x7 .byte 0 .byte 0 - .uleb128 0x54 - .uleb128 0x2e - .byte 0 - .uleb128 0x3f - .uleb128 0x19 - .uleb128 0x3c - .uleb128 0x19 - .uleb128 0x6e - .uleb128 0xe - .uleb128 0x3 - .uleb128 0xe - .uleb128 0x3a + .uleb128 0x50 + .uleb128 0x1d + .byte 0x1 + .uleb128 0x31 + .uleb128 0x13 + .uleb128 0x52 + .uleb128 0x1 + .uleb128 0x55 + .uleb128 0x17 + .uleb128 0x58 + .uleb128 0xb + .uleb128 0x59 .uleb128 0xb - .uleb128 0x3b - .uleb128 0x5 - .byte 0 .byte 0 .byte 0 - .section .debug_loc,"",@progbits -.Ldebug_loc0: -.LLST135: - .8byte .LVL334 - .8byte .LVL335 - .2byte 0x1 - .byte 0x51 - .8byte .LVL335 - .8byte .LVL336 - .2byte 0x3 - .byte 0x71 - .sleb128 1 - .byte 0x9f - .8byte 0 - .8byte 0 -.LLST133: - .8byte .LVL326 - .8byte .LVL327 - .2byte 0x1 - .byte 0x50 - .8byte .LVL327 - .8byte .LVL328 - .2byte 0x9 - .byte 0x3 - .8byte global_waveform - .8byte .LVL328 - .8byte .LVL329 - .2byte 0x1 - .byte 0x50 - .8byte .LVL329 - .8byte .LVL331 - .2byte 0x4 - .byte 0xf3 - .uleb128 0x1 - .byte 0x50 - .byte 0x9f - .8byte .LVL331 - .8byte .LVL332 - .2byte 0x1 - .byte 0x50 - .8byte .LVL332 - .8byte .LFE233 - .2byte 0x4 - .byte 0xf3 - .uleb128 0x1 - .byte 0x50 - .byte 0x9f - .8byte 0 - .8byte 0 -.LLST134: - .8byte .LVL326 - .8byte .LVL327 - .2byte 0x1 - .byte 0x50 - .8byte .LVL327 - .8byte .LVL328 - .2byte 0x9 - .byte 0x3 - .8byte global_waveform - .8byte .LVL328 - .8byte .LVL329 - .2byte 0x1 - .byte 0x50 - .8byte .LVL329 - .8byte .LVL331 - .2byte 0x4 - .byte 0xf3 - .uleb128 0x1 - .byte 0x50 - .byte 0x9f - .8byte .LVL331 - .8byte .LVL332 - .2byte 0x1 - .byte 0x50 - .8byte .LVL332 - .8byte .LFE233 - .2byte 0x4 - .byte 0xf3 - .uleb128 0x1 - .byte 0x50 - .byte 0x9f - .8byte 0 - .8byte 0 -.LLST60: - .8byte .LVL180 - .8byte .LVL188 - .2byte 0x1 - .byte 0x50 - .8byte .LVL188 - .8byte .LVL191 - .2byte 0x1 - .byte 0x63 - .8byte .LVL191 - .8byte .LVL193 - .2byte 0x1 - .byte 0x50 - .8byte .LVL193 - .8byte .LVL250 - .2byte 0x1 - .byte 0x63 - .8byte .LVL250 - .8byte .LVL251 - .2byte 0x4 - .byte 0xf3 - .uleb128 0x1 - .byte 0x50 - .byte 0x9f - .8byte .LVL251 - .8byte .LVL252 - .2byte 0x1 - .byte 0x63 - .8byte .LVL252 - .8byte .LVL253 - .2byte 0x4 - .byte 0xf3 - .uleb128 0x1 - .byte 0x50 - .byte 0x9f - .8byte .LVL253 - .8byte .LVL307 - .2byte 0x1 - .byte 0x63 - .8byte .LVL307 - .8byte .LVL320 - .2byte 0x4 - .byte 0xf3 - .uleb128 0x1 - .byte 0x50 - .byte 0x9f - .8byte .LVL320 - .8byte .LVL321 - .2byte 0x1 - .byte 0x50 - .8byte .LVL321 - .8byte .LVL322 - .2byte 0x4 - .byte 0xf3 - .uleb128 0x1 - .byte 0x50 - .byte 0x9f - .8byte .LVL322 - .8byte .LVL323 - .2byte 0x1 - .byte 0x50 - .8byte .LVL323 - .8byte .LVL324 - .2byte 0x4 - .byte 0xf3 - .uleb128 0x1 - .byte 0x50 - .byte 0x9f - .8byte .LVL324 - .8byte .LVL325 - .2byte 0x1 - .byte 0x50 - .8byte .LVL325 - .8byte .LFE232 - .2byte 0x4 - .byte 0xf3 - .uleb128 0x1 - .byte 0x50 - .byte 0x9f - .8byte 0 - .8byte 0 -.LLST61: - .8byte .LVL180 - .8byte .LVL190-1 - .2byte 0x1 - .byte 0x51 - .8byte .LVL190-1 - .8byte .LVL191 - .2byte 0x1 - .byte 0x65 - .8byte .LVL191 - .8byte .LVL193 - .2byte 0x1 - .byte 0x51 - .8byte .LVL193 - .8byte .LVL196 - .2byte 0x1 - .byte 0x65 - .8byte .LVL196 - .8byte .LVL236 - .2byte 0x4 - .byte 0xf3 - .uleb128 0x1 - .byte 0x51 - .byte 0x9f - .8byte .LVL236 - .8byte .LVL244 - .2byte 0x1 - .byte 0x65 - .8byte .LVL244 - .8byte .LVL245 - .2byte 0x4 - .byte 0xf3 - .uleb128 0x1 - .byte 0x51 - .byte 0x9f - .8byte .LVL245 - .8byte .LVL246 - .2byte 0x1 - .byte 0x65 - .8byte .LVL246 - .8byte .LVL248 - .2byte 0x4 - .byte 0xf3 - .uleb128 0x1 - .byte 0x51 - .byte 0x9f - .8byte .LVL248 - .8byte .LVL249 - .2byte 0x1 - .byte 0x65 - .8byte .LVL249 - .8byte .LVL251 - .2byte 0x4 - .byte 0xf3 - .uleb128 0x1 - .byte 0x51 - .byte 0x9f - .8byte .LVL251 - .8byte .LVL252 - .2byte 0x1 - .byte 0x65 - .8byte .LVL252 - .8byte .LVL253 - .2byte 0x4 - .byte 0xf3 - .uleb128 0x1 - .byte 0x51 - .byte 0x9f - .8byte .LVL253 - .8byte .LVL256 - .2byte 0x1 - .byte 0x65 - .8byte .LVL256 - .8byte .LVL286 - .2byte 0x4 - .byte 0xf3 - .uleb128 0x1 - .byte 0x51 - .byte 0x9f - .8byte .LVL286 - .8byte .LVL289 - .2byte 0x1 - .byte 0x65 - .8byte .LVL289 - .8byte .LVL296 - .2byte 0x4 - .byte 0xf3 - .uleb128 0x1 - .byte 0x51 - .byte 0x9f - .8byte .LVL296 - .8byte .LVL306 - .2byte 0x1 - .byte 0x65 - .8byte .LVL306 - .8byte .LVL320 - .2byte 0x4 - .byte 0xf3 - .uleb128 0x1 - .byte 0x51 - .byte 0x9f - .8byte .LVL320 - .8byte .LFE232 - .2byte 0x1 - .byte 0x51 - .8byte 0 - .8byte 0 -.LLST62: - .8byte .LVL180 - .8byte .LVL190-1 - .2byte 0x1 - .byte 0x52 - .8byte .LVL190-1 - .8byte .LVL191 - .2byte 0x4 - .byte 0xf3 - .uleb128 0x1 - .byte 0x52 - .byte 0x9f - .8byte .LVL191 - .8byte .LVL193 - .2byte 0x1 - .byte 0x52 - .8byte .LVL193 - .8byte .LVL320 - .2byte 0x4 - .byte 0xf3 - .uleb128 0x1 - .byte 0x52 - .byte 0x9f - .8byte .LVL320 - .8byte .LFE232 - .2byte 0x1 - .byte 0x52 - .8byte 0 - .8byte 0 -.LLST63: - .8byte .LVL181 - .8byte .LVL187 - .2byte 0x1 - .byte 0x52 - .8byte .LVL191 - .8byte .LVL193 - .2byte 0x1 - .byte 0x52 - .8byte 0 - .8byte 0 -.LLST64: - .8byte .LVL181 - .8byte .LVL187 - .2byte 0x1 - .byte 0x54 - .8byte .LVL191 - .8byte .LVL193 - .2byte 0x1 - .byte 0x54 - .8byte 0 - .8byte 0 -.LLST65: - .8byte .LVL181 - .8byte .LVL183 - .2byte 0x1 - .byte 0x64 - .8byte .LVL183 - .8byte .LVL184 - .2byte 0x3 - .byte 0x84 - .sleb128 1 - .byte 0x9f - .8byte .LVL184 - .8byte .LVL186 - .2byte 0x1 - .byte 0x64 - .8byte .LVL186 - .8byte .LVL187 - .2byte 0x8 - .byte 0x74 - .sleb128 38 - .byte 0x94 - .byte 0x1 - .byte 0x8 - .byte 0xff - .byte 0x1a - .byte 0x9f - .8byte .LVL191 - .8byte .LVL192 - .2byte 0x1 - .byte 0x64 - .8byte .LVL192 - .8byte .LVL193 - .2byte 0x8 - .byte 0x74 - .sleb128 38 - .byte 0x94 - .byte 0x1 - .byte 0x8 - .byte 0xff - .byte 0x1a - .byte 0x9f - .8byte 0 - .8byte 0 -.LLST66: - .8byte .LVL181 - .8byte .LVL183 - .2byte 0x3 - .byte 0x9 - .byte 0xff - .byte 0x9f - .8byte .LVL183 - .8byte .LVL184 - .2byte 0x1 - .byte 0x64 - .8byte .LVL184 - .8byte .LVL186 - .2byte 0x3 - .byte 0x9 - .byte 0xff - .byte 0x9f - .8byte .LVL191 - .8byte .LVL193 - .2byte 0x3 - .byte 0x9 - .byte 0xff - .byte 0x9f - .8byte 0 - .8byte 0 -.LLST67: - .8byte .LVL182 - .8byte .LVL185 - .2byte 0x1 - .byte 0x53 - .8byte .LVL185 - .8byte .LVL187 - .2byte 0x1 - .byte 0x55 - .8byte .LVL191 - .8byte .LVL193 - .2byte 0x1 - .byte 0x53 - .8byte 0 - .8byte 0 -.LLST68: - .8byte .LVL189 - .8byte .LVL190-1 - .2byte 0x1 - .byte 0x50 - .8byte 0 - .8byte 0 -.LLST69: - .8byte .LVL193 - .8byte .LVL197 - .2byte 0x1 - .byte 0x64 - .8byte 0 - .8byte 0 -.LLST70: - .8byte .LVL193 - .8byte .LVL216 - .2byte 0x1 - .byte 0x63 - .8byte .LVL218 - .8byte .LVL236 - .2byte 0x1 - .byte 0x63 - .8byte 0 - .8byte 0 -.LLST71: - .8byte .LVL194 - .8byte .LVL195-1 - .2byte 0x1 - .byte 0x50 - .8byte 0 - .8byte 0 -.LLST72: - .8byte .LVL198 - .8byte .LVL200 - .2byte 0x1 - .byte 0x50 - .8byte .LVL200 - .8byte .LVL216 - .2byte 0x1 - .byte 0x66 - .8byte .LVL218 - .8byte .LVL236 - .2byte 0x1 - .byte 0x66 - .8byte 0 - .8byte 0 -.LLST73: - .8byte .LVL199 - .8byte .LVL202 - .2byte 0x2 - .byte 0x30 - .byte 0x9f - .8byte 0 - .8byte 0 -.LLST74: - .8byte .LVL199 - .8byte .LVL202 - .2byte 0x1 - .byte 0x64 - .8byte 0 - .8byte 0 -.LLST75: - .8byte .LVL203 - .8byte .LVL209 - .2byte 0x1 - .byte 0x66 - .8byte .LVL218 - .8byte .LVL221 - .2byte 0x1 - .byte 0x66 - .8byte 0 - .8byte 0 -.LLST76: - .8byte .LVL203 - .8byte .LVL204 - .2byte 0x1 - .byte 0x50 - .8byte .LVL204 - .8byte .LVL209 - .2byte 0x1 - .byte 0x68 - .8byte .LVL218 - .8byte .LVL221 - .2byte 0x1 - .byte 0x68 - .8byte 0 - .8byte 0 -.LLST77: - .8byte .LVL205 - .8byte .LVL206 - .2byte 0x2 - .byte 0x30 - .byte 0x9f - .8byte .LVL207 - .8byte .LVL208 - .2byte 0x1 - .byte 0x52 - .8byte .LVL208 - .8byte .LVL209-1 - .2byte 0x1 - .byte 0x53 - .8byte .LVL218 - .8byte .LVL219 - .2byte 0x1 - .byte 0x52 - .8byte .LVL219 - .8byte .LVL220 - .2byte 0x1 - .byte 0x53 - .8byte 0 - .8byte 0 -.LLST78: - .8byte .LVL210 - .8byte .LVL214 - .2byte 0x6 - .byte 0xf2 - .4byte .Ldebug_info0+4760 - .sleb128 0 - .8byte .LVL221 - .8byte .LVL236 - .2byte 0x6 - .byte 0xf2 - .4byte .Ldebug_info0+4760 - .sleb128 0 - .8byte 0 - .8byte 0 -.LLST79: - .8byte .LVL211 - .8byte .LVL213 - .2byte 0x1 - .byte 0x68 - .8byte .LVL213 - .8byte .LVL214 - .2byte 0x8 - .byte 0x72 - .sleb128 0 - .byte 0x32 - .byte 0x24 - .byte 0x88 - .sleb128 0 - .byte 0x22 - .byte 0x9f - .8byte .LVL221 - .8byte .LVL234 - .2byte 0x8 - .byte 0x72 - .sleb128 1 - .byte 0x32 - .byte 0x24 - .byte 0x88 - .sleb128 0 - .byte 0x22 - .byte 0x9f - .8byte .LVL234 - .8byte .LVL235 - .2byte 0x8 - .byte 0x72 - .sleb128 0 - .byte 0x32 - .byte 0x24 - .byte 0x88 - .sleb128 0 - .byte 0x22 - .byte 0x9f - .8byte .LVL235 - .8byte .LVL236 - .2byte 0x1 - .byte 0x68 - .8byte 0 - .8byte 0 -.LLST80: - .8byte .LVL213 - .8byte .LVL214 - .2byte 0x1 - .byte 0x52 - .8byte .LVL221 - .8byte .LVL233 - .2byte 0x1 - .byte 0x52 - .8byte .LVL233 - .8byte .LVL234 - .2byte 0x3 - .byte 0x72 - .sleb128 1 - .byte 0x9f - .8byte 0 - .8byte 0 -.LLST81: - .8byte .LVL222 - .8byte .LVL223 - .2byte 0x2 - .byte 0x30 - .byte 0x9f - .8byte .LVL223 - .8byte .LVL231 - .2byte 0x1 - .byte 0x53 - .8byte .LVL231 - .8byte .LVL232 - .2byte 0x3 - .byte 0x73 - .sleb128 1 - .byte 0x9f - .8byte 0 - .8byte 0 -.LLST82: - .8byte .LVL224 - .8byte .LVL225 - .2byte 0x2 - .byte 0x30 - .byte 0x9f - .8byte 0 - .8byte 0 -.LLST83: - .8byte .LVL228 - .8byte .LVL229 - .2byte 0x1 - .byte 0x51 - .8byte .LVL229 - .8byte .LVL230 - .2byte 0x3 - .byte 0x71 - .sleb128 1 - .byte 0x9f - .8byte 0 - .8byte 0 -.LLST84: - .8byte .LVL222 - .8byte .LVL235 - .2byte 0x1 - .byte 0x56 - .8byte 0 - .8byte 0 -.LLST85: - .8byte .LVL210 - .8byte .LVL213 - .2byte 0x2 - .byte 0x30 - .byte 0x9f - .8byte .LVL213 - .8byte .LVL214 - .2byte 0x5 - .byte 0x72 - .sleb128 0 - .byte 0x38 - .byte 0x24 - .byte 0x9f - .8byte .LVL221 - .8byte .LVL223 - .2byte 0x5 - .byte 0x72 - .sleb128 0 - .byte 0x38 - .byte 0x24 - .byte 0x9f - .8byte .LVL223 - .8byte .LVL228 - .2byte 0xa - .byte 0x73 - .sleb128 0 - .byte 0x34 - .byte 0x24 - .byte 0x72 - .sleb128 0 - .byte 0x38 - .byte 0x24 - .byte 0x22 - .byte 0x9f - .8byte .LVL228 - .8byte .LVL229 - .2byte 0xd - .byte 0x73 - .sleb128 0 - .byte 0x34 - .byte 0x24 - .byte 0x72 - .sleb128 0 - .byte 0x38 - .byte 0x24 - .byte 0x22 - .byte 0x71 - .sleb128 0 - .byte 0x22 - .byte 0x9f - .8byte .LVL229 - .8byte .LVL230 - .2byte 0xf - .byte 0x73 - .sleb128 0 - .byte 0x34 - .byte 0x24 - .byte 0x72 - .sleb128 0 - .byte 0x38 - .byte 0x24 - .byte 0x22 - .byte 0x71 - .sleb128 0 - .byte 0x22 - .byte 0x23 - .uleb128 0x1 - .byte 0x9f - .8byte .LVL231 - .8byte .LVL232 - .2byte 0xc - .byte 0x73 - .sleb128 0 - .byte 0x34 - .byte 0x24 - .byte 0x72 - .sleb128 0 - .byte 0x38 - .byte 0x24 - .byte 0x22 - .byte 0x23 - .uleb128 0x10 - .byte 0x9f - .8byte .LVL235 - .8byte .LVL236 - .2byte 0x2 - .byte 0x30 - .byte 0x9f - .8byte 0 - .8byte 0 -.LLST86: - .8byte .LVL211 - .8byte .LVL214 - .2byte 0x1 - .byte 0x65 - .8byte .LVL221 - .8byte .LVL236 - .2byte 0x1 - .byte 0x65 - .8byte 0 - .8byte 0 -.LLST87: - .8byte .LVL211 - .8byte .LVL212 - .2byte 0x2 - .byte 0x30 - .byte 0x9f - .8byte 0 - .8byte 0 -.LLST88: - .8byte .LVL224 - .8byte .LVL227 - .2byte 0x1 - .byte 0x51 - .8byte .LVL227 - .8byte .LVL232 - .2byte 0xd - .byte 0x76 - .sleb128 0 - .byte 0x73 - .sleb128 0 - .byte 0x31 - .byte 0x24 - .byte 0x8 - .byte 0xff - .byte 0x1a - .byte 0x26 - .byte 0x33 - .byte 0x1a - .byte 0x9f - .8byte 0 - .8byte 0 -.LLST89: - .8byte .LVL224 - .8byte .LVL225 - .2byte 0x1 - .byte 0x51 - .8byte .LVL225 - .8byte .LVL235 - .2byte 0x1 - .byte 0x55 - .8byte 0 - .8byte 0 -.LLST90: - .8byte .LVL215 - .8byte .LVL216 - .2byte 0x1 - .byte 0x68 - .8byte 0 - .8byte 0 -.LLST91: - .8byte .LVL253 - .8byte .LVL264 - .2byte 0x1 - .byte 0x64 - .8byte 0 - .8byte 0 -.LLST92: - .8byte .LVL253 - .8byte .LVL286 - .2byte 0x1 - .byte 0x63 - .8byte 0 - .8byte 0 -.LLST93: - .8byte .LVL254 - .8byte .LVL255-1 - .2byte 0x1 - .byte 0x50 - .8byte .LVL262 - .8byte .LVL263-1 - .2byte 0x1 - .byte 0x50 - .8byte 0 - .8byte 0 -.LLST94: - .8byte .LVL256 - .8byte .LVL258 - .2byte 0x1 - .byte 0x50 - .8byte .LVL258 - .8byte .LVL264 - .2byte 0x1 - .byte 0x65 - .8byte .LVL264 - .8byte .LVL265 - .2byte 0x1 - .byte 0x50 - .8byte .LVL265 - .8byte .LVL272 - .2byte 0x1 - .byte 0x64 - .8byte 0 - .8byte 0 -.LLST95: - .8byte .LVL274 - .8byte .LVL275 - .2byte 0x1 - .byte 0x65 - .8byte 0 - .8byte 0 -.LLST96: - .8byte .LVL257 - .8byte .LVL260 - .2byte 0x2 - .byte 0x30 - .byte 0x9f - .8byte 0 - .8byte 0 -.LLST97: - .8byte .LVL257 - .8byte .LVL258 - .2byte 0xb - .byte 0x70 - .sleb128 0 - .byte 0x36 - .byte 0x24 - .byte 0x8 - .byte 0x20 - .byte 0x24 - .byte 0x8 - .byte 0x20 - .byte 0x26 - .byte 0x9f - .8byte .LVL258 - .8byte .LVL259 - .2byte 0xb - .byte 0x85 - .sleb128 0 - .byte 0x36 - .byte 0x24 - .byte 0x8 - .byte 0x20 - .byte 0x24 - .byte 0x8 - .byte 0x20 - .byte 0x26 - .byte 0x9f - .8byte .LVL259 - .8byte .LVL260-1 - .2byte 0x1 - .byte 0x50 - .8byte .LVL260-1 - .8byte .LVL260 - .2byte 0xb - .byte 0x85 - .sleb128 0 - .byte 0x36 - .byte 0x24 - .byte 0x8 - .byte 0x20 - .byte 0x24 - .byte 0x8 - .byte 0x20 - .byte 0x26 - .byte 0x9f - .8byte 0 - .8byte 0 -.LLST98: - .8byte .LVL266 - .8byte .LVL269 - .2byte 0x2 - .byte 0x30 - .byte 0x9f - .8byte 0 - .8byte 0 -.LLST99: - .8byte .LVL266 - .8byte .LVL267 - .2byte 0xb - .byte 0x84 - .sleb128 0 - .byte 0x33 - .byte 0x24 - .byte 0x8 - .byte 0x20 - .byte 0x24 - .byte 0x8 - .byte 0x20 - .byte 0x26 - .byte 0x9f - .8byte .LVL267 - .8byte .LVL268-1 - .2byte 0x1 - .byte 0x50 - .8byte .LVL268-1 - .8byte .LVL269 - .2byte 0xb - .byte 0x84 - .sleb128 0 - .byte 0x33 - .byte 0x24 - .byte 0x8 - .byte 0x20 - .byte 0x24 - .byte 0x8 - .byte 0x20 - .byte 0x26 - .byte 0x9f - .8byte 0 - .8byte 0 -.LLST100: - .8byte .LVL271 - .8byte .LVL286 - .2byte 0x1 - .byte 0x63 - .8byte 0 - .8byte 0 -.LLST101: - .8byte .LVL271 - .8byte .LVL274 - .2byte 0x6 - .byte 0xf2 - .4byte .Ldebug_info0+5397 - .sleb128 0 - .8byte .LVL275 - .8byte .LVL286 - .2byte 0x6 - .byte 0xf2 - .4byte .Ldebug_info0+5397 - .sleb128 0 - .8byte 0 - .8byte 0 -.LLST102: - .8byte .LVL276 - .8byte .LVL277 - .2byte 0x2 - .byte 0x30 - .byte 0x9f - .8byte .LVL277 - .8byte .LVL282 - .2byte 0x1 - .byte 0x51 - .8byte .LVL282 - .8byte .LVL283 - .2byte 0x3 - .byte 0x71 - .sleb128 1 - .byte 0x9f - .8byte 0 - .8byte 0 -.LLST103: - .8byte .LVL276 - .8byte .LVL286 - .2byte 0x1 - .byte 0x56 - .8byte 0 - .8byte 0 -.LLST104: - .8byte .LVL271 - .8byte .LVL273 - .2byte 0x1 - .byte 0x65 - .8byte .LVL273 - .8byte .LVL274 - .2byte 0x3 - .byte 0x72 - .sleb128 -4 - .byte 0x9f - .8byte .LVL275 - .8byte .LVL285 - .2byte 0x1 - .byte 0x52 - .8byte .LVL285 - .8byte .LVL286 - .2byte 0x3 - .byte 0x72 - .sleb128 -8 - .byte 0x9f - .8byte 0 - .8byte 0 -.LLST105: - .8byte .LVL271 - .8byte .LVL274 - .2byte 0x1 - .byte 0x53 - .8byte .LVL275 - .8byte .LVL277 - .2byte 0x1 - .byte 0x53 - .8byte .LVL277 - .8byte .LVL282 - .2byte 0x8 - .byte 0x71 - .sleb128 0 - .byte 0x32 - .byte 0x24 - .byte 0x73 - .sleb128 0 - .byte 0x22 - .byte 0x9f - .8byte .LVL282 - .8byte .LVL283 - .2byte 0x8 - .byte 0x71 - .sleb128 1 - .byte 0x32 - .byte 0x24 - .byte 0x73 - .sleb128 0 - .byte 0x22 - .byte 0x9f - .8byte .LVL283 - .8byte .LVL284 - .2byte 0x8 - .byte 0x71 - .sleb128 0 - .byte 0x32 - .byte 0x24 - .byte 0x73 - .sleb128 0 - .byte 0x22 - .byte 0x9f - .8byte .LVL284 - .8byte .LVL286 - .2byte 0xb - .byte 0x71 - .sleb128 0 - .byte 0x32 - .byte 0x24 - .byte 0x73 - .sleb128 0 - .byte 0x22 - .byte 0x8 - .byte 0x40 - .byte 0x1c - .byte 0x9f - .8byte 0 - .8byte 0 -.LLST106: - .8byte .LVL278 - .8byte .LVL279 - .2byte 0x1 - .byte 0x50 - .8byte .LVL279 - .8byte .LVL280 - .2byte 0x1 - .byte 0x54 - .8byte .LVL280 - .8byte .LVL281 - .2byte 0x13 - .byte 0x77 - .sleb128 0 - .byte 0x70 - .sleb128 0 - .byte 0x26 - .byte 0x33 - .byte 0x1a - .byte 0x76 - .sleb128 0 - .byte 0x70 - .sleb128 0 - .byte 0x26 - .byte 0x4e - .byte 0x24 - .byte 0x21 - .byte 0x74 - .sleb128 0 - .byte 0x21 - .byte 0x9f - .8byte .LVL281 - .8byte .LVL283 - .2byte 0x17 - .byte 0x77 - .sleb128 0 - .byte 0x71 - .sleb128 0 - .byte 0x31 - .byte 0x24 - .byte 0x26 - .byte 0x33 - .byte 0x1a - .byte 0x76 - .sleb128 0 - .byte 0x71 - .sleb128 0 - .byte 0x31 - .byte 0x24 - .byte 0x26 - .byte 0x4e - .byte 0x24 - .byte 0x21 - .byte 0x74 - .sleb128 0 - .byte 0x21 - .byte 0x9f - .8byte 0 - .8byte 0 -.LLST107: - .8byte .LVL271 - .8byte .LVL273 - .2byte 0x2 - .byte 0x30 - .byte 0x9f - .8byte 0 - .8byte 0 -.LLST108: - .8byte .LVL236 - .8byte .LVL239 - .2byte 0x1 - .byte 0x64 - .8byte 0 - .8byte 0 -.LLST109: - .8byte .LVL236 - .8byte .LVL244 - .2byte 0x1 - .byte 0x63 - .8byte .LVL245 - .8byte .LVL246 - .2byte 0x1 - .byte 0x63 - .8byte 0 - .8byte 0 -.LLST110: - .8byte .LVL237 - .8byte .LVL238-1 - .2byte 0x1 - .byte 0x50 - .8byte 0 - .8byte 0 -.LLST111: - .8byte .LVL239 - .8byte .LVL241 - .2byte 0x1 - .byte 0x50 - .8byte .LVL241 - .8byte .LVL244 - .2byte 0x1 - .byte 0x64 - .8byte .LVL245 - .8byte .LVL246 - .2byte 0x1 - .byte 0x64 - .8byte 0 - .8byte 0 -.LLST112: - .8byte .LVL240 - .8byte .LVL243 - .2byte 0x2 - .byte 0x30 - .byte 0x9f - .8byte 0 - .8byte 0 -.LLST113: - .8byte .LVL240 - .8byte .LVL241 - .2byte 0xb - .byte 0x70 - .sleb128 0 - .byte 0x36 - .byte 0x24 - .byte 0x8 - .byte 0x20 - .byte 0x24 - .byte 0x8 - .byte 0x20 - .byte 0x26 - .byte 0x9f - .8byte .LVL241 - .8byte .LVL242 - .2byte 0xb - .byte 0x84 - .sleb128 0 - .byte 0x36 - .byte 0x24 - .byte 0x8 - .byte 0x20 - .byte 0x24 - .byte 0x8 - .byte 0x20 - .byte 0x26 - .byte 0x9f - .8byte .LVL242 - .8byte .LVL243-1 - .2byte 0x1 - .byte 0x50 - .8byte .LVL243-1 - .8byte .LVL243 - .2byte 0xb - .byte 0x84 - .sleb128 0 - .byte 0x36 - .byte 0x24 - .byte 0x8 - .byte 0x20 - .byte 0x24 - .byte 0x8 - .byte 0x20 - .byte 0x26 - .byte 0x9f - .8byte 0 - .8byte 0 -.LLST114: - .8byte .LVL286 - .8byte .LVL290 - .2byte 0x1 - .byte 0x64 - .8byte .LVL292 - .8byte .LVL296 - .2byte 0x1 - .byte 0x64 - .8byte 0 - .8byte 0 -.LLST115: - .8byte .LVL286 - .8byte .LVL290 - .2byte 0x1 - .byte 0x63 - .8byte .LVL292 - .8byte .LVL296 - .2byte 0x1 - .byte 0x63 - .8byte 0 - .8byte 0 -.LLST116: - .8byte .LVL287 - .8byte .LVL288-1 - .2byte 0x1 - .byte 0x50 - .8byte 0 - .8byte 0 -.LLST117: - .8byte .LVL289 - .8byte .LVL290 - .2byte 0x1 - .byte 0x50 - .8byte .LVL292 - .8byte .LVL294 - .2byte 0x1 - .byte 0x50 - .8byte .LVL294 - .8byte .LVL296 - .2byte 0x1 - .byte 0x65 - .8byte 0 - .8byte 0 -.LLST118: - .8byte .LVL293 - .8byte .LVL295 - .2byte 0x2 - .byte 0x30 - .byte 0x9f - .8byte 0 - .8byte 0 -.LLST119: - .8byte .LVL293 - .8byte .LVL295-1 - .2byte 0xd - .byte 0x83 - .sleb128 0 - .byte 0x94 - .byte 0x4 - .byte 0x36 - .byte 0x24 - .byte 0x8 - .byte 0x20 - .byte 0x24 - .byte 0x8 - .byte 0x20 - .byte 0x26 - .byte 0x9f - .8byte .LVL295-1 - .8byte .LVL295 - .2byte 0xb - .byte 0x85 - .sleb128 0 - .byte 0x36 - .byte 0x24 - .byte 0x8 - .byte 0x20 - .byte 0x24 - .byte 0x8 - .byte 0x20 - .byte 0x26 - .byte 0x9f - .8byte 0 - .8byte 0 -.LLST120: - .8byte .LVL296 - .8byte .LVL300 - .2byte 0x1 - .byte 0x64 - .8byte 0 - .8byte 0 -.LLST121: - .8byte .LVL296 - .8byte .LVL307 - .2byte 0x1 - .byte 0x63 - .8byte .LVL307 - .8byte .LVL320 - .2byte 0x4 - .byte 0xf3 - .uleb128 0x1 - .byte 0x50 - .byte 0x9f - .8byte 0 - .8byte 0 -.LLST122: - .8byte .LVL297 - .8byte .LVL298-1 - .2byte 0x1 - .byte 0x50 - .8byte 0 - .8byte 0 -.LLST123: - .8byte .LVL299 - .8byte .LVL302 - .2byte 0x1 - .byte 0x50 - .8byte .LVL302 - .8byte .LVL320 - .2byte 0x1 - .byte 0x67 - .8byte 0 - .8byte 0 -.LLST124: - .8byte .LVL301 - .8byte .LVL304 - .2byte 0x2 - .byte 0x30 - .byte 0x9f - .8byte 0 - .8byte 0 -.LLST125: - .8byte .LVL301 - .8byte .LVL304 - .2byte 0x1 - .byte 0x64 - .8byte 0 - .8byte 0 -.LLST126: - .8byte .LVL305 - .8byte .LVL320 - .2byte 0x1 - .byte 0x67 - .8byte 0 - .8byte 0 -.LLST127: - .8byte .LVL305 - .8byte .LVL308 - .2byte 0x1 - .byte 0x50 - .8byte .LVL308 - .8byte .LVL320 - .2byte 0x1 - .byte 0x66 - .8byte 0 - .8byte 0 -.LLST128: - .8byte .LVL310 - .8byte .LVL311 - .2byte 0x2 - .byte 0x30 - .byte 0x9f - .8byte 0 - .8byte 0 -.LLST129: - .8byte .LVL309 - .8byte .LVL310 - .2byte 0x2 - .byte 0x30 - .byte 0x9f - .8byte .LVL310 - .8byte .LVL317 - .2byte 0x1 - .byte 0x53 - .8byte .LVL317 - .8byte .LVL318 - .2byte 0x3 - .byte 0x73 - .sleb128 1 - .byte 0x9f - .8byte 0 - .8byte 0 -.LLST130: - .8byte .LVL311 - .8byte .LVL315 - .2byte 0x1 - .byte 0x56 - .8byte .LVL316 - .8byte .LVL319-1 - .2byte 0x1 - .byte 0x56 - .8byte 0 - .8byte 0 -.LLST131: - .8byte .LVL311 - .8byte .LVL312 - .2byte 0x1 - .byte 0x53 - .8byte 0 - .8byte 0 -.LLST132: - .8byte .LVL311 - .8byte .LVL312 - .2byte 0x1 - .byte 0x56 - .8byte 0 - .8byte 0 -.LLST33: - .8byte .LVL141 - .8byte .LVL142 - .2byte 0x1 - .byte 0x50 - .8byte .LVL142 - .8byte .LVL150 - .2byte 0x1 - .byte 0x64 - .8byte .LVL150 - .8byte .LVL151 - .2byte 0x4 - .byte 0xf3 - .uleb128 0x1 - .byte 0x50 - .byte 0x9f - .8byte .LVL151 - .8byte .LFE229 - .2byte 0x1 - .byte 0x64 - .8byte 0 - .8byte 0 -.LLST34: - .8byte .LVL141 - .8byte .LVL143-1 - .2byte 0x1 - .byte 0x51 - .8byte .LVL143-1 - .8byte .LVL145 - .2byte 0x1 - .byte 0x63 - .8byte .LVL145 - .8byte .LFE229 - .2byte 0x4 - .byte 0xf3 - .uleb128 0x1 - .byte 0x51 - .byte 0x9f - .8byte 0 - .8byte 0 -.LLST35: - .8byte .LVL141 - .8byte .LVL143-1 - .2byte 0x1 - .byte 0x52 - .8byte .LVL143-1 - .8byte .LFE229 - .2byte 0x4 - .byte 0xf3 - .uleb128 0x1 - .byte 0x52 - .byte 0x9f - .8byte 0 - .8byte 0 -.LLST36: - .8byte .LVL143 - .8byte .LVL144-1 - .2byte 0x1 - .byte 0x50 - .8byte 0 - .8byte 0 -.LLST37: - .8byte .LVL145 - .8byte .LVL146 - .2byte 0x1 - .byte 0x50 - .8byte .LVL146 - .8byte .LVL150 - .2byte 0x1 - .byte 0x63 - .8byte .LVL151 - .8byte .LFE229 - .2byte 0x1 - .byte 0x63 - .8byte 0 - .8byte 0 -.LLST38: - .8byte .LVL145 - .8byte .LVL148 - .2byte 0x2 - .byte 0x30 - .byte 0x9f - .8byte 0 - .8byte 0 -.LLST39: - .8byte .LVL145 - .8byte .LVL146 - .2byte 0xb - .byte 0x70 - .sleb128 0 - .byte 0x36 - .byte 0x24 - .byte 0x8 - .byte 0x20 - .byte 0x24 - .byte 0x8 - .byte 0x20 - .byte 0x26 - .byte 0x9f - .8byte .LVL146 - .8byte .LVL147 - .2byte 0xb - .byte 0x83 - .sleb128 0 - .byte 0x36 - .byte 0x24 - .byte 0x8 - .byte 0x20 - .byte 0x24 - .byte 0x8 - .byte 0x20 - .byte 0x26 - .byte 0x9f - .8byte .LVL147 - .8byte .LVL148-1 - .2byte 0x1 - .byte 0x50 - .8byte .LVL148-1 - .8byte .LVL148 - .2byte 0xb - .byte 0x83 - .sleb128 0 - .byte 0x36 - .byte 0x24 - .byte 0x8 - .byte 0x20 - .byte 0x24 - .byte 0x8 - .byte 0x20 - .byte 0x26 - .byte 0x9f - .8byte 0 - .8byte 0 -.LLST40: - .8byte .LVL152 - .8byte .LVL153 - .2byte 0x1 - .byte 0x50 - .8byte .LVL153 - .8byte .LVL169 - .2byte 0x1 - .byte 0x65 - .8byte .LVL169 - .8byte .LVL170 - .2byte 0x4 - .byte 0xf3 - .uleb128 0x1 - .byte 0x50 - .byte 0x9f - .8byte .LVL170 - .8byte .LFE226 - .2byte 0x1 - .byte 0x65 - .8byte 0 - .8byte 0 -.LLST41: - .8byte .LVL152 - .8byte .LVL154-1 - .2byte 0x1 - .byte 0x51 - .8byte .LVL154-1 - .8byte .LVL156 - .2byte 0x1 - .byte 0x63 - .8byte .LVL156 - .8byte .LFE226 - .2byte 0x4 - .byte 0xf3 - .uleb128 0x1 - .byte 0x51 - .byte 0x9f - .8byte 0 - .8byte 0 -.LLST42: - .8byte .LVL154 - .8byte .LVL155-1 - .2byte 0x1 - .byte 0x50 - .8byte 0 - .8byte 0 -.LLST43: - .8byte .LVL156 - .8byte .LVL157 - .2byte 0x1 - .byte 0x50 - .8byte .LVL157 - .8byte .LVL168 - .2byte 0x1 - .byte 0x63 - .8byte .LVL170 - .8byte .LFE226 - .2byte 0x1 - .byte 0x63 - .8byte 0 - .8byte 0 -.LLST44: - .8byte .LVL156 - .8byte .LVL159 - .2byte 0x2 - .byte 0x30 - .byte 0x9f - .8byte 0 - .8byte 0 -.LLST45: - .8byte .LVL156 - .8byte .LVL157 - .2byte 0xb - .byte 0x70 - .sleb128 0 - .byte 0x33 - .byte 0x24 - .byte 0x8 - .byte 0x20 - .byte 0x24 - .byte 0x8 - .byte 0x20 - .byte 0x26 - .byte 0x9f - .8byte .LVL157 - .8byte .LVL158 - .2byte 0xb - .byte 0x83 - .sleb128 0 - .byte 0x33 - .byte 0x24 - .byte 0x8 - .byte 0x20 - .byte 0x24 - .byte 0x8 - .byte 0x20 - .byte 0x26 - .byte 0x9f - .8byte .LVL158 - .8byte .LVL159-1 - .2byte 0x1 - .byte 0x50 - .8byte .LVL159-1 - .8byte .LVL159 - .2byte 0xb - .byte 0x83 - .sleb128 0 - .byte 0x33 - .byte 0x24 - .byte 0x8 - .byte 0x20 - .byte 0x24 - .byte 0x8 - .byte 0x20 - .byte 0x26 - .byte 0x9f - .8byte 0 - .8byte 0 -.LLST46: - .8byte .LVL161 - .8byte .LVL165 - .2byte 0x6 - .byte 0xf2 - .4byte .Ldebug_info0+7384 - .sleb128 0 - .8byte .LVL170 - .8byte .LVL179 - .2byte 0x6 - .byte 0xf2 - .4byte .Ldebug_info0+7384 - .sleb128 0 - .8byte 0 - .8byte 0 -.LLST47: - .8byte .LVL161 - .8byte .LVL164 - .2byte 0x1 - .byte 0x64 - .8byte .LVL164 - .8byte .LVL165 - .2byte 0x1 - .byte 0x54 - .8byte .LVL170 - .8byte .LVL171 - .2byte 0x3 - .byte 0x74 - .sleb128 4 - .byte 0x9f - .8byte .LVL171 - .8byte .LVL178 - .2byte 0x1 - .byte 0x54 - .8byte .LVL178 - .8byte .LVL179 - .2byte 0x1 - .byte 0x64 - .8byte 0 - .8byte 0 -.LLST48: - .8byte .LVL173 - .8byte .LVL174 - .2byte 0x8 - .byte 0x78 - .sleb128 0 - .byte 0x71 - .sleb128 0 - .byte 0x26 - .byte 0x33 - .byte 0x1a - .byte 0x9f - .8byte .LVL174 - .8byte .LVL176 - .2byte 0xa - .byte 0x78 - .sleb128 0 - .byte 0x72 - .sleb128 0 - .byte 0x31 - .byte 0x24 - .byte 0x26 - .byte 0x33 - .byte 0x1a - .byte 0x9f - .8byte 0 - .8byte 0 -.LLST49: - .8byte .LVL173 - .8byte .LVL174 - .2byte 0x8 - .byte 0x77 - .sleb128 0 - .byte 0x71 - .sleb128 0 - .byte 0x26 - .byte 0x33 - .byte 0x1a - .byte 0x9f - .8byte .LVL174 - .8byte .LVL176 - .2byte 0xa - .byte 0x77 - .sleb128 0 - .byte 0x72 - .sleb128 0 - .byte 0x31 - .byte 0x24 - .byte 0x26 - .byte 0x33 - .byte 0x1a - .byte 0x9f - .8byte 0 - .8byte 0 -.LLST50: - .8byte .LVL173 - .8byte .LVL174 - .2byte 0x10 - .byte 0x78 - .sleb128 0 - .byte 0x71 - .sleb128 0 - .byte 0x26 - .byte 0x33 - .byte 0x1a - .byte 0x77 - .sleb128 0 - .byte 0x71 - .sleb128 0 - .byte 0x26 - .byte 0x4e - .byte 0x24 - .byte 0x21 - .byte 0x9f - .8byte .LVL174 - .8byte .LVL176 - .2byte 0x14 - .byte 0x78 - .sleb128 0 - .byte 0x72 - .sleb128 0 - .byte 0x31 - .byte 0x24 - .byte 0x26 - .byte 0x33 - .byte 0x1a - .byte 0x77 - .sleb128 0 - .byte 0x72 - .sleb128 0 - .byte 0x31 - .byte 0x24 - .byte 0x26 - .byte 0x4e - .byte 0x24 - .byte 0x21 - .byte 0x9f - .8byte 0 - .8byte 0 -.LLST51: - .8byte .LVL171 - .8byte .LVL178 - .2byte 0x1 - .byte 0x58 - .8byte 0 - .8byte 0 -.LLST52: - .8byte .LVL172 - .8byte .LVL178 - .2byte 0x1 - .byte 0x57 - .8byte 0 - .8byte 0 -.LLST53: - .8byte .LVL161 - .8byte .LVL164 - .2byte 0x2 - .byte 0x30 - .byte 0x9f - .8byte .LVL164 - .8byte .LVL165 - .2byte 0x5 - .byte 0x73 - .sleb128 0 - .byte 0x34 - .byte 0x24 - .byte 0x9f - .8byte .LVL170 - .8byte .LVL172 - .2byte 0x5 - .byte 0x73 - .sleb128 0 - .byte 0x34 - .byte 0x24 - .byte 0x9f - .8byte .LVL172 - .8byte .LVL175 - .2byte 0x8 - .byte 0x73 - .sleb128 0 - .byte 0x34 - .byte 0x24 - .byte 0x72 - .sleb128 0 - .byte 0x22 - .byte 0x9f - .8byte .LVL175 - .8byte .LVL176 - .2byte 0xa - .byte 0x73 - .sleb128 0 - .byte 0x34 - .byte 0x24 - .byte 0x72 - .sleb128 0 - .byte 0x22 - .byte 0x23 - .uleb128 0x1 - .byte 0x9f - .8byte .LVL178 - .8byte .LVL179 - .2byte 0x2 - .byte 0x30 - .byte 0x9f - .8byte 0 - .8byte 0 -.LLST54: - .8byte .LVL164 - .8byte .LVL165 - .2byte 0x1 - .byte 0x53 - .8byte .LVL170 - .8byte .LVL178 - .2byte 0x1 - .byte 0x53 - .8byte 0 - .8byte 0 -.LLST55: + .uleb128 0x51 + .uleb128 0x2e + .byte 0 + .uleb128 0x3f + .uleb128 0x19 + .uleb128 0x3c + .uleb128 0x19 + .uleb128 0x6e + .uleb128 0xe + .uleb128 0x3 + .uleb128 0xe + .uleb128 0x3a + .uleb128 0xb + .uleb128 0x3b + .uleb128 0xb + .byte 0 + .byte 0 + .uleb128 0x52 + .uleb128 0x2e + .byte 0 + .uleb128 0x3f + .uleb128 0x19 + .uleb128 0x3c + .uleb128 0x19 + .uleb128 0x6e + .uleb128 0xe + .uleb128 0x3 + .uleb128 0xe + .uleb128 0x3a + .uleb128 0xb + .uleb128 0x3b + .uleb128 0x5 + .byte 0 + .byte 0 + .byte 0 + .section .debug_loc,"",@progbits +.Ldebug_loc0: +.LLST47: .8byte .LVL172 - .8byte .LVL175 + .8byte .LVL173 .2byte 0x1 - .byte 0x52 - .8byte .LVL175 - .8byte .LVL176 + .byte 0x51 + .8byte .LVL173 + .8byte .LVL174 .2byte 0x3 - .byte 0x72 + .byte 0x71 .sleb128 1 .byte 0x9f .8byte 0 .8byte 0 -.LLST56: - .8byte .LVL161 +.LLST45: + .8byte .LVL164 .8byte .LVL165 .2byte 0x1 - .byte 0x63 - .8byte .LVL170 - .8byte .LVL179 + .byte 0x50 + .8byte .LVL165 + .8byte .LVL168 .2byte 0x1 .byte 0x63 - .8byte 0 - .8byte 0 -.LLST57: - .8byte .LVL161 - .8byte .LVL163 - .2byte 0x2 - .byte 0x30 - .byte 0x9f - .8byte 0 - .8byte 0 -.LLST58: - .8byte .LVL161 - .8byte .LVL162 - .2byte 0xb - .byte 0x83 - .sleb128 0 - .byte 0x36 - .byte 0x24 - .byte 0xc - .4byte 0xffffffff - .byte 0x1a - .byte 0x9f - .8byte .LVL162 - .8byte .LVL163-1 - .2byte 0x1 + .8byte .LVL168 + .8byte .LVL169 + .2byte 0x4 + .byte 0xf3 + .uleb128 0x1 .byte 0x50 - .8byte .LVL163-1 - .8byte .LVL163 - .2byte 0xb - .byte 0x83 - .sleb128 0 - .byte 0x36 - .byte 0x24 - .byte 0xc - .4byte 0xffffffff - .byte 0x1a .byte 0x9f - .8byte 0 - .8byte 0 -.LLST59: - .8byte .LVL166 - .8byte .LVL167 - .2byte 0x1 - .byte 0x64 - .8byte 0 - .8byte 0 -.LLST4: - .8byte .LVL27 - .8byte .LVL28 - .2byte 0x1 - .byte 0x50 - .8byte .LVL28 - .8byte .LVL39 - .2byte 0x1 - .byte 0x66 - .8byte .LVL39 - .8byte .LVL40-1 + .8byte .LVL169 + .8byte .LVL170 .2byte 0x1 .byte 0x50 - .8byte .LVL40-1 - .8byte .LFE224 + .8byte .LVL170 + .8byte .LFE227 .2byte 0x4 .byte 0xf3 .uleb128 0x1 @@ -10188,1012 +5326,699 @@ __func__.6107: .byte 0x9f .8byte 0 .8byte 0 -.LLST5: - .8byte .LVL27 - .8byte .LVL29 +.LLST46: + .8byte .LVL164 + .8byte .LVL165 .2byte 0x1 - .byte 0x51 - .8byte .LVL29 - .8byte .LVL38 + .byte 0x50 + .8byte .LVL165 + .8byte .LVL168 .2byte 0x1 - .byte 0x64 - .8byte .LVL38 - .8byte .LFE224 + .byte 0x63 + .8byte .LVL168 + .8byte .LVL169 .2byte 0x4 .byte 0xf3 .uleb128 0x1 - .byte 0x51 - .byte 0x9f - .8byte 0 - .8byte 0 -.LLST6: - .8byte .LVL31 - .8byte .LVL32 - .2byte 0x2 - .byte 0x30 - .byte 0x9f - .8byte 0 - .8byte 0 -.LLST7: - .8byte .LVL30 - .8byte .LVL31 - .2byte 0x2 - .byte 0x30 + .byte 0x50 .byte 0x9f - .8byte .LVL31 - .8byte .LVL36 + .8byte .LVL169 + .8byte .LVL170 .2byte 0x1 - .byte 0x54 - .8byte .LVL36 - .8byte .LVL37 - .2byte 0x3 - .byte 0x74 - .sleb128 1 + .byte 0x50 + .8byte .LVL170 + .8byte .LFE227 + .2byte 0x4 + .byte 0xf3 + .uleb128 0x1 + .byte 0x50 .byte 0x9f .8byte 0 .8byte 0 -.LLST8: - .8byte .LVL32 - .8byte .LVL33 - .2byte 0x1 - .byte 0x55 - .8byte .LVL34 - .8byte .LVL35 - .2byte 0x1 - .byte 0x55 - .8byte .LVL36 - .8byte .LVL40-1 - .2byte 0x1 - .byte 0x55 - .8byte 0 - .8byte 0 -.LLST9: - .8byte .LVL41 - .8byte .LVL42 - .2byte 0x1 - .byte 0x50 - .8byte .LVL42 - .8byte .LVL52 - .2byte 0x1 - .byte 0x66 - .8byte .LVL52 - .8byte .LVL53-1 +.LLST25: + .8byte .LVL121 + .8byte .LVL122 .2byte 0x1 .byte 0x50 - .8byte .LVL53-1 - .8byte .LFE222 + .8byte .LVL122 + .8byte .LVL123 .2byte 0x4 .byte 0xf3 .uleb128 0x1 .byte 0x50 .byte 0x9f - .8byte 0 - .8byte 0 -.LLST10: - .8byte .LVL41 - .8byte .LVL43 + .8byte .LVL123 + .8byte .LVL124 .2byte 0x1 - .byte 0x51 - .8byte .LVL43 - .8byte .LVL52 + .byte 0x50 + .8byte .LVL124 + .8byte .LVL133 .2byte 0x1 - .byte 0x65 - .8byte .LVL52 - .8byte .LFE222 + .byte 0x63 + .8byte .LVL133 + .8byte .LVL134 .2byte 0x4 .byte 0xf3 .uleb128 0x1 - .byte 0x51 - .byte 0x9f - .8byte 0 - .8byte 0 -.LLST11: - .8byte .LVL48 - .8byte .LVL50 - .2byte 0x2 - .byte 0x32 - .byte 0x9f - .8byte 0 - .8byte 0 -.LLST12: - .8byte .LVL46 - .8byte .LVL47 - .2byte 0x1 - .byte 0x54 - .8byte 0 - .8byte 0 -.LLST13: - .8byte .LVL44 - .8byte .LVL45 - .2byte 0x2 - .byte 0x30 + .byte 0x50 .byte 0x9f - .8byte .LVL45 - .8byte .LVL51 - .2byte 0x1 - .byte 0x52 - .8byte 0 - .8byte 0 -.LLST24: - .8byte .LVL117 - .8byte .LVL119 + .8byte .LVL134 + .8byte .LVL148 .2byte 0x1 - .byte 0x50 - .8byte .LVL119 - .8byte .LFE217 + .byte 0x63 + .8byte .LVL148 + .8byte .LVL149 .2byte 0x4 .byte 0xf3 .uleb128 0x1 .byte 0x50 .byte 0x9f - .8byte 0 - .8byte 0 -.LLST25: - .8byte .LVL117 - .8byte .LVL124 + .8byte .LVL149 + .8byte .LVL160 .2byte 0x1 - .byte 0x51 - .8byte .LVL124 - .8byte .LVL126 + .byte 0x63 + .8byte .LVL160 + .8byte .LVL161 + .2byte 0x1 + .byte 0x50 + .8byte .LVL161 + .8byte .LVL162 .2byte 0x4 .byte 0xf3 .uleb128 0x1 - .byte 0x51 + .byte 0x50 .byte 0x9f - .8byte .LVL126 - .8byte .LVL131 + .8byte .LVL162 + .8byte .LVL163 .2byte 0x1 - .byte 0x51 - .8byte .LVL131 - .8byte .LFE217 + .byte 0x50 + .8byte .LVL163 + .8byte .LFE226 .2byte 0x4 .byte 0xf3 .uleb128 0x1 - .byte 0x51 + .byte 0x50 .byte 0x9f .8byte 0 .8byte 0 .LLST26: - .8byte .LVL117 - .8byte .LVL124 + .8byte .LVL121 + .8byte .LVL125-1 .2byte 0x1 - .byte 0x52 - .8byte .LVL124 - .8byte .LVL126 - .2byte 0x4 - .byte 0xf3 - .uleb128 0x1 - .byte 0x52 - .byte 0x9f - .8byte .LVL126 + .byte 0x51 + .8byte .LVL125-1 .8byte .LVL133 .2byte 0x1 - .byte 0x52 + .byte 0x65 .8byte .LVL133 .8byte .LVL134 .2byte 0x4 .byte 0xf3 .uleb128 0x1 - .byte 0x52 + .byte 0x51 .byte 0x9f .8byte .LVL134 - .8byte .LVL137 + .8byte .LVL148 .2byte 0x1 - .byte 0x52 - .8byte .LVL137 - .8byte .LVL139 + .byte 0x65 + .8byte .LVL148 + .8byte .LVL149 .2byte 0x4 .byte 0xf3 .uleb128 0x1 - .byte 0x52 + .byte 0x51 .byte 0x9f - .8byte .LVL139 - .8byte .LVL140 + .8byte .LVL149 + .8byte .LVL160 + .2byte 0x1 + .byte 0x65 + .8byte .LVL160 + .8byte .LFE226 + .2byte 0x1 + .byte 0x51 + .8byte 0 + .8byte 0 +.LLST27: + .8byte .LVL121 + .8byte .LVL125-1 .2byte 0x1 .byte 0x52 - .8byte .LVL140 - .8byte .LFE217 + .8byte .LVL125-1 + .8byte .LVL160 .2byte 0x4 .byte 0xf3 .uleb128 0x1 .byte 0x52 .byte 0x9f - .8byte 0 - .8byte 0 -.LLST27: - .8byte .LVL118 - .8byte .LVL125-1 - .2byte 0x1 - .byte 0x54 - .8byte .LVL126 - .8byte .LVL139-1 - .2byte 0x1 - .byte 0x54 - .8byte .LVL139 - .8byte .LFE217 + .8byte .LVL160 + .8byte .LFE226 .2byte 0x1 - .byte 0x54 + .byte 0x52 .8byte 0 .8byte 0 .LLST28: - .8byte .LVL120 - .8byte .LVL124 - .2byte 0x1 - .byte 0x57 - .8byte .LVL126 - .8byte .LVL129 - .2byte 0x1 - .byte 0x57 - .8byte .LVL129 - .8byte .LVL139-1 - .2byte 0x1 - .byte 0x56 - .8byte .LVL139 - .8byte .LFE217 - .2byte 0x1 - .byte 0x56 - .8byte 0 - .8byte 0 -.LLST29: - .8byte .LVL122 - .8byte .LVL124 - .2byte 0x1 - .byte 0x55 - .8byte .LVL126 - .8byte .LVL131 - .2byte 0x1 - .byte 0x55 - .8byte .LVL131 - .8byte .LVL135 + .8byte .LVL121 + .8byte .LVL125-1 .2byte 0x1 - .byte 0x51 - .8byte .LVL135 - .8byte .LVL139-1 - .2byte 0x59 - .byte 0xf3 - .uleb128 0x1 - .byte 0x50 - .byte 0x32 - .byte 0x24 - .byte 0x74 - .sleb128 32 - .byte 0x94 - .byte 0x1 - .byte 0x8 - .byte 0xff - .byte 0x1a - .byte 0x22 - .byte 0x8 - .byte 0x20 - .byte 0x24 - .byte 0x8 - .byte 0x20 - .byte 0x26 - .byte 0x74 - .sleb128 0 - .byte 0x22 - .byte 0x23 - .uleb128 0x1 - .byte 0x94 - .byte 0x1 - .byte 0x8 - .byte 0xff - .byte 0x1a - .byte 0x38 - .byte 0x24 - .byte 0xf3 - .uleb128 0x1 - .byte 0x50 - .byte 0x32 - .byte 0x24 - .byte 0x74 - .sleb128 32 - .byte 0x94 - .byte 0x1 - .byte 0x8 - .byte 0xff - .byte 0x1a - .byte 0x22 - .byte 0x8 - .byte 0x20 - .byte 0x24 - .byte 0x8 - .byte 0x20 - .byte 0x26 - .byte 0x74 - .sleb128 0 - .byte 0x22 - .byte 0x23 - .uleb128 0x2 - .byte 0x94 - .byte 0x1 - .byte 0x8 - .byte 0xff - .byte 0x1a - .byte 0x40 - .byte 0x24 - .byte 0x21 - .byte 0x77 - .sleb128 0 - .byte 0x21 + .byte 0x53 + .8byte .LVL125-1 + .8byte .LVL160 + .2byte 0x4 .byte 0xf3 .uleb128 0x1 - .byte 0x51 - .byte 0x32 - .byte 0x24 - .byte 0x22 - .byte 0x8 - .byte 0x20 - .byte 0x24 - .byte 0x8 - .byte 0x20 - .byte 0x26 - .byte 0x74 - .sleb128 0 - .byte 0x22 - .byte 0x23 - .uleb128 0x1 - .byte 0x94 - .byte 0x1 - .byte 0x8 - .byte 0xff - .byte 0x1a + .byte 0x53 .byte 0x9f - .8byte .LVL139 - .8byte .LFE217 - .2byte 0x59 - .byte 0xf3 - .uleb128 0x1 - .byte 0x50 - .byte 0x32 - .byte 0x24 - .byte 0x74 - .sleb128 32 - .byte 0x94 - .byte 0x1 - .byte 0x8 - .byte 0xff - .byte 0x1a - .byte 0x22 - .byte 0x8 - .byte 0x20 - .byte 0x24 - .byte 0x8 - .byte 0x20 - .byte 0x26 - .byte 0x74 - .sleb128 0 - .byte 0x22 - .byte 0x23 - .uleb128 0x1 - .byte 0x94 - .byte 0x1 - .byte 0x8 - .byte 0xff - .byte 0x1a - .byte 0x38 - .byte 0x24 - .byte 0xf3 - .uleb128 0x1 - .byte 0x50 - .byte 0x32 - .byte 0x24 - .byte 0x74 - .sleb128 32 - .byte 0x94 - .byte 0x1 - .byte 0x8 - .byte 0xff - .byte 0x1a - .byte 0x22 - .byte 0x8 - .byte 0x20 - .byte 0x24 - .byte 0x8 - .byte 0x20 - .byte 0x26 - .byte 0x74 - .sleb128 0 - .byte 0x22 - .byte 0x23 - .uleb128 0x2 - .byte 0x94 - .byte 0x1 - .byte 0x8 - .byte 0xff - .byte 0x1a - .byte 0x40 - .byte 0x24 - .byte 0x21 - .byte 0x77 - .sleb128 0 - .byte 0x21 + .8byte .LVL160 + .8byte .LFE226 + .2byte 0x1 + .byte 0x53 + .8byte 0 + .8byte 0 +.LLST29: + .8byte .LVL121 + .8byte .LVL125-1 + .2byte 0x1 + .byte 0x54 + .8byte .LVL125-1 + .8byte .LVL133 + .2byte 0x1 + .byte 0x66 + .8byte .LVL133 + .8byte .LVL134 + .2byte 0x4 .byte 0xf3 .uleb128 0x1 - .byte 0x51 - .byte 0x32 - .byte 0x24 - .byte 0x22 - .byte 0x8 - .byte 0x20 - .byte 0x24 - .byte 0x8 - .byte 0x20 - .byte 0x26 - .byte 0x74 - .sleb128 0 - .byte 0x22 - .byte 0x23 + .byte 0x54 + .byte 0x9f + .8byte .LVL134 + .8byte .LVL148 + .2byte 0x1 + .byte 0x66 + .8byte .LVL148 + .8byte .LVL149 + .2byte 0x4 + .byte 0xf3 .uleb128 0x1 - .byte 0x94 - .byte 0x1 - .byte 0x8 - .byte 0xff - .byte 0x1a + .byte 0x54 .byte 0x9f + .8byte .LVL149 + .8byte .LVL160 + .2byte 0x1 + .byte 0x66 + .8byte .LVL160 + .8byte .LFE226 + .2byte 0x1 + .byte 0x54 .8byte 0 .8byte 0 .LLST30: - .8byte .LVL123 - .8byte .LVL124 - .2byte 0x1 - .byte 0x56 .8byte .LVL126 - .8byte .LVL129 + .8byte .LVL127 .2byte 0x1 - .byte 0x56 - .8byte .LVL129 - .8byte .LVL132 - .2byte 0x1e - .byte 0xf3 - .uleb128 0x1 .byte 0x50 - .byte 0x32 - .byte 0x24 - .byte 0x74 - .sleb128 32 - .byte 0x94 - .byte 0x1 - .byte 0x8 - .byte 0xff - .byte 0x1a - .byte 0x22 - .byte 0x8 - .byte 0x20 - .byte 0x24 - .byte 0x8 - .byte 0x20 - .byte 0x26 - .byte 0x74 - .sleb128 0 - .byte 0x22 - .byte 0x23 - .uleb128 0x2 - .byte 0x94 - .byte 0x1 - .byte 0x8 - .byte 0xff - .byte 0x1a - .byte 0x9f - .8byte .LVL132 - .8byte .LVL139-1 + .8byte .LVL127 + .8byte .LVL133 .2byte 0x1 - .byte 0x55 - .8byte .LVL139 - .8byte .LFE217 + .byte 0x64 + .8byte .LVL134 + .8byte .LVL138 .2byte 0x1 - .byte 0x55 + .byte 0x64 .8byte 0 .8byte 0 .LLST31: - .8byte .LVL123 - .8byte .LVL124 - .2byte 0x1e - .byte 0xf3 - .uleb128 0x1 - .byte 0x50 - .byte 0x32 - .byte 0x24 - .byte 0x74 - .sleb128 32 - .byte 0x94 - .byte 0x1 - .byte 0x8 - .byte 0xff - .byte 0x1a - .byte 0x22 - .byte 0x8 - .byte 0x20 - .byte 0x24 - .byte 0x8 - .byte 0x20 - .byte 0x26 - .byte 0x74 + .8byte .LVL128 + .8byte .LVL129-1 + .2byte 0x6 + .byte 0x70 .sleb128 0 - .byte 0x22 - .byte 0x23 - .uleb128 0x3 - .byte 0x94 - .byte 0x1 .byte 0x8 .byte 0xff .byte 0x1a .byte 0x9f - .8byte .LVL126 - .8byte .LVL132 - .2byte 0x1e - .byte 0xf3 - .uleb128 0x1 + .8byte 0 + .8byte 0 +.LLST32: + .8byte .LVL130 + .8byte .LVL131 + .2byte 0x1 .byte 0x50 - .byte 0x32 - .byte 0x24 - .byte 0x74 - .sleb128 32 - .byte 0x94 - .byte 0x1 - .byte 0x8 - .byte 0xff - .byte 0x1a - .byte 0x22 - .byte 0x8 - .byte 0x20 - .byte 0x24 - .byte 0x8 - .byte 0x20 - .byte 0x26 - .byte 0x74 - .sleb128 0 - .byte 0x22 - .byte 0x23 - .uleb128 0x3 - .byte 0x94 - .byte 0x1 - .byte 0x8 - .byte 0xff - .byte 0x1a + .8byte .LVL131 + .8byte .LVL133 + .2byte 0x1 + .byte 0x67 + .8byte .LVL134 + .8byte .LVL135 + .2byte 0x1 + .byte 0x50 + .8byte .LVL135 + .8byte .LVL147 + .2byte 0x1 + .byte 0x67 + .8byte .LVL149 + .8byte .LVL160 + .2byte 0x1 + .byte 0x67 + .8byte 0 + .8byte 0 +.LLST33: + .8byte .LVL136 + .8byte .LVL137-1 + .2byte 0x1 + .byte 0x50 + .8byte 0 + .8byte 0 +.LLST34: + .8byte .LVL139 + .8byte .LVL141 + .2byte 0x2 + .byte 0x30 .byte 0x9f - .8byte .LVL132 - .8byte .LVL139-1 - .2byte 0x59 - .byte 0xf3 - .uleb128 0x1 + .8byte 0 + .8byte 0 +.LLST35: + .8byte .LVL139 + .8byte .LVL141 + .2byte 0x1 + .byte 0x64 + .8byte 0 + .8byte 0 +.LLST36: + .8byte .LVL143 + .8byte .LVL146-1 + .2byte 0x9 + .byte 0x3 + .8byte need_pic + .8byte .LVL149 + .8byte .LVL150-1 + .2byte 0x9 + .byte 0x3 + .8byte need_pic + .8byte 0 + .8byte 0 +.LLST37: + .8byte .LVL143 + .8byte .LVL147 + .2byte 0x1 + .byte 0x67 + .8byte .LVL149 + .8byte .LVL160 + .2byte 0x1 + .byte 0x67 + .8byte 0 + .8byte 0 +.LLST38: + .8byte .LVL143 + .8byte .LVL148 + .2byte 0x1 + .byte 0x69 + .8byte .LVL149 + .8byte .LVL160 + .2byte 0x1 + .byte 0x69 + .8byte 0 + .8byte 0 +.LLST39: + .8byte .LVL143 + .8byte .LVL145 + .2byte 0x1 .byte 0x50 - .byte 0x32 - .byte 0x24 - .byte 0x74 - .sleb128 32 - .byte 0x94 - .byte 0x1 - .byte 0x8 - .byte 0xff - .byte 0x1a - .byte 0x22 + .8byte .LVL145 + .8byte .LVL148 + .2byte 0x1 + .byte 0x6a + .8byte .LVL149 + .8byte .LVL150-1 + .2byte 0x1 + .byte 0x50 + .8byte .LVL150-1 + .8byte .LVL160 + .2byte 0x1 + .byte 0x6a + .8byte 0 + .8byte 0 +.LLST40: + .8byte .LVL152 + .8byte .LVL156 + .2byte 0x13 + .byte 0x75 + .sleb128 0 + .byte 0x34 + .byte 0x26 .byte 0x8 .byte 0x20 .byte 0x24 .byte 0x8 .byte 0x20 .byte 0x26 - .byte 0x74 + .byte 0x71 .sleb128 0 .byte 0x22 - .byte 0x23 - .uleb128 0x1 - .byte 0x94 - .byte 0x1 - .byte 0x8 - .byte 0xff - .byte 0x1a - .byte 0x38 - .byte 0x24 - .byte 0xf3 - .uleb128 0x1 - .byte 0x50 .byte 0x32 .byte 0x24 - .byte 0x74 - .sleb128 32 - .byte 0x94 - .byte 0x1 - .byte 0x8 - .byte 0xff - .byte 0x1a + .byte 0x8a + .sleb128 0 .byte 0x22 + .byte 0x9f + .8byte .LVL156 + .8byte .LVL157 + .2byte 0x13 + .byte 0x75 + .sleb128 -16 + .byte 0x34 + .byte 0x26 .byte 0x8 .byte 0x20 .byte 0x24 .byte 0x8 .byte 0x20 .byte 0x26 - .byte 0x74 + .byte 0x71 .sleb128 0 .byte 0x22 - .byte 0x23 - .uleb128 0x2 - .byte 0x94 - .byte 0x1 - .byte 0x8 - .byte 0xff - .byte 0x1a - .byte 0x40 - .byte 0x24 - .byte 0x21 - .byte 0x77 - .sleb128 0 - .byte 0x21 - .byte 0xf3 - .uleb128 0x1 - .byte 0x51 .byte 0x32 .byte 0x24 - .byte 0x22 - .byte 0x8 - .byte 0x20 - .byte 0x24 - .byte 0x8 - .byte 0x20 - .byte 0x26 - .byte 0x74 + .byte 0x8a .sleb128 0 .byte 0x22 - .byte 0x23 - .uleb128 0x3 - .byte 0x94 - .byte 0x1 - .byte 0x8 - .byte 0xff - .byte 0x1a .byte 0x9f - .8byte .LVL139 - .8byte .LFE217 - .2byte 0x59 - .byte 0xf3 - .uleb128 0x1 - .byte 0x50 - .byte 0x32 - .byte 0x24 - .byte 0x74 - .sleb128 32 - .byte 0x94 - .byte 0x1 - .byte 0x8 - .byte 0xff - .byte 0x1a - .byte 0x22 + .8byte .LVL158 + .8byte .LVL160 + .2byte 0x13 + .byte 0x75 + .sleb128 -16 + .byte 0x34 + .byte 0x26 .byte 0x8 .byte 0x20 .byte 0x24 .byte 0x8 .byte 0x20 .byte 0x26 - .byte 0x74 + .byte 0x71 .sleb128 0 .byte 0x22 - .byte 0x23 - .uleb128 0x1 - .byte 0x94 - .byte 0x1 - .byte 0x8 - .byte 0xff - .byte 0x1a - .byte 0x38 - .byte 0x24 - .byte 0xf3 - .uleb128 0x1 - .byte 0x50 .byte 0x32 .byte 0x24 - .byte 0x74 - .sleb128 32 - .byte 0x94 - .byte 0x1 - .byte 0x8 - .byte 0xff - .byte 0x1a + .byte 0x8a + .sleb128 0 .byte 0x22 + .byte 0x9f + .8byte 0 + .8byte 0 +.LLST41: + .8byte .LVL152 + .8byte .LVL153 + .2byte 0x1c + .byte 0x7c + .sleb128 0 .byte 0x8 .byte 0x20 .byte 0x24 .byte 0x8 .byte 0x20 .byte 0x26 - .byte 0x74 - .sleb128 0 - .byte 0x22 - .byte 0x23 - .uleb128 0x2 - .byte 0x94 - .byte 0x1 - .byte 0x8 - .byte 0xff - .byte 0x1a - .byte 0x40 - .byte 0x24 - .byte 0x21 .byte 0x77 .sleb128 0 - .byte 0x21 - .byte 0xf3 - .uleb128 0x1 - .byte 0x51 - .byte 0x32 - .byte 0x24 - .byte 0x22 .byte 0x8 .byte 0x20 .byte 0x24 .byte 0x8 .byte 0x20 .byte 0x26 - .byte 0x74 + .byte 0x22 + .byte 0x89 + .sleb128 0 + .byte 0x22 + .byte 0x78 .sleb128 0 .byte 0x22 - .byte 0x23 - .uleb128 0x3 .byte 0x94 .byte 0x1 - .byte 0x8 - .byte 0xff + .byte 0x33 .byte 0x1a .byte 0x9f .8byte 0 .8byte 0 -.LLST32: - .8byte .LVL118 - .8byte .LVL119 - .2byte 0xd - .byte 0x70 - .sleb128 0 - .byte 0x32 - .byte 0x24 - .byte 0x74 - .sleb128 32 - .byte 0x94 - .byte 0x1 - .byte 0x8 - .byte 0xff - .byte 0x1a - .byte 0x22 +.LLST42: + .8byte .LVL144 + .8byte .LVL148 + .2byte 0x1 + .byte 0x68 + .8byte .LVL149 + .8byte .LVL160 + .2byte 0x1 + .byte 0x68 + .8byte 0 + .8byte 0 +.LLST43: + .8byte .LVL150 + .8byte .LVL151 + .2byte 0x2 + .byte 0x30 + .byte 0x9f + .8byte .LVL151 + .8byte .LVL160 + .2byte 0x1 + .byte 0x52 + .8byte 0 + .8byte 0 +.LLST44: + .8byte .LVL157 + .8byte .LVL158 + .2byte 0x2 + .byte 0x30 + .byte 0x9f + .8byte 0 + .8byte 0 +.LLST3: + .8byte .LVL9 + .8byte .LVL10 + .2byte 0x1 + .byte 0x50 + .8byte .LVL10 + .8byte .LFE219 + .2byte 0x4 + .byte 0xf3 + .uleb128 0x1 + .byte 0x50 + .byte 0x9f + .8byte 0 + .8byte 0 +.LLST4: + .8byte .LVL9 + .8byte .LVL15 + .2byte 0x1 + .byte 0x51 + .8byte .LVL15 + .8byte .LVL17 + .2byte 0x4 + .byte 0xf3 + .uleb128 0x1 + .byte 0x51 + .byte 0x9f + .8byte .LVL17 + .8byte .LVL19 + .2byte 0x1 + .byte 0x51 + .8byte .LVL19 + .8byte .LFE219 + .2byte 0x4 + .byte 0xf3 + .uleb128 0x1 + .byte 0x51 + .byte 0x9f + .8byte 0 + .8byte 0 +.LLST5: + .8byte .LVL11 + .8byte .LVL15 + .2byte 0x1 + .byte 0x52 + .8byte .LVL15 + .8byte .LVL16-1 + .2byte 0x9 + .byte 0x3 + .8byte global_waveform + .8byte .LVL17 + .8byte .LVL23 + .2byte 0x1 + .byte 0x52 + .8byte .LVL23 + .8byte .LVL24 + .2byte 0x9 + .byte 0x3 + .8byte global_waveform + .8byte .LVL24 + .8byte .LVL26-1 + .2byte 0x1 + .byte 0x52 + .8byte .LVL27 + .8byte .LVL29 + .2byte 0x1 + .byte 0x52 + .8byte .LVL29 + .8byte .LVL44 + .2byte 0x9 + .byte 0x3 + .8byte global_waveform + .8byte .LVL44 + .8byte .LVL45 + .2byte 0x1 + .byte 0x52 + .8byte .LVL45 + .8byte .LVL69-1 + .2byte 0x9 + .byte 0x3 + .8byte global_waveform + .8byte 0 + .8byte 0 +.LLST6: + .8byte .LVL11 + .8byte .LVL13 + .2byte 0x2 + .byte 0x30 .byte 0x9f - .8byte .LVL119 - .8byte .LVL121 + .8byte .LVL13 + .8byte .LVL14 .2byte 0x1 - .byte 0x50 - .8byte .LVL121 - .8byte .LVL124 - .2byte 0xe - .byte 0xf3 - .uleb128 0x1 - .byte 0x50 - .byte 0x32 - .byte 0x24 - .byte 0x74 - .sleb128 32 - .byte 0x94 - .byte 0x1 - .byte 0x8 - .byte 0xff - .byte 0x1a - .byte 0x22 - .byte 0x9f - .8byte .LVL126 - .8byte .LVL127 - .2byte 0xe - .byte 0xf3 - .uleb128 0x1 - .byte 0x50 - .byte 0x32 - .byte 0x24 - .byte 0x74 - .sleb128 32 - .byte 0x94 - .byte 0x1 - .byte 0x8 - .byte 0xff - .byte 0x1a + .byte 0x54 + .8byte .LVL14 + .8byte .LVL15 + .2byte 0x6 + .byte 0x72 + .sleb128 0 + .byte 0x70 + .sleb128 0 .byte 0x22 .byte 0x9f - .8byte .LVL127 - .8byte .LVL128 - .2byte 0x8 - .byte 0x71 + .8byte .LVL17 + .8byte .LVL18 + .2byte 0x6 + .byte 0x72 .sleb128 0 - .byte 0x32 - .byte 0x24 - .byte 0x73 + .byte 0x70 .sleb128 0 .byte 0x22 .byte 0x9f - .8byte .LVL128 - .8byte .LVL130 - .2byte 0x1 - .byte 0x53 - .8byte .LVL130 - .8byte .LVL131 - .2byte 0x2d - .byte 0x75 - .sleb128 0 - .byte 0x38 - .byte 0x24 + .8byte .LVL18 + .8byte .LVL21 + .2byte 0x17 .byte 0xf3 .uleb128 0x1 .byte 0x50 .byte 0x32 .byte 0x24 - .byte 0x74 - .sleb128 32 - .byte 0x94 - .byte 0x1 - .byte 0x8 - .byte 0xff - .byte 0x1a - .byte 0x22 .byte 0x8 .byte 0x20 .byte 0x24 .byte 0x8 .byte 0x20 .byte 0x26 - .byte 0x74 - .sleb128 0 - .byte 0x22 - .byte 0x23 - .uleb128 0x2 + .byte 0x72 + .sleb128 32 .byte 0x94 .byte 0x1 .byte 0x8 .byte 0xff .byte 0x1a - .byte 0x40 - .byte 0x24 - .byte 0x21 - .byte 0x77 + .byte 0x22 + .byte 0x72 + .sleb128 0 + .byte 0x22 + .byte 0x9f + .8byte .LVL21 + .8byte .LVL22 + .2byte 0x1 + .byte 0x53 + .8byte .LVL22 + .8byte .LVL23 + .2byte 0x6 + .byte 0x72 .sleb128 0 - .byte 0x21 .byte 0x71 .sleb128 0 - .byte 0x32 - .byte 0x24 .byte 0x22 .byte 0x9f - .8byte .LVL131 - .8byte .LVL132 - .2byte 0x2e - .byte 0x75 + .8byte .LVL23 + .8byte .LVL24 + .2byte 0xe + .byte 0x3 + .8byte global_waveform + .byte 0x6 + .byte 0x71 .sleb128 0 - .byte 0x38 - .byte 0x24 - .byte 0xf3 - .uleb128 0x1 - .byte 0x50 - .byte 0x32 - .byte 0x24 - .byte 0x74 - .sleb128 32 - .byte 0x94 - .byte 0x1 - .byte 0x8 - .byte 0xff - .byte 0x1a .byte 0x22 - .byte 0x8 - .byte 0x20 - .byte 0x24 - .byte 0x8 - .byte 0x20 - .byte 0x26 - .byte 0x74 + .byte 0x9f + .8byte .LVL24 + .8byte .LVL25 + .2byte 0x6 + .byte 0x72 .sleb128 0 - .byte 0x22 - .byte 0x23 - .uleb128 0x2 - .byte 0x94 - .byte 0x1 - .byte 0x8 - .byte 0xff - .byte 0x1a - .byte 0x40 - .byte 0x24 - .byte 0x21 - .byte 0x77 + .byte 0x71 .sleb128 0 - .byte 0x21 - .byte 0xf3 - .uleb128 0x1 - .byte 0x51 - .byte 0x32 - .byte 0x24 .byte 0x22 .byte 0x9f - .8byte .LVL132 - .8byte .LVL136 - .2byte 0x49 - .byte 0xf3 - .uleb128 0x1 - .byte 0x50 - .byte 0x32 - .byte 0x24 - .byte 0x74 + .8byte .LVL25 + .8byte .LVL26-1 + .2byte 0x1 + .byte 0x58 + .8byte .LVL27 + .8byte .LVL69-1 + .2byte 0x1 + .byte 0x58 + .8byte 0 + .8byte 0 +.LLST7: + .8byte .LVL11 + .8byte .LVL12 + .2byte 0x8 + .byte 0x72 .sleb128 32 .byte 0x94 .byte 0x1 .byte 0x8 .byte 0xff .byte 0x1a - .byte 0x22 - .byte 0x8 - .byte 0x20 - .byte 0x24 - .byte 0x8 - .byte 0x20 - .byte 0x26 - .byte 0x74 + .byte 0x9f + .8byte .LVL17 + .8byte .LVL18 + .2byte 0xe + .byte 0x72 .sleb128 0 - .byte 0x22 - .byte 0x23 - .uleb128 0x1 - .byte 0x94 - .byte 0x1 - .byte 0x8 - .byte 0xff - .byte 0x1a - .byte 0x38 - .byte 0x24 - .byte 0xf3 - .uleb128 0x1 - .byte 0x50 - .byte 0x32 - .byte 0x24 - .byte 0x74 - .sleb128 32 - .byte 0x94 - .byte 0x1 - .byte 0x8 - .byte 0xff - .byte 0x1a - .byte 0x22 - .byte 0x8 - .byte 0x20 - .byte 0x24 - .byte 0x8 - .byte 0x20 - .byte 0x26 - .byte 0x74 + .byte 0x70 .sleb128 0 .byte 0x22 - .byte 0x23 - .uleb128 0x2 .byte 0x94 - .byte 0x1 - .byte 0x8 - .byte 0xff + .byte 0x4 + .byte 0xc + .4byte 0xffffff .byte 0x1a - .byte 0x40 - .byte 0x24 - .byte 0x21 - .byte 0x77 + .byte 0x9f + .8byte .LVL18 + .8byte .LVL20 + .2byte 0x9 + .byte 0x70 .sleb128 0 - .byte 0x21 - .byte 0xf3 - .uleb128 0x1 - .byte 0x51 - .byte 0x32 - .byte 0x24 - .byte 0x22 + .byte 0xc + .4byte 0xffffff + .byte 0x1a .byte 0x9f - .8byte .LVL136 - .8byte .LVL138 - .2byte 0x1 - .byte 0x50 - .8byte .LVL138 - .8byte .LVL139-1 - .2byte 0x63 + .8byte .LVL20 + .8byte .LVL23 + .2byte 0x1f .byte 0xf3 .uleb128 0x1 .byte 0x50 .byte 0x32 .byte 0x24 - .byte 0x74 + .byte 0x8 + .byte 0x20 + .byte 0x24 + .byte 0x8 + .byte 0x20 + .byte 0x26 + .byte 0x72 .sleb128 32 .byte 0x94 .byte 0x1 @@ -11201,263 +6026,515 @@ __func__.6107: .byte 0xff .byte 0x1a .byte 0x22 - .byte 0x8 - .byte 0x20 - .byte 0x24 - .byte 0x8 - .byte 0x20 - .byte 0x26 - .byte 0x74 + .byte 0x72 .sleb128 0 .byte 0x22 - .byte 0x23 - .uleb128 0x1 .byte 0x94 - .byte 0x1 - .byte 0x8 - .byte 0xff + .byte 0x4 + .byte 0xc + .4byte 0xffffff .byte 0x1a - .byte 0x38 - .byte 0x24 + .byte 0x9f + .8byte .LVL23 + .8byte .LVL24 + .2byte 0x31 .byte 0xf3 .uleb128 0x1 .byte 0x50 .byte 0x32 .byte 0x24 - .byte 0x74 - .sleb128 32 - .byte 0x94 - .byte 0x1 - .byte 0x8 - .byte 0xff - .byte 0x1a - .byte 0x22 .byte 0x8 .byte 0x20 .byte 0x24 .byte 0x8 .byte 0x20 .byte 0x26 - .byte 0x74 - .sleb128 0 - .byte 0x22 + .byte 0x3 + .8byte global_waveform + .byte 0x6 .byte 0x23 - .uleb128 0x2 + .uleb128 0x20 .byte 0x94 .byte 0x1 .byte 0x8 .byte 0xff .byte 0x1a - .byte 0x40 - .byte 0x24 - .byte 0x21 - .byte 0x77 + .byte 0x22 + .byte 0x3 + .8byte global_waveform + .byte 0x6 + .byte 0x22 + .byte 0x94 + .byte 0x4 + .byte 0xc + .4byte 0xffffff + .byte 0x1a + .byte 0x9f + .8byte .LVL24 + .8byte .LVL26-1 + .2byte 0xe + .byte 0x72 .sleb128 0 - .byte 0x21 + .byte 0x71 + .sleb128 0 + .byte 0x22 + .byte 0x94 + .byte 0x4 + .byte 0xc + .4byte 0xffffff + .byte 0x1a + .byte 0x9f + .8byte .LVL27 + .8byte .LVL29 + .2byte 0xe + .byte 0x72 + .sleb128 0 + .byte 0x71 + .sleb128 0 + .byte 0x22 + .byte 0x94 + .byte 0x4 + .byte 0xc + .4byte 0xffffff + .byte 0x1a + .byte 0x9f + .8byte .LVL29 + .8byte .LVL30 + .2byte 0x16 + .byte 0x3 + .8byte global_waveform + .byte 0x6 + .byte 0x71 + .sleb128 0 + .byte 0x22 + .byte 0x94 + .byte 0x4 + .byte 0xc + .4byte 0xffffff + .byte 0x1a + .byte 0x9f + .8byte .LVL30 + .8byte .LVL31 + .2byte 0x56 .byte 0xf3 .uleb128 0x1 .byte 0x51 .byte 0x32 .byte 0x24 - .byte 0x22 .byte 0x8 .byte 0x20 .byte 0x24 .byte 0x8 .byte 0x20 .byte 0x26 - .byte 0x74 - .sleb128 0 - .byte 0x22 - .byte 0x23 + .byte 0xf3 .uleb128 0x1 + .byte 0x50 + .byte 0x32 + .byte 0x24 + .byte 0x8 + .byte 0x20 + .byte 0x24 + .byte 0x8 + .byte 0x20 + .byte 0x26 + .byte 0x3 + .8byte global_waveform + .byte 0x6 + .byte 0x23 + .uleb128 0x20 .byte 0x94 .byte 0x1 .byte 0x8 .byte 0xff .byte 0x1a - .byte 0x38 - .byte 0x24 - .byte 0x75 + .byte 0x22 + .byte 0x3 + .8byte global_waveform + .byte 0x6 + .byte 0x22 + .byte 0x94 + .byte 0x4 + .byte 0xc + .4byte 0xffffff + .byte 0x1a + .byte 0xc + .4byte 0xffffffff + .byte 0x1a + .byte 0x22 + .byte 0x3 + .8byte global_waveform + .byte 0x6 + .byte 0x22 + .byte 0x94 + .byte 0x4 + .byte 0xc + .4byte 0xffffff + .byte 0x1a + .byte 0x9f + .8byte .LVL44 + .8byte .LVL45 + .2byte 0xe + .byte 0x72 .sleb128 0 - .byte 0x40 - .byte 0x24 - .byte 0x21 - .byte 0x76 + .byte 0x71 .sleb128 0 - .byte 0x21 + .byte 0x22 + .byte 0x94 + .byte 0x4 + .byte 0xc + .4byte 0xffffff + .byte 0x1a .byte 0x9f - .8byte .LVL139 - .8byte .LFE217 + .8byte 0 + .8byte 0 +.LLST8: + .8byte .LVL25 + .8byte .LVL26-1 .2byte 0x1 - .byte 0x50 + .byte 0x58 + .8byte .LVL27 + .8byte .LVL69-1 + .2byte 0x1 + .byte 0x58 .8byte 0 .8byte 0 -.LLST0: - .8byte .LVL0 - .8byte .LVL1 +.LLST9: + .8byte .LVL25 + .8byte .LVL31 + .2byte 0x2 + .byte 0x30 + .byte 0x9f + .8byte .LVL35 + .8byte .LVL36 .2byte 0x1 - .byte 0x50 - .8byte .LVL1 - .8byte .LVL7 + .byte 0x51 + .8byte .LVL36 + .8byte .LVL41 + .2byte 0x2 + .byte 0x30 + .byte 0x9f + .8byte .LVL44 + .8byte .LVL45 + .2byte 0x2 + .byte 0x30 + .byte 0x9f + .8byte .LVL46 + .8byte .LVL47 .2byte 0x1 - .byte 0x64 - .8byte .LVL7 - .8byte .LVL8 + .byte 0x54 + .8byte .LVL47 + .8byte .LVL48 .2byte 0x3 - .byte 0x84 - .sleb128 1 + .byte 0x71 + .sleb128 3 .byte 0x9f - .8byte .LVL8 - .8byte .LVL15 - .2byte 0x1 - .byte 0x64 - .8byte .LVL15 - .8byte .LVL16 + .8byte .LVL48 + .8byte .LVL49 .2byte 0x3 - .byte 0x84 - .sleb128 1 + .byte 0x71 + .sleb128 -1 .byte 0x9f - .8byte .LVL16 - .8byte .LVL18 - .2byte 0x4 - .byte 0xf3 - .uleb128 0x1 + .8byte .LVL50 + .8byte .LVL55 + .2byte 0x2 + .byte 0x30 + .byte 0x9f + .8byte .LVL60 + .8byte .LVL62 + .2byte 0x1 + .byte 0x51 + .8byte .LVL62 + .8byte .LVL67 + .2byte 0x2 + .byte 0x30 + .byte 0x9f + .8byte .LVL71 + .8byte .LFE219 + .2byte 0x1 + .byte 0x52 + .8byte 0 + .8byte 0 +.LLST10: + .8byte .LVL25 + .8byte .LVL31 + .2byte 0x2 + .byte 0x30 + .byte 0x9f + .8byte .LVL31 + .8byte .LVL38 + .2byte 0x1 + .byte 0x50 + .8byte .LVL38 + .8byte .LVL40 + .2byte 0x2 + .byte 0x30 + .byte 0x9f + .8byte .LVL41 + .8byte .LVL44 + .2byte 0x1 + .byte 0x50 + .8byte .LVL44 + .8byte .LVL45 + .2byte 0x2 + .byte 0x30 + .byte 0x9f + .8byte .LVL45 + .8byte .LVL52 + .2byte 0x1 .byte 0x50 + .8byte .LVL52 + .8byte .LVL54 + .2byte 0x2 + .byte 0x30 .byte 0x9f - .8byte .LVL18 - .8byte .LVL23 - .2byte 0x3 - .byte 0x84 - .sleb128 1 + .8byte .LVL55 + .8byte .LVL64 + .2byte 0x1 + .byte 0x50 + .8byte .LVL64 + .8byte .LVL66 + .2byte 0x2 + .byte 0x30 .byte 0x9f - .8byte .LVL23 - .8byte .LVL25 - .2byte 0x4 - .byte 0xf3 - .uleb128 0x1 + .8byte .LVL67 + .8byte .LVL68 + .2byte 0x1 .byte 0x50 + .8byte .LVL71 + .8byte .LVL72 + .2byte 0x2 + .byte 0x30 .byte 0x9f + .8byte .LVL72 + .8byte .LFE219 + .2byte 0x1 + .byte 0x51 + .8byte 0 + .8byte 0 +.LLST11: .8byte .LVL25 - .8byte .LVL26 - .2byte 0x3 - .byte 0x84 - .sleb128 1 + .8byte .LVL31 + .2byte 0x2 + .byte 0x30 .byte 0x9f - .8byte .LVL26 - .8byte .LFE215 - .2byte 0x4 - .byte 0xf3 - .uleb128 0x1 - .byte 0x50 + .8byte .LVL31 + .8byte .LVL44 + .2byte 0x1 + .byte 0x63 + .8byte .LVL44 + .8byte .LVL45 + .2byte 0x2 + .byte 0x30 .byte 0x9f + .8byte .LVL45 + .8byte .LFE219 + .2byte 0x1 + .byte 0x63 .8byte 0 .8byte 0 -.LLST1: - .8byte .LVL2 - .8byte .LVL3 +.LLST12: + .8byte .LVL25 + .8byte .LVL31 + .2byte 0x2 + .byte 0x30 + .byte 0x9f + .8byte .LVL31 + .8byte .LVL35 .2byte 0x1 - .byte 0x52 - .8byte .LVL3 - .8byte .LVL4-1 - .2byte 0x9 - .byte 0x3 - .8byte global_waveform - .8byte .LVL5 - .8byte .LVL6 + .byte 0x5b + .8byte .LVL35 + .8byte .LVL43 .2byte 0x1 - .byte 0x52 - .8byte .LVL8 - .8byte .LVL9 + .byte 0x5f + .8byte .LVL43 + .8byte .LVL44 .2byte 0x1 - .byte 0x52 - .8byte .LVL9 - .8byte .LVL10 - .2byte 0x9 - .byte 0x3 - .8byte global_waveform - .8byte .LVL10 - .8byte .LVL11 + .byte 0x5b + .8byte .LVL44 + .8byte .LVL45 + .2byte 0x2 + .byte 0x30 + .byte 0x9f + .8byte .LVL45 + .8byte .LVL58 .2byte 0x1 - .byte 0x52 - .8byte .LVL11 - .8byte .LVL12 - .2byte 0x9 - .byte 0x3 - .8byte global_waveform - .8byte .LVL12 - .8byte .LVL13 + .byte 0x5f + .8byte .LVL58 + .8byte .LVL59 .2byte 0x1 - .byte 0x52 - .8byte .LVL13 - .8byte .LVL14 - .2byte 0x9 - .byte 0x3 - .8byte global_waveform - .8byte .LVL14 - .8byte .LVL15 + .byte 0x5b + .8byte .LVL59 + .8byte .LVL61 + .2byte 0x3 + .byte 0x7f + .sleb128 -1 + .byte 0x9f + .8byte .LVL61 + .8byte .LVL62 .2byte 0x1 - .byte 0x52 + .byte 0x5f + .8byte .LVL62 + .8byte .LVL69-1 + .2byte 0x1 + .byte 0x5b .8byte 0 .8byte 0 -.LLST2: - .8byte .LVL16 - .8byte .LVL17 +.LLST13: + .8byte .LVL34 + .8byte .LVL44 + .2byte 0x1 + .byte 0x67 + .8byte .LVL45 + .8byte .LVL58 + .2byte 0x1 + .byte 0x67 + .8byte .LVL59 + .8byte .LVL61 + .2byte 0x1 + .byte 0x5b + .8byte .LVL73 + .8byte .LFE219 + .2byte 0x1 + .byte 0x58 + .8byte 0 + .8byte 0 +.LLST14: + .8byte .LVL42 + .8byte .LVL44 + .2byte 0x1 + .byte 0x56 + .8byte .LVL45 + .8byte .LVL56 + .2byte 0x1 + .byte 0x56 + .8byte .LVL57 + .8byte .LVL58 + .2byte 0x1 + .byte 0x56 + .8byte .LVL70 + .8byte .LVL76 .2byte 0x1 .byte 0x50 - .8byte .LVL18 - .8byte .LVL19 + .8byte .LVL77 + .8byte .LFE219 + .2byte 0x1 + .byte 0x50 + .8byte 0 + .8byte 0 +.LLST15: + .8byte .LVL25 + .8byte .LVL31 .2byte 0x2 - .byte 0x34 + .byte 0x31 .byte 0x9f - .8byte .LVL19 - .8byte .LVL20 + .8byte .LVL31 + .8byte .LVL44 + .2byte 0x1 + .byte 0x5e + .8byte .LVL44 + .8byte .LVL45 .2byte 0x2 - .byte 0x35 + .byte 0x31 .byte 0x9f - .8byte .LVL20 - .8byte .LVL21 + .8byte .LVL45 + .8byte .LVL69-1 + .2byte 0x1 + .byte 0x5e + .8byte 0 + .8byte 0 +.LLST16: + .8byte .LVL25 + .8byte .LVL28 .2byte 0x2 - .byte 0x36 + .byte 0x30 .byte 0x9f - .8byte .LVL21 - .8byte .LVL22 + .8byte .LVL31 + .8byte .LVL44 + .2byte 0x1 + .byte 0x5d + .8byte .LVL44 + .8byte .LVL45 .2byte 0x2 - .byte 0x32 + .byte 0x30 .byte 0x9f - .8byte .LVL22 - .8byte .LVL23 - .2byte 0x2 - .byte 0x31 + .8byte .LVL45 + .8byte .LVL69-1 + .2byte 0x1 + .byte 0x5d + .8byte 0 + .8byte 0 +.LLST0: + .8byte .LVL0 + .8byte .LVL1 + .2byte 0x1 + .byte 0x50 + .8byte .LVL1 + .8byte .LFE218 + .2byte 0x1 + .byte 0x54 + .8byte 0 + .8byte 0 +.LLST1: + .8byte .LVL2 + .8byte .LVL4 + .2byte 0x3 + .byte 0x9 + .byte 0xff + .byte 0x9f + .8byte .LVL4 + .8byte .LVL5 + .2byte 0x1 + .byte 0x50 + .8byte .LVL5 + .8byte .LFE218 + .2byte 0x3 + .byte 0x9 + .byte 0xff .byte 0x9f .8byte 0 .8byte 0 -.LLST14: - .8byte .LVL54 - .8byte .LVL57 +.LLST2: + .8byte .LVL3 + .8byte .LVL4 + .2byte 0x1 + .byte 0x50 + .8byte .LVL4 + .8byte .LVL5 + .2byte 0x1 + .byte 0x51 + .8byte .LVL5 + .8byte .LVL6 + .2byte 0x1 + .byte 0x50 + .8byte .LVL7 + .8byte .LVL8 + .2byte 0x1 + .byte 0x50 + .8byte .LVL8 + .8byte .LFE218 + .2byte 0x1 + .byte 0x51 + .8byte 0 + .8byte 0 +.LLST22: + .8byte .LVL113 + .8byte .LVL118 .2byte 0x1 .byte 0x50 - .8byte .LVL57 - .8byte .LVL81 - .2byte 0x1 - .byte 0x67 - .8byte .LVL81 - .8byte .LVL82 + .8byte .LVL118 + .8byte .LVL119 .2byte 0x4 .byte 0xf3 .uleb128 0x1 .byte 0x50 .byte 0x9f - .8byte .LVL82 - .8byte .LVL115 - .2byte 0x1 - .byte 0x67 - .8byte .LVL115 - .8byte .LVL116 + .8byte .LVL119 + .8byte .LVL120 .2byte 0x1 .byte 0x50 - .8byte .LVL116 - .8byte .LFE212 + .8byte .LVL120 + .8byte .LFE215 .2byte 0x4 .byte 0xf3 .uleb128 0x1 @@ -11465,689 +6542,510 @@ __func__.6107: .byte 0x9f .8byte 0 .8byte 0 -.LLST15: - .8byte .LVL54 - .8byte .LVL56 +.LLST23: + .8byte .LVL113 + .8byte .LVL114 .2byte 0x1 .byte 0x51 - .8byte .LVL56 - .8byte .LVL80 - .2byte 0x1 - .byte 0x65 - .8byte .LVL80 - .8byte .LVL82 + .8byte .LVL114 + .8byte .LVL119 .2byte 0x4 .byte 0xf3 .uleb128 0x1 .byte 0x51 .byte 0x9f - .8byte .LVL82 - .8byte .LVL115 - .2byte 0x1 - .byte 0x65 - .8byte .LVL115 - .8byte .LFE212 + .8byte .LVL119 + .8byte .LFE215 .2byte 0x1 .byte 0x51 .8byte 0 .8byte 0 -.LLST16: - .8byte .LVL54 - .8byte .LVL55 +.LLST24: + .8byte .LVL115 + .8byte .LVL116 .2byte 0x1 .byte 0x52 - .8byte .LVL55 + .8byte .LVL116 + .8byte .LVL117 + .2byte 0x3 + .byte 0x72 + .sleb128 1 + .byte 0x9f + .8byte 0 + .8byte 0 +.LLST17: + .8byte .LVL78 .8byte .LVL79 .2byte 0x1 - .byte 0x64 + .byte 0x50 .8byte .LVL79 - .8byte .LVL82 + .8byte .LVL81 .2byte 0x4 .byte 0xf3 .uleb128 0x1 - .byte 0x52 - .byte 0x9f - .8byte .LVL82 - .8byte .LVL115 - .2byte 0x1 - .byte 0x64 - .8byte .LVL115 - .8byte .LFE212 - .2byte 0x1 - .byte 0x52 - .8byte 0 - .8byte 0 -.LLST17: - .8byte .LVL54 - .8byte .LVL59 - .2byte 0x2 - .byte 0x30 - .byte 0x9f - .8byte .LVL59 - .8byte .LVL68 - .2byte 0x1 - .byte 0x56 - .8byte .LVL68 - .8byte .LVL70 - .2byte 0x2 - .byte 0x30 + .byte 0x50 .byte 0x9f - .8byte .LVL70 - .8byte .LVL76-1 - .2byte 0x1 - .byte 0x56 + .8byte .LVL81 .8byte .LVL82 - .8byte .LVL90 - .2byte 0x1 - .byte 0x56 - .8byte .LVL90 - .8byte .LVL92 - .2byte 0x2 - .byte 0x30 - .byte 0x9f - .8byte .LVL92 - .8byte .LVL104 - .2byte 0x1 - .byte 0x56 - .8byte .LVL104 - .8byte .LVL106 - .2byte 0x2 - .byte 0x30 - .byte 0x9f - .8byte .LVL107 - .8byte .LVL108 - .2byte 0x2 - .byte 0x30 - .byte 0x9f - .8byte .LVL108 - .8byte .LVL110 - .2byte 0x5 - .byte 0x73 - .sleb128 0 - .byte 0x31 - .byte 0x24 - .byte 0x9f - .8byte .LVL115 - .8byte .LFE212 - .2byte 0x2 - .byte 0x30 - .byte 0x9f - .8byte 0 - .8byte 0 -.LLST18: - .8byte .LVL54 - .8byte .LVL59 - .2byte 0x2 - .byte 0x30 - .byte 0x9f - .8byte .LVL63 - .8byte .LVL64 - .2byte 0x1 - .byte 0x5c - .8byte .LVL64 - .8byte .LVL66 .2byte 0x1 - .byte 0x53 - .8byte .LVL66 - .8byte .LVL70 - .2byte 0x2 - .byte 0x30 - .byte 0x9f - .8byte .LVL73 - .8byte .LVL74 - .2byte 0x2 - .byte 0x30 - .byte 0x9f + .byte 0x50 .8byte .LVL82 - .8byte .LVL83 - .2byte 0x2 - .byte 0x30 - .byte 0x9f - .8byte .LVL84 .8byte .LVL85 - .2byte 0x1 - .byte 0x57 + .2byte 0x4 + .byte 0xf3 + .uleb128 0x1 + .byte 0x50 + .byte 0x9f .8byte .LVL85 .8byte .LVL86 - .2byte 0x3 - .byte 0x73 - .sleb128 3 - .byte 0x9f + .2byte 0x1 + .byte 0x50 .8byte .LVL86 .8byte .LVL87 - .2byte 0x3 - .byte 0x73 - .sleb128 -1 + .2byte 0x4 + .byte 0xf3 + .uleb128 0x1 + .byte 0x50 .byte 0x9f + .8byte .LVL87 .8byte .LVL88 - .8byte .LVL92 - .2byte 0x2 - .byte 0x30 - .byte 0x9f - .8byte .LVL95 - .8byte .LVL96 - .2byte 0x2 - .byte 0x30 - .byte 0x9f - .8byte .LVL98 - .8byte .LVL99 - .2byte 0x1 - .byte 0x5c - .8byte .LVL99 - .8byte .LVL102 .2byte 0x1 - .byte 0x53 - .8byte .LVL102 - .8byte .LVL106 - .2byte 0x2 - .byte 0x30 - .byte 0x9f - .8byte .LVL107 - .8byte .LVL111 - .2byte 0x5 - .byte 0x72 - .sleb128 0 - .byte 0x31 - .byte 0x24 - .byte 0x9f - .8byte .LVL111 - .8byte .LVL112 - .2byte 0x5 - .byte 0x72 - .sleb128 1 - .byte 0x31 - .byte 0x24 - .byte 0x9f - .8byte .LVL115 - .8byte .LFE212 - .2byte 0x2 - .byte 0x30 - .byte 0x9f - .8byte 0 - .8byte 0 -.LLST19: - .8byte .LVL54 - .8byte .LVL59 - .2byte 0x2 - .byte 0x30 + .byte 0x50 + .8byte .LVL88 + .8byte .LVL89 + .2byte 0x4 + .byte 0xf3 + .uleb128 0x1 + .byte 0x50 .byte 0x9f - .8byte .LVL59 - .8byte .LVL79 + .8byte .LVL89 + .8byte .LVL90 .2byte 0x1 - .byte 0x63 - .8byte .LVL79 - .8byte .LVL82 + .byte 0x50 + .8byte .LVL90 + .8byte .LVL91 + .2byte 0x4 + .byte 0xf3 + .uleb128 0x1 + .byte 0x50 + .byte 0x9f + .8byte .LVL91 + .8byte .LVL92 .2byte 0x1 .byte 0x50 - .8byte .LVL82 - .8byte .LVL115 - .2byte 0x1 - .byte 0x63 - .8byte .LVL115 - .8byte .LFE212 - .2byte 0x2 - .byte 0x30 + .8byte .LVL92 + .8byte .LFE217 + .2byte 0x4 + .byte 0xf3 + .uleb128 0x1 + .byte 0x50 .byte 0x9f .8byte 0 .8byte 0 -.LLST20: - .8byte .LVL54 - .8byte .LVL59 - .2byte 0x2 - .byte 0x30 - .byte 0x9f - .8byte .LVL59 - .8byte .LVL65 +.LLST18: + .8byte .LVL81 + .8byte .LVL82 .2byte 0x1 .byte 0x50 - .8byte .LVL65 - .8byte .LVL71 - .2byte 0x1 - .byte 0x5b - .8byte .LVL71 - .8byte .LVL72 - .2byte 0x3 - .byte 0x70 - .sleb128 1 + .8byte .LVL82 + .8byte .LVL85 + .2byte 0x4 + .byte 0xf3 + .uleb128 0x1 + .byte 0x50 .byte 0x9f - .8byte .LVL72 - .8byte .LVL75 + .8byte .LVL85 + .8byte .LVL86 .2byte 0x1 .byte 0x50 - .8byte .LVL82 - .8byte .LVL83 + .8byte .LVL86 + .8byte .LVL87 + .2byte 0x4 + .byte 0xf3 + .uleb128 0x1 + .byte 0x50 + .byte 0x9f + .8byte .LVL87 + .8byte .LVL88 .2byte 0x1 - .byte 0x5b - .8byte .LVL83 - .8byte .LVL96 - .2byte 0x3 - .byte 0x70 - .sleb128 1 + .byte 0x50 + .8byte .LVL88 + .8byte .LVL89 + .2byte 0x4 + .byte 0xf3 + .uleb128 0x1 + .byte 0x50 .byte 0x9f - .8byte .LVL96 - .8byte .LVL97 + .8byte .LVL89 + .8byte .LVL90 .2byte 0x1 .byte 0x50 - .8byte .LVL97 - .8byte .LVL101 - .2byte 0x3 - .byte 0x7b - .sleb128 -1 + .8byte .LVL90 + .8byte .LVL91 + .2byte 0x4 + .byte 0xf3 + .uleb128 0x1 + .byte 0x50 .byte 0x9f - .8byte .LVL101 - .8byte .LVL102 + .8byte .LVL91 + .8byte .LVL92 .2byte 0x1 - .byte 0x5b + .byte 0x50 + .8byte .LVL92 .8byte .LVL102 - .8byte .LVL106 - .2byte 0x1 + .2byte 0x4 + .byte 0xf3 + .uleb128 0x1 + .byte 0x50 + .byte 0x9f + .8byte .LVL103 + .8byte .LFE217 + .2byte 0x4 + .byte 0xf3 + .uleb128 0x1 .byte 0x50 - .8byte .LVL115 - .8byte .LFE212 - .2byte 0x2 - .byte 0x30 .byte 0x9f .8byte 0 .8byte 0 -.LLST21: - .8byte .LVL62 - .8byte .LVL73 - .2byte 0x1 - .byte 0x60 +.LLST19: .8byte .LVL82 - .8byte .LVL96 + .8byte .LVL85 .2byte 0x1 - .byte 0x60 - .8byte .LVL97 - .8byte .LVL100 + .byte 0x50 + .8byte .LVL93 + .8byte .LVL102 .2byte 0x1 .byte 0x50 - .8byte .LVL109 - .8byte .LVL115 + .8byte .LVL103 + .8byte .LFE217 .2byte 0x1 - .byte 0x57 + .byte 0x50 .8byte 0 .8byte 0 -.LLST22: - .8byte .LVL71 - .8byte .LVL73 - .2byte 0x1 - .byte 0x54 - .8byte .LVL77 - .8byte .LVL78 - .2byte 0x1 - .byte 0x50 +.LLST20: .8byte .LVL83 + .8byte .LVL84 + .2byte 0x1 + .byte 0x51 + .8byte .LVL84 + .8byte .LVL85 + .2byte 0x9 + .byte 0x3 + .8byte global_waveform .8byte .LVL93 + .8byte .LVL95 .2byte 0x1 - .byte 0x54 - .8byte .LVL94 + .byte 0x51 + .8byte .LVL95 + .8byte .LVL96 + .2byte 0x9 + .byte 0x3 + .8byte global_waveform .8byte .LVL96 + .8byte .LVL98 .2byte 0x1 - .byte 0x54 + .byte 0x51 + .8byte .LVL98 + .8byte .LVL99 + .2byte 0x9 + .byte 0x3 + .8byte global_waveform + .8byte .LVL99 + .8byte .LVL100 + .2byte 0x1 + .byte 0x51 + .8byte .LVL100 + .8byte .LVL103 + .2byte 0x9 + .byte 0x3 + .8byte global_waveform + .8byte .LVL103 + .8byte .LVL104 + .2byte 0x1 + .byte 0x51 + .8byte .LVL104 + .8byte .LVL105 + .2byte 0x9 + .byte 0x3 + .8byte global_waveform + .8byte .LVL105 .8byte .LVL106 - .8byte .LVL113 .2byte 0x1 - .byte 0x50 - .8byte .LVL114 - .8byte .LVL115 + .byte 0x51 + .8byte .LVL106 + .8byte .LVL107 + .2byte 0x9 + .byte 0x3 + .8byte global_waveform + .8byte .LVL107 + .8byte .LVL108 .2byte 0x1 - .byte 0x50 + .byte 0x51 + .8byte .LVL108 + .8byte .LVL109 + .2byte 0x9 + .byte 0x3 + .8byte global_waveform + .8byte .LVL109 + .8byte .LVL110 + .2byte 0x1 + .byte 0x51 + .8byte .LVL110 + .8byte .LVL111 + .2byte 0x9 + .byte 0x3 + .8byte global_waveform + .8byte .LVL111 + .8byte .LVL112 + .2byte 0x1 + .byte 0x51 + .8byte .LVL112 + .8byte .LFE217 + .2byte 0x9 + .byte 0x3 + .8byte global_waveform .8byte 0 .8byte 0 -.LLST23: - .8byte .LVL54 - .8byte .LVL59 +.LLST21: + .8byte .LVL83 + .8byte .LVL85 .2byte 0x2 - .byte 0x31 + .byte 0x30 .byte 0x9f - .8byte .LVL59 - .8byte .LVL76-1 - .2byte 0x1 - .byte 0x5a - .8byte .LVL82 - .8byte .LVL106 - .2byte 0x1 - .byte 0x5a - .8byte .LVL115 - .8byte .LFE212 + .8byte .LVL93 + .8byte .LVL94 + .2byte 0x2 + .byte 0x30 + .byte 0x9f + .8byte .LVL94 + .8byte .LVL96 + .2byte 0xa + .byte 0x3 + .8byte pvi_mode_table+27 + .byte 0x9f + .8byte .LVL96 + .8byte .LVL97 + .2byte 0x2 + .byte 0x30 + .byte 0x9f + .8byte .LVL97 + .8byte .LVL99 + .2byte 0xa + .byte 0x3 + .8byte pvi_mode_table+63 + .byte 0x9f + .8byte .LVL99 + .8byte .LVL101 + .2byte 0x2 + .byte 0x30 + .byte 0x9f + .8byte .LVL103 + .8byte .LVL105 + .2byte 0xa + .byte 0x3 + .8byte pvi_mode_table+18 + .byte 0x9f + .8byte .LVL105 + .8byte .LVL107 + .2byte 0xa + .byte 0x3 + .8byte pvi_mode_table+36 + .byte 0x9f + .8byte .LVL107 + .8byte .LVL109 + .2byte 0xa + .byte 0x3 + .8byte pvi_mode_table+45 + .byte 0x9f + .8byte .LVL109 + .8byte .LVL111 + .2byte 0xa + .byte 0x3 + .8byte pvi_mode_table+54 + .byte 0x9f + .8byte .LVL111 + .8byte .LFE217 .2byte 0x2 - .byte 0x31 + .byte 0x30 .byte 0x9f .8byte 0 .8byte 0 .section .debug_aranges,"",@progbits - .4byte 0xbc + .4byte 0x8c .2byte 0x2 .4byte .Ldebug_info0 .byte 0x8 .byte 0 .2byte 0 .2byte 0 - .8byte .LFB215 - .8byte .LFE215-.LFB215 - .8byte .LFB224 - .8byte .LFE224-.LFB224 - .8byte .LFB222 - .8byte .LFE222-.LFB222 - .8byte .LFB212 - .8byte .LFE212-.LFB212 + .8byte .LFB218 + .8byte .LFE218-.LFB218 + .8byte .LFB219 + .8byte .LFE219-.LFB219 .8byte .LFB217 .8byte .LFE217-.LFB217 - .8byte .LFB229 - .8byte .LFE229-.LFB229 + .8byte .LFB215 + .8byte .LFE215-.LFB215 .8byte .LFB226 .8byte .LFE226-.LFB226 - .8byte .LFB232 - .8byte .LFE232-.LFB232 - .8byte .LFB233 - .8byte .LFE233-.LFB233 - .8byte .LFB234 - .8byte .LFE234-.LFB234 + .8byte .LFB227 + .8byte .LFE227-.LFB227 + .8byte .LFB228 + .8byte .LFE228-.LFB228 .8byte 0 .8byte 0 .section .debug_ranges,"",@progbits .Ldebug_ranges0: - .8byte .LBB42 - .8byte .LBE42 - .8byte .LBB45 - .8byte .LBE45 - .8byte 0 - .8byte 0 - .8byte .LBB48 - .8byte .LBE48 - .8byte .LBB53 - .8byte .LBE53 - .8byte .LBB54 - .8byte .LBE54 - .8byte .LBB55 - .8byte .LBE55 - .8byte 0 - .8byte 0 - .8byte .LBB49 - .8byte .LBE49 - .8byte .LBB52 - .8byte .LBE52 - .8byte 0 - .8byte 0 - .8byte .LBB68 - .8byte .LBE68 - .8byte .LBB75 - .8byte .LBE75 - .8byte 0 - .8byte 0 - .8byte .LBB121 - .8byte .LBE121 - .8byte .LBB125 - .8byte .LBE125 - .8byte .LBB128 - .8byte .LBE128 - .8byte 0 - .8byte 0 - .8byte .LBB129 - .8byte .LBE129 - .8byte .LBB176 - .8byte .LBE176 - .8byte 0 - .8byte 0 - .8byte .LBB131 - .8byte .LBE131 - .8byte .LBB134 - .8byte .LBE134 - .8byte 0 - .8byte 0 - .8byte .LBB135 - .8byte .LBE135 - .8byte .LBB150 - .8byte .LBE150 - .8byte 0 - .8byte 0 - .8byte .LBB137 - .8byte .LBE137 - .8byte .LBB140 - .8byte .LBE140 - .8byte 0 - .8byte 0 - .8byte .LBB142 - .8byte .LBE142 - .8byte .LBB151 - .8byte .LBE151 + .8byte .LBB8 + .8byte .LBE8 + .8byte .LBB13 + .8byte .LBE13 + .8byte .LBB14 + .8byte .LBE14 + .8byte .LBB15 + .8byte .LBE15 .8byte 0 .8byte 0 - .8byte .LBB153 - .8byte .LBE153 - .8byte .LBB188 - .8byte .LBE188 - .8byte .LBB208 - .8byte .LBE208 - .8byte .LBB210 - .8byte .LBE210 + .8byte .LBB22 + .8byte .LBE22 + .8byte .LBB26 + .8byte .LBE26 + .8byte .LBB27 + .8byte .LBE27 .8byte 0 .8byte 0 - .8byte .LBB155 - .8byte .LBE155 - .8byte .LBB169 - .8byte .LBE169 + .8byte .LBB28 + .8byte .LBE28 + .8byte .LBB29 + .8byte .LBE29 .8byte 0 .8byte 0 - .8byte .LBB160 - .8byte .LBE160 - .8byte .LBB163 - .8byte .LBE163 - .8byte 0 - .8byte 0 - .8byte .LBB164 - .8byte .LBE164 - .8byte .LBB170 - .8byte .LBE170 - .8byte .LBB171 - .8byte .LBE171 - .8byte .LBB172 - .8byte .LBE172 - .8byte 0 - .8byte 0 - .8byte .LBB177 - .8byte .LBE177 - .8byte .LBB182 - .8byte .LBE182 - .8byte 0 - .8byte 0 - .8byte .LBB183 - .8byte .LBE183 - .8byte .LBB189 - .8byte .LBE189 + .8byte .LBB51 + .8byte .LBE51 + .8byte .LBB55 + .8byte .LBE55 + .8byte .LBB56 + .8byte .LBE56 .8byte 0 .8byte 0 - .8byte .LBB190 - .8byte .LBE190 - .8byte .LBB209 - .8byte .LBE209 - .8byte .LBB211 - .8byte .LBE211 + .8byte .LBB57 + .8byte .LBE57 + .8byte .LBB66 + .8byte .LBE66 .8byte 0 .8byte 0 - .8byte .LBB192 - .8byte .LBE192 - .8byte .LBB195 - .8byte .LBE195 + .8byte .LBB60 + .8byte .LBE60 + .8byte .LBB64 + .8byte .LBE64 .8byte 0 .8byte 0 - .8byte .LBB196 - .8byte .LBE196 - .8byte .LBB204 - .8byte .LBE204 - .8byte .LBB205 - .8byte .LBE205 + .8byte .LBB61 + .8byte .LBE61 + .8byte .LBB62 + .8byte .LBE62 + .8byte .LBB63 + .8byte .LBE63 .8byte 0 .8byte 0 - .8byte .LBB198 - .8byte .LBE198 - .8byte .LBB201 - .8byte .LBE201 + .8byte .LBB67 + .8byte .LBE67 + .8byte .LBB68 + .8byte .LBE68 .8byte 0 .8byte 0 - .8byte .LFB215 - .8byte .LFE215 - .8byte .LFB224 - .8byte .LFE224 - .8byte .LFB222 - .8byte .LFE222 - .8byte .LFB212 - .8byte .LFE212 + .8byte .LFB218 + .8byte .LFE218 + .8byte .LFB219 + .8byte .LFE219 .8byte .LFB217 .8byte .LFE217 - .8byte .LFB229 - .8byte .LFE229 + .8byte .LFB215 + .8byte .LFE215 .8byte .LFB226 .8byte .LFE226 - .8byte .LFB232 - .8byte .LFE232 - .8byte .LFB233 - .8byte .LFE233 - .8byte .LFB234 - .8byte .LFE234 + .8byte .LFB227 + .8byte .LFE227 + .8byte .LFB228 + .8byte .LFE228 .8byte 0 .8byte 0 .section .debug_line,"",@progbits .Ldebug_line0: .section .debug_str,"MS",@progbits,1 -.LASF391: +.LASF265: .string "level" -.LASF369: - .string "white" -.LASF82: +.LASF81: .string "off_mem_rsvmap" -.LASF165: - .string "UCLASS_I2C_EEPROM" .LASF17: .string "size_t" -.LASF170: - .string "UCLASS_IRQ" -.LASF132: +.LASF131: .string "initrd_start" -.LASF164: - .string "UCLASS_I2C" .LASF13: .string "sizetype" -.LASF252: +.LASF151: .string "net_hostname" .LASF36: .string "start" -.LASF205: - .string "UCLASS_SPI" -.LASF168: - .string "UCLASS_I2S" -.LASF274: +.LASF171: .string "NETLOOP_RESTART" -.LASF357: - .string "parse_wf_gray16_with_lut_type" -.LASF343: +.LASF238: .string "pvi_wf_get_lut" -.LASF166: - .string "UCLASS_I2C_GENERIC" -.LASF374: - .string "total" -.LASF178: - .string "UCLASS_MOD_EXP" -.LASF228: - .string "UCLASS_IO_DOMAIN" -.LASF291: +.LASF186: .string "WF_TYPE_GL16" -.LASF341: +.LASF236: .string "pvi_wf_input" -.LASF302: - .string "PVI_WF_GL16" -.LASF199: - .string "UCLASS_RKNAND" -.LASF141: - .string "UCLASS_DEMO" -.LASF90: +.LASF89: .string "ih_magic" -.LASF145: - .string "UCLASS_TEST_PROBE" -.LASF224: - .string "UCLASS_KEY" .LASF62: .string "bi_intfreq" -.LASF388: +.LASF261: .string "__func__" .LASF11: .string "phys_addr_t" -.LASF414: - .string "drivers/video/rk_eink/epdlut/pvi_waveform.c" .LASF5: .string "__u8" -.LASF273: +.LASF170: .string "NETLOOP_CONTINUE" -.LASF208: - .string "UCLASS_SPI_GENERIC" .LASF38: .string "flash_info_t" -.LASF183: - .string "UCLASS_PANEL" -.LASF107: +.LASF106: .string "comp" -.LASF102: +.LASF101: .string "image_header_t" -.LASF137: +.LASF136: .string "state" -.LASF158: - .string "UCLASS_CROS_EC" -.LASF415: - .string "/home/lyx/rk3566-11-eink/u-boot" .LASF56: .string "bi_dsp_freq" -.LASF365: - .string "get_lut_reset_data" -.LASF104: +.LASF103: .string "image_start" -.LASF143: - .string "UCLASS_TEST_FDT" .LASF47: .string "bd_info" -.LASF358: - .string "parse_wf_gray2" -.LASF271: - .string "uclass_id" -.LASF297: - .string "pvi_wf_mode" -.LASF94: +.LASF93: .string "ih_load" -.LASF242: +.LASF141: .string "__dtb_dt_spl_begin" -.LASF313: +.LASF205: .string "file_length" -.LASF321: +.LASF213: .string "wf_type" .LASF7: .string "__u32" -.LASF148: - .string "UCLASS_PCI_EMUL" -.LASF389: +.LASF263: .string "get_wf_temp_index" -.LASF308: +.LASF199: .string "epd_lut_data" -.LASF258: +.LASF157: .string "net_tx_packet" -.LASF223: - .string "UCLASS_FG" -.LASF257: +.LASF156: .string "net_server_ip" -.LASF355: - .string "parse_wf_gray16" -.LASF304: - .string "PVI_WF_GLD16" -.LASF265: +.LASF164: .string "net_native_vlan" -.LASF221: - .string "UCLASS_VIDEO_CRTC" -.LASF393: - .string "pvi_modes" -.LASF284: +.LASF252: + .string "pvi_wf_normal_fix" +.LASF182: .string "WF_TYPE_RESET" -.LASF157: - .string "UCLASS_CODEC" -.LASF413: +.LASF284: .ascii "GNU C11 6.3.1 20170404 -ms" .string "trict-align -march=armv8-a+nosimd -mlittle-endian -mabi=lp64 -g -Os -fno-builtin -ffreestanding -fshort-wchar -fno-stack-protector -fno-delete-null-pointer-checks -fstack-usage -fno-pic -ffunction-sections -fdata-sections -ffixed-r9 -fno-common -ffixed-x18" .LASF23: @@ -12156,695 +7054,503 @@ __func__.6107: .string "long int" .LASF51: .string "bi_flashsize" -.LASF188: - .string "UCLASS_PHY" -.LASF75: +.LASF74: .string "IRQ_STACK_START_IN" -.LASF86: +.LASF85: .string "size_dt_strings" -.LASF218: - .string "UCLASS_VIDEO" -.LASF399: +.LASF250: + .string "shift" +.LASF271: .string "oldpic" -.LASF268: +.LASF167: .string "net_boot_file_size" -.LASF356: - .string "parse_wf_gray32" -.LASF96: +.LASF95: .string "ih_dcrc" .LASF61: .string "bi_ethspeed" -.LASF140: - .string "UCLASS_ROOT" -.LASF380: +.LASF262: .string "get_wf_frm_num" .LASF29: .string "ide_bus_offset" -.LASF364: - .string "get_lut_gray32_data" -.LASF255: +.LASF154: .string "net_server_ethaddr" .LASF64: .string "bi_arch_number" .LASF3: .string "signed char" -.LASF171: - .string "UCLASS_KEYBOARD" .LASF20: .string "uint8_t" -.LASF332: +.LASF225: .string "waveformdata" -.LASF98: +.LASF97: .string "ih_arch" -.LASF79: +.LASF78: .string "totalsize" -.LASF401: +.LASF273: .string "frame_tmp" -.LASF91: +.LASF90: .string "ih_hcrc" -.LASF370: - .string "idata" -.LASF106: +.LASF105: .string "load" -.LASF290: +.LASF185: .string "WF_TYPE_GC16" -.LASF213: - .string "UCLASS_TPM" -.LASF301: - .string "PVI_WF_GC16" .LASF41: .string "lmb_property" -.LASF84: +.LASF83: .string "last_comp_version" .LASF0: .string "unsigned char" -.LASF66: - .string "bi_andr_version" -.LASF139: +.LASF138: .string "images" -.LASF227: - .string "UCLASS_DVFS" +.LASF256: + .string "pvi_wf_gray2_repair" .LASF57: .string "bi_ddr_freq" -.LASF172: - .string "UCLASS_LED" -.LASF93: +.LASF92: .string "ih_size" -.LASF400: - .string "newpic" -.LASF202: - .string "UCLASS_SCMI_AGENT" -.LASF231: - .string "UCLASS_MDIO" +.LASF269: + .string "pvi_wf_add_custom_mode_table" +.LASF104: + .string "image_len" +.LASF251: + .string "wf_table_to_4bit_wf_lut_data" .LASF25: .string "_Bool" -.LASF277: - .string "net_state" -.LASF339: +.LASF231: + .string "table" +.LASF234: .string "spi_id_buffer" -.LASF167: - .string "UCLASS_I2C_MUX" -.LASF309: +.LASF200: .string "frame_num" .LASF14: .string "char" .LASF27: .string "_binary_u_boot_bin_start" -.LASF217: - .string "UCLASS_USB_GADGET_GENERIC" -.LASF275: +.LASF172: .string "NETLOOP_SUCCESS" -.LASF345: +.LASF240: .string "output" -.LASF281: +.LASF178: .string "p_current" -.LASF272: +.LASF180: .string "net_loop_state" -.LASF300: - .string "PVI_WF_DU4" -.LASF156: - .string "UCLASS_AMP" -.LASF194: - .string "UCLASS_PWRSEQ" -.LASF122: +.LASF276: + .string "shift_n" +.LASF121: .string "fit_hdr_fdt" -.LASF266: +.LASF165: .string "net_restart_wrap" -.LASF254: +.LASF153: .string "net_ethaddr" -.LASF407: +.LASF279: .string "flags" -.LASF367: - .string "gray" -.LASF397: +.LASF270: .string "decodewaveform" -.LASF99: +.LASF98: .string "ih_type" -.LASF80: +.LASF79: .string "off_dt_struct" .LASF52: .string "bi_flashoffset" -.LASF267: +.LASF166: .string "net_boot_file_name" -.LASF142: - .string "UCLASS_TEST" -.LASF92: +.LASF91: .string "ih_time" -.LASF195: - .string "UCLASS_RAM" -.LASF161: - .string "UCLASS_ETH" -.LASF103: +.LASF259: + .string "wf_data" +.LASF102: .string "image_info" -.LASF219: - .string "UCLASS_VIDEO_BRIDGE" -.LASF378: - .string "temp_data" -.LASF109: +.LASF108: .string "arch" -.LASF351: - .string "input" -.LASF372: - .string "temp" .LASF31: .string "select_hwpart" -.LASF259: +.LASF158: .string "net_rx_packets" -.LASF278: +.LASF175: .string "mem_malloc_start" -.LASF74: +.LASF73: .string "_datarelro_start_ofs" .LASF19: .string "ulong" -.LASF353: - .string "parse_wf_auto" -.LASF95: +.LASF94: .string "ih_ep" .LASF43: .string "lmb_region" -.LASF338: +.LASF230: + .string "pvi_custom_mode_table" +.LASF233: .string "waveform" -.LASF408: +.LASF280: .string "printf" -.LASF117: +.LASF116: .string "fit_uname_os" +.LASF195: + .string "WF_TYPE_RK_GL16" .LASF58: .string "bi_bootflags" -.LASF256: +.LASF155: .string "net_ip" -.LASF250: +.LASF149: .string "net_dns_server" -.LASF270: +.LASF169: .string "net_ping_ip" .LASF45: .string "memory" -.LASF336: - .string "gray32_data" -.LASF363: - .string "get_lut_gray2_data" -.LASF77: +.LASF76: .string "fdt_header" -.LASF279: +.LASF176: .string "mem_malloc_end" -.LASF330: +.LASF222: .string "temperaturenumber" -.LASF174: - .string "UCLASS_MAILBOX" -.LASF129: +.LASF128: .string "rd_end" -.LASF306: - .string "PVI_WF_GCC16" -.LASF134: +.LASF133: .string "cmdline_start" -.LASF347: +.LASF224: .string "temperture" -.LASF371: - .string "odata" -.LASF203: - .string "UCLASS_SCSI" -.LASF215: - .string "UCLASS_USB_DEV_GENERIC" -.LASF175: - .string "UCLASS_MASS_STORAGE" -.LASF406: +.LASF278: .string "kzalloc" .LASF1: .string "long unsigned int" .LASF150: - .string "UCLASS_SIMPLE_BUS" -.LASF251: .string "net_nis_domain" -.LASF286: +.LASF184: .string "WF_TYPE_GRAY4" -.LASF124: +.LASF123: .string "fit_noffset_fdt" -.LASF276: +.LASF173: .string "NETLOOP_FAIL" -.LASF222: - .string "UCLASS_WDT" -.LASF398: +.LASF226: .string "maxpic" .LASF53: .string "bi_sramstart" .LASF28: .string "_binary_u_boot_bin_end" -.LASF85: +.LASF84: .string "boot_cpuid_phys" -.LASF120: +.LASF119: .string "fit_uname_rd" -.LASF352: +.LASF246: .string "mode_index" -.LASF209: - .string "UCLASS_SYSCON" -.LASF115: - .string "fit_uname_cfg" -.LASF204: - .string "UCLASS_SERIAL" -.LASF264: +.LASF114: + .string "fit_uname_cfg" +.LASF163: .string "net_our_vlan" -.LASF314: +.LASF206: .string "serial" -.LASF153: - .string "UCLASS_BLK" -.LASF110: +.LASF235: + .string "pvi_wf_get_version" +.LASF109: .string "image_info_t" -.LASF149: - .string "UCLASS_USB_EMUL" -.LASF307: +.LASF191: .string "PVI_WF_MAX" -.LASF326: +.LASF218: .string "vcom_offset" -.LASF187: - .string "UCLASS_PCI_GENERIC" -.LASF337: +.LASF227: .string "global_waveform" -.LASF327: +.LASF219: .string "xwia" -.LASF105: - .string "image_len" +.LASF286: + .string "/home/hzb/sdk/u-boot" .LASF59: .string "bi_ip_addr" -.LASF189: - .string "UCLASS_PINCONFIG" -.LASF377: - .string "decode_wf_reset" -.LASF211: - .string "UCLASS_THERMAL" -.LASF113: +.LASF112: .string "legacy_hdr_os_copy" .LASF9: .string "long long int" -.LASF382: - .string "want_pic" -.LASF292: +.LASF187: .string "WF_TYPE_GLR16" +.LASF202: + .string "wf_table" .LASF24: .string "___strtok" -.LASF269: +.LASF168: .string "net_boot_file_expected_size_in_blocks" .LASF16: .string "__kernel_size_t" -.LASF182: - .string "UCLASS_NVME" -.LASF111: +.LASF110: .string "bootm_headers" .LASF37: .string "protect" -.LASF214: - .string "UCLASS_USB" -.LASF225: - .string "UCLASS_RC" -.LASF159: - .string "UCLASS_DISPLAY" -.LASF263: +.LASF162: .string "net_null_ethaddr" -.LASF329: +.LASF221: .string "modenumber" -.LASF71: +.LASF70: .string "_datarel_start_ofs" -.LASF226: - .string "UCLASS_CHARGE_DISPLAY" -.LASF243: +.LASF142: .string "load_addr" -.LASF116: +.LASF115: .string "fit_hdr_os" -.LASF72: +.LASF71: .string "_datarelrolocal_start_ofs" -.LASF315: +.LASF196: + .string "WF_TYPE_RK_GC16" +.LASF207: .string "run_type" +.LASF247: + .string "overlay_lut" .LASF8: .string "unsigned int" .LASF18: .string "ushort" -.LASF322: +.LASF214: .string "panel_size" -.LASF379: - .string "temp1" -.LASF324: +.LASF216: .string "wfm_rev" -.LASF295: - .string "WF_TYPE_GRAY32" -.LASF396: - .string "frame" -.LASF191: - .string "UCLASS_PMIC" -.LASF350: +.LASF174: + .string "net_state" +.LASF245: .string "temp_index" -.LASF112: +.LASF229: + .string "pvi_mode_table" +.LASF111: .string "legacy_hdr_os" -.LASF81: +.LASF80: .string "off_dt_strings" -.LASF240: +.LASF139: .string "monitor_flash_len" -.LASF176: - .string "UCLASS_MISC" .LASF49: .string "bi_memsize" -.LASF298: - .string "PVI_WF_RESET" -.LASF328: +.LASF220: .string "unknown1" -.LASF331: +.LASF223: .string "unknown2" .LASF26: .string "image_base" -.LASF210: - .string "UCLASS_SYSRESET" -.LASF288: - .string "WF_TYPE_AUTO" -.LASF282: +.LASF179: .string "current" -.LASF163: - .string "UCLASS_FIRMWARE" -.LASF173: - .string "UCLASS_LPC" -.LASF383: - .string "temp2" -.LASF384: - .string "temp3" -.LASF385: - .string "temp4" -.LASF169: - .string "UCLASS_IDE" -.LASF403: +.LASF260: + .string "offset" +.LASF275: .string "israr" -.LASF405: +.LASF277: .string "block" -.LASF138: +.LASF137: .string "bootm_headers_t" .LASF55: .string "bi_arm_freq" -.LASF197: - .string "UCLASS_REMOTEPROC" -.LASF108: +.LASF107: .string "type" -.LASF119: +.LASF118: .string "fit_hdr_rd" -.LASF305: - .string "PVI_WF_A2" .LASF54: .string "bi_sramsize" -.LASF162: - .string "UCLASS_GPIO" -.LASF192: - .string "UCLASS_PWM" .LASF40: .string "long double" -.LASF402: +.LASF255: + .string "pvi_wf_regal_fix" +.LASF274: .string "tempdata" -.LASF128: +.LASF127: .string "rd_start" -.LASF193: - .string "UCLASS_POWER_DOMAIN" -.LASF196: - .string "UCLASS_REGULATOR" -.LASF325: +.LASF147: + .string "net_gateway" +.LASF217: .string "frame_rate" -.LASF245: +.LASF144: .string "save_size" -.LASF154: - .string "UCLASS_CLK" -.LASF312: +.LASF204: .string "checksum" -.LASF340: - .string "pvi_wf_get_version" -.LASF101: +.LASF253: + .string "pvi_wf_rpart_fix" +.LASF100: .string "ih_name" -.LASF97: +.LASF96: .string "ih_os" -.LASF293: +.LASF188: .string "WF_TYPE_GLD16" -.LASF135: +.LASF134: .string "cmdline_end" -.LASF260: +.LASF159: .string "net_rx_packet" -.LASF239: - .string "LOGF_MAX_CATEGORIES" +.LASF193: + .string "WF_TYPE_RK_GLR16" .LASF33: .string "size" .LASF10: .string "long long unsigned int" -.LASF89: +.LASF267: + .string "pvi_modes" +.LASF88: .string "image_header" -.LASF287: +.LASF183: .string "WF_TYPE_GRAY2" .LASF21: .string "__be32" +.LASF272: + .string "newpic" .LASF50: .string "bi_flashstart" -.LASF118: +.LASF117: .string "fit_noffset_os" -.LASF177: - .string "UCLASS_MMC" -.LASF238: - .string "UCLASS_INVALID" -.LASF216: - .string "UCLASS_USB_HUB" -.LASF362: - .string "get_lut_gray16_data" -.LASF319: - .string "wf_version" -.LASF232: - .string "UCLASS_EBC" -.LASF296: +.LASF197: .string "WF_TYPE_MAX" -.LASF411: +.LASF283: .string "memset" .LASF39: .string "flash_info" -.LASF83: +.LASF82: .string "version" .LASF44: .string "region" -.LASF87: +.LASF86: .string "size_dt_struct" -.LASF299: - .string "PVI_WF_DU" -.LASF234: - .string "UCLASS_RNG" -.LASF179: - .string "UCLASS_MTD" -.LASF373: - .string "decode_wf_gray2" -.LASF76: +.LASF75: .string "fdt32_t" -.LASF346: +.LASF241: .string "lut_type" -.LASF181: - .string "UCLASS_NORTHBRIDGE" .LASF60: .string "bi_enetaddr" -.LASF316: +.LASF208: .string "fpl_platform" -.LASF416: +.LASF287: .string "mtd_info" -.LASF375: - .string "_data" -.LASF246: +.LASF145: .string "in_addr" -.LASF261: +.LASF160: .string "net_rx_packet_len" -.LASF334: - .string "reset_data" -.LASF348: +.LASF243: .string "stype" -.LASF323: +.LASF215: .string "amepd_part_number" -.LASF387: - .string "offset" -.LASF241: +.LASF140: .string "__dtb_dt_begin" -.LASF390: +.LASF264: .string "temp_num" -.LASF368: - .string "black" -.LASF198: - .string "UCLASS_RESET" -.LASF121: +.LASF120: .string "fit_noffset_rd" -.LASF152: - .string "UCLASS_AHCI" .LASF12: .string "phys_size_t" -.LASF386: - .string "frm_num" -.LASF155: - .string "UCLASS_CPU" -.LASF70: +.LASF69: .string "FIQ_STACK_START" -.LASF136: +.LASF135: .string "verify" .LASF30: .string "name" -.LASF394: +.LASF268: .string "parse_mode_version" -.LASF410: +.LASF282: .string "kmalloc" -.LASF233: - .string "UCLASS_EINK_DISPLAY" -.LASF184: - .string "UCLASS_PANEL_BACKLIGHT" -.LASF342: +.LASF211: + .string "wf_version" +.LASF237: .string "pvi_wf" -.LASF212: - .string "UCLASS_TIMER" -.LASF207: - .string "UCLASS_SPI_FLASH" .LASF63: .string "bi_busfreq" .LASF6: .string "short int" -.LASF361: - .string "oldgray" -.LASF190: - .string "UCLASS_PINCTRL" -.LASF200: - .string "UCLASS_RAMDISK" -.LASF381: +.LASF258: .string "mode" -.LASF147: - .string "UCLASS_I2C_EMUL" -.LASF206: - .string "UCLASS_SPMI" -.LASF144: - .string "UCLASS_TEST_BUS" -.LASF244: +.LASF143: .string "save_addr" -.LASF354: - .string "parse_wf_a2" -.LASF133: +.LASF232: + .string "custom_mode_table" +.LASF132: .string "initrd_end" -.LASF404: +.LASF288: .string "kfree" -.LASF359: - .string "parse_wf_reset" -.LASF73: +.LASF254: + .string "regal_fix" +.LASF72: .string "_datarellocal_start_ofs" -.LASF360: - .string "newgray" -.LASF237: - .string "UCLASS_COUNT" -.LASF320: +.LASF194: + .string "WF_TYPE_RK_GLD16" +.LASF242: + .string "regal_pix" +.LASF212: .string "wf_subversion" .LASF32: .string "block_drvr" -.LASF412: - .string "memcpy" .LASF22: .string "gfp_t" .LASF35: .string "flash_id" -.LASF229: - .string "UCLASS_CRYPTO" -.LASF127: +.LASF126: .string "fit_noffset_setup" -.LASF88: +.LASF87: .string "working_fdt" -.LASF253: +.LASF152: .string "net_root_path" -.LASF160: - .string "UCLASS_DMA" -.LASF68: +.LASF67: .string "bd_t" -.LASF235: - .string "UCLASS_DMC" -.LASF247: +.LASF146: .string "s_addr" -.LASF262: +.LASF161: .string "net_bcast_ethaddr" .LASF65: .string "bi_boot_params" -.LASF349: +.LASF244: .string "sftemp" -.LASF280: +.LASF177: .string "mem_malloc_brk" -.LASF248: - .string "net_gateway" .LASF48: .string "bi_memstart" -.LASF283: +.LASF181: .string "epd_lut_type" -.LASF220: - .string "UCLASS_VIDEO_CONSOLE" -.LASF289: +.LASF189: .string "WF_TYPE_A2" -.LASF317: +.LASF209: .string "fpl_lot" .LASF46: .string "reserved" -.LASF409: +.LASF281: .string "free" -.LASF236: - .string "UCLASS_PD" -.LASF395: - .string "getwaveformdata" -.LASF311: +.LASF203: .string "pvi_waveform" -.LASF67: +.LASF66: .string "bi_dram" .LASF2: .string "short unsigned int" -.LASF78: +.LASF77: .string "magic" -.LASF125: +.LASF124: .string "fit_hdr_setup" -.LASF294: +.LASF190: .string "WF_TYPE_GCC16" -.LASF114: +.LASF113: .string "legacy_hdr_valid" .LASF42: .string "base" -.LASF201: - .string "UCLASS_RTC" +.LASF228: + .string "need_pic" .LASF34: .string "sector_count" -.LASF100: +.LASF99: .string "ih_comp" -.LASF285: +.LASF198: .string "WF_TYPE_GRAY16" -.LASF303: - .string "PVI_WF_GLR16" -.LASF376: - .string "_data1" -.LASF335: - .string "gray_2_data" -.LASF130: +.LASF248: + .string "lut_data" +.LASF129: .string "ft_addr" -.LASF230: - .string "UCLASS_ETH_PHY" -.LASF333: - .string "gray_data" -.LASF318: +.LASF210: .string "mode_version" .LASF4: .string "uchar" -.LASF131: +.LASF130: .string "ft_len" -.LASF310: +.LASF285: + .string "/home/hzb/sdk/ebc-dev/rk_eink/../epdlut/pvi_waveform.c" +.LASF201: .string "data" -.LASF180: - .string "UCLASS_NOP" -.LASF126: +.LASF192: + .string "WF_TYPE_AUTO" +.LASF125: .string "fit_uname_setup" -.LASF185: - .string "UCLASS_PCH" -.LASF186: - .string "UCLASS_PCI" -.LASF249: +.LASF148: .string "net_netmask" -.LASF69: +.LASF68: .string "IRQ_STACK_START" -.LASF151: - .string "UCLASS_ADC" -.LASF392: +.LASF257: + .string "pvi_wf_a2_repair" +.LASF266: .string "get_wf_mode_index" -.LASF344: +.LASF239: .string "waveform_file" -.LASF146: - .string "UCLASS_SPI_EMUL" -.LASF366: - .string "decode_wf_auto" -.LASF123: +.LASF249: + .string "is_uboot" +.LASF122: .string "fit_uname_fdt" .hidden free .ident "GCC: (Linaro GCC 6.3-2017.05) 6.3.1 20170404" diff --git a/u-boot/drivers/video/rk_eink/epdlut/rkf_waveform.S b/u-boot/drivers/video/rk_eink/epdlut/rkf_waveform.S index ae9d950daa4..11eb55016ce 100644 --- a/u-boot/drivers/video/rk_eink/epdlut/rkf_waveform.S +++ b/u-boot/drivers/video/rk_eink/epdlut/rkf_waveform.S @@ -1,7 +1,8 @@ +// SPDX-License-Identifier: GPL-2.0 /* - * (C) Copyright 2020 Rockchip Electronics Co., Ltd + * Copyright (c) 2020-2024 Rockchip Electronics Co., Ltd. * - * SPDX-License-Identifier: GPL-2.0+ + * Author: Zorro Liu */ .arch armv8-a+nosimd @@ -13,20 +14,20 @@ .align 2 .type get_wf_buf, %function get_wf_buf: -.LFB219: - .file 1 "drivers/video/rk_eink/epdlut/rkf_waveform.c" - .loc 1 193 0 +.LFB222: + .file 1 "/home/hzb/sdk/ebc-dev/rk_eink/../epdlut/rkf_waveform.c" + .loc 1 219 0 .cfi_startproc .LVL0: - .loc 1 194 0 + .loc 1 220 0 adrp x2, .LANCHOR0 - .loc 1 201 0 + .loc 1 227 0 cmp w1, 6 - .loc 1 194 0 + .loc 1 220 0 ldr x2, [x2, #:lo12:.LANCHOR0] .LVL1: - .loc 1 201 0 - bhi .L15 + .loc 1 227 0 + bhi .L17 adrp x3, .L4 add x3, x3, :lo12:.L4 ldrb w1, [x3,w1,uxtw] @@ -48,150 +49,153 @@ get_wf_buf: .byte (.L10 - .Lrtx4) / 4 .section .text.get_wf_buf .L3: - .loc 1 203 0 + .loc 1 229 0 add x1, x2, 148 .LVL3: - .loc 1 204 0 + .loc 1 230 0 add x3, x2, 596 .LVL4: .L11: -.LBB31: -.LBB32: -.LBB33: - .loc 1 176 0 +.LBB47: +.LBB48: +.LBB49: + .loc 1 205 0 cmp w0, 0 -.LBE33: -.LBB34: - .loc 1 177 0 - mov w4, 49 -.LBE34: -.LBB35: - .loc 1 176 0 +.LBE49: +.LBB50: + .loc 1 206 0 + mov w4, 50 +.LBE50: +.LBB51: + .loc 1 205 0 csel w0, w0, wzr, ge .LVL5: -.LBE35: - .loc 1 173 0 - mov w5, 0 -.LBB36: - .loc 1 177 0 - cmp w0, 49 +.LBE51: +.LBB52: + .loc 1 206 0 + cmp w0, 50 csel w0, w0, w4, le .LVL6: - mov x4, 0 +.LBE52: + .loc 1 208 0 + mov w4, 0 .LVL7: -.L14: -.LBE36: - .loc 1 180 0 - ldrb w6, [x1, x4] - cmp w0, w6 - bgt .L12 -.LVL8: - .loc 1 185 0 - add x5, x1, x4 - ldrb w5, [x5, 1] - cbz w5, .L16 - mov w5, w4 .L12: -.LVL9: - add x4, x4, 1 -.LVL10: - .loc 1 179 0 - cmp x4, 50 - bne .L14 -.LVL11: + .loc 1 209 0 + ldrb w5, [x1] + cmp w0, w5 + bge .L14 .L13: -.LBE32: -.LBE31: - .loc 1 236 0 - ldr w0, [x3, w5, sxtw 2] + .loc 1 210 0 + sub w4, w4, #1 +.LVL8: +.L15: +.LBE48: +.LBE47: + .loc 1 262 0 + ldr w0, [x3, w4, uxtw 2] add x0, x2, x0 - .loc 1 238 0 + .loc 1 264 0 ret -.LVL12: +.LVL9: .L5: - .loc 1 207 0 + .loc 1 233 0 add x1, x2, 468 -.LVL13: - .loc 1 208 0 +.LVL10: + .loc 1 234 0 add x3, x2, 1876 -.LVL14: - .loc 1 209 0 +.LVL11: + .loc 1 235 0 b .L11 -.LVL15: +.LVL12: .L6: - .loc 1 211 0 + .loc 1 237 0 add x1, x2, 212 -.LVL16: - .loc 1 212 0 +.LVL13: + .loc 1 238 0 add x3, x2, 852 -.LVL17: - .loc 1 213 0 +.LVL14: + .loc 1 239 0 b .L11 -.LVL18: +.LVL15: .L7: - .loc 1 215 0 + .loc 1 241 0 add x1, x2, 276 -.LVL19: - .loc 1 216 0 +.LVL16: + .loc 1 242 0 add x3, x2, 1108 -.LVL20: - .loc 1 217 0 +.LVL17: + .loc 1 243 0 b .L11 -.LVL21: +.LVL18: .L8: - .loc 1 219 0 + .loc 1 245 0 add x1, x2, 340 -.LVL22: - .loc 1 220 0 +.LVL19: + .loc 1 246 0 add x3, x2, 1364 -.LVL23: - .loc 1 221 0 +.LVL20: + .loc 1 247 0 b .L11 -.LVL24: +.LVL21: .L9: - .loc 1 223 0 + .loc 1 249 0 add x1, x2, 404 -.LVL25: - .loc 1 224 0 +.LVL22: + .loc 1 250 0 add x3, x2, 1620 -.LVL26: - .loc 1 225 0 +.LVL23: + .loc 1 251 0 b .L11 -.LVL27: +.LVL24: .L10: - .loc 1 227 0 + .loc 1 253 0 add x1, x2, 532 -.LVL28: - .loc 1 228 0 +.LVL25: + .loc 1 254 0 add x3, x2, 2132 -.LVL29: - .loc 1 229 0 +.LVL26: + .loc 1 255 0 b .L11 -.LVL30: +.LVL27: .L16: -.LBB38: -.LBB37: - .loc 1 185 0 - mov w5, w4 - b .L13 +.LBB54: +.LBB53: + .loc 1 209 0 + ldrb w6, [x1, 1] + cmp w6, w5 + bcc .L13 + add x1, x1, 1 + b .L12 +.LVL28: +.L14: + .loc 1 208 0 + add w4, w4, 1 +.LVL29: + cmp w4, 51 + bne .L16 + .loc 1 202 0 + mov w4, 0 +.LVL30: + b .L15 .LVL31: -.L15: -.LBE37: -.LBE38: - .loc 1 231 0 +.L17: +.LBE53: +.LBE54: + .loc 1 257 0 mov x0, 0 .LVL32: - .loc 1 239 0 + .loc 1 265 0 ret .cfi_endproc -.LFE219: +.LFE222: .size get_wf_buf, .-get_wf_buf .section .text.decode_wf_data,"ax",@progbits .align 2 .type decode_wf_data, %function decode_wf_data: -.LFB221: - .loc 1 248 0 +.LFB224: + .loc 1 274 0 .cfi_startproc .LVL33: stp x29, x30, [sp, -48]! @@ -203,24 +207,24 @@ decode_wf_data: stp x19, x20, [sp, 16] .cfi_offset 19, -32 .cfi_offset 20, -24 - .loc 1 251 0 + .loc 1 277 0 uxtw x20, w1 .LVL34: - .loc 1 248 0 + .loc 1 274 0 str x21, [sp, 32] .cfi_offset 21, -16 -.LBB39: -.LBB40: +.LBB55: +.LBB56: .file 2 "include/linux/compat.h" .loc 2 58 0 mov w1, 32768 .LVL35: -.LBE40: -.LBE39: - .loc 1 248 0 +.LBE56: +.LBE55: + .loc 1 274 0 mov x21, x0 -.LBB42: -.LBB41: +.LBB58: +.LBB57: .loc 2 58 0 mov x0, x20 .LVL36: @@ -228,17 +232,17 @@ decode_wf_data: .LVL37: mov x19, x0 .LVL38: -.LBE41: -.LBE42: - .loc 1 252 0 +.LBE57: +.LBE58: + .loc 1 278 0 cbz x0, .L19 - .loc 1 255 0 + .loc 1 281 0 mov x2, x20 add x1, x21, 4 bl memcpy .LVL39: .L19: - .loc 1 258 0 + .loc 1 284 0 mov x0, x19 ldr x21, [sp, 32] .LVL40: @@ -253,585 +257,343 @@ decode_wf_data: .cfi_def_cfa 31, 0 ret .cfi_endproc -.LFE221: +.LFE224: .size decode_wf_data, .-decode_wf_data - .section .text.parse_wf_gray16,"ax",@progbits + .section .text.rkf_lut_init_wf_table.isra.1,"ax",@progbits .align 2 - .type parse_wf_gray16, %function -parse_wf_gray16: -.LFB225: - .loc 1 349 0 + .type rkf_lut_init_wf_table.isra.1, %function +rkf_lut_init_wf_table.isra.1: +.LFB241: + .loc 1 511 0 .cfi_startproc .LVL42: - stp x29, x30, [sp, -32]! - .cfi_def_cfa_offset 32 - .cfi_offset 29, -32 - .cfi_offset 30, -24 - add x29, sp, 0 - .cfi_def_cfa_register 29 - str x19, [sp, 16] - .cfi_offset 19, -16 - .loc 1 349 0 - mov x19, x0 - mov w0, w1 +.LBB59: + .loc 1 517 0 + mov x3, 0 +.L25: .LVL43: - .loc 1 355 0 - mov w1, w2 +.LBE59: + .loc 1 516 0 + cmp w2, w3 + bgt .L29 + .loc 1 527 0 + mov w0, 0 + ret +.L29: +.LBB63: + .loc 1 517 0 + ldr x7, [x0] .LVL44: - bl get_wf_buf + lsl w10, w3, 10 + mov x5, 0 +.LBB60: + .loc 1 520 0 + add x7, x7, x3, lsl 6 .LVL45: - .loc 1 356 0 - ldrb w1, [x0] +.L26: + add w8, w10, w5, lsl 5 +.LBE60: +.LBE63: + .loc 1 511 0 + mov w4, 0 .LVL46: - .loc 1 358 0 - str w1, [x19] +.L27: +.LBB64: +.LBB61: + .loc 1 521 0 + add w11, w4, w8 + .loc 1 520 0 + ldr w6, [x7, x5, lsl 2] + lsl w12, w4, 1 +.LBE61: + .loc 1 519 0 + add w4, w4, 1 .LVL47: - .loc 1 362 0 - lsl w1, w1, 6 + cmp w4, 16 +.LBB62: + .loc 1 520 0 + lsr w6, w6, w12 + and w6, w6, 3 + .loc 1 521 0 + strb w6, [x1, x11] +.LBE62: + .loc 1 519 0 + bne .L27 .LVL48: - bl decode_wf_data + add x5, x5, 1 .LVL49: - str x0, [x19, 8] - .loc 1 366 0 - cmp x0, 0 - .loc 1 367 0 - ldr x19, [sp, 16] + .loc 1 518 0 + cmp x5, 16 + bne .L26 .LVL50: - mov w0, -22 - ldp x29, x30, [sp], 32 - .cfi_restore 30 - .cfi_restore 29 - .cfi_restore 19 - .cfi_def_cfa 31, 0 - csel w0, w0, wzr, eq - ret + add x3, x3, 1 +.LVL51: + b .L25 +.LBE64: .cfi_endproc -.LFE225: - .size parse_wf_gray16, .-parse_wf_gray16 - .section .text.rkf_wf_input,"ax",@progbits +.LFE241: + .size rkf_lut_init_wf_table.isra.1, .-rkf_lut_init_wf_table.isra.1 + .section .text.parse_wf_gray16.isra.3,"ax",@progbits .align 2 - .global rkf_wf_input - .type rkf_wf_input, %function -rkf_wf_input: -.LFB216: - .loc 1 129 0 + .type parse_wf_gray16.isra.3, %function +parse_wf_gray16.isra.3: +.LFB243: + .loc 1 383 0 .cfi_startproc -.LVL51: - stp x29, x30, [sp, -80]! - .cfi_def_cfa_offset 80 - .cfi_offset 29, -80 - .cfi_offset 30, -72 +.LVL52: + stp x29, x30, [sp, -32]! + .cfi_def_cfa_offset 32 + .cfi_offset 29, -32 + .cfi_offset 30, -24 add x29, sp, 0 .cfi_def_cfa_register 29 - stp x21, x22, [sp, 32] - .cfi_offset 21, -48 - .cfi_offset 22, -40 - .loc 1 133 0 - adrp x22, .LANCHOR0 - .loc 1 129 0 stp x19, x20, [sp, 16] - .loc 1 133 0 - ldr x1, [x22, #:lo12:.LANCHOR0] - .loc 1 129 0 - stp x23, x24, [sp, 48] - str x25, [sp, 64] - .cfi_offset 19, -64 - .cfi_offset 20, -56 - .cfi_offset 23, -32 - .cfi_offset 24, -24 - .cfi_offset 25, -16 - .loc 1 133 0 - cbnz x1, .L40 - mov x19, x0 -.LVL52: -.LBB51: -.LBB52: - .loc 1 94 0 - mov x2, 12 - adrp x1, .LC0 - add x0, x0, 4 + .cfi_offset 19, -16 + .cfi_offset 20, -8 + .loc 1 383 0 + mov x20, x0 + mov w0, w1 + .loc 1 390 0 + mov w1, w2 .LVL53: - add x1, x1, :lo12:.LC0 - bl strncmp + bl get_wf_buf .LVL54: - mov w21, w0 - cbz w0, .L30 - .loc 1 97 0 - adrp x0, .LC1 - add x0, x0, :lo12:.LC1 - bl printf +.LBB65: +.LBB66: + .loc 1 269 0 + ldrb w19, [x0] .LVL55: -.LBE52: -.LBE51: - .loc 1 138 0 - adrp x0, .LC2 - add x0, x0, :lo12:.LC2 -.L44: - .loc 1 144 0 - bl printf +.LBE66: +.LBE65: + .loc 1 394 0 + adrp x1, .LANCHOR1 + ldr w1, [x1, #:lo12:.LANCHOR1] .LVL56: - .loc 1 145 0 - mov w21, -1 - b .L28 + lsl w2, w19, 1 + mul w1, w1, w1 .LVL57: -.L36: -.LBB53: -.LBB54: -.LBB55: -.LBB56: - .loc 1 87 0 - ldrb w0, [x19, x1] - add x1, x1, 1 + mul w1, w1, w2 + .loc 1 395 0 + lsr w1, w1, 3 + bl decode_wf_data .LVL58: - eor w0, w0, w2, lsr 24 - ldr w0, [x20, x0, lsl 2] - eor w2, w0, w2, lsl 8 -.LVL59: - b .L35 -.LVL60: -.L40: -.LBE56: -.LBE55: -.LBE54: -.LBE53: - .loc 1 134 0 - mov w21, -16 -.LVL61: -.L28: - .loc 1 153 0 - mov w0, w21 - ldr x25, [sp, 64] + str x0, [x20] + .loc 1 399 0 + cmp x0, 0 + .loc 1 400 0 + mov w0, -22 + csel w0, w19, w0, ne ldp x19, x20, [sp, 16] - ldp x21, x22, [sp, 32] - ldp x23, x24, [sp, 48] - ldp x29, x30, [sp], 80 - .cfi_remember_state +.LVL59: + ldp x29, x30, [sp], 32 .cfi_restore 30 .cfi_restore 29 - .cfi_restore 25 - .cfi_restore 23 - .cfi_restore 24 - .cfi_restore 21 - .cfi_restore 22 .cfi_restore 19 .cfi_restore 20 .cfi_def_cfa 31, 0 ret + .cfi_endproc +.LFE243: + .size parse_wf_gray16.isra.3, .-parse_wf_gray16.isra.3 + .section .text.parse_wf_data,"ax",@progbits + .align 2 + .type parse_wf_data, %function +parse_wf_data: +.LFB232: + .loc 1 530 0 + .cfi_startproc +.LVL60: + stp x29, x30, [sp, -48]! + .cfi_def_cfa_offset 48 + .cfi_offset 29, -48 + .cfi_offset 30, -40 + .loc 1 534 0 + cmp w1, 7 + .loc 1 530 0 + add x29, sp, 0 + .cfi_def_cfa_register 29 + stp x19, x20, [sp, 16] + stp x21, x22, [sp, 32] + .cfi_offset 19, -32 + .cfi_offset 20, -24 + .cfi_offset 21, -16 + .cfi_offset 22, -8 + .loc 1 534 0 + bhi .L46 + mov x20, x0 + mov w0, w2 +.LVL61: + adrp x2, .L38 .LVL62: -.L30: - .cfi_restore_state -.LBB70: -.LBB69: - .loc 1 107 0 - ldr w24, [x19] - cmp w24, 262144 - bgt .L38 -.LBB67: -.LBB65: - .loc 1 84 0 - adrp x20, .LANCHOR1 - add x23, x20, :lo12:.LANCHOR1 -.LBE65: -.LBE67: - .loc 1 110 0 - ldr w25, [x19, w24, sxtw] + add x2, x2, :lo12:.L38 + ldrb w1, [x2,w1,uxtw] + adr x2, .Lrtx38 + add x1, x2, w1, sxtb #2 + br x1 +.Lrtx38: .LVL63: -.LBB68: -.LBB66: - .loc 1 84 0 - mov x2, 1024 + .section .rodata.parse_wf_data,"a",@progbits + .align 0 + .align 2 +.L38: + .byte (.L37 - .Lrtx38) / 4 + .byte (.L39 - .Lrtx38) / 4 + .byte (.L40 - .Lrtx38) / 4 + .byte (.L40 - .Lrtx38) / 4 + .byte (.L42 - .Lrtx38) / 4 + .byte (.L43 - .Lrtx38) / 4 + .byte (.L44 - .Lrtx38) / 4 + .byte (.L45 - .Lrtx38) / 4 + .section .text.parse_wf_data +.L37: +.LBB88: +.LBB89: + .loc 1 361 0 mov w1, 0 - mov x0, x23 - bl memset + bl get_wf_buf .LVL64: -.LBB57: -.LBB58: - .loc 1 70 0 - mov w4, 3511 -.LBE58: -.LBE57: - .loc 1 84 0 - mov x3, 0 -.LBB62: -.LBB59: - .loc 1 70 0 - movk w4, 0x4c1, lsl 16 +.LBB90: +.LBB91: + .loc 1 269 0 + ldrb w19, [x0] .LVL65: -.L34: - lsl w0, w3, 22 +.LBE91: +.LBE90: + .loc 1 365 0 + add w21, w19, 15 + lsr w21, w21, 4 .LVL66: -.LBE59: -.LBE62: - .loc 1 84 0 - mov w2, 8 -.LBB63: -.LBB60: - .loc 1 67 0 - mov w1, 0 + .loc 1 366 0 + lsl w1, w21, 2 .LVL67: -.L33: - .loc 1 69 0 - eor w6, w0, w1 - lsl w1, w1, 1 + bl decode_wf_data .LVL68: - .loc 1 70 0 - mov w5, w1 - cmp w6, 0 - eor w1, w1, w4 - .loc 1 73 0 - lsl w0, w0, 1 + mov x22, x0 + .loc 1 367 0 + cbz x0, .L46 .LVL69: - .loc 1 70 0 - csel w1, w1, w5, lt +.LBB92: +.LBB93: +.LBB94: +.LBB95: + .loc 2 58 0 + mov w1, 32768 + ubfiz x0, x21, 10, 5 .LVL70: - .loc 1 68 0 - subs w2, w2, #1 + bl kmalloc .LVL71: - bne .L33 - .loc 1 75 0 - str w1, [x3, x23] - add x3, x3, 4 - .loc 1 65 0 - cmp x3, 1024 - bne .L34 -.LBE60: -.LBE63: - .loc 1 87 0 - add x20, x20, :lo12:.LANCHOR1 -.LBB64: -.LBB61: - .loc 1 65 0 - mov x1, 0 +.LBE95: +.LBE94: + .loc 1 298 0 + cbz x0, .L57 + mov x2, 0 .LVL72: -.L35: -.LBE61: -.LBE64: - .loc 1 86 0 - cmp w24, w1 - bhi .L36 +.L48: + .loc 1 301 0 + cmp w21, w2 + bgt .L52 .LVL73: -.LBE66: -.LBE68: - .loc 1 113 0 - cmp w25, w2 - beq .L37 - .loc 1 114 0 - adrp x0, .LC3 - mov w1, w25 - add x0, x0, :lo12:.LC3 - bl printf +.L47: +.LBE93: +.LBE92: + .loc 1 373 0 + str x0, [x20, 8] + .loc 1 374 0 + cbnz x0, .L53 .LVL74: -.L38: -.LBE69: -.LBE70: - .loc 1 144 0 - adrp x0, .LC4 - add x0, x0, :lo12:.LC4 - b .L44 +.LBB98: +.LBB99: + .loc 2 81 0 + mov x0, x22 + bl free .LVL75: -.L37: - .loc 1 148 0 - add x1, x19, 20 - adrp x0, .LC5 - add x0, x0, :lo12:.LC5 - bl printf +.L46: +.LBE99: +.LBE98: +.LBE89: +.LBE88: + .loc 1 538 0 + mov w19, -1 + b .L35 .LVL76: - .loc 1 150 0 - str x19, [x22, #:lo12:.LANCHOR0] - .loc 1 152 0 - b .L28 - .cfi_endproc -.LFE216: - .size rkf_wf_input, .-rkf_wf_input - .section .text.rkf_wf_get_version,"ax",@progbits - .align 2 - .global rkf_wf_get_version - .type rkf_wf_get_version, %function -rkf_wf_get_version: -.LFB217: - .loc 1 163 0 - .cfi_startproc - .loc 1 164 0 - adrp x0, .LANCHOR0 - ldr x1, [x0, #:lo12:.LANCHOR0] - .loc 1 167 0 - add x0, x1, 84 - cmp x1, 0 - .loc 1 168 0 - csel x0, x0, xzr, ne - ret - .cfi_endproc -.LFE217: - .size rkf_wf_get_version, .-rkf_wf_get_version - .section .text.rkf_wf_get_lut,"ax",@progbits - .align 2 - .global rkf_wf_get_lut - .type rkf_wf_get_lut, %function -rkf_wf_get_lut: -.LFB229: - .loc 1 462 0 - .cfi_startproc +.L52: +.LBB104: +.LBB103: +.LBB100: +.LBB97: + .loc 1 302 0 + ldr w6, [x22, x2, lsl 2] .LVL77: - .loc 1 467 0 - adrp x3, .LANCHOR0 - ldr x3, [x3, #:lo12:.LANCHOR0] - cbz x3, .L74 - .loc 1 470 0 - cbz x0, .L75 - .loc 1 462 0 - stp x29, x30, [sp, -48]! - .cfi_def_cfa_offset 48 - .cfi_offset 29, -48 - .cfi_offset 30, -40 - add x29, sp, 0 - .cfi_def_cfa_register 29 - stp x19, x20, [sp, 16] - .cfi_offset 19, -32 - .cfi_offset 20, -24 - .loc 1 474 0 - adrp x20, .LANCHOR2 - .loc 1 462 0 - stp x21, x22, [sp, 32] - .cfi_offset 21, -16 - .cfi_offset 22, -8 - .loc 1 474 0 - ldr w3, [x20, #:lo12:.LANCHOR2] - cmp w3, w2 - adrp x3, .LANCHOR3 - bne .L50 - .loc 1 474 0 is_stmt 0 discriminator 1 - ldr w4, [x3, #:lo12:.LANCHOR3] - cmp w4, w1 - beq .L76 -.L50: - mov x19, x0 - .loc 1 481 0 is_stmt 1 - ldr x0, [x0, 8] + lsl x7, x2, 8 + mov x3, 0 .LVL78: - .loc 1 477 0 - str w2, [x20, #:lo12:.LANCHOR2] - mov w21, w1 - .loc 1 478 0 - str w1, [x3, #:lo12:.LANCHOR3] - .loc 1 481 0 - cbz x0, .L51 -.LVL79: -.LBB104: -.LBB105: - .loc 2 81 0 - bl free -.LVL80: -.LBE105: -.LBE104: - .loc 1 483 0 - str xzr, [x19, 8] .L51: - .loc 1 486 0 - cmp w21, 2 - beq .L56 - .loc 1 489 0 - cmp w21, 11 - beq .L53 - .loc 1 493 0 - sub w21, w21, #1 -.LVL81: - cmp w21, 9 - bhi .L70 - adrp x0, .L55 - add x0, x0, :lo12:.L55 - ldrb w0, [x0,w21,uxtw] - adr x1, .Lrtx55 - add x0, x1, w0, sxtb #2 - br x0 -.Lrtx55: - .section .rodata.rkf_wf_get_lut,"a",@progbits - .align 0 - .align 2 -.L55: - .byte (.L54 - .Lrtx55) / 4 - .byte (.L70 - .Lrtx55) / 4 - .byte (.L56 - .Lrtx55) / 4 - .byte (.L57 - .Lrtx55) / 4 - .byte (.L58 - .Lrtx55) / 4 - .byte (.L59 - .Lrtx55) / 4 - .byte (.L56 - .Lrtx55) / 4 - .byte (.L60 - .Lrtx55) / 4 - .byte (.L53 - .Lrtx55) / 4 - .byte (.L61 - .Lrtx55) / 4 - .section .text.rkf_wf_get_lut -.L54: -.LVL82: -.LBB106: -.LBB107: - .loc 1 325 0 - ldr w0, [x20, #:lo12:.LANCHOR2] - mov w1, 0 - bl get_wf_buf -.LVL83: - .loc 1 326 0 - ldrb w22, [x0] -.LVL84: - .loc 1 329 0 - add w20, w22, 15 - lsr w20, w20, 4 -.LVL85: - .loc 1 330 0 - lsl w1, w20, 2 -.LVL86: - bl decode_wf_data -.LVL87: - mov x21, x0 -.LVL88: - .loc 1 331 0 - cbz x0, .L70 - .loc 1 335 0 - str w22, [x19] -.LVL89: -.LBB108: -.LBB109: -.LBB110: -.LBB111: - .loc 2 58 0 - mov w1, 32768 - ubfiz x0, x20, 10, 5 -.LVL90: - bl kmalloc -.LVL91: -.LBE111: -.LBE110: - .loc 1 272 0 - cbz x0, .L78 - mov x2, 0 -.LVL92: -.L64: - .loc 1 275 0 - cmp w20, w2 - bgt .L68 -.LVL93: -.L63: -.LBE109: -.LBE108: - .loc 1 338 0 - str x0, [x19, 8] - .loc 1 339 0 - cbnz x0, .L69 -.LVL94: -.LBB114: -.LBB115: - .loc 2 81 0 - mov x0, x21 - bl free -.LVL95: -.L70: -.LBE115: -.LBE114: -.LBE107: -.LBE106: - .loc 1 539 0 - mov w0, -1 - b .L48 -.LVL96: -.L68: -.LBB120: -.LBB119: -.LBB116: -.LBB113: - .loc 1 276 0 - ldr w7, [x21, x2, lsl 2] -.LVL97: - lsl x6, x2, 8 - mov x3, 0 -.LVL98: -.L67: -.LBB112: - .loc 1 278 0 +.LBB96: + .loc 1 304 0 lsl w1, w3, 1 mov w4, 0 - asr w1, w7, w1 + asr w1, w6, w1 and w1, w1, 3 -.LVL99: - .loc 1 279 0 +.LVL79: + .loc 1 305 0 mov w5, w1 -.LVL100: -.L65: - .loc 1 282 0 +.LVL80: +.L49: + .loc 1 308 0 lsl w8, w1, w4 add w4, w4, 2 orr w5, w5, w8 -.LVL101: - .loc 1 281 0 +.LVL81: + .loc 1 307 0 cmp w4, 32 - bne .L65 - add x4, x6, x3, lsl 4 + bne .L49 + add x4, x7, x3, lsl 4 mov x1, 0 -.LVL102: +.LVL82: add x4, x0, x4, lsl 2 -.LVL103: -.L66: - .loc 1 285 0 +.LVL83: +.L50: + .loc 1 311 0 str w5, [x4, x1, lsl 2] -.LVL104: +.LVL84: add x1, x1, 1 -.LVL105: - .loc 1 284 0 +.LVL85: + .loc 1 310 0 cmp x1, 16 - bne .L66 -.LVL106: + bne .L50 +.LVL86: add x3, x3, 1 -.LVL107: -.LBE112: - .loc 1 277 0 +.LVL87: +.LBE96: + .loc 1 303 0 cmp x3, 16 - bne .L67 -.LVL108: + bne .L51 +.LVL88: add x2, x2, 1 -.LVL109: - b .L64 -.LVL110: -.L78: - .loc 1 273 0 +.LVL89: + b .L48 +.LVL90: +.L57: + .loc 1 299 0 mov x0, 0 - b .L63 -.LVL111: -.L69: -.LBE113: -.LBE116: -.LBB117: -.LBB118: + b .L47 +.LVL91: +.L53: +.LBE97: +.LBE100: +.LBB101: +.LBB102: .loc 2 81 0 - mov x0, x21 -.LVL112: -.L107: -.LBE118: -.LBE117: -.LBE119: -.LBE120: -.LBB121: -.LBB122: -.LBB123: -.LBB124: + mov x0, x22 bl free -.LVL113: - b .L76 -.L60: -.LBE124: -.LBE123: -.LBE122: -.LBE121: - .loc 1 507 0 - mov w2, 3 -.LVL114: -.L106: - ldr w1, [x20, #:lo12:.LANCHOR2] - mov x0, x19 - bl parse_wf_gray16 -.LVL115: - .loc 1 508 0 - cmp w0, 0 - csetm w0, ne -.LVL116: -.L48: - .loc 1 553 0 +.LVL92: +.L35: +.LBE102: +.LBE101: +.LBE103: +.LBE104: + .loc 1 594 0 + mov w0, w19 ldp x19, x20, [sp, 16] ldp x21, x22, [sp, 32] ldp x29, x30, [sp], 48 @@ -844,201 +606,907 @@ rkf_wf_get_lut: .cfi_restore 20 .cfi_def_cfa 31, 0 ret -.LVL117: -.L53: +.LVL93: +.L42: .cfi_restore_state - .loc 1 513 0 + .loc 1 548 0 + mov w2, 3 +.L69: + mov w1, w0 + add x0, x20, 8 +.LVL94: + bl parse_wf_gray16.isra.3 +.LVL95: + cmp w0, 0 + csinv w19, w0, wzr, ge + b .L35 +.LVL96: +.L43: + .loc 1 554 0 mov w2, 4 - b .L106 -.LVL118: -.L61: - .loc 1 519 0 + b .L69 +.L44: + .loc 1 560 0 mov w2, 5 - b .L106 -.LVL119: -.L56: - .loc 1 525 0 + b .L69 +.L40: + .loc 1 566 0 mov w2, 2 - b .L106 -.LVL120: -.L57: -.LBB130: -.LBB131: - .loc 1 376 0 - ldr w0, [x20, #:lo12:.LANCHOR2] + b .L69 +.L39: +.LVL97: +.LBB105: +.LBB106: + .loc 1 409 0 mov w1, 1 +.LVL98: +.L68: bl get_wf_buf -.LVL121: - .loc 1 377 0 - ldrb w20, [x0] -.LVL122: - .loc 1 381 0 - lsl w1, w20, 6 -.LVL123: +.LVL99: +.LBB107: +.LBB108: + .loc 1 269 0 + ldrb w19, [x0] +.LVL100: +.LBE108: +.LBE107: + .loc 1 413 0 + adrp x1, .LANCHOR1 + ldr w1, [x1, #:lo12:.LANCHOR1] +.LVL101: + lsl w2, w19, 1 + mul w1, w1, w1 +.LVL102: + mul w1, w2, w1 + .loc 1 414 0 + lsr w1, w1, 3 bl decode_wf_data +.LVL103: + str x0, [x20, 8] + .loc 1 415 0 + cbnz x0, .L35 + b .L46 +.LVL104: +.L45: +.LBE106: +.LBE105: +.LBB109: +.LBB110: + .loc 1 467 0 + mov w1, 6 + b .L68 +.LBE110: +.LBE109: + .cfi_endproc +.LFE232: + .size parse_wf_data, .-parse_wf_data + .section .text.rkf_wf_input,"ax",@progbits + .align 2 + .global rkf_wf_input + .type rkf_wf_input, %function +rkf_wf_input: +.LFB219: + .loc 1 156 0 + .cfi_startproc +.LVL105: + stp x29, x30, [sp, -80]! + .cfi_def_cfa_offset 80 + .cfi_offset 29, -80 + .cfi_offset 30, -72 + add x29, sp, 0 + .cfi_def_cfa_register 29 + stp x21, x22, [sp, 32] + .cfi_offset 21, -48 + .cfi_offset 22, -40 + .loc 1 160 0 + adrp x22, .LANCHOR0 + .loc 1 156 0 + stp x19, x20, [sp, 16] + .loc 1 160 0 + ldr x1, [x22, #:lo12:.LANCHOR0] + .loc 1 156 0 + stp x23, x24, [sp, 48] + str x25, [sp, 64] + .cfi_offset 19, -64 + .cfi_offset 20, -56 + .cfi_offset 23, -32 + .cfi_offset 24, -24 + .cfi_offset 25, -16 + .loc 1 160 0 + cbnz x1, .L85 +.LBB121: +.LBB122: + .loc 1 107 0 + adrp x20, .LC0 + add x20, x20, :lo12:.LC0 + add x21, x0, 20 + mov x19, x0 +.LVL106: + mov x0, x20 +.LVL107: + bl strlen +.LVL108: + mov x1, x20 + mov x2, x0 + mov x0, x21 + bl strncmp +.LVL109: + cbnz w0, .L72 + .loc 1 108 0 + mov w1, 16 +.L89: + .loc 1 110 0 + adrp x0, .LANCHOR1 + str w1, [x0, #:lo12:.LANCHOR1] + .loc 1 114 0 + adrp x0, .LANCHOR1 + mov x1, x21 + ldr w2, [x0, #:lo12:.LANCHOR1] + adrp x0, .LC2 + add x0, x0, :lo12:.LC2 + bl printf +.LVL110: +.LBE122: +.LBE121: +.LBB124: +.LBB125: + .loc 1 121 0 + mov x2, 12 + adrp x1, .LC3 + add x0, x19, 4 +.LVL111: + add x1, x1, :lo12:.LC3 + bl strncmp +.LVL112: + mov w20, w0 + cbz w0, .L75 + .loc 1 124 0 + adrp x0, .LC4 + add x0, x0, :lo12:.LC4 + bl printf +.LVL113: +.LBE125: +.LBE124: + .loc 1 171 0 + adrp x0, .LC5 + add x0, x0, :lo12:.LC5 +.L90: + .loc 1 165 0 + bl printf +.LVL114: + .loc 1 166 0 + mov w20, -1 + b .L70 +.LVL115: +.L72: +.LBB126: +.LBB123: + .loc 1 109 0 + adrp x20, .LC1 + add x20, x20, :lo12:.LC1 + mov x0, x20 + bl strlen +.LVL116: + mov x1, x20 + mov x2, x0 + mov x0, x21 + bl strncmp +.LVL117: + cbnz w0, .L74 + .loc 1 110 0 + mov w1, 32 + b .L89 +.LVL118: +.L81: +.LBE123: +.LBE126: +.LBB127: +.LBB128: +.LBB129: +.LBB130: + .loc 1 100 0 + ldrb w0, [x19, x1] + add x1, x1, 1 +.LVL119: + eor w0, w0, w2, lsr 24 + ldr w0, [x21, x0, lsl 2] + eor w2, w0, w2, lsl 8 +.LVL120: + b .L80 +.LVL121: +.L85: +.LBE130: +.LBE129: +.LBE128: +.LBE127: + .loc 1 161 0 + mov w20, -16 +.LVL122: +.L70: + .loc 1 184 0 + mov w0, w20 + ldr x25, [sp, 64] + ldp x19, x20, [sp, 16] + ldp x21, x22, [sp, 32] + ldp x23, x24, [sp, 48] + ldp x29, x30, [sp], 80 + .cfi_remember_state + .cfi_restore 30 + .cfi_restore 29 + .cfi_restore 25 + .cfi_restore 23 + .cfi_restore 24 + .cfi_restore 21 + .cfi_restore 22 + .cfi_restore 19 + .cfi_restore 20 + .cfi_def_cfa 31, 0 + ret +.LVL123: +.L74: + .cfi_restore_state + .loc 1 165 0 + adrp x0, .LC7 + add x0, x0, :lo12:.LC7 + b .L90 .LVL124: - str x0, [x19, 8] - .loc 1 382 0 - cbz x0, .L70 - .loc 1 385 0 - str w20, [x19] +.L75: +.LBB144: +.LBB143: + .loc 1 134 0 + ldr w24, [x19] + cmp w24, 1048576 + bgt .L83 +.LBB141: +.LBB139: + .loc 1 97 0 + adrp x21, .LANCHOR2 + add x23, x21, :lo12:.LANCHOR2 +.LBE139: +.LBE141: + .loc 1 137 0 + ldr w25, [x19, w24, sxtw] .LVL125: -.L76: -.LBE131: -.LBE130: - .loc 1 475 0 - mov w0, 0 - b .L48 +.LBB142: +.LBB140: + .loc 1 97 0 + mov x2, 1024 + mov w1, 0 + mov x0, x23 + bl memset .LVL126: -.L58: - .loc 1 537 0 - ldr w20, [x20, #:lo12:.LANCHOR2] -.LVL127: +.LBB131: .LBB132: -.LBB129: - .loc 1 398 0 - mov w1, 2 - mov w0, w20 - bl get_wf_buf + .loc 1 83 0 + mov w4, 3511 +.LBE132: +.LBE131: + .loc 1 97 0 + mov x3, 0 +.LBB136: +.LBB133: + .loc 1 83 0 + movk w4, 0x4c1, lsl 16 +.LVL127: +.L79: + lsl w0, w3, 22 .LVL128: - .loc 1 399 0 - ldrb w1, [x0] +.LBE133: +.LBE136: + .loc 1 97 0 + mov w2, 8 +.LBB137: +.LBB134: + .loc 1 80 0 + mov w1, 0 .LVL129: - .loc 1 401 0 - str w1, [x19] +.L78: + .loc 1 82 0 + eor w6, w0, w1 + lsl w1, w1, 1 .LVL130: - .loc 1 405 0 - lsl w1, w1, 6 + .loc 1 83 0 + mov w5, w1 + cmp w6, 0 + eor w1, w1, w4 + .loc 1 86 0 + lsl w0, w0, 1 .LVL131: - bl decode_wf_data + .loc 1 83 0 + csel w1, w1, w5, lt .LVL132: - str x0, [x19, 8] - .loc 1 406 0 - cbz x0, .L70 - .loc 1 411 0 - mov w1, 1 - mov w0, w20 - bl get_wf_buf + .loc 1 81 0 + subs w2, w2, #1 .LVL133: -.LBB125: -.LBB126: - .loc 1 243 0 - ldrb w20, [x0] + bne .L78 + .loc 1 88 0 + str w1, [x3, x23] + add x3, x3, 4 + .loc 1 78 0 + cmp x3, 1024 + bne .L79 +.LBE134: +.LBE137: + .loc 1 100 0 + add x21, x21, :lo12:.LANCHOR2 +.LBB138: +.LBB135: + .loc 1 78 0 + mov x1, 0 .LVL134: -.LBE126: -.LBE125: - .loc 1 414 0 - ldr w1, [x19] - orr w1, w1, w20, lsl 8 - str w1, [x19] +.L80: +.LBE135: +.LBE138: + .loc 1 99 0 + cmp w24, w1 + bhi .L81 .LVL135: - .loc 1 419 0 - lsl w1, w20, 6 +.LBE140: +.LBE142: + .loc 1 140 0 + cmp w25, w2 + beq .L82 + .loc 1 141 0 + adrp x0, .LC6 + mov w1, w25 + add x0, x0, :lo12:.LC6 + bl printf .LVL136: - bl decode_wf_data +.L83: +.LBE143: +.LBE144: + .loc 1 177 0 + adrp x0, .LC8 + add x0, x0, :lo12:.LC8 + b .L90 .LVL137: - .loc 1 420 0 - cbz x0, .L70 - ldr x7, [x19, 8] +.L82: + .loc 1 181 0 + str x19, [x22, #:lo12:.LANCHOR0] + .loc 1 183 0 + b .L70 + .cfi_endproc +.LFE219: + .size rkf_wf_input, .-rkf_wf_input + .section .text.rkf_wf_get_version,"ax",@progbits + .align 2 + .global rkf_wf_get_version + .type rkf_wf_get_version, %function +rkf_wf_get_version: +.LFB220: + .loc 1 193 0 + .cfi_startproc + .loc 1 194 0 + adrp x0, .LANCHOR0 + ldr x1, [x0, #:lo12:.LANCHOR0] + .loc 1 197 0 + add x0, x1, 84 + cmp x1, 0 + .loc 1 198 0 + csel x0, x0, xzr, ne + ret + .cfi_endproc +.LFE220: + .size rkf_wf_get_version, .-rkf_wf_get_version + .section .text.rkf_wf_get_lut,"ax",@progbits + .align 2 + .global rkf_wf_get_lut + .type rkf_wf_get_lut, %function +rkf_wf_get_lut: +.LFB239: + .loc 1 765 0 + .cfi_startproc .LVL138: - ubfiz x20, x20, 6, 8 + stp x29, x30, [sp, -80]! + .cfi_def_cfa_offset 80 + .cfi_offset 29, -80 + .cfi_offset 30, -72 + add x29, sp, 0 + .cfi_def_cfa_register 29 + stp x19, x20, [sp, 16] + .cfi_offset 19, -64 + .cfi_offset 20, -56 + mov x20, x0 + .loc 1 771 0 + adrp x0, .LANCHOR0 .LVL139: - mov x2, 0 + .loc 1 765 0 + stp x21, x22, [sp, 32] + stp x23, x24, [sp, 48] + .loc 1 771 0 + ldr x0, [x0, #:lo12:.LANCHOR0] + .loc 1 765 0 + str x25, [sp, 64] + .cfi_offset 21, -48 + .cfi_offset 22, -40 + .cfi_offset 23, -32 + .cfi_offset 24, -24 + .cfi_offset 25, -16 + .loc 1 771 0 + cbz x0, .L121 + .loc 1 774 0 + cbz x20, .L122 + .loc 1 777 0 + adrp x23, .LANCHOR3 + mov w21, w2 + .loc 1 779 0 + cmp w1, 8 + .loc 1 777 0 + str w3, [x23, #:lo12:.LANCHOR3] + .loc 1 779 0 + beq .L123 + .loc 1 781 0 + cmp w1, 12 + beq .L124 + .loc 1 783 0 + cmp w1, 11 + beq .L125 + .loc 1 785 0 + cmp w1, 13 + beq .L126 + .loc 1 780 0 + cmp w1, 14 + mov w0, 3 + csel w19, w1, w0, ne +.L96: .LVL140: -.L71: - add x5, x7, x2 - add x6, x0, x2 + .loc 1 793 0 + adrp x0, .LANCHOR4 + mov w1, 5 + sdiv w2, w21, w1 .LVL141: -.LBB127: -.LBB128: - .loc 1 303 0 - cmp x2, x20 - beq .L107 - mov x1, 0 + ldr w0, [x0, #:lo12:.LANCHOR4] + sdiv w0, w0, w1 + cmp w2, w0 + bne .L97 + .loc 1 793 0 is_stmt 0 discriminator 1 + adrp x0, .LANCHOR5 + ldr w0, [x0, #:lo12:.LANCHOR5] + cmp w19, w0 + beq .L128 +.L97: + .loc 1 797 0 is_stmt 1 + cmp w19, 10 + beq .L128 + .loc 1 799 0 + ldr x0, [x20, 8] + cbz x0, .L98 .LVL142: -.L72: - .loc 1 305 0 - ldr w3, [x6, x1] +.LBB172: +.LBB173: + .loc 2 81 0 + bl free .LVL143: - .loc 1 307 0 - ldr w4, [x5, x1] +.LBE173: +.LBE172: + .loc 1 801 0 + str xzr, [x20, 8] +.L98: + .loc 1 804 0 + mov w2, w21 + mov w1, w19 + mov x0, x20 + bl parse_wf_data .LVL144: - .loc 1 306 0 - and w3, w3, -1073741821 + mov w22, w0 .LVL145: - .loc 1 308 0 - and w4, w4, 1073741820 + .loc 1 805 0 + tbz w0, #31, .L99 + .loc 1 806 0 + adrp x0, .LC9 .LVL146: - .loc 1 310 0 - orr w3, w3, w4 + add x0, x0, :lo12:.LC9 + bl printf .LVL147: - str w3, [x5, x1] + .loc 1 807 0 + mov w0, -5 .LVL148: - add x1, x1, 4 +.L94: + .loc 1 866 0 + ldp x19, x20, [sp, 16] .LVL149: - .loc 1 304 0 - cmp x1, 64 - bne .L72 - add x2, x2, 64 - b .L71 + ldp x21, x22, [sp, 32] + ldp x23, x24, [sp, 48] + ldr x25, [sp, 64] + ldp x29, x30, [sp], 80 + .cfi_remember_state + .cfi_restore 30 + .cfi_restore 29 + .cfi_restore 25 + .cfi_restore 23 + .cfi_restore 24 + .cfi_restore 21 + .cfi_restore 22 + .cfi_restore 19 + .cfi_restore 20 + .cfi_def_cfa 31, 0 + ret .LVL150: -.L59: -.LBE128: -.LBE127: -.LBE129: -.LBE132: -.LBB133: -.LBB134: - .loc 1 437 0 - ldr w0, [x20, #:lo12:.LANCHOR2] - mov w1, 6 - bl get_wf_buf +.L123: + .cfi_restore_state + .loc 1 780 0 + mov w19, 3 + b .L96 +.L124: + .loc 1 782 0 + mov w19, 6 + b .L96 +.L125: + .loc 1 784 0 + mov w19, 5 + b .L96 +.L126: + .loc 1 786 0 + mov w19, 4 + b .L96 .LVL151: - .loc 1 438 0 - ldrb w1, [x0] +.L99: + .loc 1 809 0 + cbnz w19, .L100 + .loc 1 810 0 + ldr x1, [x20, 16] + mov w2, w0 + add x0, x20, 8 .LVL152: - .loc 1 440 0 - str w1, [x19] + bl rkf_lut_init_wf_table.isra.1 .LVL153: - .loc 1 444 0 - lsl w1, w1, 6 +.L101: + .loc 1 826 0 + ldr x0, [x20, 8] + cbz x0, .L113 .LVL154: - bl decode_wf_data +.LBB174: +.LBB175: + .loc 2 81 0 + bl free .LVL155: - .loc 1 445 0 - cmp x0, 0 - .loc 1 444 0 - str x0, [x19, 8] - .loc 1 445 0 - csetm w0, eq - b .L48 +.LBE175: +.LBE174: + .loc 1 828 0 + str xzr, [x20, 8] +.L113: + .loc 1 830 0 + add w21, w22, 15 .LVL156: -.L74: - .cfi_def_cfa 31, 0 - .cfi_restore 19 - .cfi_restore 20 - .cfi_restore 21 - .cfi_restore 22 - .cfi_restore 29 - .cfi_restore 30 -.LBE134: -.LBE133: - .loc 1 468 0 - mov w0, -19 +.LBB176: +.LBB177: + .loc 2 58 0 + mov w1, 32768 +.LBE177: +.LBE176: + .loc 1 830 0 + asr w21, w21, 4 + lsl w21, w21, 10 + sxtw x21, w21 .LVL157: - ret +.LBB180: +.LBB178: + .loc 2 58 0 + mov x0, x21 + bl kmalloc .LVL158: -.L75: - .loc 1 471 0 - mov w0, -22 +.LBE178: +.LBE180: + .loc 1 830 0 + str x0, [x20, 8] +.LBB181: +.LBB179: + .loc 2 58 0 + mov x24, x0 .LVL159: - ret +.LBE179: +.LBE181: + .loc 1 831 0 + cbnz x0, .L114 + .loc 1 832 0 + adrp x0, .LC10 + add x0, x0, :lo12:.LC10 + bl printf +.LVL160: + .loc 1 833 0 + mov w0, -12 + b .L94 +.LVL161: +.L100: +.LBB182: +.LBB183: +.LBB184: + .loc 1 486 0 + adrp x0, .LANCHOR1 +.LVL162: + mov w5, 16 +.LBE184: +.LBE183: +.LBE182: + .loc 1 812 0 + ldr x7, [x20, 16] +.LVL163: +.LBB192: +.LBB191: +.LBB188: + .loc 1 486 0 + mov x8, 0 + ldr w0, [x0, #:lo12:.LANCHOR1] +.LBE188: + .loc 1 485 0 + mov w1, 0 +.LBB189: + .loc 1 486 0 + sdiv w5, w0, w5 + mul w12, w0, w5 +.L102: +.LVL164: +.LBE189: + .loc 1 485 0 + cmp w22, w1 + bne .L106 + .loc 1 496 0 + cmp w0, 32 + bne .L101 + ldr w0, [x23, #:lo12:.LANCHOR3] + cmp w0, 16 + bne .L101 + mov w3, 0 +.LVL165: +.L109: + .loc 1 498 0 + cmp w1, w3 + beq .L101 + lsl w5, w3, 10 + mov w0, 0 + b .L112 +.LVL166: +.L106: +.LBB190: + .loc 1 486 0 + ldr x16, [x20, 8] +.LVL167: + lsl w14, w1, 10 + mov w10, 0 + .loc 1 487 0 + mov w6, 0 +.LVL168: +.L103: + cmp w6, w0 + beq .L105 +.LBB185: + .loc 1 489 0 + uxtw x15, w10 + add w13, w14, w6, lsl 5 + mov w2, 0 +.L104: +.LVL169: + lsl w11, w2, 1 +.LVL170: + .loc 1 491 0 + add w17, w13, w2 + .loc 1 490 0 + lsr w4, w11, 5 +.LBE185: + .loc 1 488 0 + add w2, w2, 1 +.LVL171: +.LBB186: + .loc 1 490 0 + add x4, x4, x15 +.LVL172: +.LBE186: + .loc 1 488 0 + cmp w2, w0 +.LBB187: + .loc 1 490 0 + add x4, x16, x4, lsl 2 +.LVL173: + ldr w3, [x4, x8] + lsr w3, w3, w11 + and w3, w3, 3 + .loc 1 491 0 + strb w3, [x7, x17] +.LVL174: +.LBE187: + .loc 1 488 0 + bne .L104 + .loc 1 487 0 + add w6, w6, 1 +.LVL175: + add w10, w10, w5 +.LVL176: + b .L103 +.LVL177: +.L105: +.LBE190: + .loc 1 485 0 + add w1, w1, 1 +.LVL178: + add x8, x8, x12, sxtw 2 +.LVL179: + b .L102 +.LVL180: +.L110: + .loc 1 501 0 + add w8, w6, w2 + ldrb w10, [x7, x8] +.LVL181: + .loc 1 502 0 + add w8, w4, w2, lsr 1 + .loc 1 500 0 + add w2, w2, 2 +.LVL182: + cmp w2, 32 + .loc 1 502 0 + strb w10, [x7, x8] + .loc 1 500 0 + bne .L110 + .loc 1 499 0 + add w0, w0, 2 +.LVL183: + cmp w0, 32 + beq .L111 +.LVL184: +.L112: + .loc 1 502 0 + lsr w4, w0, 1 + add w6, w5, w0, lsl 5 + add w4, w5, w4, lsl 5 + mov w2, 0 + b .L110 +.LVL185: +.L111: + .loc 1 498 0 + add w3, w3, 1 +.LVL186: + b .L109 +.LVL187: +.L114: +.LBE191: +.LBE192: + .loc 1 835 0 + ldr x25, [x20, 16] +.LVL188: +.LBB193: +.LBB194: + .loc 1 732 0 + ldr w1, [x23, #:lo12:.LANCHOR3] + cmp w1, 16 + cset w23, ne +.LVL189: + .loc 1 734 0 + cbnz x25, .L115 + .loc 1 735 0 + adrp x0, .LC11 +.LVL190: + add x0, x0, :lo12:.LC11 + bl printf +.LVL191: +.L116: +.LBE194: +.LBE193: + .loc 1 838 0 + ldr w0, [x20] + and w0, w0, 65280 + .loc 1 839 0 + orr w22, w0, w22 +.LVL192: + .loc 1 840 0 + adrp x0, .LANCHOR5 + .loc 1 839 0 + str w22, [x20] + .loc 1 840 0 + str w19, [x0, #:lo12:.LANCHOR5] +.LVL193: +.L128: + .loc 1 794 0 + mov w0, 0 + b .L94 +.LVL194: +.L115: +.LBB202: +.LBB201: + .loc 1 739 0 + mov x2, x21 + mov w1, 0 + bl memset +.LVL195: + mov w10, 32 + mov w11, 1 + lsl w10, w10, w23 +.LBB195: + .loc 1 741 0 + mov w2, 0 + lsl w11, w11, w23 +.LBB196: +.LBB197: + .loc 1 745 0 + mov w14, 16 +.LVL196: +.L117: +.LBE197: +.LBE196: + .loc 1 741 0 + cmp w22, w2 + beq .L116 +.LBB200: +.LBB198: + .loc 1 745 0 + lsl w1, w2, 8 + .loc 1 744 0 + lsl w8, w2, 10 + sxtw x8, w8 + .loc 1 745 0 + mov w5, 0 + mov w7, 0 + sdiv w1, w1, w14 + sxtw x1, w1 + b .L120 +.L118: +.LVL197: + .loc 1 744 0 + ldrb w4, [x3, w12, sxtw] + .loc 1 746 0 + and w13, w6, 30 + add w6, w6, 2 + add w12, w12, w11 +.LVL198: + and w4, w4, 3 + .loc 1 743 0 + cmp w6, 32 + .loc 1 746 0 + lsl w4, w4, w13 + ldr w13, [x0] + orr w4, w13, w4 + str w4, [x0] +.LVL199: + .loc 1 743 0 + bne .L118 +.LVL200: + add w5, w5, 16 +.LVL201: + add w7, w7, w10 +.LBE198: + .loc 1 742 0 + cmp w5, 256 + beq .L119 +.LVL202: +.L120: +.LBB199: + .loc 1 745 0 + asr w0, w5, 4 + .loc 1 744 0 + add x3, x8, x7, sxtw + .loc 1 745 0 + add x0, x1, x0, sxtw + mov w6, 0 + add x0, x24, x0, lsl 2 + mov w12, 0 + .loc 1 744 0 + add x3, x25, x3 + b .L118 +.LVL203: +.L119: +.LBE199: +.LBE200: + .loc 1 741 0 + add w2, w2, 1 +.LVL204: + b .L117 +.LVL205: +.L121: +.LBE195: +.LBE201: +.LBE202: + .loc 1 772 0 + mov w0, -19 + b .L94 +.L122: + .loc 1 775 0 + mov w0, -22 + b .L94 .cfi_endproc -.LFE229: +.LFE239: .size rkf_wf_get_lut, .-rkf_wf_get_lut .section .bss.crc32_table,"aw",@nobits .align 3 - .set .LANCHOR1,. + 0 + .set .LANCHOR2,. + 0 .type crc32_table, %object .size crc32_table, 1024 crc32_table: @@ -1050,38 +1518,65 @@ crc32_table: .size global_waveform, 8 global_waveform: .zero 8 - .section .data.sftemp.6194,"aw",@progbits + .section .data.maxpic,"aw",@progbits .align 2 - .set .LANCHOR2,. + 0 - .type sftemp.6194, %object - .size sftemp.6194, 4 -sftemp.6194: - .word -1 - .section .data.stype.6193,"aw",@progbits + .set .LANCHOR1,. + 0 + .type maxpic, %object + .size maxpic, 4 +maxpic: + .word 16 + .section .data.need_pic,"aw",@progbits .align 2 .set .LANCHOR3,. + 0 - .type stype.6193, %object - .size stype.6193, 4 -stype.6193: - .word 13 + .type need_pic, %object + .size need_pic, 4 +need_pic: + .word 16 + .section .data.sftemp.6420,"aw",@progbits + .align 2 + .set .LANCHOR4,. + 0 + .type sftemp.6420, %object + .size sftemp.6420, 4 +sftemp.6420: + .word -1 + .section .data.stype.6419,"aw",@progbits + .align 2 + .set .LANCHOR5,. + 0 + .type stype.6419, %object + .size stype.6419, 4 +stype.6419: + .word 15 + .section .rodata.rkf_wf_get_lut.str1.1,"aMS",@progbits,1 +.LC9: + .string "rkf waveform get frame number failed\n" +.LC10: + .string "kzalloc output->data failed\n" +.LC11: + .string "wf_table or lut_data is NULL\n" .section .rodata.rkf_wf_input.str1.1,"aMS",@progbits,1 .LC0: - .string "rkf waveform" + .string "rkf:v1.0" .LC1: - .string "rkf: check format failed\n" + .string "rkf:v2.0" .LC2: - .string "rkf: failed to check RKF file format\n" + .string "rkf: input waveform version: %s, gray level: %d\n" .LC3: - .string "[EINK]: waveform crc err readcrc = %x crccheck = %x\n" + .string "rkf waveform" .LC4: - .string "rkf: failed to check crc RKF waveform\n" + .string "rkf: check format failed\n" .LC5: - .string "rkf file version: %s\n" + .string "rkf: failed to check RKF file format\n" +.LC6: + .string "[EINK]: waveform crc err readcrc = %x crccheck = %x\n" +.LC7: + .string "rkf: failed to check RKF file version\n" +.LC8: + .string "rkf: failed to check crc RKF waveform\n" .text .Letext0: .file 3 "include/common.h" - .file 4 "./arch/arm/include/asm/types.h" - .file 5 "./arch/arm/include/asm/posix_types.h" + .file 4 "/home/hzb/sdk/u-boot/arch/arm/include/asm/types.h" + .file 5 "/home/hzb/sdk/u-boot/arch/arm/include/asm/posix_types.h" .file 6 "include/linux/types.h" .file 7 "include/errno.h" .file 8 "include/linux/string.h" @@ -1091,29 +1586,27 @@ stype.6193: .file 12 "include/flash.h" .file 13 "include/lmb.h" .file 14 "include/asm-generic/u-boot.h" - .file 15 "./arch/arm/include/asm/u-boot-arm.h" + .file 15 "/home/hzb/sdk/u-boot/arch/arm/include/asm/u-boot-arm.h" .file 16 "include/linux/libfdt_env.h" .file 17 "include/linux/../../scripts/dtc/libfdt/fdt.h" .file 18 "include/linux/libfdt.h" .file 19 "include/image.h" .file 20 "include/net.h" - .file 21 "include/dm/uclass-id.h" - .file 22 "include/malloc.h" - .file 23 "drivers/video/rk_eink/epdlut/epd_lut.h" - .file 24 "include/stdio.h" - .file 25 "include/log.h" + .file 21 "include/malloc.h" + .file 22 "/home/hzb/sdk/ebc-dev/rk_eink/../epdlut/epd_lut.h" + .file 23 "include/stdio.h" .section .debug_info,"",@progbits .Ldebug_info0: - .4byte 0x1d7c + .4byte 0x2095 .2byte 0x4 .4byte .Ldebug_abbrev0 .byte 0x8 .uleb128 0x1 - .4byte .LASF390 + .4byte .LASF314 .byte 0xc - .4byte .LASF391 - .4byte .LASF392 - .4byte .Ldebug_ranges0+0x210 + .4byte .LASF315 + .4byte .LASF316 + .4byte .Ldebug_ranges0+0x430 .8byte 0 .4byte .Ldebug_line0 .uleb128 0x2 @@ -1409,7 +1902,7 @@ stype.6193: .2byte 0x1ff .byte 0 .uleb128 0x17 - .4byte .LASF393 + .4byte .LASF317 .uleb128 0x8 .byte 0x8 .4byte 0x28c @@ -1510,27 +2003,27 @@ stype.6193: .uleb128 0x1c .byte 0x10 .byte 0xe - .byte 0x5d + .byte 0x5b .4byte 0x379 .uleb128 0x10 .4byte .LASF36 .byte 0xe - .byte 0x5e + .byte 0x5c .4byte 0xb3 .byte 0 .uleb128 0x10 .4byte .LASF33 .byte 0xe - .byte 0x5f + .byte 0x5d .4byte 0xb3 .byte 0x8 .byte 0 .uleb128 0x18 .4byte .LASF47 - .2byte 0x150 + .2byte 0x148 .byte 0xe .byte 0x1b - .4byte 0x477 + .4byte 0x46b .uleb128 0x10 .4byte .LASF48 .byte 0xe @@ -1642,60 +2135,54 @@ stype.6193: .uleb128 0x10 .4byte .LASF66 .byte 0xe - .byte 0x5b - .4byte 0x84 + .byte 0x5e + .4byte 0x46b .byte 0x88 - .uleb128 0x10 - .4byte .LASF67 - .byte 0xe - .byte 0x60 - .4byte 0x477 - .byte 0x90 .byte 0 .uleb128 0xa .4byte 0x358 - .4byte 0x487 + .4byte 0x47b .uleb128 0xe .4byte 0xd4 .byte 0xb .byte 0 .uleb128 0x2 - .4byte .LASF68 + .4byte .LASF67 .byte 0xe - .byte 0x62 + .byte 0x60 .4byte 0x379 .uleb128 0x5 - .4byte .LASF69 + .4byte .LASF68 .byte 0xf .byte 0x13 .4byte 0x11b .uleb128 0x5 - .4byte .LASF70 + .4byte .LASF69 .byte 0xf .byte 0x14 .4byte 0x11b .uleb128 0x5 - .4byte .LASF71 + .4byte .LASF70 .byte 0xf .byte 0x15 .4byte 0x11b .uleb128 0x5 - .4byte .LASF72 + .4byte .LASF71 .byte 0xf .byte 0x16 .4byte 0x11b .uleb128 0x5 - .4byte .LASF73 + .4byte .LASF72 .byte 0xf .byte 0x17 .4byte 0x11b .uleb128 0x5 - .4byte .LASF74 + .4byte .LASF73 .byte 0xf .byte 0x18 .4byte 0x11b .uleb128 0x5 - .4byte .LASF75 + .4byte .LASF74 .byte 0xf .byte 0x19 .4byte 0x11b @@ -1706,182 +2193,182 @@ stype.6193: .byte 0x8 .4byte 0x34 .uleb128 0x2 - .4byte .LASF76 + .4byte .LASF75 .byte 0x10 .byte 0x11 .4byte 0x131 .uleb128 0xf - .4byte .LASF77 + .4byte .LASF76 .byte 0x28 .byte 0x11 .byte 0x39 - .4byte 0x57b + .4byte 0x56f .uleb128 0x10 - .4byte .LASF78 + .4byte .LASF77 .byte 0x11 .byte 0x3a - .4byte 0x4eb + .4byte 0x4df .byte 0 .uleb128 0x10 - .4byte .LASF79 + .4byte .LASF78 .byte 0x11 .byte 0x3b - .4byte 0x4eb + .4byte 0x4df .byte 0x4 .uleb128 0x10 - .4byte .LASF80 + .4byte .LASF79 .byte 0x11 .byte 0x3c - .4byte 0x4eb + .4byte 0x4df .byte 0x8 .uleb128 0x10 - .4byte .LASF81 + .4byte .LASF80 .byte 0x11 .byte 0x3d - .4byte 0x4eb + .4byte 0x4df .byte 0xc .uleb128 0x10 - .4byte .LASF82 + .4byte .LASF81 .byte 0x11 .byte 0x3e - .4byte 0x4eb + .4byte 0x4df .byte 0x10 .uleb128 0x10 - .4byte .LASF83 + .4byte .LASF82 .byte 0x11 .byte 0x3f - .4byte 0x4eb + .4byte 0x4df .byte 0x14 .uleb128 0x10 - .4byte .LASF84 + .4byte .LASF83 .byte 0x11 .byte 0x40 - .4byte 0x4eb + .4byte 0x4df .byte 0x18 .uleb128 0x10 - .4byte .LASF85 + .4byte .LASF84 .byte 0x11 .byte 0x43 - .4byte 0x4eb + .4byte 0x4df .byte 0x1c .uleb128 0x10 - .4byte .LASF86 + .4byte .LASF85 .byte 0x11 .byte 0x46 - .4byte 0x4eb + .4byte 0x4df .byte 0x20 .uleb128 0x10 - .4byte .LASF87 + .4byte .LASF86 .byte 0x11 .byte 0x49 - .4byte 0x4eb + .4byte 0x4df .byte 0x24 .byte 0 .uleb128 0xc - .4byte .LASF88 + .4byte .LASF87 .byte 0x12 .2byte 0x136 - .4byte 0x587 + .4byte 0x57b .uleb128 0x8 .byte 0x8 - .4byte 0x4f6 + .4byte 0x4ea .uleb128 0x1d - .4byte .LASF89 + .4byte .LASF88 .byte 0x40 .byte 0x13 .2byte 0x137 - .4byte 0x637 + .4byte 0x62b .uleb128 0x1e - .4byte .LASF90 + .4byte .LASF89 .byte 0x13 .2byte 0x138 .4byte 0x131 .byte 0 .uleb128 0x1e - .4byte .LASF91 + .4byte .LASF90 .byte 0x13 .2byte 0x139 .4byte 0x131 .byte 0x4 .uleb128 0x1e - .4byte .LASF92 + .4byte .LASF91 .byte 0x13 .2byte 0x13a .4byte 0x131 .byte 0x8 .uleb128 0x1e - .4byte .LASF93 + .4byte .LASF92 .byte 0x13 .2byte 0x13b .4byte 0x131 .byte 0xc .uleb128 0x1e - .4byte .LASF94 + .4byte .LASF93 .byte 0x13 .2byte 0x13c .4byte 0x131 .byte 0x10 .uleb128 0x1e - .4byte .LASF95 + .4byte .LASF94 .byte 0x13 .2byte 0x13d .4byte 0x131 .byte 0x14 .uleb128 0x1e - .4byte .LASF96 + .4byte .LASF95 .byte 0x13 .2byte 0x13e .4byte 0x131 .byte 0x18 .uleb128 0x1e - .4byte .LASF97 + .4byte .LASF96 .byte 0x13 .2byte 0x13f .4byte 0x126 .byte 0x1c .uleb128 0x1e - .4byte .LASF98 + .4byte .LASF97 .byte 0x13 .2byte 0x140 .4byte 0x126 .byte 0x1d .uleb128 0x1e - .4byte .LASF99 + .4byte .LASF98 .byte 0x13 .2byte 0x141 .4byte 0x126 .byte 0x1e .uleb128 0x1e - .4byte .LASF100 + .4byte .LASF99 .byte 0x13 .2byte 0x142 .4byte 0x126 .byte 0x1f .uleb128 0x1e - .4byte .LASF101 + .4byte .LASF100 .byte 0x13 .2byte 0x143 - .4byte 0x637 + .4byte 0x62b .byte 0x20 .byte 0 .uleb128 0xa .4byte 0x126 - .4byte 0x647 + .4byte 0x63b .uleb128 0xe .4byte 0xd4 .byte 0x1f .byte 0 .uleb128 0x1f - .4byte .LASF102 + .4byte .LASF101 .byte 0x13 .2byte 0x144 - .4byte 0x58d + .4byte 0x581 .uleb128 0x1d - .4byte .LASF103 + .4byte .LASF102 .byte 0x30 .byte 0x13 .2byte 0x146 - .4byte 0x6d5 + .4byte 0x6c9 .uleb128 0x1e .4byte .LASF36 .byte 0x13 @@ -1895,31 +2382,31 @@ stype.6193: .4byte 0x11b .byte 0x8 .uleb128 0x1e - .4byte .LASF104 + .4byte .LASF103 .byte 0x13 .2byte 0x148 .4byte 0x11b .byte 0x10 .uleb128 0x1e - .4byte .LASF105 + .4byte .LASF104 .byte 0x13 .2byte 0x148 .4byte 0x11b .byte 0x18 .uleb128 0x1e - .4byte .LASF106 + .4byte .LASF105 .byte 0x13 .2byte 0x149 .4byte 0x11b .byte 0x20 .uleb128 0x1e - .4byte .LASF107 + .4byte .LASF106 .byte 0x13 .2byte 0x14a .4byte 0x126 .byte 0x28 .uleb128 0x1e - .4byte .LASF108 + .4byte .LASF107 .byte 0x13 .2byte 0x14a .4byte 0x126 @@ -1931,115 +2418,115 @@ stype.6193: .4byte 0x126 .byte 0x2a .uleb128 0x1e - .4byte .LASF109 + .4byte .LASF108 .byte 0x13 .2byte 0x14b .4byte 0x126 .byte 0x2b .byte 0 .uleb128 0x1f - .4byte .LASF110 + .4byte .LASF109 .byte 0x13 .2byte 0x14c - .4byte 0x653 + .4byte 0x647 .uleb128 0x21 - .4byte .LASF111 + .4byte .LASF110 .2byte 0x380 .byte 0x13 .2byte 0x152 - .4byte 0x87e + .4byte 0x872 .uleb128 0x1e - .4byte .LASF112 + .4byte .LASF111 .byte 0x13 .2byte 0x158 - .4byte 0x87e + .4byte 0x872 .byte 0 .uleb128 0x1e - .4byte .LASF113 + .4byte .LASF112 .byte 0x13 .2byte 0x159 - .4byte 0x647 + .4byte 0x63b .byte 0x8 .uleb128 0x1e - .4byte .LASF114 + .4byte .LASF113 .byte 0x13 .2byte 0x15a .4byte 0x11b .byte 0x48 .uleb128 0x1e - .4byte .LASF115 + .4byte .LASF114 .byte 0x13 .2byte 0x15d .4byte 0xdb .byte 0x50 .uleb128 0x1e - .4byte .LASF116 + .4byte .LASF115 .byte 0x13 .2byte 0x15f .4byte 0x147 .byte 0x58 .uleb128 0x1e - .4byte .LASF117 + .4byte .LASF116 .byte 0x13 .2byte 0x160 .4byte 0xdb .byte 0x60 .uleb128 0x1e - .4byte .LASF118 + .4byte .LASF117 .byte 0x13 .2byte 0x161 .4byte 0x59 .byte 0x68 .uleb128 0x1e - .4byte .LASF119 + .4byte .LASF118 .byte 0x13 .2byte 0x163 .4byte 0x147 .byte 0x70 .uleb128 0x1e - .4byte .LASF120 + .4byte .LASF119 .byte 0x13 .2byte 0x164 .4byte 0xdb .byte 0x78 .uleb128 0x1e - .4byte .LASF121 + .4byte .LASF120 .byte 0x13 .2byte 0x165 .4byte 0x59 .byte 0x80 .uleb128 0x1e - .4byte .LASF122 + .4byte .LASF121 .byte 0x13 .2byte 0x167 .4byte 0x147 .byte 0x88 .uleb128 0x1e - .4byte .LASF123 + .4byte .LASF122 .byte 0x13 .2byte 0x168 .4byte 0xdb .byte 0x90 .uleb128 0x1e - .4byte .LASF124 + .4byte .LASF123 .byte 0x13 .2byte 0x169 .4byte 0x59 .byte 0x98 .uleb128 0x1e - .4byte .LASF125 + .4byte .LASF124 .byte 0x13 .2byte 0x16b .4byte 0x147 .byte 0xa0 .uleb128 0x1e - .4byte .LASF126 + .4byte .LASF125 .byte 0x13 .2byte 0x16c .4byte 0xdb .byte 0xa8 .uleb128 0x1e - .4byte .LASF127 + .4byte .LASF126 .byte 0x13 .2byte 0x16d .4byte 0x59 @@ -2048,7 +2535,7 @@ stype.6193: .string "os" .byte 0x13 .2byte 0x171 - .4byte 0x6d5 + .4byte 0x6c9 .byte 0xb8 .uleb128 0x20 .string "ep" @@ -2057,49 +2544,49 @@ stype.6193: .4byte 0x11b .byte 0xe8 .uleb128 0x1e - .4byte .LASF128 + .4byte .LASF127 .byte 0x13 .2byte 0x174 .4byte 0x11b .byte 0xf0 .uleb128 0x1e - .4byte .LASF129 + .4byte .LASF128 .byte 0x13 .2byte 0x174 .4byte 0x11b .byte 0xf8 .uleb128 0x22 - .4byte .LASF130 + .4byte .LASF129 .byte 0x13 .2byte 0x176 .4byte 0xff .2byte 0x100 .uleb128 0x22 - .4byte .LASF131 + .4byte .LASF130 .byte 0x13 .2byte 0x177 .4byte 0x11b .2byte 0x108 .uleb128 0x22 - .4byte .LASF132 + .4byte .LASF131 .byte 0x13 .2byte 0x179 .4byte 0x11b .2byte 0x110 .uleb128 0x22 - .4byte .LASF133 + .4byte .LASF132 .byte 0x13 .2byte 0x17a .4byte 0x11b .2byte 0x118 .uleb128 0x22 - .4byte .LASF134 + .4byte .LASF133 .byte 0x13 .2byte 0x17b .4byte 0x11b .2byte 0x120 .uleb128 0x22 - .4byte .LASF135 + .4byte .LASF134 .byte 0x13 .2byte 0x17c .4byte 0x11b @@ -2108,16 +2595,16 @@ stype.6193: .string "kbd" .byte 0x13 .2byte 0x17d - .4byte 0x884 + .4byte 0x878 .2byte 0x130 .uleb128 0x22 - .4byte .LASF136 + .4byte .LASF135 .byte 0x13 .2byte 0x180 .4byte 0x59 .2byte 0x138 .uleb128 0x22 - .4byte .LASF137 + .4byte .LASF136 .byte 0x13 .2byte 0x18d .4byte 0x59 @@ -2131,1036 +2618,1290 @@ stype.6193: .byte 0 .uleb128 0x8 .byte 0x8 - .4byte 0x647 + .4byte 0x63b .uleb128 0x8 .byte 0x8 - .4byte 0x487 + .4byte 0x47b .uleb128 0x1f - .4byte .LASF138 + .4byte .LASF137 .byte 0x13 .2byte 0x196 - .4byte 0x6e1 + .4byte 0x6d5 .uleb128 0xc - .4byte .LASF139 + .4byte .LASF138 .byte 0x13 .2byte 0x198 - .4byte 0x88a - .uleb128 0x24 - .4byte .LASF271 - .byte 0x4 - .4byte 0x59 - .byte 0x15 - .byte 0xe - .4byte 0xb05 - .uleb128 0x25 - .4byte .LASF140 + .4byte 0x87e + .uleb128 0xa + .4byte 0xe1 + .4byte 0x8a6 + .uleb128 0xe + .4byte 0xd4 + .byte 0xf .byte 0 - .uleb128 0x25 + .uleb128 0xa + .4byte 0xe1 + .4byte 0x8b7 + .uleb128 0x16 + .4byte 0xd4 + .2byte 0x3ff + .byte 0 + .uleb128 0xa + .4byte 0xe1 + .4byte 0x8c7 + .uleb128 0xe + .4byte 0xd4 + .byte 0x1f + .byte 0 + .uleb128 0x5 + .4byte .LASF139 + .byte 0x3 + .byte 0xad + .4byte 0x11b + .uleb128 0xa + .4byte 0x99 + .4byte 0x8dd + .uleb128 0xb + .byte 0 + .uleb128 0x5 + .4byte .LASF140 + .byte 0x3 + .byte 0xaf + .4byte 0x8d2 + .uleb128 0x5 .4byte .LASF141 - .byte 0x1 - .uleb128 0x25 + .byte 0x3 + .byte 0xb0 + .4byte 0x8d2 + .uleb128 0x5 .4byte .LASF142 - .byte 0x2 - .uleb128 0x25 + .byte 0x3 + .byte 0xfe + .4byte 0x11b + .uleb128 0x5 .4byte .LASF143 .byte 0x3 - .uleb128 0x25 + .byte 0xff + .4byte 0x11b + .uleb128 0xc .4byte .LASF144 - .byte 0x4 - .uleb128 0x25 + .byte 0x3 + .2byte 0x100 + .4byte 0x11b + .uleb128 0xf .4byte .LASF145 - .byte 0x5 - .uleb128 0x25 + .byte 0x4 + .byte 0x14 + .byte 0x2e + .4byte 0x92e + .uleb128 0x10 .4byte .LASF146 - .byte 0x6 - .uleb128 0x25 + .byte 0x14 + .byte 0x2f + .4byte 0x131 + .byte 0 + .byte 0 + .uleb128 0x8 + .byte 0x8 + .4byte 0x29 + .uleb128 0xa + .4byte 0x99 + .4byte 0x944 + .uleb128 0xe + .4byte 0xd4 + .byte 0x5 + .byte 0 + .uleb128 0xc .4byte .LASF147 - .byte 0x7 - .uleb128 0x25 + .byte 0x14 + .2byte 0x1fd + .4byte 0x915 + .uleb128 0xc .4byte .LASF148 - .byte 0x8 - .uleb128 0x25 + .byte 0x14 + .2byte 0x1fe + .4byte 0x915 + .uleb128 0xc .4byte .LASF149 - .byte 0x9 - .uleb128 0x25 + .byte 0x14 + .2byte 0x200 + .4byte 0x915 + .uleb128 0xc .4byte .LASF150 - .byte 0xa - .uleb128 0x25 + .byte 0x14 + .2byte 0x205 + .4byte 0x8b7 + .uleb128 0xc .4byte .LASF151 - .byte 0xb - .uleb128 0x25 + .byte 0x14 + .2byte 0x206 + .4byte 0x8b7 + .uleb128 0xa + .4byte 0xe1 + .4byte 0x990 + .uleb128 0xe + .4byte 0xd4 + .byte 0x3f + .byte 0 + .uleb128 0xc .4byte .LASF152 - .byte 0xc - .uleb128 0x25 + .byte 0x14 + .2byte 0x207 + .4byte 0x980 + .uleb128 0xc .4byte .LASF153 - .byte 0xd - .uleb128 0x25 + .byte 0x14 + .2byte 0x209 + .4byte 0x934 + .uleb128 0xc .4byte .LASF154 - .byte 0xe - .uleb128 0x25 + .byte 0x14 + .2byte 0x20a + .4byte 0x934 + .uleb128 0xc .4byte .LASF155 - .byte 0xf - .uleb128 0x25 + .byte 0x14 + .2byte 0x20b + .4byte 0x915 + .uleb128 0xc .4byte .LASF156 - .byte 0x10 - .uleb128 0x25 + .byte 0x14 + .2byte 0x20c + .4byte 0x915 + .uleb128 0xc .4byte .LASF157 - .byte 0x11 - .uleb128 0x25 + .byte 0x14 + .2byte 0x20d + .4byte 0x92e + .uleb128 0xa + .4byte 0x92e + .4byte 0x9e8 + .uleb128 0xe + .4byte 0xd4 + .byte 0x3 + .byte 0 + .uleb128 0xc .4byte .LASF158 - .byte 0x12 - .uleb128 0x25 + .byte 0x14 + .2byte 0x20e + .4byte 0x9d8 + .uleb128 0xc .4byte .LASF159 - .byte 0x13 - .uleb128 0x25 + .byte 0x14 + .2byte 0x20f + .4byte 0x92e + .uleb128 0xc .4byte .LASF160 .byte 0x14 - .uleb128 0x25 + .2byte 0x210 + .4byte 0x59 + .uleb128 0xa + .4byte 0xa3 + .4byte 0xa1c + .uleb128 0xe + .4byte 0xd4 + .byte 0x5 + .byte 0 + .uleb128 0x4 + .4byte 0xa0c + .uleb128 0xc .4byte .LASF161 - .byte 0x15 - .uleb128 0x25 + .byte 0x14 + .2byte 0x211 + .4byte 0xa1c + .uleb128 0xc .4byte .LASF162 - .byte 0x16 - .uleb128 0x25 + .byte 0x14 + .2byte 0x212 + .4byte 0xa1c + .uleb128 0xc .4byte .LASF163 - .byte 0x17 - .uleb128 0x25 + .byte 0x14 + .2byte 0x216 + .4byte 0x110 + .uleb128 0xc .4byte .LASF164 - .byte 0x18 - .uleb128 0x25 + .byte 0x14 + .2byte 0x217 + .4byte 0x110 + .uleb128 0xc .4byte .LASF165 - .byte 0x19 - .uleb128 0x25 + .byte 0x14 + .2byte 0x219 + .4byte 0x59 + .uleb128 0xc .4byte .LASF166 - .byte 0x1a - .uleb128 0x25 + .byte 0x14 + .2byte 0x220 + .4byte 0x8a6 + .uleb128 0xc .4byte .LASF167 - .byte 0x1b - .uleb128 0x25 + .byte 0x14 + .2byte 0x222 + .4byte 0xa8 + .uleb128 0xc .4byte .LASF168 - .byte 0x1c - .uleb128 0x25 + .byte 0x14 + .2byte 0x224 + .4byte 0xa8 + .uleb128 0xc .4byte .LASF169 - .byte 0x1d + .byte 0x14 + .2byte 0x230 + .4byte 0x915 + .uleb128 0x24 + .4byte .LASF180 + .byte 0x4 + .4byte 0x84 + .byte 0x14 + .2byte 0x286 + .4byte 0xab7 .uleb128 0x25 .4byte .LASF170 - .byte 0x1e + .byte 0 .uleb128 0x25 .4byte .LASF171 - .byte 0x1f + .byte 0x1 .uleb128 0x25 .4byte .LASF172 - .byte 0x20 + .byte 0x2 .uleb128 0x25 .4byte .LASF173 - .byte 0x21 - .uleb128 0x25 + .byte 0x3 + .byte 0 + .uleb128 0xc .4byte .LASF174 - .byte 0x22 - .uleb128 0x25 + .byte 0x14 + .2byte 0x28c + .4byte 0xa8d + .uleb128 0xc .4byte .LASF175 - .byte 0x23 - .uleb128 0x25 + .byte 0x15 + .2byte 0x3ba + .4byte 0x11b + .uleb128 0xc .4byte .LASF176 - .byte 0x24 - .uleb128 0x25 + .byte 0x15 + .2byte 0x3bb + .4byte 0x11b + .uleb128 0xc .4byte .LASF177 - .byte 0x25 - .uleb128 0x25 + .byte 0x15 + .2byte 0x3bc + .4byte 0x11b + .uleb128 0xf .4byte .LASF178 - .byte 0x26 - .uleb128 0x25 + .byte 0x4 + .byte 0x2 + .byte 0xd + .4byte 0xb00 + .uleb128 0x19 + .string "pid" + .byte 0x2 + .byte 0xe + .4byte 0x59 + .byte 0 + .byte 0 + .uleb128 0x5 .4byte .LASF179 - .byte 0x27 - .uleb128 0x25 - .4byte .LASF180 - .byte 0x28 - .uleb128 0x25 + .byte 0x2 + .byte 0x11 + .4byte 0xb0b + .uleb128 0x8 + .byte 0x8 + .4byte 0xae7 + .uleb128 0x26 .4byte .LASF181 - .byte 0x29 + .byte 0x4 + .4byte 0x84 + .byte 0x16 + .byte 0x11 + .4byte 0xb88 .uleb128 0x25 .4byte .LASF182 - .byte 0x2a + .byte 0 .uleb128 0x25 .4byte .LASF183 - .byte 0x2b + .byte 0x1 .uleb128 0x25 .4byte .LASF184 - .byte 0x2c + .byte 0x2 .uleb128 0x25 .4byte .LASF185 - .byte 0x2d + .byte 0x3 .uleb128 0x25 .4byte .LASF186 - .byte 0x2e + .byte 0x4 .uleb128 0x25 .4byte .LASF187 - .byte 0x2f + .byte 0x5 .uleb128 0x25 .4byte .LASF188 - .byte 0x30 + .byte 0x6 .uleb128 0x25 .4byte .LASF189 - .byte 0x31 + .byte 0x7 .uleb128 0x25 .4byte .LASF190 - .byte 0x32 + .byte 0x8 .uleb128 0x25 .4byte .LASF191 - .byte 0x33 + .byte 0x9 .uleb128 0x25 .4byte .LASF192 - .byte 0x34 + .byte 0xa .uleb128 0x25 .4byte .LASF193 - .byte 0x35 + .byte 0xb .uleb128 0x25 .4byte .LASF194 - .byte 0x36 + .byte 0xc .uleb128 0x25 .4byte .LASF195 - .byte 0x37 + .byte 0xd .uleb128 0x25 .4byte .LASF196 - .byte 0x38 + .byte 0xe .uleb128 0x25 .4byte .LASF197 - .byte 0x39 + .byte 0xf .uleb128 0x25 .4byte .LASF198 - .byte 0x3a - .uleb128 0x25 + .byte 0x10 + .byte 0 + .uleb128 0xf .4byte .LASF199 - .byte 0x3b - .uleb128 0x25 + .byte 0x20 + .byte 0x16 + .byte 0x26 + .4byte 0xbb9 + .uleb128 0x10 .4byte .LASF200 - .byte 0x3c - .uleb128 0x25 + .byte 0x16 + .byte 0x27 + .4byte 0x84 + .byte 0 + .uleb128 0x10 .4byte .LASF201 - .byte 0x3d - .uleb128 0x25 + .byte 0x16 + .byte 0x28 + .4byte 0xbb9 + .byte 0x8 + .uleb128 0x10 .4byte .LASF202 - .byte 0x3e - .uleb128 0x25 + .byte 0x16 + .byte 0x29 + .4byte 0xbbf + .byte 0x10 + .byte 0 + .uleb128 0x8 + .byte 0x8 + .4byte 0x84 + .uleb128 0xa + .4byte 0xbcf + .4byte 0xbcf + .uleb128 0xe + .4byte 0xd4 + .byte 0x1 + .byte 0 + .uleb128 0x8 + .byte 0x8 + .4byte 0x99 + .uleb128 0x27 + .4byte .LASF242 + .byte 0x1 + .byte 0x15 + .4byte 0x154 + .uleb128 0x26 .4byte .LASF203 - .byte 0x3f + .byte 0x4 + .4byte 0x84 + .byte 0x1 + .byte 0x20 + .4byte 0xc1b .uleb128 0x25 .4byte .LASF204 - .byte 0x40 + .byte 0 .uleb128 0x25 .4byte .LASF205 - .byte 0x41 + .byte 0x1 .uleb128 0x25 .4byte .LASF206 - .byte 0x42 + .byte 0x2 .uleb128 0x25 .4byte .LASF207 - .byte 0x43 + .byte 0x3 .uleb128 0x25 .4byte .LASF208 - .byte 0x44 + .byte 0x4 .uleb128 0x25 .4byte .LASF209 - .byte 0x45 + .byte 0x5 .uleb128 0x25 .4byte .LASF210 - .byte 0x46 - .uleb128 0x25 + .byte 0x6 + .byte 0 + .uleb128 0x18 .4byte .LASF211 - .byte 0x47 - .uleb128 0x25 + .2byte 0x954 + .byte 0x1 + .byte 0x2a + .4byte 0xd31 + .uleb128 0x10 .4byte .LASF212 - .byte 0x48 - .uleb128 0x25 + .byte 0x1 + .byte 0x2b + .4byte 0x59 + .byte 0 + .uleb128 0x10 .4byte .LASF213 - .byte 0x49 - .uleb128 0x25 + .byte 0x1 + .byte 0x2c + .4byte 0x896 + .byte 0x4 + .uleb128 0x10 + .4byte .LASF82 + .byte 0x1 + .byte 0x2d + .4byte 0x896 + .byte 0x14 + .uleb128 0x10 .4byte .LASF214 - .byte 0x4a - .uleb128 0x25 + .byte 0x1 + .byte 0x2e + .4byte 0x896 + .byte 0x24 + .uleb128 0x10 .4byte .LASF215 - .byte 0x4b - .uleb128 0x25 + .byte 0x1 + .byte 0x2f + .4byte 0x896 + .byte 0x34 + .uleb128 0x10 .4byte .LASF216 - .byte 0x4c - .uleb128 0x25 + .byte 0x1 + .byte 0x30 + .4byte 0x896 + .byte 0x44 + .uleb128 0x10 .4byte .LASF217 - .byte 0x4d - .uleb128 0x25 + .byte 0x1 + .byte 0x31 + .4byte 0x980 + .byte 0x54 + .uleb128 0x10 .4byte .LASF218 - .byte 0x4e - .uleb128 0x25 + .byte 0x1 + .byte 0x32 + .4byte 0x980 + .byte 0x94 + .uleb128 0x10 .4byte .LASF219 - .byte 0x4f - .uleb128 0x25 + .byte 0x1 + .byte 0x33 + .4byte 0x980 + .byte 0xd4 + .uleb128 0x14 .4byte .LASF220 - .byte 0x50 - .uleb128 0x25 + .byte 0x1 + .byte 0x34 + .4byte 0x980 + .2byte 0x114 + .uleb128 0x14 .4byte .LASF221 - .byte 0x51 - .uleb128 0x25 + .byte 0x1 + .byte 0x35 + .4byte 0x980 + .2byte 0x154 + .uleb128 0x14 .4byte .LASF222 - .byte 0x52 - .uleb128 0x25 + .byte 0x1 + .byte 0x36 + .4byte 0x980 + .2byte 0x194 + .uleb128 0x14 .4byte .LASF223 - .byte 0x53 - .uleb128 0x25 + .byte 0x1 + .byte 0x37 + .4byte 0x980 + .2byte 0x1d4 + .uleb128 0x14 .4byte .LASF224 - .byte 0x54 - .uleb128 0x25 + .byte 0x1 + .byte 0x38 + .4byte 0x980 + .2byte 0x214 + .uleb128 0x14 .4byte .LASF225 - .byte 0x55 - .uleb128 0x25 + .byte 0x1 + .byte 0x39 + .4byte 0xd31 + .2byte 0x254 + .uleb128 0x14 .4byte .LASF226 - .byte 0x56 - .uleb128 0x25 + .byte 0x1 + .byte 0x3a + .4byte 0xd31 + .2byte 0x354 + .uleb128 0x14 .4byte .LASF227 - .byte 0x57 - .uleb128 0x25 + .byte 0x1 + .byte 0x3b + .4byte 0xd31 + .2byte 0x454 + .uleb128 0x14 .4byte .LASF228 - .byte 0x58 - .uleb128 0x25 - .4byte .LASF229 - .byte 0x59 - .uleb128 0x25 + .byte 0x1 + .byte 0x3c + .4byte 0xd31 + .2byte 0x554 + .uleb128 0x14 + .4byte .LASF229 + .byte 0x1 + .byte 0x3d + .4byte 0xd31 + .2byte 0x654 + .uleb128 0x14 .4byte .LASF230 - .byte 0x5a - .uleb128 0x25 + .byte 0x1 + .byte 0x3e + .4byte 0xd31 + .2byte 0x754 + .uleb128 0x14 .4byte .LASF231 - .byte 0x5b - .uleb128 0x25 - .4byte .LASF232 - .byte 0x5c - .uleb128 0x25 - .4byte .LASF233 - .byte 0x5d - .uleb128 0x25 - .4byte .LASF234 - .byte 0x5e - .uleb128 0x25 - .4byte .LASF235 - .byte 0x5f - .uleb128 0x25 - .4byte .LASF236 - .byte 0x60 - .uleb128 0x25 - .4byte .LASF237 - .byte 0x61 - .uleb128 0x26 - .4byte .LASF238 - .sleb128 -1 - .byte 0 - .uleb128 0x27 - .byte 0x4 - .4byte 0x84 - .byte 0x19 - .byte 0xf6 - .4byte 0xb18 - .uleb128 0x25 - .4byte .LASF239 - .byte 0x5 + .byte 0x1 + .byte 0x3f + .4byte 0xd31 + .2byte 0x854 .byte 0 .uleb128 0xa - .4byte 0xe1 - .4byte 0xb28 + .4byte 0x84 + .4byte 0xd41 .uleb128 0xe .4byte 0xd4 - .byte 0x1f + .byte 0x3f .byte 0 - .uleb128 0x5 - .4byte .LASF240 + .uleb128 0x28 + .4byte .LASF232 + .byte 0x1 + .byte 0x43 + .4byte 0xd56 + .uleb128 0x9 .byte 0x3 - .byte 0xad - .4byte 0x11b + .8byte global_waveform + .uleb128 0x8 + .byte 0x8 + .4byte 0xc1b .uleb128 0xa - .4byte 0x99 - .4byte 0xb3e - .uleb128 0xb + .4byte 0x84 + .4byte 0xd6c + .uleb128 0xe + .4byte 0xd4 + .byte 0xff .byte 0 - .uleb128 0x5 - .4byte .LASF241 + .uleb128 0x28 + .4byte .LASF233 + .byte 0x1 + .byte 0x44 + .4byte 0xd5c + .uleb128 0x9 .byte 0x3 - .byte 0xaf - .4byte 0xb33 - .uleb128 0x5 - .4byte .LASF242 + .8byte crc32_table + .uleb128 0x28 + .4byte .LASF234 + .byte 0x1 + .byte 0x45 + .4byte 0x59 + .uleb128 0x9 .byte 0x3 - .byte 0xb0 - .4byte 0xb33 - .uleb128 0x5 - .4byte .LASF243 + .8byte maxpic + .uleb128 0x28 + .4byte .LASF235 + .byte 0x1 + .byte 0x46 + .4byte 0x59 + .uleb128 0x9 .byte 0x3 - .byte 0xfe - .4byte 0x11b - .uleb128 0x5 - .4byte .LASF244 + .8byte need_pic + .uleb128 0x29 + .4byte .LASF287 + .byte 0x1 + .2byte 0x2fc + .4byte 0x59 + .8byte .LFB239 + .8byte .LFE239-.LFB239 + .uleb128 0x1 + .byte 0x9c + .4byte 0x10f0 + .uleb128 0x2a + .4byte .LASF236 + .byte 0x1 + .2byte 0x2fc + .4byte 0x10f0 + .4byte .LLST71 + .uleb128 0x2a + .4byte .LASF237 + .byte 0x1 + .2byte 0x2fc + .4byte 0xb11 + .4byte .LLST72 + .uleb128 0x2a + .4byte .LASF238 + .byte 0x1 + .2byte 0x2fc + .4byte 0x59 + .4byte .LLST73 + .uleb128 0x2b + .string "pic" + .byte 0x1 + .2byte 0x2fc + .4byte 0x59 + .4byte .LLST74 + .uleb128 0x2a + .4byte .LASF239 + .byte 0x1 + .2byte 0x2fc + .4byte 0x59 + .4byte .LLST75 + .uleb128 0x2c + .4byte .LASF240 + .byte 0x1 + .2byte 0x2fe + .4byte 0xb11 + .uleb128 0x9 .byte 0x3 - .byte 0xff - .4byte 0x11b - .uleb128 0xc - .4byte .LASF245 + .8byte stype.6419 + .uleb128 0x2c + .4byte .LASF241 + .byte 0x1 + .2byte 0x2ff + .4byte 0x59 + .uleb128 0x9 .byte 0x3 - .2byte 0x100 - .4byte 0x11b - .uleb128 0xf - .4byte .LASF246 - .byte 0x4 - .byte 0x14 - .byte 0x2e - .4byte 0xb8f - .uleb128 0x10 - .4byte .LASF247 - .byte 0x14 - .byte 0x2f - .4byte 0x131 + .8byte sftemp.6420 + .uleb128 0x2d + .4byte .LASF243 + .byte 0x1 + .2byte 0x300 + .4byte 0x59 + .uleb128 0x2e + .4byte .LASF200 + .byte 0x1 + .2byte 0x301 + .4byte 0x59 + .4byte .LLST76 + .uleb128 0x2f + .4byte 0x1f04 + .8byte .LBB172 + .8byte .LBE172-.LBB172 + .byte 0x1 + .2byte 0x320 + .4byte 0xe98 + .uleb128 0x30 + .4byte 0x1f10 + .4byte .LLST77 + .uleb128 0x31 + .8byte .LVL143 + .4byte 0x2048 .byte 0 + .uleb128 0x2f + .4byte 0x1f04 + .8byte .LBB174 + .8byte .LBE174-.LBB174 + .byte 0x1 + .2byte 0x33b + .4byte 0xecb + .uleb128 0x30 + .4byte 0x1f10 + .4byte .LLST78 + .uleb128 0x31 + .8byte .LVL155 + .4byte 0x2048 .byte 0 - .uleb128 0x8 - .byte 0x8 - .4byte 0x29 - .uleb128 0xa - .4byte 0x99 - .4byte 0xba5 - .uleb128 0xe - .4byte 0xd4 - .byte 0x5 + .uleb128 0x32 + .4byte 0x1f1c + .8byte .LBB176 + .4byte .Ldebug_ranges0+0x290 + .byte 0x1 + .2byte 0x33e + .4byte 0xf11 + .uleb128 0x30 + .4byte 0x1f37 + .4byte .LLST79 + .uleb128 0x30 + .4byte 0x1f2c + .4byte .LLST80 + .uleb128 0x33 + .8byte .LVL158 + .4byte 0x2054 + .uleb128 0x34 + .uleb128 0x1 + .byte 0x50 + .uleb128 0x2 + .byte 0x85 + .sleb128 0 + .uleb128 0x34 + .uleb128 0x1 + .byte 0x51 + .uleb128 0x3 + .byte 0xa + .2byte 0x8000 .byte 0 - .uleb128 0xc - .4byte .LASF248 - .byte 0x14 - .2byte 0x1fd - .4byte 0xb76 - .uleb128 0xc - .4byte .LASF249 - .byte 0x14 - .2byte 0x1fe - .4byte 0xb76 - .uleb128 0xc - .4byte .LASF250 - .byte 0x14 - .2byte 0x200 - .4byte 0xb76 - .uleb128 0xc - .4byte .LASF251 - .byte 0x14 - .2byte 0x205 - .4byte 0xb18 - .uleb128 0xc - .4byte .LASF252 - .byte 0x14 - .2byte 0x206 - .4byte 0xb18 - .uleb128 0xa - .4byte 0xe1 - .4byte 0xbf1 - .uleb128 0xe - .4byte 0xd4 - .byte 0x3f .byte 0 - .uleb128 0xc - .4byte .LASF253 - .byte 0x14 - .2byte 0x207 - .4byte 0xbe1 - .uleb128 0xc - .4byte .LASF254 - .byte 0x14 - .2byte 0x209 - .4byte 0xb95 - .uleb128 0xc - .4byte .LASF255 - .byte 0x14 - .2byte 0x20a - .4byte 0xb95 - .uleb128 0xc - .4byte .LASF256 - .byte 0x14 - .2byte 0x20b - .4byte 0xb76 - .uleb128 0xc - .4byte .LASF257 - .byte 0x14 - .2byte 0x20c - .4byte 0xb76 - .uleb128 0xc - .4byte .LASF258 - .byte 0x14 - .2byte 0x20d - .4byte 0xb8f - .uleb128 0xa - .4byte 0xb8f - .4byte 0xc49 - .uleb128 0xe - .4byte 0xd4 - .byte 0x3 + .uleb128 0x32 + .4byte 0x16cc + .8byte .LBB182 + .4byte .Ldebug_ranges0+0x2d0 + .byte 0x1 + .2byte 0x32c + .4byte 0xf96 + .uleb128 0x30 + .4byte 0x16dd + .4byte .LLST81 + .uleb128 0x30 + .4byte 0x16f5 + .4byte .LLST82 + .uleb128 0x30 + .4byte 0x16e9 + .4byte .LLST83 + .uleb128 0x35 + .4byte .Ldebug_ranges0+0x2d0 + .uleb128 0x36 + .4byte 0x1701 + .4byte .LLST84 + .uleb128 0x36 + .4byte 0x170b + .4byte .LLST85 + .uleb128 0x36 + .4byte 0x1717 + .4byte .LLST86 + .uleb128 0x36 + .4byte 0x1723 + .4byte .LLST87 + .uleb128 0x35 + .4byte .Ldebug_ranges0+0x300 + .uleb128 0x36 + .4byte 0x1730 + .4byte .LLST88 + .uleb128 0x35 + .4byte .Ldebug_ranges0+0x350 + .uleb128 0x36 + .4byte 0x173d + .4byte .LLST89 + .uleb128 0x36 + .4byte 0x1749 + .4byte .LLST90 .byte 0 - .uleb128 0xc - .4byte .LASF259 - .byte 0x14 - .2byte 0x20e - .4byte 0xc39 - .uleb128 0xc - .4byte .LASF260 - .byte 0x14 - .2byte 0x20f - .4byte 0xb8f - .uleb128 0xc - .4byte .LASF261 - .byte 0x14 - .2byte 0x210 - .4byte 0x59 - .uleb128 0xa - .4byte 0xa3 - .4byte 0xc7d - .uleb128 0xe - .4byte 0xd4 - .byte 0x5 .byte 0 - .uleb128 0x4 - .4byte 0xc6d - .uleb128 0xc - .4byte .LASF262 - .byte 0x14 - .2byte 0x211 - .4byte 0xc7d - .uleb128 0xc - .4byte .LASF263 - .byte 0x14 - .2byte 0x212 - .4byte 0xc7d - .uleb128 0xc - .4byte .LASF264 - .byte 0x14 - .2byte 0x216 - .4byte 0x110 - .uleb128 0xc - .4byte .LASF265 - .byte 0x14 - .2byte 0x217 - .4byte 0x110 - .uleb128 0xc - .4byte .LASF266 - .byte 0x14 - .2byte 0x219 - .4byte 0x59 - .uleb128 0xa - .4byte 0xe1 - .4byte 0xccf - .uleb128 0x16 - .4byte 0xd4 - .2byte 0x3ff .byte 0 - .uleb128 0xc - .4byte .LASF267 - .byte 0x14 - .2byte 0x220 - .4byte 0xcbe - .uleb128 0xc - .4byte .LASF268 - .byte 0x14 - .2byte 0x222 - .4byte 0xa8 - .uleb128 0xc - .4byte .LASF269 - .byte 0x14 - .2byte 0x224 - .4byte 0xa8 - .uleb128 0xc - .4byte .LASF270 - .byte 0x14 - .2byte 0x230 - .4byte 0xb76 - .uleb128 0x28 - .4byte .LASF272 - .byte 0x4 - .4byte 0x84 - .byte 0x14 - .2byte 0x286 - .4byte 0xd29 - .uleb128 0x25 - .4byte .LASF273 .byte 0 - .uleb128 0x25 - .4byte .LASF274 + .uleb128 0x32 + .4byte 0x10f6 + .8byte .LBB193 + .4byte .Ldebug_ranges0+0x390 .byte 0x1 - .uleb128 0x25 - .4byte .LASF275 - .byte 0x2 - .uleb128 0x25 - .4byte .LASF276 + .2byte 0x343 + .4byte 0x1065 + .uleb128 0x30 + .4byte 0x112b + .4byte .LLST91 + .uleb128 0x30 + .4byte 0x111f + .4byte .LLST92 + .uleb128 0x30 + .4byte 0x1113 + .4byte .LLST93 + .uleb128 0x30 + .4byte 0x1107 + .4byte .LLST94 + .uleb128 0x35 + .4byte .Ldebug_ranges0+0x390 + .uleb128 0x36 + .4byte 0x1137 + .4byte .LLST95 + .uleb128 0x36 + .4byte 0x1143 + .4byte .LLST96 + .uleb128 0x36 + .4byte 0x114f + .4byte .LLST97 + .uleb128 0x37 + .8byte .LBB195 + .8byte .LBE195-.LBB195 + .4byte 0x102b + .uleb128 0x36 + .4byte 0x115c + .4byte .LLST98 + .uleb128 0x35 + .4byte .Ldebug_ranges0+0x3c0 + .uleb128 0x38 + .4byte 0x1167 + .uleb128 0x35 + .4byte .Ldebug_ranges0+0x3f0 + .uleb128 0x36 + .4byte 0x1174 + .4byte .LLST99 + .byte 0 + .byte 0 + .byte 0 + .uleb128 0x39 + .8byte .LVL191 + .4byte 0x205f + .4byte 0x104a + .uleb128 0x34 + .uleb128 0x1 + .byte 0x50 + .uleb128 0x9 + .byte 0x3 + .8byte .LC11 + .byte 0 + .uleb128 0x33 + .8byte .LVL195 + .4byte 0x206a + .uleb128 0x34 + .uleb128 0x1 + .byte 0x51 + .uleb128 0x1 + .byte 0x30 + .uleb128 0x34 + .uleb128 0x1 + .byte 0x52 + .uleb128 0x2 + .byte 0x85 + .sleb128 0 + .byte 0 + .byte 0 + .byte 0 + .uleb128 0x39 + .8byte .LVL144 + .4byte 0x12e2 + .4byte 0x1089 + .uleb128 0x34 + .uleb128 0x1 + .byte 0x50 + .uleb128 0x2 + .byte 0x84 + .sleb128 0 + .uleb128 0x34 + .uleb128 0x1 + .byte 0x51 + .uleb128 0x2 + .byte 0x83 + .sleb128 0 + .uleb128 0x34 + .uleb128 0x1 + .byte 0x52 + .uleb128 0x2 + .byte 0x85 + .sleb128 0 + .byte 0 + .uleb128 0x39 + .8byte .LVL147 + .4byte 0x205f + .4byte 0x10a8 + .uleb128 0x34 + .uleb128 0x1 + .byte 0x50 + .uleb128 0x9 .byte 0x3 + .8byte .LC9 .byte 0 - .uleb128 0xc - .4byte .LASF277 - .byte 0x14 - .2byte 0x28c - .4byte 0xcff - .uleb128 0xc - .4byte .LASF278 - .byte 0x16 - .2byte 0x3ba - .4byte 0x11b - .uleb128 0xc - .4byte .LASF279 - .byte 0x16 - .2byte 0x3bb - .4byte 0x11b - .uleb128 0xc - .4byte .LASF280 - .byte 0x16 - .2byte 0x3bc - .4byte 0x11b - .uleb128 0xf - .4byte .LASF281 - .byte 0x4 - .byte 0x2 - .byte 0xd - .4byte 0xd72 - .uleb128 0x19 - .string "pid" - .byte 0x2 - .byte 0xe - .4byte 0x59 + .uleb128 0x39 + .8byte .LVL153 + .4byte 0x1f43 + .4byte 0x10d4 + .uleb128 0x34 + .uleb128 0x1 + .byte 0x50 + .uleb128 0x2 + .byte 0x84 + .sleb128 8 + .uleb128 0x34 + .uleb128 0x1 + .byte 0x51 + .uleb128 0x2 + .byte 0x71 + .sleb128 0 + .uleb128 0x34 + .uleb128 0x1 + .byte 0x52 + .uleb128 0x2 + .byte 0x72 + .sleb128 0 + .uleb128 0x3a + .4byte 0x1669 + .uleb128 0x2 + .byte 0x84 + .sleb128 0 + .byte 0 + .uleb128 0x33 + .8byte .LVL160 + .4byte 0x205f + .uleb128 0x34 + .uleb128 0x1 + .byte 0x50 + .uleb128 0x9 + .byte 0x3 + .8byte .LC10 .byte 0 .byte 0 - .uleb128 0x5 - .4byte .LASF282 - .byte 0x2 - .byte 0x11 - .4byte 0xd7d .uleb128 0x8 .byte 0x8 - .4byte 0xd59 - .uleb128 0x24 - .4byte .LASF283 - .byte 0x4 - .4byte 0x84 - .byte 0x17 - .byte 0x14 - .4byte 0xde2 - .uleb128 0x25 - .4byte .LASF284 + .4byte 0xb88 + .uleb128 0x3b + .4byte .LASF246 .byte 0x1 - .uleb128 0x25 - .4byte .LASF285 - .byte 0x2 - .uleb128 0x25 - .4byte .LASF286 - .byte 0x3 - .uleb128 0x25 - .4byte .LASF287 - .byte 0x4 - .uleb128 0x25 - .4byte .LASF288 - .byte 0x5 - .uleb128 0x25 - .4byte .LASF289 - .byte 0x6 - .uleb128 0x25 - .4byte .LASF290 - .byte 0x7 - .uleb128 0x25 - .4byte .LASF291 - .byte 0x8 - .uleb128 0x25 - .4byte .LASF292 - .byte 0x9 - .uleb128 0x25 - .4byte .LASF293 - .byte 0xa - .uleb128 0x25 - .4byte .LASF294 - .byte 0xb - .uleb128 0x25 - .4byte .LASF295 - .byte 0xc - .uleb128 0x25 - .4byte .LASF296 - .byte 0xd + .2byte 0x2da + .4byte 0x59 + .byte 0x1 + .4byte 0x1184 + .uleb128 0x3c + .4byte .LASF244 + .byte 0x1 + .2byte 0x2da + .4byte 0x1184 + .uleb128 0x3c + .4byte .LASF202 + .byte 0x1 + .2byte 0x2da + .4byte 0xbcf + .uleb128 0x3c + .4byte .LASF200 + .byte 0x1 + .2byte 0x2da + .4byte 0x59 + .uleb128 0x3d + .string "pic" + .byte 0x1 + .2byte 0x2da + .4byte 0x59 + .uleb128 0x3e + .string "lut" + .byte 0x1 + .2byte 0x2db + .4byte 0x1184 + .uleb128 0x2d + .4byte .LASF201 + .byte 0x1 + .2byte 0x2dc + .4byte 0x99 + .uleb128 0x2d + .4byte .LASF245 + .byte 0x1 + .2byte 0x2dc + .4byte 0x99 + .uleb128 0x3f + .uleb128 0x3e + .string "f" + .byte 0x1 + .2byte 0x2e5 + .4byte 0x59 + .uleb128 0x3f + .uleb128 0x3e + .string "old" + .byte 0x1 + .2byte 0x2e6 + .4byte 0x99 + .uleb128 0x3f + .uleb128 0x3e + .string "new" + .byte 0x1 + .2byte 0x2e7 + .4byte 0x99 + .byte 0 .byte 0 - .uleb128 0xf - .4byte .LASF297 - .byte 0x10 - .byte 0x17 - .byte 0x43 - .4byte 0xe07 - .uleb128 0x10 - .4byte .LASF298 - .byte 0x17 - .byte 0x44 - .4byte 0x84 .byte 0 - .uleb128 0x10 - .4byte .LASF299 - .byte 0x17 - .byte 0x45 - .4byte 0xe07 - .byte 0x8 .byte 0 .uleb128 0x8 .byte 0x8 - .4byte 0x84 - .uleb128 0x8 - .byte 0x8 - .4byte 0xde2 - .uleb128 0x24 - .4byte .LASF300 - .byte 0x4 - .4byte 0x84 + .4byte 0xa8 + .uleb128 0x3b + .4byte .LASF247 .byte 0x1 - .byte 0x15 - .4byte 0xe4e - .uleb128 0x25 - .4byte .LASF301 - .byte 0 - .uleb128 0x25 - .4byte .LASF302 + .2byte 0x2b3 + .4byte 0x59 .byte 0x1 - .uleb128 0x25 - .4byte .LASF303 - .byte 0x2 - .uleb128 0x25 - .4byte .LASF304 - .byte 0x3 - .uleb128 0x25 - .4byte .LASF305 - .byte 0x4 - .uleb128 0x25 - .4byte .LASF306 - .byte 0x5 - .uleb128 0x25 - .4byte .LASF307 - .byte 0x6 - .byte 0 - .uleb128 0x18 - .4byte .LASF308 - .2byte 0x954 + .4byte 0x11d6 + .uleb128 0x3c + .4byte .LASF202 .byte 0x1 - .byte 0x1f - .4byte 0xf64 - .uleb128 0x10 - .4byte .LASF309 + .2byte 0x2b3 + .4byte 0xbcf + .uleb128 0x3c + .4byte .LASF200 .byte 0x1 - .byte 0x20 + .2byte 0x2b3 + .4byte 0x59 + .uleb128 0x3d + .string "fix" + .byte 0x1 + .2byte 0x2b3 + .4byte 0x59 + .uleb128 0x3e + .string "f" + .byte 0x1 + .2byte 0x2b5 .4byte 0x59 + .uleb128 0x2d + .4byte .LASF248 + .byte 0x1 + .2byte 0x2b6 + .4byte 0xbcf .byte 0 - .uleb128 0x10 - .4byte .LASF310 + .uleb128 0x3b + .4byte .LASF249 .byte 0x1 - .byte 0x21 - .4byte 0xf64 - .byte 0x4 - .uleb128 0x10 - .4byte .LASF83 + .2byte 0x29c + .4byte 0x59 .byte 0x1 - .byte 0x22 - .4byte 0xf64 - .byte 0x14 - .uleb128 0x10 - .4byte .LASF311 + .4byte 0x1222 + .uleb128 0x3c + .4byte .LASF202 + .byte 0x1 + .2byte 0x29c + .4byte 0xbcf + .uleb128 0x3c + .4byte .LASF200 + .byte 0x1 + .2byte 0x29c + .4byte 0x59 + .uleb128 0x3c + .4byte .LASF250 + .byte 0x1 + .2byte 0x29c + .4byte 0x59 + .uleb128 0x3e + .string "f" + .byte 0x1 + .2byte 0x29e + .4byte 0x59 + .uleb128 0x2d + .4byte .LASF248 .byte 0x1 - .byte 0x23 - .4byte 0xf64 - .byte 0x24 - .uleb128 0x10 - .4byte .LASF312 + .2byte 0x29f + .4byte 0xbcf + .byte 0 + .uleb128 0x3b + .4byte .LASF251 .byte 0x1 - .byte 0x24 - .4byte 0xf64 - .byte 0x34 - .uleb128 0x10 - .4byte .LASF313 + .2byte 0x28d + .4byte 0x59 .byte 0x1 - .byte 0x25 - .4byte 0xf64 - .byte 0x44 - .uleb128 0x10 - .4byte .LASF314 + .4byte 0x1262 + .uleb128 0x3c + .4byte .LASF202 .byte 0x1 - .byte 0x26 - .4byte 0xbe1 - .byte 0x54 - .uleb128 0x10 - .4byte .LASF315 + .2byte 0x28d + .4byte 0xbcf + .uleb128 0x3c + .4byte .LASF200 .byte 0x1 - .byte 0x27 - .4byte 0xbe1 - .byte 0x94 - .uleb128 0x10 - .4byte .LASF316 + .2byte 0x28d + .4byte 0x59 + .uleb128 0x3e + .string "f" .byte 0x1 - .byte 0x28 - .4byte 0xbe1 - .byte 0xd4 - .uleb128 0x14 - .4byte .LASF317 + .2byte 0x28f + .4byte 0x59 + .uleb128 0x2d + .4byte .LASF248 .byte 0x1 - .byte 0x29 - .4byte 0xbe1 - .2byte 0x114 - .uleb128 0x14 - .4byte .LASF318 + .2byte 0x290 + .4byte 0xbcf + .byte 0 + .uleb128 0x3b + .4byte .LASF252 .byte 0x1 - .byte 0x2a - .4byte 0xbe1 - .2byte 0x154 - .uleb128 0x14 - .4byte .LASF319 + .2byte 0x271 + .4byte 0x59 .byte 0x1 - .byte 0x2b - .4byte 0xbe1 - .2byte 0x194 - .uleb128 0x14 - .4byte .LASF320 + .4byte 0x12a2 + .uleb128 0x3c + .4byte .LASF202 .byte 0x1 - .byte 0x2c - .4byte 0xbe1 - .2byte 0x1d4 - .uleb128 0x14 - .4byte .LASF321 + .2byte 0x271 + .4byte 0xbcf + .uleb128 0x3c + .4byte .LASF200 .byte 0x1 - .byte 0x2d - .4byte 0xbe1 - .2byte 0x214 - .uleb128 0x14 - .4byte .LASF322 + .2byte 0x271 + .4byte 0x59 + .uleb128 0x3e + .string "f" .byte 0x1 - .byte 0x2e - .4byte 0xf74 - .2byte 0x254 - .uleb128 0x14 - .4byte .LASF323 + .2byte 0x273 + .4byte 0x59 + .uleb128 0x2d + .4byte .LASF248 .byte 0x1 - .byte 0x2f - .4byte 0xf74 - .2byte 0x354 - .uleb128 0x14 - .4byte .LASF324 + .2byte 0x274 + .4byte 0xbcf + .byte 0 + .uleb128 0x3b + .4byte .LASF253 .byte 0x1 - .byte 0x30 - .4byte 0xf74 - .2byte 0x454 - .uleb128 0x14 - .4byte .LASF325 + .2byte 0x254 + .4byte 0x59 .byte 0x1 - .byte 0x31 - .4byte 0xf74 - .2byte 0x554 - .uleb128 0x14 - .4byte .LASF326 + .4byte 0x12e2 + .uleb128 0x3c + .4byte .LASF202 .byte 0x1 - .byte 0x32 - .4byte 0xf74 - .2byte 0x654 - .uleb128 0x14 - .4byte .LASF327 + .2byte 0x254 + .4byte 0xbcf + .uleb128 0x3c + .4byte .LASF200 .byte 0x1 - .byte 0x33 - .4byte 0xf74 - .2byte 0x754 - .uleb128 0x14 - .4byte .LASF328 + .2byte 0x254 + .4byte 0x59 + .uleb128 0x3e + .string "f" .byte 0x1 - .byte 0x34 - .4byte 0xf74 - .2byte 0x854 - .byte 0 - .uleb128 0xa - .4byte 0xe1 - .4byte 0xf74 - .uleb128 0xe - .4byte 0xd4 - .byte 0xf - .byte 0 - .uleb128 0xa - .4byte 0x84 - .4byte 0xf84 - .uleb128 0xe - .4byte 0xd4 - .byte 0x3f - .byte 0 - .uleb128 0x29 - .4byte .LASF329 + .2byte 0x256 + .4byte 0x59 + .uleb128 0x2d + .4byte .LASF248 .byte 0x1 - .byte 0x38 - .4byte 0xf99 - .uleb128 0x9 - .byte 0x3 - .8byte global_waveform - .uleb128 0x8 - .byte 0x8 - .4byte 0xe4e - .uleb128 0xa - .4byte 0x84 - .4byte 0xfaf - .uleb128 0xe - .4byte 0xd4 - .byte 0xff + .2byte 0x257 + .4byte 0xbcf .byte 0 - .uleb128 0x29 - .4byte .LASF330 - .byte 0x1 - .byte 0x39 - .4byte 0xf9f - .uleb128 0x9 - .byte 0x3 - .8byte crc32_table - .uleb128 0x2a - .4byte .LASF364 + .uleb128 0x40 + .4byte .LASF272 .byte 0x1 - .2byte 0x1cd + .2byte 0x211 .4byte 0x59 - .8byte .LFB229 - .8byte .LFE229-.LFB229 + .8byte .LFB232 + .8byte .LFE232-.LFB232 .uleb128 0x1 .byte 0x9c - .4byte 0x14e4 - .uleb128 0x2b - .4byte .LASF331 - .byte 0x1 - .2byte 0x1cd - .4byte 0xe0d - .4byte .LLST35 - .uleb128 0x2b - .4byte .LASF332 - .byte 0x1 - .2byte 0x1cd - .4byte 0xd83 - .4byte .LLST36 - .uleb128 0x2b - .4byte .LASF333 + .4byte 0x1658 + .uleb128 0x2a + .4byte .LASF236 .byte 0x1 - .2byte 0x1cd - .4byte 0x59 - .4byte .LLST37 - .uleb128 0x2c - .4byte .LASF334 + .2byte 0x211 + .4byte 0x10f0 + .4byte .LLST26 + .uleb128 0x2a + .4byte .LASF237 .byte 0x1 - .2byte 0x1cf - .4byte 0xd83 - .uleb128 0x9 - .byte 0x3 - .8byte stype.6193 - .uleb128 0x2c - .4byte .LASF335 + .2byte 0x211 + .4byte 0xb11 + .4byte .LLST27 + .uleb128 0x2a + .4byte .LASF238 .byte 0x1 - .2byte 0x1d0 + .2byte 0x211 .4byte 0x59 - .uleb128 0x9 - .byte 0x3 - .8byte sftemp.6194 - .uleb128 0x2d - .string "ret" + .4byte .LLST28 + .uleb128 0x2e + .4byte .LASF200 .byte 0x1 - .2byte 0x1d1 + .2byte 0x213 .4byte 0x59 - .4byte .LLST38 - .uleb128 0x2e - .4byte 0x1cfb - .8byte .LBB104 - .8byte .LBE104-.LBB104 + .4byte .LLST29 + .uleb128 0x32 + .4byte 0x184e + .8byte .LBB88 + .4byte .Ldebug_ranges0+0x140 .byte 0x1 - .2byte 0x1e2 - .4byte 0x1085 - .uleb128 0x2f - .4byte 0x1d07 - .4byte .LLST39 + .2byte 0x218 + .4byte 0x154c .uleb128 0x30 - .8byte .LVL80 - .4byte 0x1d3a - .byte 0 - .uleb128 0x31 - .4byte 0x168a - .8byte .LBB106 - .4byte .Ldebug_ranges0+0x180 - .byte 0x1 - .2byte 0x1ef - .4byte 0x124c - .uleb128 0x2f - .4byte 0x16a7 - .4byte .LLST40 + .4byte 0x185f + .4byte .LLST30 + .uleb128 0x30 + .4byte 0x186b + .4byte .LLST31 + .uleb128 0x35 + .4byte .Ldebug_ranges0+0x140 + .uleb128 0x38 + .4byte 0x1877 + .uleb128 0x36 + .4byte 0x1883 + .4byte .LLST32 + .uleb128 0x36 + .4byte 0x188f + .4byte .LLST33 + .uleb128 0x36 + .4byte 0x189b + .4byte .LLST34 .uleb128 0x2f - .4byte 0x169b - .4byte .LLST41 - .uleb128 0x32 - .4byte .Ldebug_ranges0+0x180 - .uleb128 0x33 - .4byte 0x16b3 - .uleb128 0x34 - .4byte 0x16bf - .4byte .LLST42 - .uleb128 0x34 - .4byte 0x16cb - .4byte .LLST43 - .uleb128 0x34 - .4byte 0x16d7 - .4byte .LLST44 - .uleb128 0x31 - .4byte 0x1750 - .8byte .LBB108 - .4byte .Ldebug_ranges0+0x1b0 + .4byte 0x19f9 + .8byte .LBB90 + .8byte .LBE90-.LBB90 .byte 0x1 - .2byte 0x152 - .4byte 0x11bd - .uleb128 0x2f - .4byte 0x1761 - .4byte .LLST45 + .2byte 0x16a + .4byte 0x13b9 + .uleb128 0x30 + .4byte 0x1a0a + .4byte .LLST35 + .byte 0 .uleb128 0x32 - .4byte .Ldebug_ranges0+0x1b0 - .uleb128 0x34 - .4byte 0x176d - .4byte .LLST46 - .uleb128 0x33 - .4byte 0x1779 - .uleb128 0x34 - .4byte 0x1785 - .4byte .LLST47 - .uleb128 0x34 - .4byte 0x178f - .4byte .LLST48 - .uleb128 0x34 - .4byte 0x1799 - .4byte .LLST49 - .uleb128 0x34 - .4byte 0x17a3 - .4byte .LLST50 - .uleb128 0x34 - .4byte 0x17ad - .4byte .LLST51 - .uleb128 0x34 - .4byte 0x17b9 - .4byte .LLST52 - .uleb128 0x34 - .4byte 0x17c5 - .4byte .LLST53 - .uleb128 0x2e - .4byte 0x1d13 - .8byte .LBB110 - .8byte .LBE110-.LBB110 + .4byte 0x18a8 + .8byte .LBB92 + .4byte .Ldebug_ranges0+0x170 .byte 0x1 - .2byte 0x10f - .4byte 0x1197 - .uleb128 0x2f - .4byte 0x1d2e - .4byte .LLST54 - .uleb128 0x2f - .4byte 0x1d23 - .4byte .LLST55 + .2byte 0x175 + .4byte 0x14a2 + .uleb128 0x30 + .4byte 0x18b9 + .4byte .LLST36 .uleb128 0x35 - .8byte .LVL91 - .4byte 0x1d46 + .4byte .Ldebug_ranges0+0x170 + .uleb128 0x36 + .4byte 0x18c5 + .4byte .LLST37 + .uleb128 0x38 + .4byte 0x18d1 + .uleb128 0x36 + .4byte 0x18dd + .4byte .LLST38 + .uleb128 0x36 + .4byte 0x18e7 + .4byte .LLST39 + .uleb128 0x36 + .4byte 0x18f1 + .4byte .LLST40 .uleb128 0x36 + .4byte 0x18fb + .4byte .LLST41 + .uleb128 0x36 + .4byte 0x1905 + .4byte .LLST42 + .uleb128 0x36 + .4byte 0x1911 + .4byte .LLST43 + .uleb128 0x36 + .4byte 0x191d + .4byte .LLST44 + .uleb128 0x2f + .4byte 0x1f1c + .8byte .LBB94 + .8byte .LBE94-.LBB94 + .byte 0x1 + .2byte 0x129 + .4byte 0x147c + .uleb128 0x30 + .4byte 0x1f37 + .4byte .LLST45 + .uleb128 0x30 + .4byte 0x1f2c + .4byte .LLST46 + .uleb128 0x33 + .8byte .LVL71 + .4byte 0x2054 + .uleb128 0x34 .uleb128 0x1 .byte 0x50 .uleb128 0x8 - .byte 0x84 + .byte 0x85 .sleb128 0 .byte 0x3a .byte 0x24 .byte 0xa .2byte 0x7c00 .byte 0x1a - .uleb128 0x36 + .uleb128 0x34 .uleb128 0x1 .byte 0x51 .uleb128 0x3 @@ -3168,687 +3909,560 @@ stype.6193: .2byte 0x8000 .byte 0 .byte 0 - .uleb128 0x37 - .8byte .LBB112 - .8byte .LBE112-.LBB112 - .uleb128 0x34 - .4byte 0x17d2 - .4byte .LLST56 - .uleb128 0x34 - .4byte 0x17de - .4byte .LLST57 + .uleb128 0x41 + .8byte .LBB96 + .8byte .LBE96-.LBB96 + .uleb128 0x36 + .4byte 0x192a + .4byte .LLST47 + .uleb128 0x36 + .4byte 0x1936 + .4byte .LLST48 .byte 0 .byte 0 .byte 0 - .uleb128 0x2e - .4byte 0x1cfb - .8byte .LBB114 - .8byte .LBE114-.LBB114 - .byte 0x1 - .2byte 0x154 - .4byte 0x11f7 .uleb128 0x2f - .4byte 0x1d07 - .4byte .LLST58 - .uleb128 0x35 - .8byte .LVL95 - .4byte 0x1d3a - .uleb128 0x36 + .4byte 0x1f04 + .8byte .LBB98 + .8byte .LBE98-.LBB98 + .byte 0x1 + .2byte 0x177 + .4byte 0x14dc + .uleb128 0x30 + .4byte 0x1f10 + .4byte .LLST49 + .uleb128 0x33 + .8byte .LVL75 + .4byte 0x2048 + .uleb128 0x34 .uleb128 0x1 .byte 0x50 .uleb128 0x2 - .byte 0x85 - .sleb128 0 - .byte 0 - .byte 0 - .uleb128 0x2e - .4byte 0x1cfb - .8byte .LBB117 - .8byte .LBE117-.LBB117 - .byte 0x1 - .2byte 0x158 - .4byte 0x121d - .uleb128 0x2f - .4byte 0x1d07 - .4byte .LLST59 - .byte 0 - .uleb128 0x38 - .8byte .LVL83 - .4byte 0x18b8 - .4byte 0x1234 - .uleb128 0x36 - .uleb128 0x1 - .byte 0x51 - .uleb128 0x1 - .byte 0x30 - .byte 0 - .uleb128 0x35 - .8byte .LVL87 - .4byte 0x17ec - .uleb128 0x36 - .uleb128 0x1 - .byte 0x51 - .uleb128 0x4 - .byte 0x84 + .byte 0x86 .sleb128 0 - .byte 0x32 - .byte 0x24 .byte 0 .byte 0 - .byte 0 - .uleb128 0x31 - .4byte 0x1532 - .8byte .LBB121 - .4byte .Ldebug_ranges0+0x1e0 - .byte 0x1 - .2byte 0x219 - .4byte 0x13c6 - .uleb128 0x2f - .4byte 0x154f - .4byte .LLST60 .uleb128 0x2f - .4byte 0x1543 - .4byte .LLST61 - .uleb128 0x32 - .4byte .Ldebug_ranges0+0x1e0 - .uleb128 0x33 - .4byte 0x155b - .uleb128 0x34 - .4byte 0x1567 - .4byte .LLST62 - .uleb128 0x34 - .4byte 0x1573 - .4byte .LLST63 - .uleb128 0x34 - .4byte 0x157f - .4byte .LLST64 - .uleb128 0x2e - .4byte 0x1cfb - .8byte .LBB123 - .8byte .LBE123-.LBB123 + .4byte 0x1f04 + .8byte .LBB101 + .8byte .LBE101-.LBB101 .byte 0x1 - .2byte 0x1aa - .4byte 0x12ce - .uleb128 0x2f - .4byte 0x1d07 - .4byte .LLST65 + .2byte 0x17b + .4byte 0x1516 .uleb128 0x30 - .8byte .LVL113 - .4byte 0x1d3a - .byte 0 - .uleb128 0x2e - .4byte 0x189c - .8byte .LBB125 - .8byte .LBE125-.LBB125 - .byte 0x1 - .2byte 0x19c - .4byte 0x12f4 - .uleb128 0x2f - .4byte 0x18ac - .4byte .LLST66 - .byte 0 - .uleb128 0x2e - .4byte 0x16e4 - .8byte .LBB127 - .8byte .LBE127-.LBB127 - .byte 0x1 - .2byte 0x1a8 - .4byte 0x1367 - .uleb128 0x2f - .4byte 0x16fd - .4byte .LLST67 - .uleb128 0x2f - .4byte 0x16f1 - .4byte .LLST68 - .uleb128 0x37 - .8byte .LBB128 - .8byte .LBE128-.LBB128 + .4byte 0x1f10 + .4byte .LLST50 .uleb128 0x33 - .4byte 0x1709 - .uleb128 0x34 - .4byte 0x1715 - .4byte .LLST69 - .uleb128 0x34 - .4byte 0x1721 - .4byte .LLST70 - .uleb128 0x34 - .4byte 0x172d - .4byte .LLST71 - .uleb128 0x34 - .4byte 0x1739 - .4byte .LLST72 + .8byte .LVL92 + .4byte 0x2048 .uleb128 0x34 - .4byte 0x1745 - .4byte .LLST73 - .byte 0 - .byte 0 - .uleb128 0x38 - .8byte .LVL128 - .4byte 0x18b8 - .4byte 0x1384 - .uleb128 0x36 .uleb128 0x1 .byte 0x50 .uleb128 0x2 - .byte 0x84 + .byte 0x86 .sleb128 0 - .uleb128 0x36 - .uleb128 0x1 - .byte 0x51 - .uleb128 0x1 - .byte 0x32 .byte 0 - .uleb128 0x30 - .8byte .LVL132 - .4byte 0x17ec - .uleb128 0x38 - .8byte .LVL133 - .4byte 0x18b8 - .4byte 0x13ae - .uleb128 0x36 + .byte 0 + .uleb128 0x39 + .8byte .LVL64 + .4byte 0x1a17 + .4byte 0x1534 + .uleb128 0x34 .uleb128 0x1 .byte 0x50 - .uleb128 0x2 - .byte 0x84 - .sleb128 0 - .uleb128 0x36 + .uleb128 0x3 + .byte 0xf3 + .uleb128 0x1 + .byte 0x52 + .uleb128 0x34 .uleb128 0x1 .byte 0x51 .uleb128 0x1 - .byte 0x31 + .byte 0x30 .byte 0 - .uleb128 0x35 - .8byte .LVL137 - .4byte 0x17ec - .uleb128 0x36 + .uleb128 0x33 + .8byte .LVL68 + .4byte 0x1944 + .uleb128 0x34 .uleb128 0x1 .byte 0x51 .uleb128 0x4 - .byte 0x84 + .byte 0x85 .sleb128 0 - .byte 0x36 + .byte 0x32 .byte 0x24 .byte 0 .byte 0 .byte 0 - .uleb128 0x2e - .4byte 0x158c - .8byte .LBB130 - .8byte .LBE130-.LBB130 - .byte 0x1 - .2byte 0x213 - .4byte 0x144f - .uleb128 0x2f - .4byte 0x15a9 - .4byte .LLST74 .uleb128 0x2f - .4byte 0x159d - .4byte .LLST75 - .uleb128 0x37 - .8byte .LBB131 - .8byte .LBE131-.LBB131 - .uleb128 0x34 - .4byte 0x15b5 - .4byte .LLST76 - .uleb128 0x34 - .4byte 0x15c1 - .4byte .LLST77 - .uleb128 0x34 - .4byte 0x15cd - .4byte .LLST78 - .uleb128 0x38 - .8byte .LVL121 - .4byte 0x18b8 - .4byte 0x1437 + .4byte 0x17a6 + .8byte .LBB105 + .8byte .LBE105-.LBB105 + .byte 0x1 + .2byte 0x23c + .4byte 0x15e8 + .uleb128 0x30 + .4byte 0x17b7 + .4byte .LLST51 + .uleb128 0x30 + .4byte 0x17c3 + .4byte .LLST52 + .uleb128 0x41 + .8byte .LBB106 + .8byte .LBE106-.LBB106 .uleb128 0x36 - .uleb128 0x1 - .byte 0x51 - .uleb128 0x1 - .byte 0x31 - .byte 0 - .uleb128 0x35 - .8byte .LVL124 - .4byte 0x17ec + .4byte 0x17cf + .4byte .LLST53 .uleb128 0x36 - .uleb128 0x1 - .byte 0x51 - .uleb128 0x4 - .byte 0x84 - .sleb128 0 - .byte 0x36 - .byte 0x24 + .4byte 0x17db + .4byte .LLST54 + .uleb128 0x36 + .4byte 0x17e7 + .4byte .LLST55 + .uleb128 0x2f + .4byte 0x19f9 + .8byte .LBB107 + .8byte .LBE107-.LBB107 + .byte 0x1 + .2byte 0x19a + .4byte 0x15cc + .uleb128 0x30 + .4byte 0x1a0a + .4byte .LLST56 .byte 0 + .uleb128 0x31 + .8byte .LVL99 + .4byte 0x1a17 + .uleb128 0x31 + .8byte .LVL103 + .4byte 0x1944 .byte 0 .byte 0 - .uleb128 0x2e - .4byte 0x14e4 - .8byte .LBB133 - .8byte .LBE133-.LBB133 - .byte 0x1 - .2byte 0x21f - .4byte 0x14cf .uleb128 0x2f - .4byte 0x1501 - .4byte .LLST79 - .uleb128 0x2f - .4byte 0x14f5 - .4byte .LLST80 - .uleb128 0x37 - .8byte .LBB134 - .8byte .LBE134-.LBB134 - .uleb128 0x34 - .4byte 0x150d - .4byte .LLST81 - .uleb128 0x34 - .4byte 0x1519 - .4byte .LLST82 - .uleb128 0x34 - .4byte 0x1525 - .4byte .LLST83 - .uleb128 0x38 - .8byte .LVL151 - .4byte 0x18b8 - .4byte 0x14c0 - .uleb128 0x36 + .4byte 0x1758 + .8byte .LBB109 + .8byte .LBE109-.LBB109 + .byte 0x1 + .2byte 0x248 + .4byte 0x1634 + .uleb128 0x42 + .4byte 0x1769 .uleb128 0x1 - .byte 0x51 + .byte 0x64 + .uleb128 0x42 + .4byte 0x1775 .uleb128 0x1 - .byte 0x36 - .byte 0 - .uleb128 0x30 - .8byte .LVL155 - .4byte 0x17ec + .byte 0x50 + .uleb128 0x41 + .8byte .LBB110 + .8byte .LBE110-.LBB110 + .uleb128 0x38 + .4byte 0x1781 + .uleb128 0x38 + .4byte 0x178d + .uleb128 0x38 + .4byte 0x1799 .byte 0 .byte 0 - .uleb128 0x35 - .8byte .LVL115 - .4byte 0x15da - .uleb128 0x36 + .uleb128 0x33 + .8byte .LVL95 + .4byte 0x1fa7 + .uleb128 0x34 + .uleb128 0x1 + .byte 0x50 + .uleb128 0x2 + .byte 0x84 + .sleb128 8 + .uleb128 0x34 + .uleb128 0x1 + .byte 0x51 + .uleb128 0x3 + .byte 0xf3 .uleb128 0x1 - .byte 0x50 + .byte 0x52 + .uleb128 0x3a + .4byte 0x1805 .uleb128 0x2 - .byte 0x83 + .byte 0x84 .sleb128 0 .byte 0 .byte 0 - .uleb128 0x39 - .4byte .LASF338 + .uleb128 0x3b + .4byte .LASF254 .byte 0x1 - .2byte 0x1af + .2byte 0x1ff .4byte 0x59 .byte 0x1 - .4byte 0x1532 - .uleb128 0x3a - .4byte .LASF331 + .4byte 0x16cc + .uleb128 0x3c + .4byte .LASF201 .byte 0x1 - .2byte 0x1af - .4byte 0xe0d - .uleb128 0x3a - .4byte .LASF336 + .2byte 0x1ff + .4byte 0x10f0 + .uleb128 0x3c + .4byte .LASF202 + .byte 0x1 + .2byte 0x1ff + .4byte 0xbcf + .uleb128 0x3c + .4byte .LASF200 .byte 0x1 - .2byte 0x1af + .2byte 0x1ff .4byte 0x59 - .uleb128 0x3b - .4byte .LASF337 + .uleb128 0x3e + .string "i" .byte 0x1 - .2byte 0x1b1 - .4byte 0x4df - .uleb128 0x3b - .4byte .LASF298 + .2byte 0x201 + .4byte 0x59 + .uleb128 0x2d + .4byte .LASF255 .byte 0x1 - .2byte 0x1b2 - .4byte 0x84 - .uleb128 0x3b - .4byte .LASF309 + .2byte 0x202 + .4byte 0xa8 + .uleb128 0x2d + .4byte .LASF256 .byte 0x1 - .2byte 0x1b3 - .4byte 0x84 + .2byte 0x202 + .4byte 0xa8 + .uleb128 0x3f + .uleb128 0x2d + .4byte .LASF244 + .byte 0x1 + .2byte 0x205 + .4byte 0xbb9 + .uleb128 0x3f + .uleb128 0x2d + .4byte .LASF257 + .byte 0x1 + .2byte 0x208 + .4byte 0x99 .byte 0 - .uleb128 0x39 - .4byte .LASF339 + .byte 0 + .byte 0 + .uleb128 0x3b + .4byte .LASF258 .byte 0x1 - .2byte 0x186 + .2byte 0x1df .4byte 0x59 .byte 0x1 - .4byte 0x158c - .uleb128 0x3a - .4byte .LASF331 + .4byte 0x1758 + .uleb128 0x3c + .4byte .LASF201 .byte 0x1 - .2byte 0x186 - .4byte 0xe0d - .uleb128 0x3a - .4byte .LASF336 + .2byte 0x1df + .4byte 0x10f0 + .uleb128 0x3c + .4byte .LASF202 .byte 0x1 - .2byte 0x186 + .2byte 0x1df + .4byte 0xbcf + .uleb128 0x3c + .4byte .LASF200 + .byte 0x1 + .2byte 0x1df .4byte 0x59 - .uleb128 0x3b - .4byte .LASF340 + .uleb128 0x3e + .string "i" .byte 0x1 - .2byte 0x188 - .4byte 0xde2 - .uleb128 0x3b - .4byte .LASF337 + .2byte 0x1e1 + .4byte 0x59 + .uleb128 0x2d + .4byte .LASF255 .byte 0x1 - .2byte 0x189 - .4byte 0x4df - .uleb128 0x3b - .4byte .LASF298 + .2byte 0x1e2 + .4byte 0xa8 + .uleb128 0x2d + .4byte .LASF256 .byte 0x1 - .2byte 0x18a - .4byte 0x84 - .uleb128 0x3b - .4byte .LASF309 + .2byte 0x1e2 + .4byte 0xa8 + .uleb128 0x2d + .4byte .LASF259 .byte 0x1 - .2byte 0x18b - .4byte 0x84 + .2byte 0x1e3 + .4byte 0x99 + .uleb128 0x3f + .uleb128 0x2d + .4byte .LASF244 + .byte 0x1 + .2byte 0x1e6 + .4byte 0xbb9 + .uleb128 0x3f + .uleb128 0x3e + .string "tmp" + .byte 0x1 + .2byte 0x1e9 + .4byte 0xbb9 + .uleb128 0x2d + .4byte .LASF257 + .byte 0x1 + .2byte 0x1ea + .4byte 0x99 .byte 0 - .uleb128 0x39 - .4byte .LASF341 + .byte 0 + .byte 0 + .uleb128 0x3b + .4byte .LASF260 .byte 0x1 - .2byte 0x171 + .2byte 0x1cd .4byte 0x59 .byte 0x1 - .4byte 0x15da - .uleb128 0x3a - .4byte .LASF331 + .4byte 0x17a6 + .uleb128 0x3c + .4byte .LASF236 .byte 0x1 - .2byte 0x171 - .4byte 0xe0d - .uleb128 0x3a - .4byte .LASF336 + .2byte 0x1cd + .4byte 0x10f0 + .uleb128 0x3c + .4byte .LASF261 .byte 0x1 - .2byte 0x171 + .2byte 0x1cd .4byte 0x59 - .uleb128 0x3b - .4byte .LASF337 + .uleb128 0x2d + .4byte .LASF262 .byte 0x1 - .2byte 0x173 - .4byte 0x4df - .uleb128 0x3b - .4byte .LASF298 + .2byte 0x1cf + .4byte 0x4d3 + .uleb128 0x2d + .4byte .LASF200 .byte 0x1 - .2byte 0x174 + .2byte 0x1d0 .4byte 0x84 - .uleb128 0x3b - .4byte .LASF309 + .uleb128 0x2d + .4byte .LASF212 .byte 0x1 - .2byte 0x175 + .2byte 0x1d1 .4byte 0x84 .byte 0 - .uleb128 0x3c - .4byte .LASF349 + .uleb128 0x3b + .4byte .LASF263 .byte 0x1 - .2byte 0x15c + .2byte 0x192 .4byte 0x59 - .8byte .LFB225 - .8byte .LFE225-.LFB225 - .uleb128 0x1 - .byte 0x9c - .4byte 0x168a - .uleb128 0x2b - .4byte .LASF331 .byte 0x1 - .2byte 0x15c - .4byte 0xe0d - .4byte .LLST16 - .uleb128 0x2b - .4byte .LASF336 + .4byte 0x17f4 + .uleb128 0x3c + .4byte .LASF236 .byte 0x1 - .2byte 0x15c - .4byte 0x59 - .4byte .LLST17 - .uleb128 0x2b - .4byte .LASF332 + .2byte 0x192 + .4byte 0x10f0 + .uleb128 0x3c + .4byte .LASF261 .byte 0x1 - .2byte 0x15c - .4byte 0xe13 - .4byte .LLST18 - .uleb128 0x3d - .4byte .LASF337 + .2byte 0x192 + .4byte 0x59 + .uleb128 0x2d + .4byte .LASF262 .byte 0x1 - .2byte 0x15e - .4byte 0x4df - .4byte .LLST19 - .uleb128 0x3d - .4byte .LASF298 + .2byte 0x194 + .4byte 0x4d3 + .uleb128 0x2d + .4byte .LASF200 .byte 0x1 - .2byte 0x15f + .2byte 0x195 .4byte 0x84 - .4byte .LLST20 - .uleb128 0x3d - .4byte .LASF309 + .uleb128 0x2d + .4byte .LASF212 .byte 0x1 - .2byte 0x160 + .2byte 0x196 .4byte 0x84 - .4byte .LLST21 - .uleb128 0x38 - .8byte .LVL45 - .4byte 0x18b8 - .4byte 0x167c - .uleb128 0x36 - .uleb128 0x1 - .byte 0x50 - .uleb128 0x3 - .byte 0xf3 - .uleb128 0x1 - .byte 0x51 - .uleb128 0x36 - .uleb128 0x1 - .byte 0x51 - .uleb128 0x3 - .byte 0xf3 - .uleb128 0x1 - .byte 0x52 - .byte 0 - .uleb128 0x30 - .8byte .LVL49 - .4byte 0x17ec .byte 0 - .uleb128 0x39 - .4byte .LASF342 + .uleb128 0x3b + .4byte .LASF264 .byte 0x1 - .2byte 0x13d + .2byte 0x17f .4byte 0x59 .byte 0x1 - .4byte 0x16e4 - .uleb128 0x3a - .4byte .LASF331 + .4byte 0x184e + .uleb128 0x3c + .4byte .LASF236 .byte 0x1 - .2byte 0x13d - .4byte 0xe0d - .uleb128 0x3a - .4byte .LASF336 + .2byte 0x17f + .4byte 0x10f0 + .uleb128 0x3c + .4byte .LASF261 .byte 0x1 - .2byte 0x13d + .2byte 0x17f .4byte 0x59 - .uleb128 0x3b - .4byte .LASF340 + .uleb128 0x3c + .4byte .LASF237 .byte 0x1 - .2byte 0x13f - .4byte 0xde2 - .uleb128 0x3b - .4byte .LASF337 + .2byte 0x17f + .4byte 0xbe0 + .uleb128 0x2d + .4byte .LASF262 .byte 0x1 - .2byte 0x140 - .4byte 0x4df - .uleb128 0x3b - .4byte .LASF298 + .2byte 0x181 + .4byte 0x4d3 + .uleb128 0x2d + .4byte .LASF200 .byte 0x1 - .2byte 0x141 + .2byte 0x182 .4byte 0x84 - .uleb128 0x3b - .4byte .LASF309 + .uleb128 0x2d + .4byte .LASF212 .byte 0x1 - .2byte 0x142 + .2byte 0x183 .4byte 0x84 .byte 0 - .uleb128 0x3e - .4byte .LASF375 - .byte 0x1 - .2byte 0x124 - .byte 0x1 - .4byte 0x1750 - .uleb128 0x3a - .4byte .LASF340 - .byte 0x1 - .2byte 0x124 - .4byte 0xe0d - .uleb128 0x3a - .4byte .LASF331 - .byte 0x1 - .2byte 0x125 - .4byte 0xe0d .uleb128 0x3b - .4byte .LASF343 + .4byte .LASF265 .byte 0x1 - .2byte 0x127 + .2byte 0x161 .4byte 0x59 - .uleb128 0x3b - .4byte .LASF344 .byte 0x1 - .2byte 0x128 - .4byte 0xe07 - .uleb128 0x3b - .4byte .LASF345 + .4byte 0x18a8 + .uleb128 0x3c + .4byte .LASF236 .byte 0x1 - .2byte 0x128 - .4byte 0xe07 - .uleb128 0x3b - .4byte .LASF336 + .2byte 0x161 + .4byte 0x10f0 + .uleb128 0x3c + .4byte .LASF261 .byte 0x1 - .2byte 0x129 + .2byte 0x161 .4byte 0x59 - .uleb128 0x3b - .4byte .LASF346 + .uleb128 0x2d + .4byte .LASF266 .byte 0x1 - .2byte 0x129 - .4byte 0x59 - .uleb128 0x3f - .string "i" + .2byte 0x163 + .4byte 0xb88 + .uleb128 0x2d + .4byte .LASF262 + .byte 0x1 + .2byte 0x164 + .4byte 0x4d3 + .uleb128 0x2d + .4byte .LASF200 + .byte 0x1 + .2byte 0x165 + .4byte 0x84 + .uleb128 0x2d + .4byte .LASF212 .byte 0x1 - .2byte 0x12a - .4byte 0x59 + .2byte 0x166 + .4byte 0x84 .byte 0 - .uleb128 0x39 - .4byte .LASF347 + .uleb128 0x3b + .4byte .LASF267 .byte 0x1 - .2byte 0x104 - .4byte 0xe07 + .2byte 0x11e + .4byte 0xbb9 .byte 0x1 - .4byte 0x17ec - .uleb128 0x3a - .4byte .LASF340 + .4byte 0x1944 + .uleb128 0x3c + .4byte .LASF266 .byte 0x1 - .2byte 0x104 - .4byte 0xe0d - .uleb128 0x3b - .4byte .LASF344 + .2byte 0x11e + .4byte 0x10f0 + .uleb128 0x2d + .4byte .LASF268 .byte 0x1 - .2byte 0x106 - .4byte 0xe07 - .uleb128 0x3b - .4byte .LASF345 + .2byte 0x120 + .4byte 0xbb9 + .uleb128 0x2d + .4byte .LASF269 .byte 0x1 - .2byte 0x106 - .4byte 0xe07 - .uleb128 0x3f + .2byte 0x120 + .4byte 0xbb9 + .uleb128 0x3e .string "i" .byte 0x1 - .2byte 0x107 + .2byte 0x121 .4byte 0x59 - .uleb128 0x3f + .uleb128 0x3e .string "j" .byte 0x1 - .2byte 0x107 + .2byte 0x121 .4byte 0x59 - .uleb128 0x3f + .uleb128 0x3e .string "k" .byte 0x1 - .2byte 0x107 + .2byte 0x121 .4byte 0x59 - .uleb128 0x3f + .uleb128 0x3e .string "h" .byte 0x1 - .2byte 0x107 + .2byte 0x121 .4byte 0x59 - .uleb128 0x3b - .4byte .LASF348 + .uleb128 0x2d + .4byte .LASF270 .byte 0x1 - .2byte 0x108 + .2byte 0x122 .4byte 0x59 - .uleb128 0x3f + .uleb128 0x3e .string "num" .byte 0x1 - .2byte 0x109 + .2byte 0x123 .4byte 0x59 - .uleb128 0x3f + .uleb128 0x3e .string "len" .byte 0x1 - .2byte 0x10a + .2byte 0x124 .4byte 0x59 - .uleb128 0x40 - .uleb128 0x3b - .4byte .LASF336 + .uleb128 0x3f + .uleb128 0x2d + .4byte .LASF261 .byte 0x1 - .2byte 0x116 + .2byte 0x130 .4byte 0x59 - .uleb128 0x3b - .4byte .LASF346 + .uleb128 0x2d + .4byte .LASF271 .byte 0x1 - .2byte 0x117 + .2byte 0x131 .4byte 0x59 .byte 0 .byte 0 - .uleb128 0x41 - .4byte .LASF350 + .uleb128 0x40 + .4byte .LASF273 .byte 0x1 - .byte 0xf6 - .4byte 0xe07 - .8byte .LFB221 - .8byte .LFE221-.LFB221 + .2byte 0x110 + .4byte 0xbb9 + .8byte .LFB224 + .8byte .LFE224-.LFB224 .uleb128 0x1 .byte 0x9c - .4byte 0x189c - .uleb128 0x42 - .4byte .LASF337 + .4byte 0x19f9 + .uleb128 0x2a + .4byte .LASF262 .byte 0x1 - .byte 0xf6 - .4byte 0x4df + .2byte 0x110 + .4byte 0x4d3 .4byte .LLST12 - .uleb128 0x42 - .4byte .LASF309 + .uleb128 0x2a + .4byte .LASF212 .byte 0x1 - .byte 0xf7 + .2byte 0x111 .4byte 0x84 .4byte .LLST13 - .uleb128 0x43 + .uleb128 0x3e .string "out" .byte 0x1 - .byte 0xf9 - .4byte 0x4e5 - .uleb128 0x44 - .4byte 0x1d13 - .8byte .LBB39 + .2byte 0x113 + .4byte 0x4d9 + .uleb128 0x32 + .4byte 0x1f1c + .8byte .LBB55 .4byte .Ldebug_ranges0+0x90 .byte 0x1 - .byte 0xfb - .4byte 0x187b - .uleb128 0x2f - .4byte 0x1d2e + .2byte 0x115 + .4byte 0x19d8 + .uleb128 0x30 + .4byte 0x1f37 .4byte .LLST14 - .uleb128 0x2f - .4byte 0x1d23 + .uleb128 0x30 + .4byte 0x1f2c .4byte .LLST15 - .uleb128 0x35 + .uleb128 0x33 .8byte .LVL37 - .4byte 0x1d46 - .uleb128 0x36 + .4byte 0x2054 + .uleb128 0x34 .uleb128 0x1 .byte 0x50 .uleb128 0x2 .byte 0x84 .sleb128 0 - .uleb128 0x36 + .uleb128 0x34 .uleb128 0x1 .byte 0x51 .uleb128 0x3 @@ -3856,22 +4470,22 @@ stype.6193: .2byte 0x8000 .byte 0 .byte 0 - .uleb128 0x35 + .uleb128 0x33 .8byte .LVL39 - .4byte 0x1d51 - .uleb128 0x36 + .4byte 0x2076 + .uleb128 0x34 .uleb128 0x1 .byte 0x50 .uleb128 0x2 .byte 0x83 .sleb128 0 - .uleb128 0x36 + .uleb128 0x34 .uleb128 0x1 .byte 0x51 .uleb128 0x2 .byte 0x85 .sleb128 4 - .uleb128 0x36 + .uleb128 0x34 .uleb128 0x1 .byte 0x52 .uleb128 0x2 @@ -3879,329 +4493,412 @@ stype.6193: .sleb128 0 .byte 0 .byte 0 - .uleb128 0x45 - .4byte .LASF351 + .uleb128 0x3b + .4byte .LASF274 .byte 0x1 - .byte 0xf1 + .2byte 0x10b .4byte 0x34 .byte 0x3 - .4byte 0x18b8 - .uleb128 0x46 - .4byte .LASF337 + .4byte 0x1a17 + .uleb128 0x3c + .4byte .LASF262 .byte 0x1 - .byte 0xf1 - .4byte 0x4df + .2byte 0x10b + .4byte 0x4d3 .byte 0 - .uleb128 0x41 - .4byte .LASF352 + .uleb128 0x43 + .4byte .LASF275 .byte 0x1 - .byte 0xc0 - .4byte 0x4df - .8byte .LFB219 - .8byte .LFE219-.LFB219 + .byte 0xda + .4byte 0x4d3 + .8byte .LFB222 + .8byte .LFE222-.LFB222 .uleb128 0x1 .byte 0x9c - .4byte 0x19b5 - .uleb128 0x42 - .4byte .LASF336 + .4byte 0x1b15 + .uleb128 0x44 + .4byte .LASF261 .byte 0x1 - .byte 0xc0 + .byte 0xda .4byte 0x59 .4byte .LLST0 - .uleb128 0x42 - .4byte .LASF353 + .uleb128 0x44 + .4byte .LASF276 .byte 0x1 - .byte 0xc0 + .byte 0xda .4byte 0x59 .4byte .LLST1 - .uleb128 0x29 - .4byte .LASF354 + .uleb128 0x28 + .4byte .LASF277 .byte 0x1 - .byte 0xc2 - .4byte 0xf99 + .byte 0xdc + .4byte 0xd56 .uleb128 0x1 .byte 0x52 - .uleb128 0x47 - .4byte .LASF355 + .uleb128 0x45 + .4byte .LASF278 .byte 0x1 - .byte 0xc3 - .4byte 0xe07 + .byte 0xdd + .4byte 0xbb9 .4byte .LLST2 - .uleb128 0x47 - .4byte .LASF356 + .uleb128 0x45 + .4byte .LASF279 .byte 0x1 - .byte 0xc4 + .byte 0xde .4byte 0xff .4byte .LLST3 - .uleb128 0x47 - .4byte .LASF357 + .uleb128 0x45 + .4byte .LASF280 .byte 0x1 - .byte 0xc5 + .byte 0xdf .4byte 0x84 .4byte .LLST4 - .uleb128 0x48 + .uleb128 0x46 .string "pt" .byte 0x1 - .byte 0xc6 + .byte 0xe0 .4byte 0x84 .4byte .LLST5 - .uleb128 0x49 - .4byte .LASF337 + .uleb128 0x27 + .4byte .LASF262 .byte 0x1 - .byte 0xc7 + .byte 0xe1 .4byte 0x147 - .uleb128 0x4a - .4byte 0x19b5 - .8byte .LBB31 + .uleb128 0x47 + .4byte 0x1b15 + .8byte .LBB47 .4byte .Ldebug_ranges0+0 .byte 0x1 - .byte 0xea - .uleb128 0x2f - .4byte 0x19d0 + .2byte 0x104 + .uleb128 0x30 + .4byte 0x1b30 .4byte .LLST6 - .uleb128 0x2f - .4byte 0x19c5 + .uleb128 0x30 + .4byte 0x1b25 .4byte .LLST7 - .uleb128 0x32 + .uleb128 0x35 .4byte .Ldebug_ranges0+0 - .uleb128 0x34 - .4byte 0x19db + .uleb128 0x36 + .4byte 0x1b3b .4byte .LLST8 - .uleb128 0x34 - .4byte 0x19e6 + .uleb128 0x36 + .4byte 0x1b46 .4byte .LLST9 - .uleb128 0x4b + .uleb128 0x48 .4byte .Ldebug_ranges0+0x30 - .4byte 0x199a - .uleb128 0x33 - .4byte 0x19f4 - .uleb128 0x33 - .4byte 0x19ff + .4byte 0x1afa + .uleb128 0x38 + .4byte 0x1b54 + .uleb128 0x38 + .4byte 0x1b5f .byte 0 - .uleb128 0x32 + .uleb128 0x35 .4byte .Ldebug_ranges0+0x60 - .uleb128 0x34 - .4byte 0x1a0c + .uleb128 0x36 + .4byte 0x1b6c .4byte .LLST10 - .uleb128 0x34 - .4byte 0x1a17 + .uleb128 0x36 + .4byte 0x1b77 .4byte .LLST11 .byte 0 .byte 0 .byte 0 .byte 0 - .uleb128 0x45 - .4byte .LASF358 + .uleb128 0x49 + .4byte .LASF281 .byte 0x1 - .byte 0xab + .byte 0xc8 .4byte 0x59 .byte 0x1 - .4byte 0x1a24 - .uleb128 0x46 - .4byte .LASF355 + .4byte 0x1b84 + .uleb128 0x4a + .4byte .LASF278 .byte 0x1 - .byte 0xab + .byte 0xc8 .4byte 0xff - .uleb128 0x46 - .4byte .LASF336 + .uleb128 0x4a + .4byte .LASF261 .byte 0x1 - .byte 0xab + .byte 0xc8 .4byte 0x59 - .uleb128 0x49 - .4byte .LASF359 + .uleb128 0x27 + .4byte .LASF282 .byte 0x1 - .byte 0xad + .byte 0xca .4byte 0x59 - .uleb128 0x43 + .uleb128 0x4b .string "i" .byte 0x1 - .byte 0xae + .byte 0xcb .4byte 0x59 .uleb128 0x4c - .4byte 0x1a0b - .uleb128 0x49 - .4byte .LASF360 + .4byte 0x1b6b + .uleb128 0x27 + .4byte .LASF283 .byte 0x1 - .byte 0xb0 + .byte 0xcd .4byte 0x59 - .uleb128 0x49 - .4byte .LASF361 + .uleb128 0x27 + .4byte .LASF284 .byte 0x1 - .byte 0xb0 + .byte 0xcd .4byte 0x59 .byte 0 - .uleb128 0x40 - .uleb128 0x49 - .4byte .LASF362 + .uleb128 0x3f + .uleb128 0x27 + .4byte .LASF285 .byte 0x1 - .byte 0xb1 + .byte 0xce .4byte 0x59 - .uleb128 0x49 - .4byte .LASF363 + .uleb128 0x27 + .4byte .LASF286 .byte 0x1 - .byte 0xb1 + .byte 0xce .4byte 0x59 .byte 0 .byte 0 .uleb128 0x4d - .4byte .LASF394 + .4byte .LASF318 .byte 0x1 - .byte 0xa2 + .byte 0xc0 .4byte 0xdb - .8byte .LFB217 - .8byte .LFE217-.LFB217 + .8byte .LFB220 + .8byte .LFE220-.LFB220 + .uleb128 0x1 + .byte 0x9c + .uleb128 0x4e + .4byte .LASF288 + .byte 0x1 + .byte 0x9b + .4byte 0x59 + .8byte .LFB219 + .8byte .LFE219-.LFB219 + .uleb128 0x1 + .byte 0x9c + .4byte 0x1e14 + .uleb128 0x44 + .4byte .LASF289 + .byte 0x1 + .byte 0x9b + .4byte 0x147 + .4byte .LLST57 + .uleb128 0x4b + .string "ret" + .byte 0x1 + .byte 0x9d + .4byte 0x59 + .uleb128 0x46 + .string "wf" + .byte 0x1 + .byte 0x9e + .4byte 0xd56 + .4byte .LLST58 + .uleb128 0x4f + .4byte 0x1e62 + .8byte .LBB121 + .4byte .Ldebug_ranges0+0x1a0 + .byte 0x1 + .byte 0xa3 + .4byte 0x1c98 + .uleb128 0x30 + .4byte 0x1e72 + .4byte .LLST59 + .uleb128 0x39 + .8byte .LVL108 + .4byte 0x2082 + .4byte 0x1c22 + .uleb128 0x34 + .uleb128 0x1 + .byte 0x50 + .uleb128 0x2 + .byte 0x84 + .sleb128 0 + .byte 0 + .uleb128 0x39 + .8byte .LVL109 + .4byte 0x208d + .4byte 0x1c40 + .uleb128 0x34 + .uleb128 0x1 + .byte 0x50 + .uleb128 0x2 + .byte 0x85 + .sleb128 0 + .uleb128 0x34 + .uleb128 0x1 + .byte 0x51 + .uleb128 0x2 + .byte 0x84 + .sleb128 0 + .byte 0 + .uleb128 0x39 + .8byte .LVL110 + .4byte 0x205f + .4byte 0x1c65 + .uleb128 0x34 + .uleb128 0x1 + .byte 0x50 + .uleb128 0x9 + .byte 0x3 + .8byte .LC2 + .uleb128 0x34 + .uleb128 0x1 + .byte 0x51 + .uleb128 0x2 + .byte 0x85 + .sleb128 0 + .byte 0 + .uleb128 0x39 + .8byte .LVL116 + .4byte 0x2082 + .4byte 0x1c7d + .uleb128 0x34 + .uleb128 0x1 + .byte 0x50 + .uleb128 0x2 + .byte 0x84 + .sleb128 0 + .byte 0 + .uleb128 0x33 + .8byte .LVL117 + .4byte 0x208d + .uleb128 0x34 .uleb128 0x1 - .byte 0x9c - .uleb128 0x4e - .4byte .LASF365 - .byte 0x1 - .byte 0x80 - .4byte 0x59 - .8byte .LFB216 - .8byte .LFE216-.LFB216 + .byte 0x50 + .uleb128 0x2 + .byte 0x85 + .sleb128 0 + .uleb128 0x34 .uleb128 0x1 - .byte 0x9c - .4byte 0x1c27 - .uleb128 0x42 - .4byte .LASF366 - .byte 0x1 - .byte 0x80 - .4byte 0x147 - .4byte .LLST22 - .uleb128 0x43 - .string "ret" - .byte 0x1 - .byte 0x82 - .4byte 0x59 - .uleb128 0x48 - .string "wf" - .byte 0x1 - .byte 0x83 - .4byte 0xf99 - .4byte .LLST23 - .uleb128 0x4f - .4byte 0x1c59 - .8byte .LBB51 - .8byte .LBE51-.LBB51 + .byte 0x51 + .uleb128 0x2 + .byte 0x84 + .sleb128 0 + .byte 0 + .byte 0 + .uleb128 0x50 + .4byte 0x1e46 + .8byte .LBB124 + .8byte .LBE124-.LBB124 .byte 0x1 - .byte 0x88 - .4byte 0x1af4 - .uleb128 0x2f - .4byte 0x1c69 - .4byte .LLST24 - .uleb128 0x38 - .8byte .LVL54 - .4byte 0x1d5d - .4byte 0x1ad8 - .uleb128 0x36 + .byte 0xa9 + .4byte 0x1d02 + .uleb128 0x30 + .4byte 0x1e56 + .4byte .LLST60 + .uleb128 0x39 + .8byte .LVL112 + .4byte 0x208d + .4byte 0x1ce6 + .uleb128 0x34 .uleb128 0x1 .byte 0x50 .uleb128 0x2 .byte 0x83 .sleb128 4 - .uleb128 0x36 + .uleb128 0x34 .uleb128 0x1 .byte 0x51 .uleb128 0x9 .byte 0x3 - .8byte .LC0 - .uleb128 0x36 + .8byte .LC3 + .uleb128 0x34 .uleb128 0x1 .byte 0x52 .uleb128 0x1 .byte 0x3c .byte 0 - .uleb128 0x35 - .8byte .LVL55 - .4byte 0x1d68 - .uleb128 0x36 + .uleb128 0x33 + .8byte .LVL113 + .4byte 0x205f + .uleb128 0x34 .uleb128 0x1 .byte 0x50 .uleb128 0x9 .byte 0x3 - .8byte .LC1 + .8byte .LC4 .byte 0 .byte 0 - .uleb128 0x44 - .4byte 0x1c27 - .8byte .LBB53 - .4byte .Ldebug_ranges0+0xc0 + .uleb128 0x4f + .4byte 0x1e14 + .8byte .LBB127 + .4byte .Ldebug_ranges0+0x1d0 .byte 0x1 - .byte 0x8e - .4byte 0x1bf8 - .uleb128 0x2f - .4byte 0x1c37 - .4byte .LLST25 - .uleb128 0x32 - .4byte .Ldebug_ranges0+0xc0 - .uleb128 0x33 - .4byte 0x1c42 - .uleb128 0x34 - .4byte 0x1c4d - .4byte .LLST26 - .uleb128 0x44 - .4byte 0x1c75 - .8byte .LBB55 - .4byte .Ldebug_ranges0+0xf0 + .byte 0xaf + .4byte 0x1e06 + .uleb128 0x30 + .4byte 0x1e24 + .4byte .LLST61 + .uleb128 0x35 + .4byte .Ldebug_ranges0+0x1d0 + .uleb128 0x38 + .4byte 0x1e2f + .uleb128 0x36 + .4byte 0x1e3a + .4byte .LLST62 + .uleb128 0x4f + .4byte 0x1e7e + .8byte .LBB129 + .4byte .Ldebug_ranges0+0x200 .byte 0x1 - .byte 0x6f - .4byte 0x1bd5 - .uleb128 0x2f - .4byte 0x1c90 - .4byte .LLST27 - .uleb128 0x2f - .4byte 0x1c85 - .4byte .LLST28 - .uleb128 0x32 - .4byte .Ldebug_ranges0+0xf0 - .uleb128 0x34 - .4byte 0x1c9b - .4byte .LLST29 - .uleb128 0x34 - .4byte 0x1ca4 - .4byte .LLST30 - .uleb128 0x44 - .4byte 0x1cb0 - .8byte .LBB57 - .4byte .Ldebug_ranges0+0x130 + .byte 0x8a + .4byte 0x1de3 + .uleb128 0x30 + .4byte 0x1e99 + .4byte .LLST63 + .uleb128 0x30 + .4byte 0x1e8e + .4byte .LLST64 + .uleb128 0x35 + .4byte .Ldebug_ranges0+0x200 + .uleb128 0x36 + .4byte 0x1ea4 + .4byte .LLST65 + .uleb128 0x36 + .4byte 0x1ead + .4byte .LLST66 + .uleb128 0x4f + .4byte 0x1eb9 + .8byte .LBB131 + .4byte .Ldebug_ranges0+0x240 .byte 0x1 - .byte 0x55 - .4byte 0x1bb3 - .uleb128 0x50 - .4byte 0x1cbc - .uleb128 0x50 - .4byte 0x1cc7 - .uleb128 0x32 - .4byte .Ldebug_ranges0+0x130 - .uleb128 0x34 - .4byte 0x1cd2 - .4byte .LLST31 - .uleb128 0x34 - .4byte 0x1cdb - .4byte .LLST32 - .uleb128 0x34 - .4byte 0x1ce4 - .4byte .LLST33 - .uleb128 0x34 - .4byte 0x1cef - .4byte .LLST34 - .byte 0 - .byte 0 + .byte 0x62 + .4byte 0x1dc1 + .uleb128 0x51 + .4byte 0x1ec5 + .uleb128 0x51 + .4byte 0x1ed0 .uleb128 0x35 - .8byte .LVL64 - .4byte 0x1d73 + .4byte .Ldebug_ranges0+0x240 + .uleb128 0x36 + .4byte 0x1edb + .4byte .LLST67 + .uleb128 0x36 + .4byte 0x1ee4 + .4byte .LLST68 + .uleb128 0x36 + .4byte 0x1eed + .4byte .LLST69 .uleb128 0x36 + .4byte 0x1ef8 + .4byte .LLST70 + .byte 0 + .byte 0 + .uleb128 0x33 + .8byte .LVL126 + .4byte 0x206a + .uleb128 0x34 .uleb128 0x1 .byte 0x50 .uleb128 0x2 .byte 0x87 .sleb128 0 - .uleb128 0x36 + .uleb128 0x34 .uleb128 0x1 .byte 0x51 .uleb128 0x1 .byte 0x30 - .uleb128 0x36 + .uleb128 0x34 .uleb128 0x1 .byte 0x52 .uleb128 0x3 @@ -4210,16 +4907,16 @@ stype.6193: .byte 0 .byte 0 .byte 0 - .uleb128 0x35 - .8byte .LVL74 - .4byte 0x1d68 - .uleb128 0x36 + .uleb128 0x33 + .8byte .LVL136 + .4byte 0x205f + .uleb128 0x34 .uleb128 0x1 .byte 0x50 .uleb128 0x9 .byte 0x3 - .8byte .LC3 - .uleb128 0x36 + .8byte .LC6 + .uleb128 0x34 .uleb128 0x1 .byte 0x51 .uleb128 0x2 @@ -4228,187 +4925,285 @@ stype.6193: .byte 0 .byte 0 .byte 0 - .uleb128 0x30 - .8byte .LVL56 - .4byte 0x1d68 - .uleb128 0x35 - .8byte .LVL76 - .4byte 0x1d68 - .uleb128 0x36 - .uleb128 0x1 - .byte 0x50 - .uleb128 0x9 - .byte 0x3 - .8byte .LC5 - .uleb128 0x36 - .uleb128 0x1 - .byte 0x51 - .uleb128 0x2 - .byte 0x83 - .sleb128 20 - .byte 0 + .uleb128 0x31 + .8byte .LVL114 + .4byte 0x205f .byte 0 - .uleb128 0x45 - .4byte .LASF367 + .uleb128 0x49 + .4byte .LASF290 .byte 0x1 - .byte 0x66 + .byte 0x81 .4byte 0x59 .byte 0x1 - .4byte 0x1c59 - .uleb128 0x46 - .4byte .LASF354 + .4byte 0x1e46 + .uleb128 0x4a + .4byte .LASF277 .byte 0x1 - .byte 0x66 - .4byte 0xf99 - .uleb128 0x49 - .4byte .LASF368 + .byte 0x81 + .4byte 0xd56 + .uleb128 0x27 + .4byte .LASF291 .byte 0x1 - .byte 0x68 + .byte 0x83 .4byte 0xa8 - .uleb128 0x49 - .4byte .LASF369 + .uleb128 0x27 + .4byte .LASF292 .byte 0x1 - .byte 0x69 + .byte 0x84 .4byte 0xa8 .byte 0 - .uleb128 0x45 - .4byte .LASF370 + .uleb128 0x49 + .4byte .LASF293 .byte 0x1 - .byte 0x5c + .byte 0x77 .4byte 0x59 .byte 0x1 - .4byte 0x1c75 - .uleb128 0x51 + .4byte 0x1e62 + .uleb128 0x52 .string "buf" .byte 0x1 - .byte 0x5c + .byte 0x77 .4byte 0xff .byte 0 - .uleb128 0x45 - .4byte .LASF371 + .uleb128 0x49 + .4byte .LASF294 .byte 0x1 - .byte 0x4f + .byte 0x69 + .4byte 0x59 + .byte 0x1 + .4byte 0x1e7e + .uleb128 0x4a + .4byte .LASF277 + .byte 0x1 + .byte 0x69 + .4byte 0xd56 + .byte 0 + .uleb128 0x49 + .4byte .LASF295 + .byte 0x1 + .byte 0x5c .4byte 0x84 .byte 0x1 - .4byte 0x1cb0 - .uleb128 0x46 - .4byte .LASF372 + .4byte 0x1eb9 + .uleb128 0x4a + .4byte .LASF296 .byte 0x1 - .byte 0x4f - .4byte 0x4e5 - .uleb128 0x46 - .4byte .LASF373 + .byte 0x5c + .4byte 0x4d9 + .uleb128 0x4a + .4byte .LASF297 .byte 0x1 - .byte 0x4f + .byte 0x5c .4byte 0x84 - .uleb128 0x43 + .uleb128 0x4b .string "i" .byte 0x1 - .byte 0x51 + .byte 0x5e .4byte 0x84 - .uleb128 0x49 - .4byte .LASF374 + .uleb128 0x27 + .4byte .LASF298 .byte 0x1 - .byte 0x52 + .byte 0x5f .4byte 0x84 .byte 0 - .uleb128 0x52 - .4byte .LASF376 + .uleb128 0x53 + .4byte .LASF302 .byte 0x1 - .byte 0x3b + .byte 0x48 .byte 0x1 - .4byte 0x1cfb - .uleb128 0x46 - .4byte .LASF377 + .4byte 0x1f04 + .uleb128 0x4a + .4byte .LASF299 .byte 0x1 - .byte 0x3b + .byte 0x48 .4byte 0x84 - .uleb128 0x46 - .4byte .LASF378 + .uleb128 0x4a + .4byte .LASF300 .byte 0x1 - .byte 0x3b - .4byte 0xe07 - .uleb128 0x43 + .byte 0x48 + .4byte 0xbb9 + .uleb128 0x4b .string "i" .byte 0x1 - .byte 0x3d + .byte 0x4a .4byte 0x84 - .uleb128 0x43 + .uleb128 0x4b .string "j" .byte 0x1 - .byte 0x3d + .byte 0x4a .4byte 0x84 - .uleb128 0x49 - .4byte .LASF379 + .uleb128 0x27 + .4byte .LASF301 .byte 0x1 - .byte 0x3e + .byte 0x4b .4byte 0x84 - .uleb128 0x49 - .4byte .LASF374 + .uleb128 0x27 + .4byte .LASF298 .byte 0x1 - .byte 0x3f + .byte 0x4c .4byte 0x84 .byte 0 - .uleb128 0x52 - .4byte .LASF380 + .uleb128 0x53 + .4byte .LASF303 .byte 0x2 .byte 0x4f .byte 0x3 - .4byte 0x1d13 - .uleb128 0x46 - .4byte .LASF381 + .4byte 0x1f1c + .uleb128 0x4a + .4byte .LASF304 .byte 0x2 .byte 0x4f .4byte 0x18a .byte 0 - .uleb128 0x45 - .4byte .LASF382 + .uleb128 0x49 + .4byte .LASF305 .byte 0x2 .byte 0x38 .4byte 0x147 .byte 0x3 - .4byte 0x1d3a - .uleb128 0x46 + .4byte 0x1f43 + .uleb128 0x4a .4byte .LASF33 .byte 0x2 .byte 0x38 .4byte 0x105 - .uleb128 0x46 - .4byte .LASF383 + .uleb128 0x4a + .4byte .LASF306 .byte 0x2 .byte 0x38 .4byte 0x13c .byte 0 - .uleb128 0x53 - .4byte .LASF384 - .4byte .LASF384 - .byte 0x16 - .2byte 0x399 .uleb128 0x54 - .4byte .LASF385 - .4byte .LASF385 + .4byte 0x1658 + .8byte .LFB241 + .8byte .LFE241-.LFB241 + .uleb128 0x1 + .byte 0x9c + .4byte 0x1fa7 + .uleb128 0x42 + .4byte 0x1675 + .uleb128 0x1 + .byte 0x51 + .uleb128 0x42 + .4byte 0x1681 + .uleb128 0x1 + .byte 0x52 + .uleb128 0x51 + .4byte 0x1669 + .uleb128 0x36 + .4byte 0x168d + .4byte .LLST16 + .uleb128 0x36 + .4byte 0x1697 + .4byte .LLST17 + .uleb128 0x36 + .4byte 0x16a3 + .4byte .LLST18 + .uleb128 0x35 + .4byte .Ldebug_ranges0+0xc0 + .uleb128 0x36 + .4byte 0x16b0 + .4byte .LLST19 + .uleb128 0x35 + .4byte .Ldebug_ranges0+0x100 + .uleb128 0x38 + .4byte 0x16bd + .byte 0 + .byte 0 + .byte 0 + .uleb128 0x54 + .4byte 0x17f4 + .8byte .LFB243 + .8byte .LFE243-.LFB243 + .uleb128 0x1 + .byte 0x9c + .4byte 0x2048 + .uleb128 0x30 + .4byte 0x1811 + .4byte .LLST20 + .uleb128 0x30 + .4byte 0x181d + .4byte .LLST21 + .uleb128 0x51 + .4byte 0x1805 + .uleb128 0x36 + .4byte 0x1829 + .4byte .LLST22 + .uleb128 0x36 + .4byte 0x1835 + .4byte .LLST23 + .uleb128 0x36 + .4byte 0x1841 + .4byte .LLST24 + .uleb128 0x2f + .4byte 0x19f9 + .8byte .LBB65 + .8byte .LBE65-.LBB65 + .byte 0x1 + .2byte 0x187 + .4byte 0x201a + .uleb128 0x30 + .4byte 0x1a0a + .4byte .LLST25 + .byte 0 + .uleb128 0x39 + .8byte .LVL54 + .4byte 0x1a17 + .4byte 0x203a + .uleb128 0x34 + .uleb128 0x1 + .byte 0x50 + .uleb128 0x3 + .byte 0xf3 + .uleb128 0x1 + .byte 0x51 + .uleb128 0x34 + .uleb128 0x1 + .byte 0x51 + .uleb128 0x3 + .byte 0xf3 + .uleb128 0x1 + .byte 0x52 + .byte 0 + .uleb128 0x31 + .8byte .LVL58 + .4byte 0x1944 + .byte 0 + .uleb128 0x55 + .4byte .LASF307 + .4byte .LASF307 + .byte 0x15 + .2byte 0x399 + .uleb128 0x56 + .4byte .LASF308 + .4byte .LASF308 .byte 0x2 .byte 0x36 - .uleb128 0x53 - .4byte .LASF386 - .4byte .LASF386 - .byte 0x16 + .uleb128 0x56 + .4byte .LASF309 + .4byte .LASF309 + .byte 0x17 + .byte 0x13 + .uleb128 0x55 + .4byte .LASF310 + .4byte .LASF310 + .byte 0x15 + .2byte 0x16c + .uleb128 0x55 + .4byte .LASF311 + .4byte .LASF311 + .byte 0x15 .2byte 0x16d - .uleb128 0x54 - .4byte .LASF387 - .4byte .LASF387 + .uleb128 0x56 + .4byte .LASF312 + .4byte .LASF312 + .byte 0x8 + .byte 0x4a + .uleb128 0x56 + .4byte .LASF313 + .4byte .LASF313 .byte 0x8 .byte 0x2a - .uleb128 0x54 - .4byte .LASF388 - .4byte .LASF388 - .byte 0x18 - .byte 0x13 - .uleb128 0x53 - .4byte .LASF389 - .4byte .LASF389 - .byte 0x16 - .2byte 0x16c .byte 0 .section .debug_abbrev,"",@progbits .Ldebug_abbrev0: @@ -4863,7 +5658,7 @@ stype.6193: .uleb128 0x3a .uleb128 0xb .uleb128 0x3b - .uleb128 0xb + .uleb128 0x5 .uleb128 0x1 .uleb128 0x13 .byte 0 @@ -4878,17 +5673,10 @@ stype.6193: .byte 0 .byte 0 .uleb128 0x26 - .uleb128 0x28 - .byte 0 - .uleb128 0x3 - .uleb128 0xe - .uleb128 0x1c - .uleb128 0xd - .byte 0 - .byte 0 - .uleb128 0x27 .uleb128 0x4 .byte 0x1 + .uleb128 0x3 + .uleb128 0xe .uleb128 0xb .uleb128 0xb .uleb128 0x49 @@ -4901,24 +5689,20 @@ stype.6193: .uleb128 0x13 .byte 0 .byte 0 - .uleb128 0x28 - .uleb128 0x4 - .byte 0x1 + .uleb128 0x27 + .uleb128 0x34 + .byte 0 .uleb128 0x3 .uleb128 0xe - .uleb128 0xb - .uleb128 0xb - .uleb128 0x49 - .uleb128 0x13 .uleb128 0x3a .uleb128 0xb .uleb128 0x3b - .uleb128 0x5 - .uleb128 0x1 + .uleb128 0xb + .uleb128 0x49 .uleb128 0x13 .byte 0 .byte 0 - .uleb128 0x29 + .uleb128 0x28 .uleb128 0x34 .byte 0 .uleb128 0x3 @@ -4933,7 +5717,7 @@ stype.6193: .uleb128 0x18 .byte 0 .byte 0 - .uleb128 0x2a + .uleb128 0x29 .uleb128 0x2e .byte 0x1 .uleb128 0x3f @@ -4960,7 +5744,7 @@ stype.6193: .uleb128 0x13 .byte 0 .byte 0 - .uleb128 0x2b + .uleb128 0x2a .uleb128 0x5 .byte 0 .uleb128 0x3 @@ -4975,6 +5759,21 @@ stype.6193: .uleb128 0x17 .byte 0 .byte 0 + .uleb128 0x2b + .uleb128 0x5 + .byte 0 + .uleb128 0x3 + .uleb128 0x8 + .uleb128 0x3a + .uleb128 0xb + .uleb128 0x3b + .uleb128 0x5 + .uleb128 0x49 + .uleb128 0x13 + .uleb128 0x2 + .uleb128 0x17 + .byte 0 + .byte 0 .uleb128 0x2c .uleb128 0x34 .byte 0 @@ -4994,7 +5793,20 @@ stype.6193: .uleb128 0x34 .byte 0 .uleb128 0x3 - .uleb128 0x8 + .uleb128 0xe + .uleb128 0x3a + .uleb128 0xb + .uleb128 0x3b + .uleb128 0x5 + .uleb128 0x49 + .uleb128 0x13 + .byte 0 + .byte 0 + .uleb128 0x2e + .uleb128 0x34 + .byte 0 + .uleb128 0x3 + .uleb128 0xe .uleb128 0x3a .uleb128 0xb .uleb128 0x3b @@ -5005,7 +5817,7 @@ stype.6193: .uleb128 0x17 .byte 0 .byte 0 - .uleb128 0x2e + .uleb128 0x2f .uleb128 0x1d .byte 0x1 .uleb128 0x31 @@ -5022,7 +5834,7 @@ stype.6193: .uleb128 0x13 .byte 0 .byte 0 - .uleb128 0x2f + .uleb128 0x30 .uleb128 0x5 .byte 0 .uleb128 0x31 @@ -5031,7 +5843,7 @@ stype.6193: .uleb128 0x17 .byte 0 .byte 0 - .uleb128 0x30 + .uleb128 0x31 .uleb128 0x4109 .byte 0 .uleb128 0x11 @@ -5040,7 +5852,7 @@ stype.6193: .uleb128 0x13 .byte 0 .byte 0 - .uleb128 0x31 + .uleb128 0x32 .uleb128 0x1d .byte 0x1 .uleb128 0x31 @@ -5057,45 +5869,38 @@ stype.6193: .uleb128 0x13 .byte 0 .byte 0 - .uleb128 0x32 - .uleb128 0xb - .byte 0x1 - .uleb128 0x55 - .uleb128 0x17 - .byte 0 - .byte 0 .uleb128 0x33 - .uleb128 0x34 - .byte 0 + .uleb128 0x4109 + .byte 0x1 + .uleb128 0x11 + .uleb128 0x1 .uleb128 0x31 .uleb128 0x13 .byte 0 .byte 0 .uleb128 0x34 - .uleb128 0x34 + .uleb128 0x410a .byte 0 - .uleb128 0x31 - .uleb128 0x13 .uleb128 0x2 - .uleb128 0x17 + .uleb128 0x18 + .uleb128 0x2111 + .uleb128 0x18 .byte 0 .byte 0 .uleb128 0x35 - .uleb128 0x4109 + .uleb128 0xb .byte 0x1 - .uleb128 0x11 - .uleb128 0x1 - .uleb128 0x31 - .uleb128 0x13 + .uleb128 0x55 + .uleb128 0x17 .byte 0 .byte 0 .uleb128 0x36 - .uleb128 0x410a + .uleb128 0x34 .byte 0 + .uleb128 0x31 + .uleb128 0x13 .uleb128 0x2 - .uleb128 0x18 - .uleb128 0x2111 - .uleb128 0x18 + .uleb128 0x17 .byte 0 .byte 0 .uleb128 0x37 @@ -5105,9 +5910,18 @@ stype.6193: .uleb128 0x1 .uleb128 0x12 .uleb128 0x7 + .uleb128 0x1 + .uleb128 0x13 .byte 0 .byte 0 .uleb128 0x38 + .uleb128 0x34 + .byte 0 + .uleb128 0x31 + .uleb128 0x13 + .byte 0 + .byte 0 + .uleb128 0x39 .uleb128 0x4109 .byte 0x1 .uleb128 0x11 @@ -5118,7 +5932,16 @@ stype.6193: .uleb128 0x13 .byte 0 .byte 0 - .uleb128 0x39 + .uleb128 0x3a + .uleb128 0x410a + .byte 0 + .uleb128 0x31 + .uleb128 0x13 + .uleb128 0x2111 + .uleb128 0x18 + .byte 0 + .byte 0 + .uleb128 0x3b .uleb128 0x2e .byte 0x1 .uleb128 0x3 @@ -5133,15 +5956,28 @@ stype.6193: .uleb128 0x13 .uleb128 0x20 .uleb128 0xb - .uleb128 0x1 + .uleb128 0x1 + .uleb128 0x13 + .byte 0 + .byte 0 + .uleb128 0x3c + .uleb128 0x5 + .byte 0 + .uleb128 0x3 + .uleb128 0xe + .uleb128 0x3a + .uleb128 0xb + .uleb128 0x3b + .uleb128 0x5 + .uleb128 0x49 .uleb128 0x13 .byte 0 .byte 0 - .uleb128 0x3a + .uleb128 0x3d .uleb128 0x5 .byte 0 .uleb128 0x3 - .uleb128 0xe + .uleb128 0x8 .uleb128 0x3a .uleb128 0xb .uleb128 0x3b @@ -5150,11 +5986,11 @@ stype.6193: .uleb128 0x13 .byte 0 .byte 0 - .uleb128 0x3b + .uleb128 0x3e .uleb128 0x34 .byte 0 .uleb128 0x3 - .uleb128 0xe + .uleb128 0x8 .uleb128 0x3a .uleb128 0xb .uleb128 0x3b @@ -5163,7 +5999,12 @@ stype.6193: .uleb128 0x13 .byte 0 .byte 0 - .uleb128 0x3c + .uleb128 0x3f + .uleb128 0xb + .byte 0x1 + .byte 0 + .byte 0 + .uleb128 0x40 .uleb128 0x2e .byte 0x1 .uleb128 0x3 @@ -5188,57 +6029,25 @@ stype.6193: .uleb128 0x13 .byte 0 .byte 0 - .uleb128 0x3d - .uleb128 0x34 - .byte 0 - .uleb128 0x3 - .uleb128 0xe - .uleb128 0x3a + .uleb128 0x41 .uleb128 0xb - .uleb128 0x3b - .uleb128 0x5 - .uleb128 0x49 - .uleb128 0x13 - .uleb128 0x2 - .uleb128 0x17 - .byte 0 - .byte 0 - .uleb128 0x3e - .uleb128 0x2e .byte 0x1 - .uleb128 0x3 - .uleb128 0xe - .uleb128 0x3a - .uleb128 0xb - .uleb128 0x3b - .uleb128 0x5 - .uleb128 0x27 - .uleb128 0x19 - .uleb128 0x20 - .uleb128 0xb + .uleb128 0x11 .uleb128 0x1 - .uleb128 0x13 - .byte 0 + .uleb128 0x12 + .uleb128 0x7 .byte 0 - .uleb128 0x3f - .uleb128 0x34 .byte 0 - .uleb128 0x3 - .uleb128 0x8 - .uleb128 0x3a - .uleb128 0xb - .uleb128 0x3b + .uleb128 0x42 .uleb128 0x5 - .uleb128 0x49 - .uleb128 0x13 .byte 0 - .byte 0 - .uleb128 0x40 - .uleb128 0xb - .byte 0x1 + .uleb128 0x31 + .uleb128 0x13 + .uleb128 0x2 + .uleb128 0x18 .byte 0 .byte 0 - .uleb128 0x41 + .uleb128 0x43 .uleb128 0x2e .byte 0x1 .uleb128 0x3 @@ -5263,7 +6072,7 @@ stype.6193: .uleb128 0x13 .byte 0 .byte 0 - .uleb128 0x42 + .uleb128 0x44 .uleb128 0x5 .byte 0 .uleb128 0x3 @@ -5278,7 +6087,22 @@ stype.6193: .uleb128 0x17 .byte 0 .byte 0 - .uleb128 0x43 + .uleb128 0x45 + .uleb128 0x34 + .byte 0 + .uleb128 0x3 + .uleb128 0xe + .uleb128 0x3a + .uleb128 0xb + .uleb128 0x3b + .uleb128 0xb + .uleb128 0x49 + .uleb128 0x13 + .uleb128 0x2 + .uleb128 0x17 + .byte 0 + .byte 0 + .uleb128 0x46 .uleb128 0x34 .byte 0 .uleb128 0x3 @@ -5289,9 +6113,11 @@ stype.6193: .uleb128 0xb .uleb128 0x49 .uleb128 0x13 + .uleb128 0x2 + .uleb128 0x17 .byte 0 .byte 0 - .uleb128 0x44 + .uleb128 0x47 .uleb128 0x1d .byte 0x1 .uleb128 0x31 @@ -5303,12 +6129,19 @@ stype.6193: .uleb128 0x58 .uleb128 0xb .uleb128 0x59 + .uleb128 0x5 + .byte 0 + .byte 0 + .uleb128 0x48 .uleb128 0xb + .byte 0x1 + .uleb128 0x55 + .uleb128 0x17 .uleb128 0x1 .uleb128 0x13 .byte 0 .byte 0 - .uleb128 0x45 + .uleb128 0x49 .uleb128 0x2e .byte 0x1 .uleb128 0x3 @@ -5327,7 +6160,7 @@ stype.6193: .uleb128 0x13 .byte 0 .byte 0 - .uleb128 0x46 + .uleb128 0x4a .uleb128 0x5 .byte 0 .uleb128 0x3 @@ -5340,22 +6173,7 @@ stype.6193: .uleb128 0x13 .byte 0 .byte 0 - .uleb128 0x47 - .uleb128 0x34 - .byte 0 - .uleb128 0x3 - .uleb128 0xe - .uleb128 0x3a - .uleb128 0xb - .uleb128 0x3b - .uleb128 0xb - .uleb128 0x49 - .uleb128 0x13 - .uleb128 0x2 - .uleb128 0x17 - .byte 0 - .byte 0 - .uleb128 0x48 + .uleb128 0x4b .uleb128 0x34 .byte 0 .uleb128 0x3 @@ -5366,45 +6184,6 @@ stype.6193: .uleb128 0xb .uleb128 0x49 .uleb128 0x13 - .uleb128 0x2 - .uleb128 0x17 - .byte 0 - .byte 0 - .uleb128 0x49 - .uleb128 0x34 - .byte 0 - .uleb128 0x3 - .uleb128 0xe - .uleb128 0x3a - .uleb128 0xb - .uleb128 0x3b - .uleb128 0xb - .uleb128 0x49 - .uleb128 0x13 - .byte 0 - .byte 0 - .uleb128 0x4a - .uleb128 0x1d - .byte 0x1 - .uleb128 0x31 - .uleb128 0x13 - .uleb128 0x52 - .uleb128 0x1 - .uleb128 0x55 - .uleb128 0x17 - .uleb128 0x58 - .uleb128 0xb - .uleb128 0x59 - .uleb128 0xb - .byte 0 - .byte 0 - .uleb128 0x4b - .uleb128 0xb - .byte 0x1 - .uleb128 0x55 - .uleb128 0x17 - .uleb128 0x1 - .uleb128 0x13 .byte 0 .byte 0 .uleb128 0x4c @@ -5471,6 +6250,23 @@ stype.6193: .byte 0x1 .uleb128 0x31 .uleb128 0x13 + .uleb128 0x52 + .uleb128 0x1 + .uleb128 0x55 + .uleb128 0x17 + .uleb128 0x58 + .uleb128 0xb + .uleb128 0x59 + .uleb128 0xb + .uleb128 0x1 + .uleb128 0x13 + .byte 0 + .byte 0 + .uleb128 0x50 + .uleb128 0x1d + .byte 0x1 + .uleb128 0x31 + .uleb128 0x13 .uleb128 0x11 .uleb128 0x1 .uleb128 0x12 @@ -5483,14 +6279,14 @@ stype.6193: .uleb128 0x13 .byte 0 .byte 0 - .uleb128 0x50 + .uleb128 0x51 .uleb128 0x5 .byte 0 .uleb128 0x31 .uleb128 0x13 .byte 0 .byte 0 - .uleb128 0x51 + .uleb128 0x52 .uleb128 0x5 .byte 0 .uleb128 0x3 @@ -5503,7 +6299,7 @@ stype.6193: .uleb128 0x13 .byte 0 .byte 0 - .uleb128 0x52 + .uleb128 0x53 .uleb128 0x2e .byte 0x1 .uleb128 0x3 @@ -5520,7 +6316,24 @@ stype.6193: .uleb128 0x13 .byte 0 .byte 0 - .uleb128 0x53 + .uleb128 0x54 + .uleb128 0x2e + .byte 0x1 + .uleb128 0x31 + .uleb128 0x13 + .uleb128 0x11 + .uleb128 0x1 + .uleb128 0x12 + .uleb128 0x7 + .uleb128 0x40 + .uleb128 0x18 + .uleb128 0x2117 + .uleb128 0x19 + .uleb128 0x1 + .uleb128 0x13 + .byte 0 + .byte 0 + .uleb128 0x55 .uleb128 0x2e .byte 0 .uleb128 0x3f @@ -5537,7 +6350,7 @@ stype.6193: .uleb128 0x5 .byte 0 .byte 0 - .uleb128 0x54 + .uleb128 0x56 .uleb128 0x2e .byte 0 .uleb128 0x3f @@ -5557,958 +6370,1233 @@ stype.6193: .byte 0 .section .debug_loc,"",@progbits .Ldebug_loc0: -.LLST35: - .8byte .LVL77 - .8byte .LVL78 +.LLST71: + .8byte .LVL138 + .8byte .LVL139 .2byte 0x1 .byte 0x50 - .8byte .LVL78 - .8byte .LVL116 + .8byte .LVL139 + .8byte .LVL149 + .2byte 0x1 + .byte 0x64 + .8byte .LVL149 + .8byte .LVL150 + .2byte 0x4 + .byte 0xf3 + .uleb128 0x1 + .byte 0x50 + .byte 0x9f + .8byte .LVL150 + .8byte .LFE239 + .2byte 0x1 + .byte 0x64 + .8byte 0 + .8byte 0 +.LLST72: + .8byte .LVL138 + .8byte .LVL140 + .2byte 0x1 + .byte 0x51 + .8byte .LVL140 + .8byte .LVL148 + .2byte 0x1 + .byte 0x63 + .8byte .LVL150 + .8byte .LVL151 + .2byte 0x1 + .byte 0x51 + .8byte .LVL151 + .8byte .LVL205 + .2byte 0x1 + .byte 0x63 + .8byte .LVL205 + .8byte .LFE239 + .2byte 0x1 + .byte 0x51 + .8byte 0 + .8byte 0 +.LLST73: + .8byte .LVL138 + .8byte .LVL141 + .2byte 0x1 + .byte 0x52 + .8byte .LVL141 + .8byte .LVL148 .2byte 0x1 - .byte 0x63 - .8byte .LVL116 - .8byte .LVL117 + .byte 0x65 + .8byte .LVL148 + .8byte .LVL150 .2byte 0x4 .byte 0xf3 .uleb128 0x1 - .byte 0x50 + .byte 0x52 .byte 0x9f - .8byte .LVL117 - .8byte .LVL125 + .8byte .LVL150 + .8byte .LVL151 .2byte 0x1 - .byte 0x63 - .8byte .LVL125 - .8byte .LVL126 - .2byte 0x4 - .byte 0xf3 - .uleb128 0x1 - .byte 0x50 - .byte 0x9f - .8byte .LVL126 + .byte 0x52 + .8byte .LVL151 .8byte .LVL156 .2byte 0x1 - .byte 0x63 + .byte 0x65 .8byte .LVL156 - .8byte .LVL157 - .2byte 0x1 - .byte 0x50 - .8byte .LVL157 - .8byte .LVL158 + .8byte .LVL161 .2byte 0x4 .byte 0xf3 .uleb128 0x1 - .byte 0x50 + .byte 0x52 .byte 0x9f - .8byte .LVL158 - .8byte .LVL159 + .8byte .LVL161 + .8byte .LVL187 .2byte 0x1 - .byte 0x50 - .8byte .LVL159 - .8byte .LFE229 + .byte 0x65 + .8byte .LVL187 + .8byte .LVL205 .2byte 0x4 .byte 0xf3 .uleb128 0x1 - .byte 0x50 + .byte 0x52 .byte 0x9f + .8byte .LVL205 + .8byte .LFE239 + .2byte 0x1 + .byte 0x52 .8byte 0 .8byte 0 -.LLST36: - .8byte .LVL77 - .8byte .LVL80-1 - .2byte 0x1 - .byte 0x51 - .8byte .LVL80-1 - .8byte .LVL81 +.LLST74: + .8byte .LVL138 + .8byte .LVL143-1 .2byte 0x1 - .byte 0x65 - .8byte .LVL81 - .8byte .LVL88 - .2byte 0x3 - .byte 0x85 - .sleb128 1 - .byte 0x9f - .8byte .LVL88 - .8byte .LVL114 + .byte 0x53 + .8byte .LVL143-1 + .8byte .LVL150 .2byte 0x4 .byte 0xf3 .uleb128 0x1 - .byte 0x51 - .byte 0x9f - .8byte .LVL118 - .8byte .LVL119 - .2byte 0x3 - .byte 0x85 - .sleb128 1 + .byte 0x53 .byte 0x9f - .8byte .LVL119 - .8byte .LVL120 + .8byte .LVL150 + .8byte .LVL151 + .2byte 0x1 + .byte 0x53 + .8byte .LVL151 + .8byte .LVL205 .2byte 0x4 .byte 0xf3 .uleb128 0x1 - .byte 0x51 - .byte 0x9f - .8byte .LVL120 - .8byte .LVL125 - .2byte 0x3 - .byte 0x85 - .sleb128 1 + .byte 0x53 .byte 0x9f - .8byte .LVL125 - .8byte .LVL126 + .8byte .LVL205 + .8byte .LFE239 + .2byte 0x1 + .byte 0x53 + .8byte 0 + .8byte 0 +.LLST75: + .8byte .LVL138 + .8byte .LVL143-1 + .2byte 0x1 + .byte 0x54 + .8byte .LVL143-1 + .8byte .LVL150 .2byte 0x4 .byte 0xf3 .uleb128 0x1 - .byte 0x51 - .byte 0x9f - .8byte .LVL126 - .8byte .LVL140 - .2byte 0x3 - .byte 0x85 - .sleb128 1 + .byte 0x54 .byte 0x9f - .8byte .LVL140 .8byte .LVL150 + .8byte .LVL151 + .2byte 0x1 + .byte 0x54 + .8byte .LVL151 + .8byte .LVL205 .2byte 0x4 .byte 0xf3 .uleb128 0x1 - .byte 0x51 - .byte 0x9f - .8byte .LVL150 - .8byte .LVL156 - .2byte 0x3 - .byte 0x85 - .sleb128 1 + .byte 0x54 .byte 0x9f - .8byte .LVL156 - .8byte .LFE229 + .8byte .LVL205 + .8byte .LFE239 .2byte 0x1 - .byte 0x51 + .byte 0x54 .8byte 0 .8byte 0 -.LLST37: - .8byte .LVL77 - .8byte .LVL80-1 +.LLST76: + .8byte .LVL145 + .8byte .LVL146 .2byte 0x1 - .byte 0x52 - .8byte .LVL80-1 - .8byte .LVL156 - .2byte 0x4 - .byte 0xf3 - .uleb128 0x1 - .byte 0x52 - .byte 0x9f - .8byte .LVL156 - .8byte .LFE229 + .byte 0x50 + .8byte .LVL146 + .8byte .LVL148 .2byte 0x1 - .byte 0x52 + .byte 0x66 + .8byte .LVL151 + .8byte .LVL152 + .2byte 0x1 + .byte 0x50 + .8byte .LVL152 + .8byte .LVL161 + .2byte 0x1 + .byte 0x66 + .8byte .LVL161 + .8byte .LVL162 + .2byte 0x1 + .byte 0x50 + .8byte .LVL162 + .8byte .LVL192 + .2byte 0x1 + .byte 0x66 + .8byte .LVL194 + .8byte .LVL205 + .2byte 0x1 + .byte 0x66 .8byte 0 .8byte 0 -.LLST38: - .8byte .LVL115 - .8byte .LVL116 +.LLST77: + .8byte .LVL142 + .8byte .LVL143-1 .2byte 0x1 .byte 0x50 .8byte 0 .8byte 0 -.LLST39: - .8byte .LVL79 - .8byte .LVL80-1 +.LLST78: + .8byte .LVL154 + .8byte .LVL155-1 .2byte 0x1 .byte 0x50 .8byte 0 .8byte 0 -.LLST40: - .8byte .LVL82 - .8byte .LVL83-1 - .2byte 0x9 - .byte 0x3 - .8byte sftemp.6194 +.LLST79: + .8byte .LVL157 + .8byte .LVL159 + .2byte 0x2 + .byte 0x30 + .byte 0x9f .8byte 0 .8byte 0 -.LLST41: - .8byte .LVL82 - .8byte .LVL95 - .2byte 0x1 - .byte 0x63 - .8byte .LVL96 - .8byte .LVL112 +.LLST80: + .8byte .LVL157 + .8byte .LVL159 .2byte 0x1 - .byte 0x63 + .byte 0x65 .8byte 0 .8byte 0 -.LLST42: - .8byte .LVL83 - .8byte .LVL87-1 +.LLST81: + .8byte .LVL163 + .8byte .LVL187 .2byte 0x1 - .byte 0x50 + .byte 0x64 .8byte 0 .8byte 0 -.LLST43: - .8byte .LVL84 - .8byte .LVL95 +.LLST82: + .8byte .LVL163 + .8byte .LVL187 .2byte 0x1 .byte 0x66 - .8byte .LVL96 - .8byte .LVL112 + .8byte 0 + .8byte 0 +.LLST83: + .8byte .LVL163 + .8byte .LVL187 .2byte 0x1 - .byte 0x66 + .byte 0x57 .8byte 0 .8byte 0 -.LLST44: - .8byte .LVL85 - .8byte .LVL86 - .2byte 0x5 - .byte 0x84 - .sleb128 0 - .byte 0x32 - .byte 0x24 - .byte 0x9f - .8byte .LVL86 - .8byte .LVL87-1 +.LLST84: + .8byte .LVL164 + .8byte .LVL165 .2byte 0x1 .byte 0x51 - .8byte .LVL87-1 - .8byte .LVL95 - .2byte 0x5 - .byte 0x84 + .8byte .LVL165 + .8byte .LVL166 + .2byte 0x1 + .byte 0x53 + .8byte .LVL166 + .8byte .LVL180 + .2byte 0x1 + .byte 0x51 + .8byte .LVL180 + .8byte .LVL187 + .2byte 0x1 + .byte 0x53 + .8byte 0 + .8byte 0 +.LLST85: + .8byte .LVL167 + .8byte .LVL168 + .2byte 0x2 + .byte 0x30 + .byte 0x9f + .8byte .LVL168 + .8byte .LVL180 + .2byte 0x1 + .byte 0x56 + .8byte .LVL180 + .8byte .LVL187 + .2byte 0x1 + .byte 0x50 + .8byte 0 + .8byte 0 +.LLST86: + .8byte .LVL169 + .8byte .LVL177 + .2byte 0x1 + .byte 0x52 + .8byte .LVL180 + .8byte .LVL184 + .2byte 0x1 + .byte 0x52 + .8byte .LVL184 + .8byte .LVL185 + .2byte 0x2 + .byte 0x30 + .byte 0x9f + .8byte .LVL185 + .8byte .LVL187 + .2byte 0x1 + .byte 0x52 + .8byte 0 + .8byte 0 +.LLST87: + .8byte .LVL181 + .8byte .LVL184 + .2byte 0x1 + .byte 0x5a + .8byte .LVL185 + .8byte .LVL187 + .2byte 0x1 + .byte 0x5a + .8byte 0 + .8byte 0 +.LLST88: + .8byte .LVL167 + .8byte .LVL179 + .2byte 0x6 + .byte 0x80 .sleb128 0 - .byte 0x32 - .byte 0x24 + .byte 0x78 + .sleb128 0 + .byte 0x22 .byte 0x9f - .8byte .LVL96 - .8byte .LVL112 - .2byte 0x5 - .byte 0x84 + .8byte 0 + .8byte 0 +.LLST89: + .8byte .LVL169 + .8byte .LVL176 + .2byte 0xf + .byte 0x7a + .sleb128 0 + .byte 0xc + .4byte 0xffffffff + .byte 0x1a + .byte 0x80 .sleb128 0 - .byte 0x32 - .byte 0x24 + .byte 0x22 + .byte 0x78 + .sleb128 0 + .byte 0x22 .byte 0x9f - .8byte 0 - .8byte 0 -.LLST45: - .8byte .LVL89 - .8byte .LVL93 - .2byte 0x6 - .byte 0xf2 - .4byte .Ldebug_info0+4276 + .8byte .LVL176 + .8byte .LVL177 + .2byte 0xf + .byte 0x7f .sleb128 0 - .8byte .LVL96 - .8byte .LVL111 - .2byte 0x6 - .byte 0xf2 - .4byte .Ldebug_info0+4276 + .byte 0xc + .4byte 0xffffffff + .byte 0x1a + .byte 0x80 + .sleb128 0 + .byte 0x22 + .byte 0x78 .sleb128 0 + .byte 0x22 + .byte 0x9f .8byte 0 .8byte 0 -.LLST46: - .8byte .LVL89 - .8byte .LVL90 - .2byte 0x1 - .byte 0x50 - .8byte .LVL90 - .8byte .LVL92 - .2byte 0x1 - .byte 0x65 - .8byte .LVL92 - .8byte .LVL93 - .2byte 0x8 - .byte 0x72 +.LLST90: + .8byte .LVL170 + .8byte .LVL172 + .2byte 0x1f + .byte 0x7b .sleb128 0 + .byte 0x35 + .byte 0x25 + .byte 0xc + .4byte 0xffffffff + .byte 0x1a + .byte 0x7f + .sleb128 0 + .byte 0x22 .byte 0x32 .byte 0x24 - .byte 0x85 + .byte 0x80 .sleb128 0 .byte 0x22 + .byte 0x78 + .sleb128 0 + .byte 0x22 + .byte 0x94 + .byte 0x4 + .byte 0x7b + .sleb128 0 + .byte 0x4e + .byte 0x1a + .byte 0x25 + .byte 0x33 + .byte 0x1a .byte 0x9f - .8byte .LVL96 - .8byte .LVL109 - .2byte 0x8 - .byte 0x72 - .sleb128 1 + .8byte .LVL172 + .8byte .LVL173 + .2byte 0x14 + .byte 0x74 + .sleb128 0 .byte 0x32 .byte 0x24 - .byte 0x85 + .byte 0x80 + .sleb128 0 + .byte 0x22 + .byte 0x78 .sleb128 0 .byte 0x22 + .byte 0x94 + .byte 0x4 + .byte 0x7b + .sleb128 0 + .byte 0x4e + .byte 0x1a + .byte 0x25 + .byte 0x33 + .byte 0x1a .byte 0x9f - .8byte .LVL109 - .8byte .LVL110 - .2byte 0x8 - .byte 0x72 + .8byte .LVL173 + .8byte .LVL174 + .2byte 0x1f + .byte 0x7b + .sleb128 0 + .byte 0x35 + .byte 0x25 + .byte 0xc + .4byte 0xffffffff + .byte 0x1a + .byte 0x7f .sleb128 0 + .byte 0x22 .byte 0x32 .byte 0x24 - .byte 0x85 + .byte 0x80 .sleb128 0 .byte 0x22 + .byte 0x78 + .sleb128 0 + .byte 0x22 + .byte 0x94 + .byte 0x4 + .byte 0x7b + .sleb128 0 + .byte 0x4e + .byte 0x1a + .byte 0x25 + .byte 0x33 + .byte 0x1a .byte 0x9f - .8byte .LVL110 - .8byte .LVL111 - .2byte 0x1 - .byte 0x65 .8byte 0 .8byte 0 -.LLST47: - .8byte .LVL92 - .8byte .LVL93 - .2byte 0x1 - .byte 0x52 - .8byte .LVL96 - .8byte .LVL108 - .2byte 0x1 - .byte 0x52 - .8byte .LVL108 - .8byte .LVL109 - .2byte 0x3 - .byte 0x72 - .sleb128 1 - .byte 0x9f +.LLST91: + .8byte .LVL188 + .8byte .LVL191-1 + .2byte 0x9 + .byte 0x3 + .8byte need_pic + .8byte .LVL194 + .8byte .LVL195-1 + .2byte 0x9 + .byte 0x3 + .8byte need_pic .8byte 0 .8byte 0 -.LLST48: - .8byte .LVL97 - .8byte .LVL98 - .2byte 0x2 - .byte 0x30 - .byte 0x9f - .8byte .LVL98 - .8byte .LVL106 +.LLST92: + .8byte .LVL188 + .8byte .LVL192 .2byte 0x1 - .byte 0x53 - .8byte .LVL106 - .8byte .LVL107 - .2byte 0x3 - .byte 0x73 - .sleb128 1 - .byte 0x9f - .8byte 0 - .8byte 0 -.LLST49: - .8byte .LVL99 - .8byte .LVL100 - .2byte 0x2 - .byte 0x30 - .byte 0x9f + .byte 0x66 + .8byte .LVL194 + .8byte .LVL205 + .2byte 0x1 + .byte 0x66 .8byte 0 .8byte 0 -.LLST50: - .8byte .LVL103 - .8byte .LVL104 +.LLST93: + .8byte .LVL188 + .8byte .LVL193 .2byte 0x1 - .byte 0x51 - .8byte .LVL104 - .8byte .LVL105 - .2byte 0x3 - .byte 0x71 - .sleb128 1 - .byte 0x9f + .byte 0x69 + .8byte .LVL194 + .8byte .LVL205 + .2byte 0x1 + .byte 0x69 .8byte 0 .8byte 0 -.LLST51: - .8byte .LVL97 - .8byte .LVL110 +.LLST94: + .8byte .LVL188 + .8byte .LVL190 .2byte 0x1 - .byte 0x57 + .byte 0x50 + .8byte .LVL190 + .8byte .LVL193 + .2byte 0x1 + .byte 0x68 + .8byte .LVL194 + .8byte .LVL195-1 + .2byte 0x1 + .byte 0x50 + .8byte .LVL195-1 + .8byte .LVL205 + .2byte 0x1 + .byte 0x68 .8byte 0 .8byte 0 -.LLST52: - .8byte .LVL89 - .8byte .LVL92 - .2byte 0x2 - .byte 0x30 - .byte 0x9f - .8byte .LVL92 - .8byte .LVL93 - .2byte 0x5 - .byte 0x72 - .sleb128 0 - .byte 0x38 - .byte 0x24 - .byte 0x9f - .8byte .LVL96 - .8byte .LVL98 - .2byte 0x5 - .byte 0x72 - .sleb128 0 - .byte 0x38 - .byte 0x24 - .byte 0x9f - .8byte .LVL98 - .8byte .LVL103 - .2byte 0xa - .byte 0x73 +.LLST95: + .8byte .LVL197 + .8byte .LVL201 + .2byte 0x13 + .byte 0x75 .sleb128 0 .byte 0x34 + .byte 0x26 + .byte 0x8 + .byte 0x20 .byte 0x24 - .byte 0x72 + .byte 0x8 + .byte 0x20 + .byte 0x26 + .byte 0x71 .sleb128 0 - .byte 0x38 + .byte 0x22 + .byte 0x32 .byte 0x24 + .byte 0x88 + .sleb128 0 .byte 0x22 .byte 0x9f - .8byte .LVL103 - .8byte .LVL104 - .2byte 0xd - .byte 0x73 - .sleb128 0 + .8byte .LVL201 + .8byte .LVL202 + .2byte 0x13 + .byte 0x75 + .sleb128 -16 .byte 0x34 + .byte 0x26 + .byte 0x8 + .byte 0x20 .byte 0x24 - .byte 0x72 + .byte 0x8 + .byte 0x20 + .byte 0x26 + .byte 0x71 .sleb128 0 - .byte 0x38 - .byte 0x24 .byte 0x22 - .byte 0x71 + .byte 0x32 + .byte 0x24 + .byte 0x88 .sleb128 0 .byte 0x22 .byte 0x9f - .8byte .LVL104 - .8byte .LVL105 - .2byte 0xf - .byte 0x73 - .sleb128 0 + .8byte .LVL203 + .8byte .LVL205 + .2byte 0x13 + .byte 0x75 + .sleb128 -16 .byte 0x34 + .byte 0x26 + .byte 0x8 + .byte 0x20 .byte 0x24 - .byte 0x72 - .sleb128 0 - .byte 0x38 - .byte 0x24 - .byte 0x22 + .byte 0x8 + .byte 0x20 + .byte 0x26 .byte 0x71 .sleb128 0 .byte 0x22 - .byte 0x23 - .uleb128 0x1 + .byte 0x32 + .byte 0x24 + .byte 0x88 + .sleb128 0 + .byte 0x22 .byte 0x9f - .8byte .LVL106 - .8byte .LVL107 - .2byte 0xc - .byte 0x73 + .8byte 0 + .8byte 0 +.LLST96: + .8byte .LVL197 + .8byte .LVL198 + .2byte 0x1c + .byte 0x7c .sleb128 0 - .byte 0x34 + .byte 0x8 + .byte 0x20 .byte 0x24 - .byte 0x72 + .byte 0x8 + .byte 0x20 + .byte 0x26 + .byte 0x77 .sleb128 0 - .byte 0x38 + .byte 0x8 + .byte 0x20 .byte 0x24 + .byte 0x8 + .byte 0x20 + .byte 0x26 .byte 0x22 - .byte 0x23 - .uleb128 0x10 - .byte 0x9f - .8byte .LVL110 - .8byte .LVL111 - .2byte 0x2 - .byte 0x30 + .byte 0x89 + .sleb128 0 + .byte 0x22 + .byte 0x78 + .sleb128 0 + .byte 0x22 + .byte 0x94 + .byte 0x1 + .byte 0x33 + .byte 0x1a .byte 0x9f .8byte 0 .8byte 0 -.LLST53: - .8byte .LVL89 - .8byte .LVL93 +.LLST97: + .8byte .LVL189 + .8byte .LVL193 .2byte 0x1 - .byte 0x64 - .8byte .LVL96 - .8byte .LVL111 + .byte 0x67 + .8byte .LVL194 + .8byte .LVL205 .2byte 0x1 - .byte 0x64 + .byte 0x67 .8byte 0 .8byte 0 -.LLST54: - .8byte .LVL89 - .8byte .LVL91 +.LLST98: + .8byte .LVL195 + .8byte .LVL196 .2byte 0x2 .byte 0x30 .byte 0x9f + .8byte .LVL196 + .8byte .LVL205 + .2byte 0x1 + .byte 0x52 .8byte 0 .8byte 0 -.LLST55: - .8byte .LVL89 - .8byte .LVL91 - .2byte 0xb - .byte 0x84 - .sleb128 0 - .byte 0x3a - .byte 0x24 - .byte 0x8 - .byte 0x20 - .byte 0x24 - .byte 0x8 - .byte 0x20 - .byte 0x26 +.LLST99: + .8byte .LVL202 + .8byte .LVL203 + .2byte 0x2 + .byte 0x30 .byte 0x9f .8byte 0 .8byte 0 -.LLST56: - .8byte .LVL99 - .8byte .LVL102 +.LLST26: + .8byte .LVL60 + .8byte .LVL61 .2byte 0x1 - .byte 0x51 - .8byte .LVL102 - .8byte .LVL107 - .2byte 0xd - .byte 0x77 - .sleb128 0 - .byte 0x73 - .sleb128 0 - .byte 0x31 - .byte 0x24 - .byte 0x8 - .byte 0xff - .byte 0x1a - .byte 0x26 - .byte 0x33 - .byte 0x1a + .byte 0x50 + .8byte .LVL61 + .8byte .LVL75 + .2byte 0x1 + .byte 0x64 + .8byte .LVL75 + .8byte .LVL76 + .2byte 0x4 + .byte 0xf3 + .uleb128 0x1 + .byte 0x50 + .byte 0x9f + .8byte .LVL76 + .8byte .LVL92 + .2byte 0x1 + .byte 0x64 + .8byte .LVL92 + .8byte .LVL93 + .2byte 0x4 + .byte 0xf3 + .uleb128 0x1 + .byte 0x50 .byte 0x9f + .8byte .LVL93 + .8byte .LFE232 + .2byte 0x1 + .byte 0x64 .8byte 0 .8byte 0 -.LLST57: - .8byte .LVL99 - .8byte .LVL100 +.LLST27: + .8byte .LVL60 + .8byte .LVL63 .2byte 0x1 .byte 0x51 - .8byte .LVL100 - .8byte .LVL110 - .2byte 0x1 - .byte 0x55 + .8byte .LVL63 + .8byte .LFE232 + .2byte 0x4 + .byte 0xf3 + .uleb128 0x1 + .byte 0x51 + .byte 0x9f .8byte 0 .8byte 0 -.LLST58: +.LLST28: + .8byte .LVL60 + .8byte .LVL62 + .2byte 0x1 + .byte 0x52 + .8byte .LVL62 + .8byte .LVL64-1 + .2byte 0x1 + .byte 0x50 + .8byte .LVL64-1 + .8byte .LVL93 + .2byte 0x4 + .byte 0xf3 + .uleb128 0x1 + .byte 0x52 + .byte 0x9f + .8byte .LVL93 .8byte .LVL94 - .8byte .LVL95 .2byte 0x1 - .byte 0x65 + .byte 0x50 + .8byte .LVL94 + .8byte .LVL95-1 + .2byte 0x1 + .byte 0x51 + .8byte .LVL95-1 + .8byte .LVL96 + .2byte 0x4 + .byte 0xf3 + .uleb128 0x1 + .byte 0x52 + .byte 0x9f + .8byte .LVL96 + .8byte .LVL99-1 + .2byte 0x1 + .byte 0x50 + .8byte .LVL99-1 + .8byte .LVL104 + .2byte 0x4 + .byte 0xf3 + .uleb128 0x1 + .byte 0x52 + .byte 0x9f + .8byte .LVL104 + .8byte .LFE232 + .2byte 0x1 + .byte 0x50 .8byte 0 .8byte 0 -.LLST59: - .8byte .LVL111 - .8byte .LVL112 +.LLST29: + .8byte .LVL60 + .8byte .LVL75 + .2byte 0x3 + .byte 0x9 + .byte 0xff + .byte 0x9f + .8byte .LVL76 + .8byte .LVL92 + .2byte 0x3 + .byte 0x9 + .byte 0xff + .byte 0x9f + .8byte .LVL93 + .8byte .LVL95 + .2byte 0x3 + .byte 0x9 + .byte 0xff + .byte 0x9f + .8byte .LVL95 + .8byte .LVL96 .2byte 0x1 - .byte 0x65 + .byte 0x50 + .8byte .LVL96 + .8byte .LFE232 + .2byte 0x3 + .byte 0x9 + .byte 0xff + .byte 0x9f .8byte 0 .8byte 0 -.LLST60: - .8byte .LVL127 - .8byte .LVL134 +.LLST30: + .8byte .LVL63 + .8byte .LVL75 .2byte 0x1 .byte 0x64 - .8byte 0 - .8byte 0 -.LLST61: - .8byte .LVL127 - .8byte .LVL150 + .8byte .LVL76 + .8byte .LVL92 .2byte 0x1 - .byte 0x63 + .byte 0x64 .8byte 0 .8byte 0 -.LLST62: - .8byte .LVL128 - .8byte .LVL132-1 +.LLST31: + .8byte .LVL63 + .8byte .LVL64-1 .2byte 0x1 .byte 0x50 - .8byte .LVL133 - .8byte .LVL137-1 + .8byte .LVL64-1 + .8byte .LVL75 + .2byte 0x4 + .byte 0xf3 + .uleb128 0x1 + .byte 0x52 + .byte 0x9f + .8byte .LVL76 + .8byte .LVL92 + .2byte 0x4 + .byte 0xf3 + .uleb128 0x1 + .byte 0x52 + .byte 0x9f + .8byte 0 + .8byte 0 +.LLST32: + .8byte .LVL64 + .8byte .LVL68-1 .2byte 0x1 .byte 0x50 .8byte 0 .8byte 0 -.LLST63: - .8byte .LVL129 - .8byte .LVL131 - .2byte 0x1 - .byte 0x51 - .8byte .LVL131 - .8byte .LVL132-1 - .2byte 0x2 +.LLST33: + .8byte .LVL65 + .8byte .LVL75 + .2byte 0x6 .byte 0x83 .sleb128 0 - .8byte .LVL134 - .8byte .LVL139 - .2byte 0x1 - .byte 0x64 + .byte 0x8 + .byte 0xff + .byte 0x1a + .byte 0x9f + .8byte .LVL76 + .8byte .LVL92 + .2byte 0x6 + .byte 0x83 + .sleb128 0 + .byte 0x8 + .byte 0xff + .byte 0x1a + .byte 0x9f .8byte 0 .8byte 0 -.LLST64: - .8byte .LVL130 - .8byte .LVL131 +.LLST34: + .8byte .LVL66 + .8byte .LVL67 .2byte 0x5 - .byte 0x71 + .byte 0x85 .sleb128 0 - .byte 0x36 + .byte 0x32 .byte 0x24 .byte 0x9f - .8byte .LVL131 - .8byte .LVL132-1 + .8byte .LVL67 + .8byte .LVL68-1 .2byte 0x1 .byte 0x51 - .8byte .LVL135 - .8byte .LVL136 + .8byte .LVL68-1 + .8byte .LVL75 .2byte 0x5 - .byte 0x84 + .byte 0x85 .sleb128 0 - .byte 0x36 + .byte 0x32 .byte 0x24 .byte 0x9f - .8byte .LVL136 - .8byte .LVL137-1 - .2byte 0x1 - .byte 0x51 - .8byte .LVL137-1 - .8byte .LVL139 + .8byte .LVL76 + .8byte .LVL92 .2byte 0x5 - .byte 0x84 + .byte 0x85 .sleb128 0 - .byte 0x36 + .byte 0x32 .byte 0x24 .byte 0x9f .8byte 0 .8byte 0 -.LLST65: - .8byte .LVL112 - .8byte .LVL113-1 - .2byte 0x1 - .byte 0x50 - .8byte 0 - .8byte 0 -.LLST66: - .8byte .LVL133 - .8byte .LVL134 +.LLST35: + .8byte .LVL64 + .8byte .LVL65 .2byte 0x1 .byte 0x50 .8byte 0 .8byte 0 -.LLST67: - .8byte .LVL138 - .8byte .LVL150 - .2byte 0x1 - .byte 0x63 - .8byte 0 - .8byte 0 -.LLST68: - .8byte .LVL138 - .8byte .LVL150 +.LLST36: + .8byte .LVL69 + .8byte .LVL73 + .2byte 0x6 + .byte 0xf2 + .4byte .Ldebug_info0+4979 + .sleb128 0 + .8byte .LVL76 + .8byte .LVL91 .2byte 0x6 .byte 0xf2 - .4byte .Ldebug_info0+4731 + .4byte .Ldebug_info0+4979 .sleb128 0 .8byte 0 .8byte 0 -.LLST69: - .8byte .LVL138 - .8byte .LVL140 +.LLST37: + .8byte .LVL69 + .8byte .LVL70 .2byte 0x1 .byte 0x50 - .8byte .LVL141 - .8byte .LVL142 + .8byte .LVL70 + .8byte .LVL72 .2byte 0x1 - .byte 0x56 - .8byte .LVL142 - .8byte .LVL148 - .2byte 0x6 - .byte 0x76 + .byte 0x66 + .8byte .LVL72 + .8byte .LVL73 + .2byte 0x8 + .byte 0x72 .sleb128 0 - .byte 0x71 + .byte 0x32 + .byte 0x24 + .byte 0x86 .sleb128 0 .byte 0x22 .byte 0x9f - .8byte .LVL148 - .8byte .LVL149 + .8byte .LVL76 + .8byte .LVL89 .2byte 0x8 - .byte 0x76 - .sleb128 0 - .byte 0x71 + .byte 0x72 + .sleb128 1 + .byte 0x32 + .byte 0x24 + .byte 0x86 .sleb128 0 .byte 0x22 - .byte 0x23 - .uleb128 0x4 .byte 0x9f - .8byte .LVL149 - .8byte .LVL150 - .2byte 0x6 - .byte 0x76 + .8byte .LVL89 + .8byte .LVL90 + .2byte 0x8 + .byte 0x72 .sleb128 0 - .byte 0x71 + .byte 0x32 + .byte 0x24 + .byte 0x86 .sleb128 0 .byte 0x22 .byte 0x9f + .8byte .LVL90 + .8byte .LVL91 + .2byte 0x1 + .byte 0x66 + .8byte 0 + .8byte 0 +.LLST38: + .8byte .LVL72 + .8byte .LVL73 + .2byte 0x1 + .byte 0x52 + .8byte .LVL76 + .8byte .LVL88 + .2byte 0x1 + .byte 0x52 + .8byte .LVL88 + .8byte .LVL89 + .2byte 0x3 + .byte 0x72 + .sleb128 1 + .byte 0x9f .8byte 0 .8byte 0 -.LLST70: - .8byte .LVL138 - .8byte .LVL140 +.LLST39: + .8byte .LVL77 + .8byte .LVL78 + .2byte 0x2 + .byte 0x30 + .byte 0x9f + .8byte .LVL78 + .8byte .LVL86 .2byte 0x1 - .byte 0x57 - .8byte .LVL141 - .8byte .LVL142 + .byte 0x53 + .8byte .LVL86 + .8byte .LVL87 + .2byte 0x3 + .byte 0x73 + .sleb128 1 + .byte 0x9f + .8byte 0 + .8byte 0 +.LLST40: + .8byte .LVL79 + .8byte .LVL80 + .2byte 0x2 + .byte 0x30 + .byte 0x9f + .8byte 0 + .8byte 0 +.LLST41: + .8byte .LVL83 + .8byte .LVL84 .2byte 0x1 - .byte 0x55 - .8byte .LVL142 - .8byte .LVL148 - .2byte 0x6 - .byte 0x75 - .sleb128 0 + .byte 0x51 + .8byte .LVL84 + .8byte .LVL85 + .2byte 0x3 .byte 0x71 - .sleb128 0 - .byte 0x22 + .sleb128 1 .byte 0x9f - .8byte .LVL148 - .8byte .LVL149 - .2byte 0x8 - .byte 0x75 + .8byte 0 + .8byte 0 +.LLST42: + .8byte .LVL77 + .8byte .LVL90 + .2byte 0x1 + .byte 0x56 + .8byte 0 + .8byte 0 +.LLST43: + .8byte .LVL69 + .8byte .LVL72 + .2byte 0x2 + .byte 0x30 + .byte 0x9f + .8byte .LVL72 + .8byte .LVL73 + .2byte 0x5 + .byte 0x72 .sleb128 0 - .byte 0x71 + .byte 0x38 + .byte 0x24 + .byte 0x9f + .8byte .LVL76 + .8byte .LVL78 + .2byte 0x5 + .byte 0x72 .sleb128 0 - .byte 0x22 - .byte 0x23 - .uleb128 0x4 + .byte 0x38 + .byte 0x24 .byte 0x9f - .8byte .LVL149 - .8byte .LVL150 - .2byte 0x6 - .byte 0x75 + .8byte .LVL78 + .8byte .LVL83 + .2byte 0xa + .byte 0x73 .sleb128 0 - .byte 0x71 + .byte 0x34 + .byte 0x24 + .byte 0x72 .sleb128 0 + .byte 0x38 + .byte 0x24 .byte 0x22 .byte 0x9f - .8byte 0 - .8byte 0 -.LLST71: - .8byte .LVL143 - .8byte .LVL145 - .2byte 0xa + .8byte .LVL83 + .8byte .LVL84 + .2byte 0xd .byte 0x73 .sleb128 0 - .byte 0x11 - .sleb128 -1073741821 - .byte 0x1a + .byte 0x34 + .byte 0x24 + .byte 0x72 + .sleb128 0 + .byte 0x38 + .byte 0x24 + .byte 0x22 + .byte 0x71 + .sleb128 0 + .byte 0x22 .byte 0x9f - .8byte .LVL145 - .8byte .LVL147 - .2byte 0x1 - .byte 0x53 - .8byte .LVL147 - .8byte .LVL148 + .8byte .LVL84 + .8byte .LVL85 .2byte 0xf - .byte 0x76 + .byte 0x73 + .sleb128 0 + .byte 0x34 + .byte 0x24 + .byte 0x72 .sleb128 0 + .byte 0x38 + .byte 0x24 + .byte 0x22 .byte 0x71 .sleb128 0 .byte 0x22 - .byte 0x94 - .byte 0x4 - .byte 0x11 - .sleb128 -1073741821 - .byte 0x1a + .byte 0x23 + .uleb128 0x1 .byte 0x9f - .8byte 0 - .8byte 0 -.LLST72: - .8byte .LVL144 - .8byte .LVL146 - .2byte 0x9 - .byte 0x74 + .8byte .LVL86 + .8byte .LVL87 + .2byte 0xc + .byte 0x73 .sleb128 0 - .byte 0xc - .4byte 0x3ffffffc - .byte 0x1a + .byte 0x34 + .byte 0x24 + .byte 0x72 + .sleb128 0 + .byte 0x38 + .byte 0x24 + .byte 0x22 + .byte 0x23 + .uleb128 0x10 .byte 0x9f - .8byte .LVL146 - .8byte .LVL150 - .2byte 0x1 - .byte 0x54 - .8byte 0 - .8byte 0 -.LLST73: - .8byte .LVL138 - .8byte .LVL140 + .8byte .LVL90 + .8byte .LVL91 .2byte 0x2 .byte 0x30 .byte 0x9f .8byte 0 .8byte 0 -.LLST74: - .8byte .LVL120 - .8byte .LVL121-1 - .2byte 0x9 - .byte 0x3 - .8byte sftemp.6194 - .8byte 0 - .8byte 0 -.LLST75: - .8byte .LVL120 - .8byte .LVL125 +.LLST44: + .8byte .LVL69 + .8byte .LVL73 .2byte 0x1 - .byte 0x63 - .8byte 0 - .8byte 0 -.LLST76: - .8byte .LVL121 - .8byte .LVL124-1 + .byte 0x65 + .8byte .LVL76 + .8byte .LVL91 .2byte 0x1 - .byte 0x50 + .byte 0x65 .8byte 0 .8byte 0 -.LLST77: - .8byte .LVL122 - .8byte .LVL125 - .2byte 0x1 - .byte 0x64 +.LLST45: + .8byte .LVL69 + .8byte .LVL71 + .2byte 0x2 + .byte 0x30 + .byte 0x9f .8byte 0 .8byte 0 -.LLST78: - .8byte .LVL122 - .8byte .LVL123 - .2byte 0x5 - .byte 0x84 +.LLST46: + .8byte .LVL69 + .8byte .LVL71 + .2byte 0xb + .byte 0x85 .sleb128 0 - .byte 0x36 + .byte 0x3a + .byte 0x24 + .byte 0x8 + .byte 0x20 .byte 0x24 + .byte 0x8 + .byte 0x20 + .byte 0x26 .byte 0x9f - .8byte .LVL123 - .8byte .LVL124-1 + .8byte 0 + .8byte 0 +.LLST47: + .8byte .LVL79 + .8byte .LVL82 .2byte 0x1 .byte 0x51 - .8byte .LVL124-1 - .8byte .LVL125 - .2byte 0x5 - .byte 0x84 + .8byte .LVL82 + .8byte .LVL87 + .2byte 0xd + .byte 0x76 .sleb128 0 - .byte 0x36 + .byte 0x73 + .sleb128 0 + .byte 0x31 .byte 0x24 + .byte 0x8 + .byte 0xff + .byte 0x1a + .byte 0x26 + .byte 0x33 + .byte 0x1a .byte 0x9f .8byte 0 .8byte 0 -.LLST79: - .8byte .LVL150 - .8byte .LVL151-1 - .2byte 0x9 - .byte 0x3 - .8byte sftemp.6194 - .8byte 0 - .8byte 0 -.LLST80: - .8byte .LVL150 - .8byte .LVL156 +.LLST48: + .8byte .LVL79 + .8byte .LVL80 .2byte 0x1 - .byte 0x63 + .byte 0x51 + .8byte .LVL80 + .8byte .LVL90 + .2byte 0x1 + .byte 0x55 .8byte 0 .8byte 0 -.LLST81: - .8byte .LVL151 - .8byte .LVL155-1 +.LLST49: + .8byte .LVL74 + .8byte .LVL75 .2byte 0x1 - .byte 0x50 + .byte 0x66 .8byte 0 .8byte 0 -.LLST82: - .8byte .LVL152 - .8byte .LVL154 +.LLST50: + .8byte .LVL91 + .8byte .LVL92 .2byte 0x1 - .byte 0x51 - .8byte .LVL154 - .8byte .LVL155-1 - .2byte 0x2 - .byte 0x83 - .sleb128 0 + .byte 0x66 .8byte 0 .8byte 0 -.LLST83: - .8byte .LVL153 - .8byte .LVL154 - .2byte 0x5 - .byte 0x71 - .sleb128 0 - .byte 0x36 - .byte 0x24 - .byte 0x9f - .8byte .LVL154 - .8byte .LVL155-1 +.LLST51: + .8byte .LVL97 + .8byte .LVL98 .2byte 0x1 - .byte 0x51 + .byte 0x64 .8byte 0 .8byte 0 -.LLST16: - .8byte .LVL42 - .8byte .LVL43 - .2byte 0x1 - .byte 0x50 - .8byte .LVL43 - .8byte .LVL50 +.LLST52: + .8byte .LVL97 + .8byte .LVL98 .2byte 0x1 - .byte 0x63 - .8byte .LVL50 - .8byte .LFE225 - .2byte 0x4 - .byte 0xf3 - .uleb128 0x1 .byte 0x50 - .byte 0x9f .8byte 0 .8byte 0 -.LLST17: - .8byte .LVL42 - .8byte .LVL44 - .2byte 0x1 - .byte 0x51 - .8byte .LVL44 - .8byte .LVL45-1 +.LLST53: + .8byte .LVL99 + .8byte .LVL103-1 .2byte 0x1 .byte 0x50 - .8byte .LVL45-1 - .8byte .LFE225 - .2byte 0x4 - .byte 0xf3 - .uleb128 0x1 - .byte 0x51 - .byte 0x9f .8byte 0 .8byte 0 -.LLST18: - .8byte .LVL42 - .8byte .LVL45-1 - .2byte 0x1 - .byte 0x52 - .8byte .LVL45-1 - .8byte .LFE225 - .2byte 0x4 - .byte 0xf3 - .uleb128 0x1 - .byte 0x52 +.LLST54: + .8byte .LVL100 + .8byte .LVL104 + .2byte 0x6 + .byte 0x83 + .sleb128 0 + .byte 0x8 + .byte 0xff + .byte 0x1a .byte 0x9f .8byte 0 .8byte 0 -.LLST19: - .8byte .LVL45 - .8byte .LVL49-1 - .2byte 0x1 - .byte 0x50 - .8byte 0 - .8byte 0 -.LLST20: - .8byte .LVL46 - .8byte .LVL48 - .2byte 0x1 - .byte 0x51 - .8byte .LVL48 - .8byte .LVL49-1 - .2byte 0x2 +.LLST55: + .8byte .LVL101 + .8byte .LVL102 + .2byte 0x10 .byte 0x83 .sleb128 0 - .8byte 0 - .8byte 0 -.LLST21: - .8byte .LVL47 - .8byte .LVL48 - .2byte 0x5 + .byte 0x8 + .byte 0xff + .byte 0x1a + .byte 0x31 + .byte 0x24 + .byte 0x71 + .sleb128 0 + .byte 0x1e .byte 0x71 .sleb128 0 - .byte 0x36 + .byte 0x1e + .byte 0x33 + .byte 0x25 + .byte 0x9f + .8byte .LVL102 + .8byte .LVL103-1 + .2byte 0x22 + .byte 0x83 + .sleb128 0 + .byte 0x8 + .byte 0xff + .byte 0x1a + .byte 0x31 .byte 0x24 + .byte 0x3 + .8byte maxpic + .byte 0x94 + .byte 0x4 + .byte 0x1e + .byte 0x3 + .8byte maxpic + .byte 0x94 + .byte 0x4 + .byte 0x1e + .byte 0x33 + .byte 0x25 .byte 0x9f - .8byte .LVL48 - .8byte .LVL49-1 + .8byte 0 + .8byte 0 +.LLST56: + .8byte .LVL99 + .8byte .LVL100 .2byte 0x1 - .byte 0x51 + .byte 0x50 .8byte 0 .8byte 0 .LLST12: @@ -6521,7 +7609,7 @@ stype.6193: .2byte 0x1 .byte 0x65 .8byte .LVL40 - .8byte .LFE221 + .8byte .LFE224 .2byte 0x4 .byte 0xf3 .uleb128 0x1 @@ -6539,7 +7627,7 @@ stype.6193: .2byte 0x1 .byte 0x64 .8byte .LVL41 - .8byte .LFE221 + .8byte .LFE224 .2byte 0x4 .byte 0xf3 .uleb128 0x1 @@ -6568,17 +7656,17 @@ stype.6193: .2byte 0x1 .byte 0x50 .8byte .LVL5 - .8byte .LVL12 + .8byte .LVL9 .2byte 0x4 .byte 0xf3 .uleb128 0x1 .byte 0x50 .byte 0x9f - .8byte .LVL12 - .8byte .LVL30 + .8byte .LVL9 + .8byte .LVL27 .2byte 0x1 .byte 0x50 - .8byte .LVL30 + .8byte .LVL27 .8byte .LVL31 .2byte 0x4 .byte 0xf3 @@ -6590,7 +7678,7 @@ stype.6193: .2byte 0x1 .byte 0x50 .8byte .LVL32 - .8byte .LFE219 + .8byte .LFE222 .2byte 0x4 .byte 0xf3 .uleb128 0x1 @@ -6611,13 +7699,17 @@ stype.6193: .byte 0x51 .byte 0x9f .8byte .LVL31 - .8byte .LFE219 + .8byte .LFE222 .2byte 0x1 .byte 0x51 .8byte 0 .8byte 0 .LLST2: .8byte .LVL4 + .8byte .LVL9 + .2byte 0x1 + .byte 0x53 + .8byte .LVL11 .8byte .LVL12 .2byte 0x1 .byte 0x53 @@ -6638,10 +7730,6 @@ stype.6193: .2byte 0x1 .byte 0x53 .8byte .LVL26 - .8byte .LVL27 - .2byte 0x1 - .byte 0x53 - .8byte .LVL29 .8byte .LVL31 .2byte 0x1 .byte 0x53 @@ -6649,6 +7737,10 @@ stype.6193: .8byte 0 .LLST3: .8byte .LVL3 + .8byte .LVL7 + .2byte 0x1 + .byte 0x51 + .8byte .LVL10 .8byte .LVL12 .2byte 0x1 .byte 0x51 @@ -6672,24 +7764,17 @@ stype.6193: .8byte .LVL27 .2byte 0x1 .byte 0x51 - .8byte .LVL28 - .8byte .LVL31 - .2byte 0x1 - .byte 0x51 .8byte 0 .8byte 0 .LLST4: - .8byte .LVL11 - .8byte .LVL12 + .8byte .LVL8 + .8byte .LVL9 .2byte 0xd - .byte 0x75 + .byte 0x74 .sleb128 0 - .byte 0x8 - .byte 0x20 - .byte 0x24 - .byte 0x8 - .byte 0x20 - .byte 0x26 + .byte 0xc + .4byte 0xffffffff + .byte 0x1a .byte 0x32 .byte 0x24 .byte 0x73 @@ -6698,10 +7783,10 @@ stype.6193: .8byte 0 .8byte 0 .LLST5: - .8byte .LVL11 - .8byte .LVL12 + .8byte .LVL8 + .8byte .LVL9 .2byte 0x1 - .byte 0x55 + .byte 0x54 .8byte 0 .8byte 0 .LLST6: @@ -6749,10 +7834,10 @@ stype.6193: .byte 0x13 .byte 0x9f .8byte .LVL6 - .8byte .LVL11 + .8byte .LVL8 .2byte 0x1 .byte 0x50 - .8byte .LVL30 + .8byte .LVL27 .8byte .LVL31 .2byte 0x1 .byte 0x50 @@ -6760,29 +7845,22 @@ stype.6193: .8byte 0 .LLST7: .8byte .LVL4 - .8byte .LVL11 - .2byte 0x1 - .byte 0x51 - .8byte .LVL30 - .8byte .LVL31 + .8byte .LVL7 .2byte 0x1 .byte 0x51 .8byte 0 .8byte 0 .LLST8: .8byte .LVL4 - .8byte .LVL7 + .8byte .LVL8 + .2byte 0x2 + .byte 0x30 + .byte 0x9f + .8byte .LVL27 + .8byte .LVL31 .2byte 0x2 .byte 0x30 .byte 0x9f - .8byte .LVL7 - .8byte .LVL8 - .2byte 0x1 - .byte 0x55 - .8byte .LVL9 - .8byte .LVL11 - .2byte 0x1 - .byte 0x55 .8byte 0 .8byte 0 .LLST9: @@ -6791,18 +7869,12 @@ stype.6193: .2byte 0x2 .byte 0x30 .byte 0x9f - .8byte .LVL7 - .8byte .LVL9 + .8byte .LVL27 + .8byte .LVL28 .2byte 0x1 .byte 0x54 - .8byte .LVL9 - .8byte .LVL10 - .2byte 0x3 - .byte 0x74 - .sleb128 1 - .byte 0x9f + .8byte .LVL29 .8byte .LVL30 - .8byte .LVL31 .2byte 0x1 .byte 0x54 .8byte 0 @@ -6858,122 +7930,137 @@ stype.6193: .8byte .LVL6 .2byte 0x3 .byte 0x8 - .byte 0x31 + .byte 0x32 .byte 0x9f .8byte 0 .8byte 0 -.LLST22: - .8byte .LVL51 - .8byte .LVL53 +.LLST57: + .8byte .LVL105 + .8byte .LVL107 .2byte 0x1 .byte 0x50 - .8byte .LVL53 - .8byte .LVL60 + .8byte .LVL107 + .8byte .LVL121 .2byte 0x1 .byte 0x63 - .8byte .LVL60 - .8byte .LVL61 + .8byte .LVL121 + .8byte .LVL122 .2byte 0x1 .byte 0x50 - .8byte .LVL61 - .8byte .LVL62 + .8byte .LVL122 + .8byte .LVL123 .2byte 0x4 .byte 0xf3 .uleb128 0x1 .byte 0x50 .byte 0x9f - .8byte .LVL62 - .8byte .LFE216 + .8byte .LVL123 + .8byte .LFE219 .2byte 0x1 .byte 0x63 .8byte 0 .8byte 0 -.LLST23: - .8byte .LVL51 - .8byte .LVL53 +.LLST58: + .8byte .LVL105 + .8byte .LVL107 .2byte 0x1 .byte 0x50 - .8byte .LVL53 - .8byte .LVL60 + .8byte .LVL107 + .8byte .LVL121 .2byte 0x1 .byte 0x63 - .8byte .LVL60 - .8byte .LVL61 + .8byte .LVL121 + .8byte .LVL122 .2byte 0x1 .byte 0x50 - .8byte .LVL61 - .8byte .LVL62 + .8byte .LVL122 + .8byte .LVL123 .2byte 0x4 .byte 0xf3 .uleb128 0x1 .byte 0x50 .byte 0x9f - .8byte .LVL62 - .8byte .LFE216 + .8byte .LVL123 + .8byte .LFE219 .2byte 0x1 .byte 0x63 .8byte 0 .8byte 0 -.LLST24: - .8byte .LVL52 - .8byte .LVL53 +.LLST59: + .8byte .LVL106 + .8byte .LVL107 + .2byte 0x1 + .byte 0x50 + .8byte .LVL107 + .8byte .LVL110 + .2byte 0x1 + .byte 0x63 + .8byte .LVL115 + .8byte .LVL118 + .2byte 0x1 + .byte 0x63 + .8byte 0 + .8byte 0 +.LLST60: + .8byte .LVL110 + .8byte .LVL111 .2byte 0x3 - .byte 0x70 + .byte 0x83 .sleb128 4 .byte 0x9f - .8byte .LVL53 - .8byte .LVL54-1 + .8byte .LVL111 + .8byte .LVL112-1 .2byte 0x1 .byte 0x50 - .8byte .LVL54-1 - .8byte .LVL55 + .8byte .LVL112-1 + .8byte .LVL113 .2byte 0x3 .byte 0x83 .sleb128 4 .byte 0x9f .8byte 0 .8byte 0 -.LLST25: - .8byte .LVL57 - .8byte .LVL60 +.LLST61: + .8byte .LVL118 + .8byte .LVL121 .2byte 0x1 .byte 0x63 - .8byte .LVL62 - .8byte .LVL74 + .8byte .LVL124 + .8byte .LVL136 .2byte 0x1 .byte 0x63 .8byte 0 .8byte 0 -.LLST26: - .8byte .LVL57 - .8byte .LVL60 +.LLST62: + .8byte .LVL118 + .8byte .LVL121 .2byte 0x1 .byte 0x69 - .8byte .LVL63 - .8byte .LVL74 + .8byte .LVL125 + .8byte .LVL136 .2byte 0x1 .byte 0x69 .8byte 0 .8byte 0 -.LLST27: - .8byte .LVL57 - .8byte .LVL60 +.LLST63: + .8byte .LVL118 + .8byte .LVL121 .2byte 0x1 .byte 0x68 - .8byte .LVL63 - .8byte .LVL64-1 + .8byte .LVL125 + .8byte .LVL126-1 .2byte 0x2 .byte 0x83 .sleb128 0 - .8byte .LVL64-1 - .8byte .LVL73 + .8byte .LVL126-1 + .8byte .LVL135 .2byte 0x1 .byte 0x68 .8byte 0 .8byte 0 -.LLST28: - .8byte .LVL57 - .8byte .LVL58 +.LLST64: + .8byte .LVL118 + .8byte .LVL119 .2byte 0x8 .byte 0x83 .sleb128 0 @@ -6983,8 +8070,8 @@ stype.6193: .byte 0x23 .uleb128 0x1 .byte 0x9f - .8byte .LVL58 - .8byte .LVL60 + .8byte .LVL119 + .8byte .LVL121 .2byte 0x6 .byte 0x83 .sleb128 0 @@ -6992,12 +8079,12 @@ stype.6193: .sleb128 0 .byte 0x22 .byte 0x9f - .8byte .LVL63 - .8byte .LVL72 + .8byte .LVL125 + .8byte .LVL134 .2byte 0x1 .byte 0x63 - .8byte .LVL72 - .8byte .LVL73 + .8byte .LVL134 + .8byte .LVL135 .2byte 0x6 .byte 0x83 .sleb128 0 @@ -7007,65 +8094,65 @@ stype.6193: .byte 0x9f .8byte 0 .8byte 0 -.LLST29: - .8byte .LVL57 - .8byte .LVL58 +.LLST65: + .8byte .LVL118 + .8byte .LVL119 .2byte 0x1 .byte 0x51 - .8byte .LVL72 - .8byte .LVL73 + .8byte .LVL134 + .8byte .LVL135 .2byte 0x1 .byte 0x51 .8byte 0 - .8byte 0 -.LLST30: - .8byte .LVL57 - .8byte .LVL60 + .8byte 0 +.LLST66: + .8byte .LVL118 + .8byte .LVL121 .2byte 0x1 .byte 0x52 - .8byte .LVL63 - .8byte .LVL72 + .8byte .LVL125 + .8byte .LVL134 .2byte 0x2 .byte 0x30 .byte 0x9f - .8byte .LVL72 - .8byte .LVL73 + .8byte .LVL134 + .8byte .LVL135 .2byte 0x1 .byte 0x52 .8byte 0 .8byte 0 -.LLST31: - .8byte .LVL64 - .8byte .LVL65 +.LLST67: + .8byte .LVL126 + .8byte .LVL127 .2byte 0x2 .byte 0x30 .byte 0x9f .8byte 0 .8byte 0 -.LLST32: - .8byte .LVL66 - .8byte .LVL67 +.LLST68: + .8byte .LVL128 + .8byte .LVL129 .2byte 0x2 .byte 0x30 .byte 0x9f - .8byte .LVL67 - .8byte .LVL70 + .8byte .LVL129 + .8byte .LVL132 .2byte 0x5 .byte 0x38 .byte 0x72 .sleb128 0 .byte 0x1c .byte 0x9f - .8byte .LVL70 - .8byte .LVL71 + .8byte .LVL132 + .8byte .LVL133 .2byte 0x5 .byte 0x39 .byte 0x72 .sleb128 0 .byte 0x1c .byte 0x9f - .8byte .LVL71 - .8byte .LVL72 + .8byte .LVL133 + .8byte .LVL134 .2byte 0x5 .byte 0x38 .byte 0x72 @@ -7074,20 +8161,20 @@ stype.6193: .byte 0x9f .8byte 0 .8byte 0 -.LLST33: - .8byte .LVL66 - .8byte .LVL69 +.LLST69: + .8byte .LVL128 + .8byte .LVL131 .2byte 0x1 .byte 0x50 - .8byte .LVL70 - .8byte .LVL72 + .8byte .LVL132 + .8byte .LVL134 .2byte 0x1 .byte 0x50 .8byte 0 .8byte 0 -.LLST34: - .8byte .LVL57 - .8byte .LVL60 +.LLST70: + .8byte .LVL118 + .8byte .LVL121 .2byte 0x7 .byte 0x87 .sleb128 0 @@ -7096,21 +8183,21 @@ stype.6193: .byte 0x22 .byte 0x34 .byte 0x1c - .8byte .LVL66 - .8byte .LVL67 + .8byte .LVL128 + .8byte .LVL129 .2byte 0x2 .byte 0x30 .byte 0x9f - .8byte .LVL67 - .8byte .LVL68 + .8byte .LVL129 + .8byte .LVL130 .2byte 0x1 .byte 0x51 - .8byte .LVL70 - .8byte .LVL72 + .8byte .LVL132 + .8byte .LVL134 .2byte 0x1 .byte 0x51 - .8byte .LVL72 - .8byte .LVL74-1 + .8byte .LVL134 + .8byte .LVL136-1 .2byte 0x7 .byte 0x87 .sleb128 0 @@ -7119,8 +8206,8 @@ stype.6193: .byte 0x22 .byte 0x34 .byte 0x1c - .8byte .LVL75 - .8byte .LVL76-1 + .8byte .LVL137 + .8byte .LFE219 .2byte 0x7 .byte 0x87 .sleb128 0 @@ -7131,903 +8218,987 @@ stype.6193: .byte 0x1c .8byte 0 .8byte 0 +.LLST16: + .8byte .LVL43 + .8byte .LVL50 + .2byte 0x1 + .byte 0x53 + .8byte .LVL50 + .8byte .LVL51 + .2byte 0x3 + .byte 0x73 + .sleb128 1 + .byte 0x9f + .8byte 0 + .8byte 0 +.LLST17: + .8byte .LVL44 + .8byte .LVL45 + .2byte 0x2 + .byte 0x30 + .byte 0x9f + .8byte .LVL45 + .8byte .LVL48 + .2byte 0x1 + .byte 0x55 + .8byte .LVL48 + .8byte .LVL49 + .2byte 0x3 + .byte 0x75 + .sleb128 1 + .byte 0x9f + .8byte 0 + .8byte 0 +.LLST18: + .8byte .LVL45 + .8byte .LVL46 + .2byte 0x2 + .byte 0x30 + .byte 0x9f + .8byte .LVL46 + .8byte .LFE241 + .2byte 0x1 + .byte 0x54 + .8byte 0 + .8byte 0 +.LLST19: + .8byte .LVL44 + .8byte .LVL45 + .2byte 0x8 + .byte 0x73 + .sleb128 0 + .byte 0x36 + .byte 0x24 + .byte 0x77 + .sleb128 0 + .byte 0x22 + .byte 0x9f + .8byte 0 + .8byte 0 +.LLST20: + .8byte .LVL52 + .8byte .LVL53 + .2byte 0x1 + .byte 0x51 + .8byte .LVL53 + .8byte .LVL54-1 + .2byte 0x1 + .byte 0x50 + .8byte .LVL54-1 + .8byte .LFE243 + .2byte 0x4 + .byte 0xf3 + .uleb128 0x1 + .byte 0x51 + .byte 0x9f + .8byte 0 + .8byte 0 +.LLST21: + .8byte .LVL52 + .8byte .LVL54-1 + .2byte 0x1 + .byte 0x52 + .8byte .LVL54-1 + .8byte .LFE243 + .2byte 0x4 + .byte 0xf3 + .uleb128 0x1 + .byte 0x52 + .byte 0x9f + .8byte 0 + .8byte 0 +.LLST22: + .8byte .LVL54 + .8byte .LVL58-1 + .2byte 0x1 + .byte 0x50 + .8byte 0 + .8byte 0 +.LLST23: + .8byte .LVL55 + .8byte .LVL59 + .2byte 0x6 + .byte 0x83 + .sleb128 0 + .byte 0x8 + .byte 0xff + .byte 0x1a + .byte 0x9f + .8byte 0 + .8byte 0 +.LLST24: + .8byte .LVL56 + .8byte .LVL57 + .2byte 0x10 + .byte 0x83 + .sleb128 0 + .byte 0x8 + .byte 0xff + .byte 0x1a + .byte 0x31 + .byte 0x24 + .byte 0x71 + .sleb128 0 + .byte 0x1e + .byte 0x71 + .sleb128 0 + .byte 0x1e + .byte 0x33 + .byte 0x25 + .byte 0x9f + .8byte .LVL57 + .8byte .LVL58-1 + .2byte 0x22 + .byte 0x83 + .sleb128 0 + .byte 0x8 + .byte 0xff + .byte 0x1a + .byte 0x31 + .byte 0x24 + .byte 0x3 + .8byte maxpic + .byte 0x94 + .byte 0x4 + .byte 0x1e + .byte 0x3 + .8byte maxpic + .byte 0x94 + .byte 0x4 + .byte 0x1e + .byte 0x33 + .byte 0x25 + .byte 0x9f + .8byte 0 + .8byte 0 +.LLST25: + .8byte .LVL54 + .8byte .LVL55 + .2byte 0x1 + .byte 0x50 + .8byte 0 + .8byte 0 .section .debug_aranges,"",@progbits - .4byte 0x7c + .4byte 0x9c .2byte 0x2 .4byte .Ldebug_info0 .byte 0x8 .byte 0 .2byte 0 .2byte 0 + .8byte .LFB222 + .8byte .LFE222-.LFB222 + .8byte .LFB224 + .8byte .LFE224-.LFB224 + .8byte .LFB241 + .8byte .LFE241-.LFB241 + .8byte .LFB243 + .8byte .LFE243-.LFB243 + .8byte .LFB232 + .8byte .LFE232-.LFB232 .8byte .LFB219 .8byte .LFE219-.LFB219 - .8byte .LFB221 - .8byte .LFE221-.LFB221 - .8byte .LFB225 - .8byte .LFE225-.LFB225 - .8byte .LFB216 - .8byte .LFE216-.LFB216 - .8byte .LFB217 - .8byte .LFE217-.LFB217 - .8byte .LFB229 - .8byte .LFE229-.LFB229 + .8byte .LFB220 + .8byte .LFE220-.LFB220 + .8byte .LFB239 + .8byte .LFE239-.LFB239 .8byte 0 .8byte 0 .section .debug_ranges,"",@progbits .Ldebug_ranges0: - .8byte .LBB31 - .8byte .LBE31 - .8byte .LBB38 - .8byte .LBE38 - .8byte 0 + .8byte .LBB47 + .8byte .LBE47 + .8byte .LBB54 + .8byte .LBE54 .8byte 0 - .8byte .LBB33 - .8byte .LBE33 - .8byte .LBB35 - .8byte .LBE35 .8byte 0 - .8byte 0 - .8byte .LBB34 - .8byte .LBE34 - .8byte .LBB36 - .8byte .LBE36 - .8byte 0 - .8byte 0 - .8byte .LBB39 - .8byte .LBE39 - .8byte .LBB42 - .8byte .LBE42 + .8byte .LBB49 + .8byte .LBE49 + .8byte .LBB51 + .8byte .LBE51 .8byte 0 .8byte 0 - .8byte .LBB53 - .8byte .LBE53 - .8byte .LBB70 - .8byte .LBE70 + .8byte .LBB50 + .8byte .LBE50 + .8byte .LBB52 + .8byte .LBE52 .8byte 0 .8byte 0 .8byte .LBB55 .8byte .LBE55 - .8byte .LBB67 - .8byte .LBE67 - .8byte .LBB68 - .8byte .LBE68 + .8byte .LBB58 + .8byte .LBE58 .8byte 0 .8byte 0 - .8byte .LBB57 - .8byte .LBE57 - .8byte .LBB62 - .8byte .LBE62 + .8byte .LBB59 + .8byte .LBE59 .8byte .LBB63 .8byte .LBE63 .8byte .LBB64 .8byte .LBE64 .8byte 0 .8byte 0 - .8byte .LBB106 - .8byte .LBE106 - .8byte .LBB120 - .8byte .LBE120 + .8byte .LBB60 + .8byte .LBE60 + .8byte .LBB61 + .8byte .LBE61 + .8byte .LBB62 + .8byte .LBE62 + .8byte 0 + .8byte 0 + .8byte .LBB88 + .8byte .LBE88 + .8byte .LBB104 + .8byte .LBE104 .8byte 0 .8byte 0 - .8byte .LBB108 - .8byte .LBE108 - .8byte .LBB116 - .8byte .LBE116 + .8byte .LBB92 + .8byte .LBE92 + .8byte .LBB100 + .8byte .LBE100 .8byte 0 .8byte 0 .8byte .LBB121 .8byte .LBE121 - .8byte .LBB132 - .8byte .LBE132 + .8byte .LBB126 + .8byte .LBE126 .8byte 0 .8byte 0 + .8byte .LBB127 + .8byte .LBE127 + .8byte .LBB144 + .8byte .LBE144 + .8byte 0 + .8byte 0 + .8byte .LBB129 + .8byte .LBE129 + .8byte .LBB141 + .8byte .LBE141 + .8byte .LBB142 + .8byte .LBE142 + .8byte 0 + .8byte 0 + .8byte .LBB131 + .8byte .LBE131 + .8byte .LBB136 + .8byte .LBE136 + .8byte .LBB137 + .8byte .LBE137 + .8byte .LBB138 + .8byte .LBE138 + .8byte 0 + .8byte 0 + .8byte .LBB176 + .8byte .LBE176 + .8byte .LBB180 + .8byte .LBE180 + .8byte .LBB181 + .8byte .LBE181 + .8byte 0 + .8byte 0 + .8byte .LBB182 + .8byte .LBE182 + .8byte .LBB192 + .8byte .LBE192 + .8byte 0 + .8byte 0 + .8byte .LBB184 + .8byte .LBE184 + .8byte .LBB188 + .8byte .LBE188 + .8byte .LBB189 + .8byte .LBE189 + .8byte .LBB190 + .8byte .LBE190 + .8byte 0 + .8byte 0 + .8byte .LBB185 + .8byte .LBE185 + .8byte .LBB186 + .8byte .LBE186 + .8byte .LBB187 + .8byte .LBE187 + .8byte 0 + .8byte 0 + .8byte .LBB193 + .8byte .LBE193 + .8byte .LBB202 + .8byte .LBE202 + .8byte 0 + .8byte 0 + .8byte .LBB196 + .8byte .LBE196 + .8byte .LBB200 + .8byte .LBE200 + .8byte 0 + .8byte 0 + .8byte .LBB197 + .8byte .LBE197 + .8byte .LBB198 + .8byte .LBE198 + .8byte .LBB199 + .8byte .LBE199 + .8byte 0 + .8byte 0 + .8byte .LFB222 + .8byte .LFE222 + .8byte .LFB224 + .8byte .LFE224 + .8byte .LFB241 + .8byte .LFE241 + .8byte .LFB243 + .8byte .LFE243 + .8byte .LFB232 + .8byte .LFE232 .8byte .LFB219 .8byte .LFE219 - .8byte .LFB221 - .8byte .LFE221 - .8byte .LFB225 - .8byte .LFE225 - .8byte .LFB216 - .8byte .LFE216 - .8byte .LFB217 - .8byte .LFE217 - .8byte .LFB229 - .8byte .LFE229 + .8byte .LFB220 + .8byte .LFE220 + .8byte .LFB239 + .8byte .LFE239 .8byte 0 .8byte 0 .section .debug_line,"",@progbits .Ldebug_line0: .section .debug_str,"MS",@progbits,1 -.LASF368: +.LASF291: .string "crccheck" -.LASF359: +.LASF282: .string "level" -.LASF82: +.LASF81: .string "off_mem_rsvmap" -.LASF165: - .string "UCLASS_I2C_EEPROM" -.LASF319: +.LASF252: + .string "rkf_wf_gray2_repair" +.LASF222: .string "gld16_temp_list" .LASF17: .string "size_t" -.LASF170: - .string "UCLASS_IRQ" -.LASF132: +.LASF131: .string "initrd_start" -.LASF164: - .string "UCLASS_I2C" .LASF13: .string "sizetype" -.LASF252: +.LASF151: .string "net_hostname" -.LASF36: - .string "start" -.LASF205: - .string "UCLASS_SPI" -.LASF168: - .string "UCLASS_I2S" -.LASF274: +.LASF36: + .string "start" +.LASF171: .string "NETLOOP_RESTART" -.LASF166: - .string "UCLASS_I2C_GENERIC" -.LASF178: - .string "UCLASS_MOD_EXP" -.LASF228: - .string "UCLASS_IO_DOMAIN" -.LASF291: +.LASF186: .string "WF_TYPE_GL16" -.LASF199: - .string "UCLASS_RKNAND" -.LASF141: - .string "UCLASS_DEMO" -.LASF324: +.LASF227: .string "gl16_list" -.LASF90: +.LASF89: .string "ih_magic" -.LASF321: - .string "a2_temp_list" -.LASF145: - .string "UCLASS_TEST_PROBE" .LASF224: - .string "UCLASS_KEY" + .string "a2_temp_list" .LASF62: .string "bi_intfreq" .LASF11: .string "phys_addr_t" -.LASF219: - .string "UCLASS_VIDEO_BRIDGE" .LASF5: .string "__u8" -.LASF215: - .string "UCLASS_USB_DEV_GENERIC" -.LASF357: +.LASF280: .string "wf_offset" -.LASF273: +.LASF170: .string "NETLOOP_CONTINUE" -.LASF208: - .string "UCLASS_SPI_GENERIC" .LASF38: .string "flash_info_t" -.LASF183: - .string "UCLASS_PANEL" -.LASF107: +.LASF106: .string "comp" -.LASF102: +.LASF101: .string "image_header_t" -.LASF137: +.LASF136: .string "state" -.LASF158: - .string "UCLASS_CROS_EC" -.LASF392: - .string "/home/lyx/rk3566-11-eink/u-boot" .LASF56: .string "bi_dsp_freq" -.LASF104: +.LASF103: .string "image_start" -.LASF143: - .string "UCLASS_TEST_FDT" .LASF47: .string "bd_info" -.LASF341: +.LASF263: .string "parse_wf_gray2" -.LASF271: - .string "uclass_id" -.LASF94: +.LASF93: .string "ih_load" -.LASF242: +.LASF141: .string "__dtb_dt_spl_begin" -.LASF338: +.LASF260: .string "parse_wf_a2" .LASF7: .string "__u32" -.LASF148: - .string "UCLASS_PCI_EMUL" -.LASF297: +.LASF199: .string "epd_lut_data" -.LASF258: +.LASF157: .string "net_tx_packet" -.LASF223: - .string "UCLASS_FG" -.LASF257: +.LASF156: .string "net_server_ip" -.LASF349: +.LASF264: .string "parse_wf_gray16" -.LASF265: +.LASF164: .string "net_native_vlan" -.LASF221: - .string "UCLASS_VIDEO_CRTC" -.LASF284: +.LASF288: + .string "rkf_wf_input" +.LASF182: .string "WF_TYPE_RESET" -.LASF157: - .string "UCLASS_CODEC" -.LASF390: +.LASF314: .ascii "GNU C11 6.3.1 20170404 -ms" .string "trict-align -march=armv8-a+nosimd -mlittle-endian -mabi=lp64 -g -Os -fno-builtin -ffreestanding -fshort-wchar -fno-stack-protector -fno-delete-null-pointer-checks -fstack-usage -fno-pic -ffunction-sections -fdata-sections -ffixed-r9 -fno-common -ffixed-x18" +.LASF249: + .string "rkf_wf_rpart_fix" .LASF23: .string "errno" -.LASF303: +.LASF206: .string "RKF_WF_GC16" .LASF15: .string "long int" .LASF51: .string "bi_flashsize" -.LASF188: - .string "UCLASS_PHY" -.LASF75: +.LASF74: .string "IRQ_STACK_START_IN" -.LASF86: +.LASF85: .string "size_dt_strings" -.LASF218: - .string "UCLASS_VIDEO" -.LASF268: +.LASF245: + .string "shift" +.LASF167: .string "net_boot_file_size" -.LASF311: +.LASF214: .string "timeandday" -.LASF96: +.LASF95: .string "ih_dcrc" .LASF61: .string "bi_ethspeed" -.LASF140: - .string "UCLASS_ROOT" -.LASF351: +.LASF274: .string "get_wf_frm_num" .LASF29: .string "ide_bus_offset" -.LASF255: +.LASF154: .string "net_server_ethaddr" .LASF64: .string "bi_arch_number" .LASF3: .string "signed char" -.LASF171: - .string "UCLASS_KEYBOARD" .LASF20: .string "uint8_t" -.LASF98: +.LASF97: .string "ih_arch" -.LASF79: +.LASF78: .string "totalsize" -.LASF91: +.LASF90: .string "ih_hcrc" -.LASF344: +.LASF268: .string "idata" -.LASF106: +.LASF105: .string "load" -.LASF290: +.LASF185: .string "WF_TYPE_GC16" -.LASF213: - .string "UCLASS_TPM" .LASF41: .string "lmb_property" -.LASF84: +.LASF83: .string "last_comp_version" .LASF0: .string "unsigned char" -.LASF66: - .string "bi_andr_version" -.LASF139: +.LASF247: + .string "rkf_wf_normal_fix" +.LASF138: .string "images" -.LASF227: - .string "UCLASS_DVFS" .LASF57: .string "bi_ddr_freq" -.LASF172: - .string "UCLASS_LED" -.LASF93: +.LASF219: + .string "gc16_temp_list" +.LASF92: .string "ih_size" -.LASF202: - .string "UCLASS_SCMI_AGENT" -.LASF231: - .string "UCLASS_MDIO" +.LASF104: + .string "image_len" +.LASF246: + .string "wf_table_to_4bit_wf_lut_data" .LASF25: .string "_Bool" -.LASF277: - .string "net_state" -.LASF167: - .string "UCLASS_I2C_MUX" -.LASF298: +.LASF248: + .string "table" +.LASF200: .string "frame_num" .LASF14: .string "char" .LASF27: .string "_binary_u_boot_bin_start" -.LASF389: +.LASF310: .string "memset" -.LASF217: - .string "UCLASS_USB_GADGET_GENERIC" -.LASF275: +.LASF172: .string "NETLOOP_SUCCESS" -.LASF331: +.LASF236: .string "output" -.LASF337: +.LASF255: + .string "old_gray" +.LASF262: .string "pbuf" -.LASF281: +.LASF178: .string "p_current" -.LASF272: +.LASF180: .string "net_loop_state" -.LASF356: +.LASF279: .string "templist" -.LASF305: +.LASF208: .string "RKF_WF_GLR16" -.LASF156: - .string "UCLASS_AMP" -.LASF194: - .string "UCLASS_PWRSEQ" -.LASF122: +.LASF121: .string "fit_hdr_fdt" -.LASF266: +.LASF165: .string "net_restart_wrap" -.LASF254: +.LASF153: .string "net_ethaddr" -.LASF363: - .string "_min2" -.LASF383: +.LASF306: .string "flags" -.LASF343: - .string "gray" -.LASF99: +.LASF312: + .string "strlen" +.LASF98: .string "ih_type" -.LASF80: +.LASF79: .string "off_dt_struct" .LASF52: .string "bi_flashoffset" -.LASF267: +.LASF166: .string "net_boot_file_name" -.LASF367: +.LASF290: .string "check_wf_crc" -.LASF142: - .string "UCLASS_TEST" -.LASF92: +.LASF91: .string "ih_time" -.LASF358: +.LASF281: .string "get_wf_level" -.LASF195: - .string "UCLASS_RAM" -.LASF161: - .string "UCLASS_ETH" -.LASF103: - .string "image_info" -.LASF348: +.LASF315: + .string "/home/hzb/sdk/ebc-dev/rk_eink/../epdlut/rkf_waveform.c" +.LASF270: .string "temp_data" -.LASF109: +.LASF108: .string "arch" -.LASF328: +.LASF231: .string "a2_list" -.LASF340: +.LASF266: .string "input" -.LASF336: +.LASF261: .string "temp" .LASF31: .string "select_hwpart" -.LASF259: +.LASF158: .string "net_rx_packets" -.LASF278: +.LASF175: .string "mem_malloc_start" -.LASF74: +.LASF73: .string "_datarelro_start_ofs" .LASF19: .string "ulong" -.LASF339: - .string "parse_wf_auto" -.LASF95: +.LASF94: .string "ih_ep" .LASF43: .string "lmb_region" -.LASF354: +.LASF277: .string "waveform" -.LASF388: +.LASF309: .string "printf" -.LASF117: +.LASF294: + .string "check_wf_version" +.LASF116: .string "fit_uname_os" +.LASF195: + .string "WF_TYPE_RK_GL16" .LASF58: .string "bi_bootflags" -.LASF256: +.LASF155: .string "net_ip" -.LASF250: +.LASF149: .string "net_dns_server" -.LASF270: +.LASF169: .string "net_ping_ip" .LASF45: .string "memory" -.LASF77: +.LASF76: .string "fdt_header" -.LASF279: +.LASF176: .string "mem_malloc_end" -.LASF174: - .string "UCLASS_MAILBOX" -.LASF129: +.LASF128: .string "rd_end" -.LASF364: +.LASF287: .string "rkf_wf_get_lut" -.LASF134: +.LASF133: .string "cmdline_start" -.LASF333: +.LASF238: .string "temperture" -.LASF345: +.LASF269: .string "odata" -.LASF322: +.LASF225: .string "reset_list" -.LASF203: - .string "UCLASS_SCSI" -.LASF391: - .string "drivers/video/rk_eink/epdlut/rkf_waveform.c" -.LASF175: - .string "UCLASS_MASS_STORAGE" +.LASF228: + .string "glr16_list" .LASF1: .string "long unsigned int" -.LASF150: - .string "UCLASS_SIMPLE_BUS" -.LASF301: +.LASF204: .string "RKF_WF_RESET" -.LASF310: +.LASF213: .string "format" -.LASF251: +.LASF150: .string "net_nis_domain" -.LASF286: +.LASF184: .string "WF_TYPE_GRAY4" -.LASF360: +.LASF283: .string "_max1" -.LASF361: +.LASF284: .string "_max2" -.LASF124: +.LASF123: .string "fit_noffset_fdt" -.LASF276: +.LASF173: .string "NETLOOP_FAIL" -.LASF222: - .string "UCLASS_WDT" +.LASF234: + .string "maxpic" .LASF53: .string "bi_sramstart" .LASF28: .string "_binary_u_boot_bin_end" -.LASF85: +.LASF84: .string "boot_cpuid_phys" -.LASF120: +.LASF119: .string "fit_uname_rd" -.LASF320: +.LASF223: .string "du_temp_list" -.LASF209: - .string "UCLASS_SYSCON" -.LASF115: +.LASF114: .string "fit_uname_cfg" -.LASF204: - .string "UCLASS_SERIAL" -.LASF264: +.LASF163: .string "net_our_vlan" -.LASF153: - .string "UCLASS_BLK" -.LASF110: +.LASF109: .string "image_info_t" -.LASF149: - .string "UCLASS_USB_EMUL" -.LASF385: +.LASF191: + .string "PVI_WF_MAX" +.LASF308: .string "kmalloc" -.LASF306: +.LASF209: .string "RKF_WF_GLD16" -.LASF187: - .string "UCLASS_PCI_GENERIC" -.LASF330: +.LASF253: + .string "rkf_wf_a2_repair" +.LASF233: .string "crc32_table" -.LASF105: - .string "image_len" -.LASF318: +.LASF316: + .string "/home/hzb/sdk/u-boot" +.LASF221: .string "glr16_temp_list" .LASF59: .string "bi_ip_addr" -.LASF369: +.LASF292: .string "readcrc" -.LASF189: - .string "UCLASS_PINCONFIG" -.LASF347: +.LASF267: .string "decode_wf_reset" -.LASF211: - .string "UCLASS_THERMAL" -.LASF113: +.LASF112: .string "legacy_hdr_os_copy" .LASF9: .string "long long int" -.LASF350: +.LASF273: .string "decode_wf_data" -.LASF292: +.LASF187: .string "WF_TYPE_GLR16" +.LASF202: + .string "wf_table" .LASF24: .string "___strtok" -.LASF269: +.LASF168: .string "net_boot_file_expected_size_in_blocks" .LASF16: .string "__kernel_size_t" -.LASF182: - .string "UCLASS_NVME" -.LASF111: +.LASF110: .string "bootm_headers" .LASF37: .string "protect" -.LASF214: - .string "UCLASS_USB" -.LASF225: - .string "UCLASS_RC" -.LASF159: - .string "UCLASS_DISPLAY" -.LASF263: +.LASF162: .string "net_null_ethaddr" -.LASF327: +.LASF230: .string "du_list" -.LASF226: - .string "UCLASS_CHARGE_DISPLAY" -.LASF243: +.LASF142: .string "load_addr" -.LASF116: +.LASF115: .string "fit_hdr_os" -.LASF374: +.LASF298: .string "n_accum" -.LASF72: +.LASF71: .string "_datarelrolocal_start_ofs" +.LASF196: + .string "WF_TYPE_RK_GC16" +.LASF243: + .string "overlay_lut" .LASF8: .string "unsigned int" .LASF18: .string "ushort" -.LASF346: - .string "temp1" -.LASF295: - .string "WF_TYPE_GRAY32" -.LASF191: - .string "UCLASS_PMIC" -.LASF112: +.LASF174: + .string "net_state" +.LASF111: .string "legacy_hdr_os" -.LASF81: +.LASF80: .string "off_dt_strings" -.LASF240: +.LASF139: .string "monitor_flash_len" -.LASF176: - .string "UCLASS_MISC" .LASF49: .string "bi_memsize" -.LASF308: +.LASF211: .string "rkf_waveform" -.LASF329: +.LASF232: .string "global_waveform" .LASF26: .string "image_base" -.LASF379: +.LASF301: .string "n_data" -.LASF210: - .string "UCLASS_SYSRESET" -.LASF288: - .string "WF_TYPE_AUTO" -.LASF282: +.LASF179: .string "current" -.LASF307: +.LASF210: .string "RKF_WF_A2" -.LASF163: - .string "UCLASS_FIRMWARE" -.LASF173: - .string "UCLASS_LPC" -.LASF169: - .string "UCLASS_IDE" -.LASF355: +.LASF271: + .string "temp1" +.LASF256: + .string "new_gray" +.LASF278: .string "list" -.LASF381: +.LASF304: .string "block" -.LASF138: +.LASF137: .string "bootm_headers_t" .LASF55: .string "bi_arm_freq" -.LASF197: - .string "UCLASS_REMOTEPROC" -.LASF108: +.LASF107: .string "type" -.LASF119: +.LASF118: .string "fit_hdr_rd" .LASF54: .string "bi_sramsize" -.LASF315: +.LASF218: .string "reset_temp_list" -.LASF162: - .string "UCLASS_GPIO" -.LASF192: - .string "UCLASS_PWM" .LASF40: .string "long double" -.LASF387: +.LASF313: .string "strncmp" -.LASF325: - .string "glr16_list" -.LASF128: +.LASF259: + .string "tempdata" +.LASF127: .string "rd_start" -.LASF193: - .string "UCLASS_POWER_DOMAIN" -.LASF196: - .string "UCLASS_REGULATOR" -.LASF245: +.LASF147: + .string "net_gateway" +.LASF144: .string "save_size" -.LASF154: - .string "UCLASS_CLK" -.LASF71: +.LASF70: .string "_datarel_start_ofs" -.LASF101: +.LASF100: .string "ih_name" -.LASF97: +.LASF96: .string "ih_os" -.LASF293: +.LASF188: .string "WF_TYPE_GLD16" -.LASF135: +.LASF134: .string "cmdline_end" -.LASF260: +.LASF159: .string "net_rx_packet" -.LASF239: - .string "LOGF_MAX_CATEGORIES" -.LASF373: +.LASF297: .string "a_size" +.LASF193: + .string "WF_TYPE_RK_GLR16" .LASF33: .string "size" .LASF10: .string "long long unsigned int" -.LASF89: +.LASF88: .string "image_header" -.LASF309: +.LASF212: .string "length" -.LASF287: +.LASF183: .string "WF_TYPE_GRAY2" .LASF21: .string "__be32" .LASF50: .string "bi_flashstart" -.LASF118: +.LASF117: .string "fit_noffset_os" -.LASF362: +.LASF285: .string "_min1" -.LASF177: - .string "UCLASS_MMC" -.LASF238: - .string "UCLASS_INVALID" -.LASF302: +.LASF286: + .string "_min2" +.LASF102: + .string "image_info" +.LASF258: + .string "rkf_lut_wf_table" +.LASF205: .string "RKF_WF_DU" -.LASF216: - .string "UCLASS_USB_HUB" -.LASF232: - .string "UCLASS_EBC" -.LASF296: +.LASF197: .string "WF_TYPE_MAX" -.LASF394: +.LASF318: .string "rkf_wf_get_version" .LASF39: .string "flash_info" -.LASF83: +.LASF82: .string "version" .LASF44: .string "region" -.LASF87: +.LASF86: .string "size_dt_struct" -.LASF234: - .string "UCLASS_RNG" -.LASF179: - .string "UCLASS_MTD" -.LASF378: +.LASF300: .string "crc_table" -.LASF76: +.LASF75: .string "fdt32_t" -.LASF332: +.LASF257: + .string "pix0" +.LASF237: .string "lut_type" -.LASF181: - .string "UCLASS_NORTHBRIDGE" .LASF60: .string "bi_enetaddr" -.LASF382: +.LASF305: .string "kzalloc" -.LASF393: +.LASF317: .string "mtd_info" -.LASF246: +.LASF145: .string "in_addr" -.LASF261: +.LASF160: .string "net_rx_packet_len" -.LASF334: +.LASF240: .string "stype" -.LASF241: +.LASF140: .string "__dtb_dt_begin" -.LASF198: - .string "UCLASS_RESET" -.LASF121: +.LASF120: .string "fit_noffset_rd" -.LASF152: - .string "UCLASS_AHCI" .LASF12: .string "phys_size_t" -.LASF155: - .string "UCLASS_CPU" -.LASF70: +.LASF69: .string "FIQ_STACK_START" -.LASF136: +.LASF135: .string "verify" .LASF30: .string "name" -.LASF233: - .string "UCLASS_EINK_DISPLAY" -.LASF184: - .string "UCLASS_PANEL_BACKLIGHT" -.LASF212: - .string "UCLASS_TIMER" -.LASF207: - .string "UCLASS_SPI_FLASH" -.LASF316: - .string "gc16_temp_list" .LASF63: .string "bi_busfreq" .LASF6: .string "short int" -.LASF190: - .string "UCLASS_PINCTRL" -.LASF200: - .string "UCLASS_RAMDISK" -.LASF353: +.LASF276: .string "mode" -.LASF376: +.LASF302: .string "crc_build_table32" -.LASF147: - .string "UCLASS_I2C_EMUL" -.LASF206: - .string "UCLASS_SPMI" -.LASF144: - .string "UCLASS_TEST_BUS" -.LASF371: +.LASF272: + .string "parse_wf_data" +.LASF295: .string "crc_32" -.LASF300: +.LASF203: .string "rkf_waveform_type" -.LASF244: +.LASF143: .string "save_addr" -.LASF133: +.LASF132: .string "initrd_end" -.LASF380: +.LASF303: .string "kfree" -.LASF342: +.LASF250: + .string "regal_fix" +.LASF265: .string "parse_wf_reset" -.LASF326: +.LASF229: .string "gld16_list" -.LASF73: +.LASF72: .string "_datarellocal_start_ofs" -.LASF313: +.LASF194: + .string "WF_TYPE_RK_GLD16" +.LASF216: .string "panel_info" -.LASF237: - .string "UCLASS_COUNT" +.LASF239: + .string "regal_pix" .LASF32: .string "block_drvr" -.LASF386: +.LASF311: .string "memcpy" .LASF22: .string "gfp_t" .LASF35: .string "flash_id" -.LASF229: - .string "UCLASS_CRYPTO" -.LASF127: +.LASF126: .string "fit_noffset_setup" -.LASF88: +.LASF87: .string "working_fdt" -.LASF253: +.LASF152: .string "net_root_path" -.LASF160: - .string "UCLASS_DMA" -.LASF68: +.LASF67: .string "bd_t" -.LASF235: - .string "UCLASS_DMC" -.LASF247: +.LASF146: .string "s_addr" -.LASF352: +.LASF275: .string "get_wf_buf" -.LASF314: +.LASF217: .string "full_version" -.LASF262: +.LASF161: .string "net_bcast_ethaddr" .LASF65: .string "bi_boot_params" -.LASF335: +.LASF241: .string "sftemp" -.LASF280: +.LASF177: .string "mem_malloc_brk" -.LASF248: - .string "net_gateway" .LASF48: .string "bi_memstart" -.LASF283: +.LASF181: .string "epd_lut_type" -.LASF220: - .string "UCLASS_VIDEO_CONSOLE" -.LASF289: +.LASF189: .string "WF_TYPE_A2" .LASF46: .string "reserved" -.LASF384: +.LASF307: .string "free" -.LASF236: - .string "UCLASS_PD" -.LASF67: +.LASF66: .string "bi_dram" -.LASF377: +.LASF299: .string "a_poly" .LASF2: .string "short unsigned int" -.LASF78: +.LASF77: .string "magic" -.LASF372: +.LASF296: .string "a_data" -.LASF125: +.LASF124: .string "fit_hdr_setup" -.LASF294: +.LASF190: .string "WF_TYPE_GCC16" -.LASF114: +.LASF113: .string "legacy_hdr_valid" +.LASF251: + .string "rkf_wf_regal_fix" .LASF42: .string "base" -.LASF201: - .string "UCLASS_RTC" +.LASF235: + .string "need_pic" .LASF34: .string "sector_count" -.LASF100: +.LASF99: .string "ih_comp" -.LASF285: +.LASF198: .string "WF_TYPE_GRAY16" -.LASF130: +.LASF244: + .string "lut_data" +.LASF129: .string "ft_addr" -.LASF230: - .string "UCLASS_ETH_PHY" -.LASF304: +.LASF207: .string "RKF_WF_GL16" -.LASF370: +.LASF293: .string "check_wf_format" -.LASF365: - .string "rkf_wf_input" .LASF4: .string "uchar" -.LASF131: +.LASF130: .string "ft_len" -.LASF375: - .string "decode_wf_auto" -.LASF317: +.LASF220: .string "gl16_temp_list" -.LASF299: +.LASF201: .string "data" -.LASF180: - .string "UCLASS_NOP" -.LASF126: +.LASF192: + .string "WF_TYPE_AUTO" +.LASF125: .string "fit_uname_setup" -.LASF185: - .string "UCLASS_PCH" -.LASF186: - .string "UCLASS_PCI" -.LASF249: +.LASF254: + .string "rkf_lut_init_wf_table" +.LASF148: .string "net_netmask" -.LASF323: +.LASF226: .string "gc16_list" -.LASF69: +.LASF68: .string "IRQ_STACK_START" -.LASF151: - .string "UCLASS_ADC" -.LASF366: +.LASF289: .string "waveform_file" -.LASF146: - .string "UCLASS_SPI_EMUL" -.LASF312: +.LASF215: .string "panel_name" -.LASF123: +.LASF242: + .string "is_uboot" +.LASF122: .string "fit_uname_fdt" .hidden free .ident "GCC: (Linaro GCC 6.3-2017.05) 6.3.1 20170404" diff --git a/u-boot/drivers/video/rk_eink/rk_ebc.h b/u-boot/drivers/video/rk_eink/rk_ebc.h index d152d6cc5b6..c144a14f807 100644 --- a/u-boot/drivers/video/rk_eink/rk_ebc.h +++ b/u-boot/drivers/video/rk_eink/rk_ebc.h @@ -40,7 +40,6 @@ struct ebc_panel { u32 *lut_pbuf; u32 lut_pbuf_size; struct epd_lut_data lut_data; - struct epd_lut_ops lut_ops; }; struct rk_ebc_tcon_ops { diff --git a/u-boot/drivers/video/rk_eink/rk_eink_display.c b/u-boot/drivers/video/rk_eink/rk_eink_display.c index 768b2fa7609..540e6c2feeb 100644 --- a/u-boot/drivers/video/rk_eink/rk_eink_display.c +++ b/u-boot/drivers/video/rk_eink/rk_eink_display.c @@ -160,7 +160,7 @@ static int read_waveform(struct udevice *dev) flush_dcache_range((ulong)plat->lut_pbuf, ALIGN((ulong)plat->lut_pbuf + cnt, CONFIG_SYS_CACHELINE_SIZE)); - ret = epd_lut_from_mem_init(plat->lut_pbuf, &plat->lut_ops); + ret = epd_lut_from_mem_init(plat->lut_pbuf); if (ret < 0) { printf("lut init failed\n"); return -EINVAL; @@ -521,7 +521,6 @@ static int eink_display(struct udevice *dev, u32 pre_img_buf, u32 frame_num; struct rockchip_eink_display_priv *priv = dev_get_priv(dev); struct ebc_panel *plat = dev_get_platdata(dev); - struct epd_lut_ops *lut_ops = &plat->lut_ops; struct udevice *ebc_pwr_dev = priv->ebc_pwr_dev; struct rk_ebc_pwr_ops *pwr_ops = NULL; struct udevice *ebc_tcon_dev = priv->ebc_tcon_dev; @@ -540,13 +539,14 @@ static int eink_display(struct udevice *dev, u32 pre_img_buf, temperature = 25; } - if (!lut_ops->lut_get) { - printf("get lut ops failed\n"); - return -EIO; - } - lut_ops->lut_get(&plat->lut_data, lut_type, temperature); - frame_num = plat->lut_data.frame_num; - debug("lut_type=%d, frame num=%d, temp=%d\n", lut_type, + if(!plat->lut_data.wf_table[0]) + plat->lut_data.wf_table[0] = kzalloc(MAXFRAME * 32 * 32, GFP_KERNEL); + epd_lut_get(&plat->lut_data, lut_type, temperature, WF_4BIT, 0); + kfree(plat->lut_data.wf_table[0]); + plat->lut_data.wf_table[0] = NULL; + + frame_num = plat->lut_data.frame_num & 0xff; + printk("lut_type=%d, frame num=%d, temp=%d\n", lut_type, frame_num, temperature); ebc_tcon_ops->wait_for_last_frame_complete(ebc_tcon_dev); @@ -876,6 +876,12 @@ static int rockchip_eink_display_ofdata_to_platdata(struct udevice *dev) struct device_node *disp_mem; struct device_node *waveform_mem; struct ebc_panel *plat = dev_get_platdata(dev); + void * data; + int len; + + data = (void *)dev_read_prop(dev, "wf,mode_table", &len); + if (len > 0 && pvi_wf_add_custom_mode_table(data, len)) + return -ENODEV; plat->width = dev_read_u32_default(dev, "panel,width", 0); plat->height = dev_read_u32_default(dev, "panel,height", 0); diff --git a/u-boot/drivers/video/video-uclass.c b/u-boot/drivers/video/video-uclass.c index 6a0e4faedfe..e0f60868c32 100644 --- a/u-boot/drivers/video/video-uclass.c +++ b/u-boot/drivers/video/video-uclass.c @@ -60,7 +60,7 @@ static ulong alloc_fb(struct udevice *dev, ulong *addrp) if (!plat->size) return 0; - align = plat->align ? plat->align : 1 << 20; + align = plat->align ? plat->align : 2 << 20; /* kernel cma alloc alignment. */ base = *addrp - plat->size; base &= ~(align - 1); plat->base = base; @@ -87,13 +87,14 @@ int video_reserve(ulong *addrp) size = DRM_ROCKCHIP_FB_SIZE + MEMORY_POOL_SIZE + cubic_lut_size; *addrp = *addrp - size; - *addrp &= ~((1 << 20) - 1); + *addrp &= ~((2 << 20) - 1); /* kernel cma alloc alignment. */ debug("Reserving %lx Bytes for video at: %lx\n", size, *addrp); #else for (uclass_find_first_device(UCLASS_VIDEO, &dev); dev; uclass_find_next_device(&dev)) { size = alloc_fb(dev, addrp); + *addrp &= ~((2 << 20) - 1); /* kernel cma alloc alignment. */ debug("%s: Reserving %lx bytes at %lx for video device '%s'\n", __func__, size, *addrp, dev->name); } diff --git a/u-boot/dts/Kconfig b/u-boot/dts/Kconfig index f1c1d9a15e3..0905e296165 100644 --- a/u-boot/dts/Kconfig +++ b/u-boot/dts/Kconfig @@ -29,6 +29,14 @@ config OF_CONTROL This feature provides for run-time configuration of U-Boot via a flattened device tree. +config OF_ADDR_SIZE_AUTO_NOPARENT + bool "FDT get address/size cell auto from parent node" + depends on OF_CONTROL && ARM64 + help + Enable this to use 'fdtdec_get_addr_size_auto_noparent' instead of + 'fdtdec_get_addr_size_fixed' in case of 64-bit U-Boot use 32-bit + platform dtb. + config OF_BOARD_FIXUP bool "Board-specific manipulation of Device Tree" help diff --git a/u-boot/env/envf.c b/u-boot/env/envf.c index e6263118954..f48bfb77505 100644 --- a/u-boot/env/envf.c +++ b/u-boot/env/envf.c @@ -211,9 +211,15 @@ char *envf_get(struct blk_desc *desc, const char *name) { const char *list = NULL; static env_t *env; /* static */ + static enum if_type if_type; + static int devnum; - if (!env) + /* Only when first read env or storage is changed, need to read again. */ + if (!env || if_type != desc->if_type || devnum != desc->devnum) { env = envf_read(desc); + if_type = desc->if_type; + devnum = desc->devnum; + } if (!env) goto out; diff --git a/u-boot/include/asm-generic/global_data.h b/u-boot/include/asm-generic/global_data.h index 16766fbaed1..22c30c8f314 100644 --- a/u-boot/include/asm-generic/global_data.h +++ b/u-boot/include/asm-generic/global_data.h @@ -66,7 +66,7 @@ typedef struct global_data { unsigned long env_addr; /* Address of Environment struct */ unsigned long env_valid; /* Environment valid? enum env_valid */ - unsigned long ram_top; /* Top address of RAM used by U-Boot */ + uint64_t ram_top; /* Top address of RAM used by U-Boot */ unsigned long ram_top_ext_size; /* Extend size of RAM top */ unsigned long relocaddr; /* Start address of U-Boot in RAM */ phys_size_t ram_size; /* RAM size */ @@ -149,7 +149,7 @@ typedef struct global_data { u32 rollback_index; #endif #ifdef CONFIG_PSTORE - u64 pstore_addr; + ulong pstore_addr; u32 pstore_size; #endif } gd_t; diff --git a/u-boot/include/blk.h b/u-boot/include/blk.h index 72dac439ee9..b61a252ec48 100644 --- a/u-boot/include/blk.h +++ b/u-boot/include/blk.h @@ -245,6 +245,18 @@ struct blk_ops { unsigned long (*write)(struct udevice *dev, lbaint_t start, lbaint_t blkcnt, const void *buffer); + /** + * write_zeroes() - write zeroes to a block device + * + * @dev: Device to write to + * @start: Start block number to write (0=first) + * @blkcnt: Number of blocks to write + * @return number of blocks written, or -ve error number (see the + * IS_ERR_VALUE() macro + */ + unsigned long (*write_zeroes)(struct udevice *dev, lbaint_t start, + lbaint_t blkcnt); + /** * erase() - erase a section of a block device * @@ -289,6 +301,8 @@ unsigned long blk_dread(struct blk_desc *block_dev, lbaint_t start, lbaint_t blkcnt, void *buffer); unsigned long blk_dwrite(struct blk_desc *block_dev, lbaint_t start, lbaint_t blkcnt, const void *buffer); +unsigned long blk_dwrite_zeroes(struct blk_desc *block_dev, lbaint_t start, + lbaint_t blkcnt); unsigned long blk_derase(struct blk_desc *block_dev, lbaint_t start, lbaint_t blkcnt); @@ -650,6 +664,17 @@ ulong blk_read_devnum(enum if_type if_type, int devnum, lbaint_t start, ulong blk_write_devnum(enum if_type if_type, int devnum, lbaint_t start, lbaint_t blkcnt, const void *buffer); +/** + * blk_write_zeroes_devnum() - write blocks to a device with zero data + * + * @if_type: Block device type + * @devnum: Device number + * @blkcnt: Number of blocks to write + * @return number of blocks written, or -ve error number on error + */ +ulong blk_write_zeroes_devnum(enum if_type if_type, int devnum, lbaint_t start, + lbaint_t blkcnt); + /** * blk_erase_devnum() - erase blocks to a device * diff --git a/u-boot/include/configs/evb_rv1126b.h b/u-boot/include/configs/evb_rv1126b.h new file mode 100644 index 00000000000..8818923c604 --- /dev/null +++ b/u-boot/include/configs/evb_rv1126b.h @@ -0,0 +1,25 @@ +/* + * SPDX-License-Identifier: GPL-2.0+ + * + * Copyright (c) 2025 Rockchip Electronics Co., Ltd + */ + +#ifndef __CONFIGS_RV1126B_EVB_H +#define __CONFIGS_RV1126B_EVB_H + +#include + +#ifndef CONFIG_SPL_BUILD + +#undef ROCKCHIP_DEVICE_SETTINGS +#define ROCKCHIP_DEVICE_SETTINGS \ + "stdout=serial,vidconsole\0" \ + "stderr=serial,vidconsole\0" + +#define CONFIG_SYS_MMC_ENV_DEV 0 + +#undef CONFIG_BOOTCOMMAND +#define CONFIG_BOOTCOMMAND RKIMG_BOOTCOMMAND + +#endif /* CONFIG_SPL_BUILD */ +#endif /* __CONFIGS_RV1126B_EVB_H */ diff --git a/u-boot/include/configs/rv1108_common.h b/u-boot/include/configs/rv1108_common.h index 0463f236b8c..c3981e677b0 100644 --- a/u-boot/include/configs/rv1108_common.h +++ b/u-boot/include/configs/rv1108_common.h @@ -22,7 +22,7 @@ /* SPL support */ #define CONFIG_SPL_STACK 0x10080700 #define CONFIG_SPL_TEXT_BASE 0x10080800 -#define CONFIG_SPL_MAX_SIZE 0x4000 +#define CONFIG_SPL_MAX_SIZE 0x5000 /* BSS setup */ #define CONFIG_SPL_BSS_MAX_SIZE 0x100 diff --git a/u-boot/include/configs/rv1126b_common.h b/u-boot/include/configs/rv1126b_common.h new file mode 100644 index 00000000000..49853dfc499 --- /dev/null +++ b/u-boot/include/configs/rv1126b_common.h @@ -0,0 +1,91 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * (C) Copyright 2025 Rockchip Electronics Co., Ltd + * + */ + +#ifndef __CONFIG_RV1126B_COMMON_H +#define __CONFIG_RV1126B_COMMON_H + +#define CFG_CPUID_OFFSET 0x22 + +#include "rockchip-common.h" + +#define CONFIG_SPL_FRAMEWORK +#define CONFIG_SPL_TEXT_BASE 0x4fe00000 +#define CONFIG_SPL_MAX_SIZE 0x00040000 +#define CONFIG_SPL_BSS_START_ADDR 0x4fee0000 +#define CONFIG_SPL_BSS_MAX_SIZE 0x20000 +#define CONFIG_SPL_STACK 0x4fe00000 +#ifdef CONFIG_SPL_LOAD_FIT_ADDRESS +#undef CONFIG_SPL_LOAD_FIT_ADDRESS +#endif +#define CONFIG_SPL_LOAD_FIT_ADDRESS 0x42000000 + +#define CONFIG_SYS_MALLOC_LEN (32 << 20) +#define CONFIG_SYS_CBSIZE 1024 + +#ifdef CONFIG_SUPPORT_USBPLUG +#define CONFIG_SYS_TEXT_BASE 0x40000000 +#else +#define CONFIG_SYS_TEXT_BASE 0x40200000 +#endif + +#define CONFIG_SYS_INIT_SP_ADDR 0x40600000 +#define CONFIG_SYS_LOAD_ADDR 0x40700800 +#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* 64M */ + +#define GICD_BASE 0x21201000 +#define GICC_BASE 0x21202000 + +#define CONFIG_BOUNCE_BUFFER +/* For most, U-Boot no need to use 0-1G space. */ +#define CONFIG_SYS_SDRAM_BASE 0x40000000 +#define SDRAM_MAX_SIZE 0xc0000000ULL /* max 3G */ +#define CONFIG_SYS_NONCACHED_MEMORY (1 << 20) /* 1M */ + +/* env used only in U-Boot */ +#ifndef CONFIG_SPL_BUILD +/* usb mass storage */ +#define CONFIG_USB_FUNCTION_MASS_STORAGE +#define CONFIG_ROCKUSB_G_DNL_PID 0x110f + +#ifdef CONFIG_ARM64 +#define ENV_MEM_LAYOUT_SETTINGS \ + "scriptaddr=0x40600000\0" \ + "pxefile_addr_r=0x40700000\0" \ + "fdt_addr_r=0x48300000\0" \ + "kernel_addr_r=0x40200000\0" \ + "kernel_addr_aarch32_r=0x40208000\0" \ + "kernel_addr_c=0x45480000\0" \ + "ramdisk_addr_r=0x4a200000\0" +#endif + +#include + +#define CONFIG_EXTRA_ENV_SETTINGS \ + ENV_MEM_LAYOUT_SETTINGS \ + "partitions=" PARTS_RKIMG \ + ROCKCHIP_DEVICE_SETTINGS \ + RKIMG_DET_BOOTDEV \ + BOOTENV + +#undef RKIMG_BOOTCOMMAND +#ifdef CONFIG_FIT_SIGNATURE +#define RKIMG_BOOTCOMMAND \ + "boot_fit;" +#else +#define RKIMG_BOOTCOMMAND \ + "boot_fit;" \ + "boot_android ${devtype} ${devnum};" +#endif +#endif /* !CONFIG_SPL_BUILD */ + +/* rockchip ohci host driver */ +#define CONFIG_USB_OHCI_NEW +#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 1 + +#define CONFIG_PREBOOT +#define CONFIG_LIB_HW_RAND + +#endif /* __CONFIG_RV1126B_COMMON_H */ diff --git a/u-boot/include/crypto.h b/u-boot/include/crypto.h index d5eed1aea2e..464e196c010 100644 --- a/u-boot/include/crypto.h +++ b/u-boot/include/crypto.h @@ -23,6 +23,10 @@ #define CRYPTO_RSA2048 BIT(12) #define CRYPTO_RSA3072 BIT(13) #define CRYPTO_RSA4096 BIT(14) +#define CRYPTO_SM2 BIT(15) +#define CRYPTO_ECC_192R1 BIT(16) +#define CRYPTO_ECC_224R1 BIT(17) +#define CRYPTO_ECC_256R1 BIT(18) #define CRYPTO_DES BIT(20) #define CRYPTO_AES BIT(21) @@ -37,6 +41,7 @@ #define BYTE2WORD(bytes) ((bytes) / 4) #define BITS2BYTE(nbits) ((nbits) / 8) #define BITS2WORD(nbits) ((nbits) / 32) +#define WORD2BYTE(words) ((words) * 4) enum RK_CRYPTO_MODE { RK_MODE_ECB = 0, @@ -66,6 +71,13 @@ typedef struct { u32 *c; /* Optional, a accelerate factor for some crypto */ } rsa_key; +typedef struct { + u32 algo; /* Algorithm: CRYPTO_SM2/CRYPTO_ECC_192R1/CRYPTO_ECC_224R1... */ + u32 *x; /* public key x */ + u32 *y; /* public key y */ + u32 *d; /* private key */ +} ec_key; + typedef struct { u32 algo; u32 mode; @@ -76,6 +88,15 @@ typedef struct { u32 iv_len; } cipher_context; +typedef struct { + u32 algo; + u32 mode; + u32 key_len; + const u8 *iv; + u32 iv_len; + u32 fw_keyid; +} cipher_fw_context; + struct dm_crypto_ops { /* Hardware algorithm capability */ u32 (*capability)(struct udevice *dev); @@ -88,6 +109,11 @@ struct dm_crypto_ops { /* RSA verify */ int (*rsa_verify)(struct udevice *dev, rsa_key *ctx, u8 *sign, u8 *output); + + /* EC verify */ + int (*ec_verify)(struct udevice *dev, ec_key *ctx, + u8 *hash, u32 hash_len, u8 *sign); + /* HMAC init/update/final */ int (*hmac_init)(struct udevice *dev, sha_context *ctx, u8 *key, u32 key_len); @@ -107,6 +133,11 @@ struct dm_crypto_ops { const u8 *in, u32 len, const u8 *aad, u32 aad_len, u8 *out, u8 *tag); + /* cipher firmware encryption and decryption */ + int (*cipher_fw_crypt)(struct udevice *dev, cipher_fw_context *ctx, + const u8 *in, u8 *out, u32 len, bool enc); + + ulong (*keytable_addr)(struct udevice *dev); }; /** @@ -198,6 +229,19 @@ int crypto_sha_regions_csum(struct udevice *dev, sha_context *ctx, */ int crypto_rsa_verify(struct udevice *dev, rsa_key *ctx, u8 *sign, u8 *output); +/** + * crypto_ec_verify() - Crypto ec verify + * + * @dev: crypto device + * @ctx: ec key context + * @hash: hash data buffer + * @hash_len: hash data length + * @sign: signature + * + * @return 0 on success, otherwise failed + */ +int crypto_ec_verify(struct udevice *dev, ec_key *ctx, u8 *hash, u32 hash_len, u8 *sign); + /** * crypto_hmac_init() - Crypto hmac init * @@ -275,4 +319,26 @@ int crypto_ae(struct udevice *dev, cipher_context *ctx, const u8 *in, u32 len, const u8 *aad, u32 aad_len, u8 *out, u8 *tag); +/** + * crypto_fw_cipher() - Crypto cipher firmware crypt + * + * @dev: crypto device + * @ctx: cipher firmware context + * @in: input data buffer + * @out: output data buffer + * @len: input data length + * @enc: true for encrypt, false for decrypt + * @return 0 on success, otherwise failed + */ +int crypto_fw_cipher(struct udevice *dev, cipher_fw_context *ctx, + const u8 *in, u8 *out, u32 len, bool enc); + +/** + * crypto_keytable_addr() - Crypto keytable address + * + * @dev: crypto device + * @return crypto keytable address + */ +ulong crypto_keytable_addr(struct udevice *dev); + #endif diff --git a/u-boot/include/dm/uclass-id.h b/u-boot/include/dm/uclass-id.h index c2e12d4fa39..0829251c3bf 100644 --- a/u-boot/include/dm/uclass-id.h +++ b/u-boot/include/dm/uclass-id.h @@ -114,6 +114,7 @@ enum uclass_id { UCLASS_RNG, /* Random Number Generator */ UCLASS_DMC, /* Dynamic Memory Interface */ UCLASS_PD, /* power delivery */ + UCLASS_KEYLAD, /* keylad used to transfer otp key */ UCLASS_COUNT, UCLASS_INVALID = -1, }; diff --git a/u-boot/include/drm/drm_dp_helper.h b/u-boot/include/drm/drm_dp_helper.h index 3711c875dba..73d8299e4dc 100644 --- a/u-boot/include/drm/drm_dp_helper.h +++ b/u-boot/include/drm/drm_dp_helper.h @@ -1165,6 +1165,13 @@ drm_dp_channel_coding_supported(const u8 dpcd[DP_RECEIVER_CAP_SIZE]) return dpcd[DP_MAIN_LINK_CHANNEL_CODING] & DP_CAP_ANSI_8B10B; } +static inline bool +drm_dp_alternate_scrambler_reset_cap(const u8 dpcd[DP_RECEIVER_CAP_SIZE]) +{ + return dpcd[DP_EDP_CONFIGURATION_CAP] & + DP_ALTERNATE_SCRAMBLER_RESET_CAP; +} + struct drm_dp_aux_msg { unsigned int address; u8 request; diff --git a/u-boot/include/dt-bindings/clock/rockchip,rv1126b-cru.h b/u-boot/include/dt-bindings/clock/rockchip,rv1126b-cru.h new file mode 100644 index 00000000000..8000ac5814f --- /dev/null +++ b/u-boot/include/dt-bindings/clock/rockchip,rv1126b-cru.h @@ -0,0 +1,787 @@ +/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ +/* + * Copyright (c) 2024 Rockchip Electronics Co., Ltd. + * Author: Elaine Zhang + */ + +#ifndef _DT_BINDINGS_CLK_ROCKCHIP_RV1126B_H +#define _DT_BINDINGS_CLK_ROCKCHIP_RV1126B_H + +/* pll clocks */ +#define PLL_GPLL 1 +#define PLL_CPLL 2 +#define PLL_AUPLL 3 +#define ARMCLK 4 +#define SCLK_DDR 5 + +/* clk (clocks) */ +#define CLK_CPLL_DIV20 8 +#define CLK_CPLL_DIV10 9 +#define CLK_CPLL_DIV8 10 +#define CLK_GPLL_DIV8 11 +#define CLK_GPLL_DIV6 12 +#define CLK_GPLL_DIV4 13 +#define CLK_CPLL_DIV3 14 +#define CLK_GPLL_DIV3 15 +#define CLK_CPLL_DIV2 16 +#define CLK_GPLL_DIV2 17 +#define CLK_CM_FRAC0 18 +#define CLK_CM_FRAC1 19 +#define CLK_CM_FRAC2 20 +#define CLK_UART_FRAC0 21 +#define CLK_UART_FRAC1 22 +#define CLK_AUDIO_FRAC0 23 +#define CLK_AUDIO_FRAC1 24 +#define CLK_AUDIO_INT0 25 +#define CLK_AUDIO_INT1 26 +#define SCLK_UART0_SRC 27 +#define SCLK_UART1 28 +#define SCLK_UART2 29 +#define SCLK_UART3 30 +#define SCLK_UART4 31 +#define SCLK_UART5 32 +#define SCLK_UART6 33 +#define SCLK_UART7 34 +#define MCLK_SAI0 35 +#define MCLK_SAI1 36 +#define MCLK_SAI2 37 +#define MCLK_PDM 38 +#define CLKOUT_PDM 39 +#define MCLK_ASRC0 40 +#define MCLK_ASRC1 41 +#define MCLK_ASRC2 42 +#define MCLK_ASRC3 43 +#define CLK_ASRC0 44 +#define CLK_ASRC1 45 +#define CLK_CORE_PLL 46 +#define CLK_NPU_PLL 47 +#define CLK_VEPU_PLL 48 +#define CLK_ISP_PLL 49 +#define CLK_AISP_PLL 50 +#define CLK_SARADC0_SRC 51 +#define CLK_SARADC1_SRC 52 +#define CLK_SARADC2_SRC 53 +#define HCLK_NPU_ROOT 54 +#define PCLK_NPU_ROOT 55 +#define ACLK_VEPU_ROOT 56 +#define HCLK_VEPU_ROOT 57 +#define PCLK_VEPU_ROOT 58 +#define CLK_CORE_RGA_SRC 59 +#define ACLK_GMAC_ROOT 60 +#define ACLK_VI_ROOT 61 +#define HCLK_VI_ROOT 62 +#define PCLK_VI_ROOT 63 +#define DCLK_VICAP_ROOT 64 +#define CLK_SYS_DSMC_ROOT 65 +#define ACLK_VDO_ROOT 66 +#define ACLK_RKVDEC_ROOT 67 +#define HCLK_VDO_ROOT 68 +#define PCLK_VDO_ROOT 69 +#define DCLK_OOC_SRC 70 +#define DCLK_VOP 71 +#define DCLK_DECOM_SRC 72 +#define PCLK_DDR_ROOT 73 +#define ACLK_SYSMEM_SRC 74 +#define ACLK_TOP_ROOT 75 +#define ACLK_BUS_ROOT 76 +#define HCLK_BUS_ROOT 77 +#define PCLK_BUS_ROOT 78 +#define CCLK_SDMMC0 79 +#define CCLK_SDMMC1 80 +#define CCLK_EMMC 81 +#define SCLK_2X_FSPI0 82 +#define CLK_GMAC_PTP_REF_SRC 83 +#define CLK_GMAC_125M 84 +#define CLK_TIMER_ROOT 85 +#define TCLK_WDT_NS_SRC 86 +#define TCLK_WDT_S 87 +#define TCLK_WDT_HPMCU 88 +#define CLK_CAN0 89 +#define CLK_CAN1 90 +#define PCLK_PERI_ROOT 91 +#define ACLK_PERI_ROOT 92 +#define CLK_I2C_BUS_SRC 93 +#define CLK_SPI0 94 +#define CLK_SPI1 95 +#define BUSCLK_PMU_SRC 96 +#define CLK_PWM0 97 +#define CLK_PWM2 98 +#define CLK_PWM3 99 +#define CLK_PKA_RKCE_SRC 100 +#define ACLK_RKCE_SRC 101 +#define ACLK_VCP_ROOT 102 +#define HCLK_VCP_ROOT 103 +#define PCLK_VCP_ROOT 104 +#define CLK_CORE_FEC_SRC 105 +#define CLK_CORE_AVSP_SRC 106 +#define CLK_50M_GMAC_IOBUF_VI 107 +#define PCLK_TOP_ROOT 108 +#define CLK_MIPI0_OUT2IO 109 +#define CLK_MIPI1_OUT2IO 110 +#define CLK_MIPI2_OUT2IO 111 +#define CLK_MIPI3_OUT2IO 112 +#define CLK_CIF_OUT2IO 113 +#define CLK_MAC_OUT2IO 114 +#define MCLK_SAI0_OUT2IO 115 +#define MCLK_SAI1_OUT2IO 116 +#define MCLK_SAI2_OUT2IO 117 +#define CLK_CM_FRAC0_SRC 118 +#define CLK_CM_FRAC1_SRC 119 +#define CLK_CM_FRAC2_SRC 120 +#define CLK_UART_FRAC0_SRC 121 +#define CLK_UART_FRAC1_SRC 122 +#define CLK_AUDIO_FRAC0_SRC 123 +#define CLK_AUDIO_FRAC1_SRC 124 +#define ACLK_NPU_ROOT 125 +#define HCLK_RKNN 126 +#define ACLK_RKNN 127 +#define PCLK_GPIO3 128 +#define DBCLK_GPIO3 129 +#define PCLK_IOC_VCCIO3 130 +#define PCLK_SARADC0 131 +#define CLK_SARADC0 132 +#define HCLK_SDMMC1 133 +#define HCLK_VEPU 134 +#define ACLK_VEPU 135 +#define CLK_CORE_VEPU 136 +#define HCLK_FEC 137 +#define ACLK_FEC 138 +#define CLK_CORE_FEC 139 +#define HCLK_AVSP 140 +#define ACLK_AVSP 141 +#define BUSCLK_PMU1_ROOT 142 +#define HCLK_AISP 143 +#define ACLK_AISP 144 +#define CLK_CORE_AISP 145 +#define CLK_CORE_ISP_ROOT 146 +#define PCLK_DSMC 147 +#define ACLK_DSMC 148 +#define HCLK_CAN0 149 +#define HCLK_CAN1 150 +#define PCLK_GPIO2 151 +#define DBCLK_GPIO2 152 +#define PCLK_GPIO4 153 +#define DBCLK_GPIO4 154 +#define PCLK_GPIO5 155 +#define DBCLK_GPIO5 156 +#define PCLK_GPIO6 157 +#define DBCLK_GPIO6 158 +#define PCLK_GPIO7 159 +#define DBCLK_GPIO7 160 +#define PCLK_IOC_VCCIO2 161 +#define PCLK_IOC_VCCIO4 162 +#define PCLK_IOC_VCCIO5 163 +#define PCLK_IOC_VCCIO6 164 +#define PCLK_IOC_VCCIO7 165 +#define HCLK_ISP 166 +#define ACLK_ISP 167 +#define CLK_CORE_ISP 168 +#define HCLK_VICAP 169 +#define ACLK_VICAP 170 +#define DCLK_VICAP 171 +#define ISP0CLK_VICAP 172 +#define HCLK_VPSS 173 +#define ACLK_VPSS 174 +#define CLK_CORE_VPSS 175 +#define PCLK_CSI2HOST0 176 +#define DCLK_CSI2HOST0 177 +#define PCLK_CSI2HOST1 178 +#define DCLK_CSI2HOST1 179 +#define PCLK_CSI2HOST2 180 +#define DCLK_CSI2HOST2 181 +#define PCLK_CSI2HOST3 182 +#define DCLK_CSI2HOST3 183 +#define HCLK_SDMMC0 184 +#define ACLK_GMAC 185 +#define PCLK_GMAC 186 +#define CLK_GMAC_PTP_REF 187 +#define PCLK_CSIPHY0 188 +#define PCLK_CSIPHY1 189 +#define PCLK_MACPHY 190 +#define PCLK_SARADC1 191 +#define CLK_SARADC1 192 +#define PCLK_SARADC2 193 +#define CLK_SARADC2 194 +#define ACLK_RKVDEC 195 +#define HCLK_RKVDEC 196 +#define CLK_HEVC_CA_RKVDEC 197 +#define ACLK_VOP 198 +#define HCLK_VOP 199 +#define HCLK_RKJPEG 200 +#define ACLK_RKJPEG 201 +#define ACLK_RKMMU_DECOM 202 +#define HCLK_RKMMU_DECOM 203 +#define DCLK_DECOM 204 +#define ACLK_DECOM 205 +#define PCLK_DECOM 206 +#define PCLK_MIPI_DSI 207 +#define PCLK_DSIPHY 208 +#define ACLK_OOC 209 +#define ACLK_SYSMEM 210 +#define PCLK_DDRC 211 +#define PCLK_DDRMON 212 +#define CLK_TIMER_DDRMON 213 +#define PCLK_DFICTRL 214 +#define PCLK_DDRPHY 215 +#define PCLK_DMA2DDR 216 +#define CLK_RCOSC_SRC 217 +#define BUSCLK_PMU_MUX 218 +#define BUSCLK_PMU_ROOT 219 +#define PCLK_PMU 220 +#define CLK_XIN_RC_DIV 221 +#define CLK_32K 222 +#define PCLK_PMU_GPIO0 223 +#define DBCLK_PMU_GPIO0 224 +#define PCLK_PMU_HP_TIMER 225 +#define CLK_PMU_HP_TIMER 226 +#define CLK_PMU_32K_HP_TIMER 227 +#define PCLK_PWM1 228 +#define CLK_PWM1 229 +#define CLK_OSC_PWM1 230 +#define CLK_RC_PWM1 231 +#define CLK_FREQ_PWM1 232 +#define CLK_COUNTER_PWM1 233 +#define PCLK_I2C2 234 +#define CLK_I2C2 235 +#define PCLK_UART0 236 +#define SCLK_UART0 237 +#define PCLK_RCOSC_CTRL 238 +#define CLK_OSC_RCOSC_CTRL 239 +#define CLK_REF_RCOSC_CTRL 240 +#define PCLK_IOC_PMUIO0 241 +#define CLK_REFOUT 242 +#define CLK_PREROLL 243 +#define CLK_PREROLL_32K 244 +#define HCLK_PMU_SRAM 245 +#define PCLK_WDT_LPMCU 246 +#define TCLK_WDT_LPMCU 247 +#define CLK_LPMCU 248 +#define CLK_LPMCU_RTC 249 +#define PCLK_LPMCU_MAILBOX 250 +#define HCLK_OOC 251 +#define PCLK_SPI2AHB 252 +#define HCLK_SPI2AHB 253 +#define HCLK_FSPI1 254 +#define HCLK_XIP_FSPI1 255 +#define SCLK_1X_FSPI1 256 +#define PCLK_IOC_PMUIO1 257 +#define PCLK_AUDIO_ADC_PMU 258 +#define MCLK_AUDIO_ADC_PMU 259 +#define MCLK_AUDIO_ADC_DIV4_PMU 260 +#define MCLK_LPSAI 261 +#define ACLK_GIC400 262 +#define PCLK_WDT_NS 263 +#define TCLK_WDT_NS 264 +#define PCLK_WDT_HPMCU 265 +#define HCLK_CACHE 266 +#define PCLK_HPMCU_MAILBOX 267 +#define PCLK_HPMCU_INTMUX 268 +#define CLK_HPMCU 269 +#define CLK_HPMCU_RTC 270 +#define PCLK_RKDMA 271 +#define ACLK_RKDMA 272 +#define PCLK_DCF 273 +#define ACLK_DCF 274 +#define HCLK_RGA 275 +#define ACLK_RGA 276 +#define CLK_CORE_RGA 277 +#define PCLK_TIMER 278 +#define CLK_TIMER0 279 +#define CLK_TIMER1 280 +#define CLK_TIMER2 281 +#define CLK_TIMER3 282 +#define CLK_TIMER4 283 +#define CLK_TIMER5 284 +#define PCLK_I2C0 285 +#define CLK_I2C0 286 +#define PCLK_I2C1 287 +#define CLK_I2C1 288 +#define PCLK_I2C3 289 +#define CLK_I2C3 290 +#define PCLK_I2C4 291 +#define CLK_I2C4 292 +#define PCLK_I2C5 293 +#define CLK_I2C5 294 +#define PCLK_SPI0 295 +#define PCLK_SPI1 296 +#define PCLK_PWM0 297 +#define CLK_OSC_PWM0 298 +#define CLK_RC_PWM0 299 +#define PCLK_PWM2 300 +#define CLK_OSC_PWM2 301 +#define CLK_RC_PWM2 302 +#define PCLK_PWM3 303 +#define CLK_OSC_PWM3 304 +#define CLK_RC_PWM3 305 +#define PCLK_UART1 306 +#define PCLK_UART2 307 +#define PCLK_UART3 308 +#define PCLK_UART4 309 +#define PCLK_UART5 310 +#define PCLK_UART6 311 +#define PCLK_UART7 312 +#define PCLK_TSADC 313 +#define CLK_TSADC 314 +#define HCLK_SAI0 315 +#define HCLK_SAI1 316 +#define HCLK_SAI2 317 +#define HCLK_RKDSM 318 +#define MCLK_RKDSM 319 +#define HCLK_PDM 320 +#define HCLK_ASRC0 321 +#define HCLK_ASRC1 322 +#define PCLK_AUDIO_ADC_BUS 323 +#define MCLK_AUDIO_ADC_BUS 324 +#define MCLK_AUDIO_ADC_DIV4_BUS 325 +#define PCLK_RKCE 326 +#define HCLK_NS_RKCE 327 +#define PCLK_OTPC_NS 328 +#define CLK_SBPI_OTPC_NS 329 +#define CLK_USER_OTPC_NS 330 +#define CLK_OTPC_ARB 331 +#define PCLK_OTP_MASK 332 +#define CLK_TSADC_PHYCTRL 333 +#define LRCK_SRC_ASRC0 334 +#define LRCK_DST_ASRC0 335 +#define LRCK_SRC_ASRC1 336 +#define LRCK_DST_ASRC1 337 +#define PCLK_KEY_READER 338 +#define ACLK_NSRKCE 339 +#define CLK_PKA_NSRKCE 340 +#define PCLK_RTC_ROOT 341 +#define PCLK_GPIO1 342 +#define DBCLK_GPIO1 343 +#define PCLK_IOC_VCCIO1 344 +#define ACLK_USB3OTG 345 +#define CLK_REF_USB3OTG 346 +#define CLK_SUSPEND_USB3OTG 347 +#define HCLK_USB2HOST 348 +#define HCLK_ARB_USB2HOST 349 +#define PCLK_RTC_TEST 350 +#define HCLK_EMMC 351 +#define HCLK_FSPI0 352 +#define HCLK_XIP_FSPI0 353 +#define PCLK_PIPEPHY 354 +#define PCLK_USB2PHY 355 +#define CLK_REF_PIPEPHY_CPLL_SRC 356 +#define CLK_REF_PIPEPHY 357 +#define HCLK_VPSL 358 +#define ACLK_VPSL 359 +#define CLK_CORE_VPSL 360 + +#define CLK_NR_CLKS (CLK_CORE_VPSL + 1) + +// ======================= TOPCRU module definition bank=0 ======================== +// TOPCRU_SOFTRST_CON15(Offset:0xA3C) +#define SRST_PRESETN_CRU 0x000000F1 +#define SRST_PRESETN_CRU_BIU 0x000000F2 + +// ======================= BUSCRU module definition bank=1 ======================== +// BUSCRU_SOFTRST_CON00(Offset:0xA00) +#define SRST_ARESETN_TOP_BIU 0x00040000 +#define SRST_ARESETN_RKCE_BIU 0x00040001 +#define SRST_ARESETN_BUS_BIU 0x00040002 +#define SRST_HRESETN_BUS_BIU 0x00040003 +#define SRST_PRESETN_BUS_BIU 0x00040004 +#define SRST_PRESETN_CRU_BUS 0x00040005 +#define SRST_PRESETN_SYS_GRF 0x00040006 +#define SRST_HRESETN_BOOTROM 0x00040007 +#define SRST_ARESETN_GIC400 0x00040008 +#define SRST_ARESETN_SPINLOCK 0x00040009 +#define SRST_PRESETN_WDT_NS 0x0004000A +#define SRST_TRESETN_WDT_NS 0x0004000B + +// BUSCRU_SOFTRST_CON01(Offset:0xA04) +#define SRST_PRESETN_WDT_HPMCU 0x00040010 +#define SRST_TRESETN_WDT_HPMCU 0x00040011 +#define SRST_HRESETN_CACHE 0x00040012 +#define SRST_PRESETN_HPMCU_MAILBOX 0x00040013 +#define SRST_PRESETN_HPMCU_INTMUX 0x00040014 +#define SRST_RESETN_HPMCU_FULL_CLUSTER 0x00040015 +#define SRST_RESETN_HPMCU_PWUP 0x00040016 +#define SRST_RESETN_HPMCU_ONLY_CORE 0x00040017 +#define SRST_TRESETN_HPMCU_JTAG 0x00040018 +#define SRST_PRESETN_RKDMA 0x0004001B +#define SRST_ARESETN_RKDMA 0x0004001C + +// BUSCRU_SOFTRST_CON02(Offset:0xA08) +#define SRST_PRESETN_DCF 0x00040020 +#define SRST_ARESETN_DCF 0x00040021 +#define SRST_HRESETN_RGA 0x00040022 +#define SRST_ARESETN_RGA 0x00040023 +#define SRST_RESETN_CORE_RGA 0x00040024 +#define SRST_PRESETN_TIMER 0x00040025 +#define SRST_RESETN_TIMER0 0x00040026 +#define SRST_RESETN_TIMER1 0x00040027 +#define SRST_RESETN_TIMER2 0x00040028 +#define SRST_RESETN_TIMER3 0x00040029 +#define SRST_RESETN_TIMER4 0x0004002A +#define SRST_RESETN_TIMER5 0x0004002B +#define SRST_ARESETN_RKCE 0x0004002C +#define SRST_RESETN_PKA_RKCE 0x0004002D +#define SRST_HRESETN_RKRNG_S 0x0004002E +#define SRST_HRESETN_RKRNG_NS 0x0004002F + +// BUSCRU_SOFTRST_CON03(Offset:0xA0C) +#define SRST_PRESETN_I2C0 0x00040030 +#define SRST_RESETN_I2C0 0x00040031 +#define SRST_PRESETN_I2C1 0x00040032 +#define SRST_RESETN_I2C1 0x00040033 +#define SRST_PRESETN_I2C3 0x00040034 +#define SRST_RESETN_I2C3 0x00040035 +#define SRST_PRESETN_I2C4 0x00040036 +#define SRST_RESETN_I2C4 0x00040037 +#define SRST_PRESETN_I2C5 0x00040038 +#define SRST_RESETN_I2C5 0x00040039 +#define SRST_PRESETN_SPI0 0x0004003A +#define SRST_RESETN_SPI0 0x0004003B +#define SRST_PRESETN_SPI1 0x0004003C +#define SRST_RESETN_SPI1 0x0004003D + +// BUSCRU_SOFTRST_CON04(Offset:0xA10) +#define SRST_PRESETN_PWM0 0x00040040 +#define SRST_RESETN_PWM0 0x00040041 +#define SRST_PRESETN_PWM2 0x00040044 +#define SRST_RESETN_PWM2 0x00040045 +#define SRST_PRESETN_PWM3 0x00040048 +#define SRST_RESETN_PWM3 0x00040049 + +// BUSCRU_SOFTRST_CON05(Offset:0xA14) +#define SRST_PRESETN_UART1 0x00040050 +#define SRST_SRESETN_UART1 0x00040051 +#define SRST_PRESETN_UART2 0x00040052 +#define SRST_SRESETN_UART2 0x00040053 +#define SRST_PRESETN_UART3 0x00040054 +#define SRST_SRESETN_UART3 0x00040055 +#define SRST_PRESETN_UART4 0x00040056 +#define SRST_SRESETN_UART4 0x00040057 +#define SRST_PRESETN_UART5 0x00040058 +#define SRST_SRESETN_UART5 0x00040059 +#define SRST_PRESETN_UART6 0x0004005A +#define SRST_SRESETN_UART6 0x0004005B +#define SRST_PRESETN_UART7 0x0004005C +#define SRST_SRESETN_UART7 0x0004005D + +// BUSCRU_SOFTRST_CON06(Offset:0xA18) +#define SRST_PRESETN_TSADC 0x00040060 +#define SRST_RESETN_TSADC 0x00040061 +#define SRST_HRESETN_SAI0 0x00040062 +#define SRST_MRESETN_SAI0 0x00040063 +#define SRST_HRESETN_SAI1 0x00040064 +#define SRST_MRESETN_SAI1 0x00040065 +#define SRST_HRESETN_SAI2 0x00040066 +#define SRST_MRESETN_SAI2 0x00040067 +#define SRST_HRESETN_RKDSM 0x00040068 +#define SRST_MRESETN_RKDSM 0x00040069 +#define SRST_HRESETN_PDM 0x0004006A +#define SRST_MRESETN_PDM 0x0004006B +#define SRST_RESETN_PDM 0x0004006C + +// BUSCRU_SOFTRST_CON07(Offset:0xA1C) +#define SRST_HRESETN_ASRC0 0x00040070 +#define SRST_RESETN_ASRC0 0x00040071 +#define SRST_HRESETN_ASRC1 0x00040072 +#define SRST_RESETN_ASRC1 0x00040073 +#define SRST_PRESETN_AUDIO_ADC_BUS 0x00040074 +#define SRST_MRESETN_AUDIO_ADC_BUS 0x00040075 +#define SRST_PRESETN_RKCE 0x00040076 +#define SRST_HRESETN_NS_RKCE 0x00040077 +#define SRST_PRESETN_OTPC_NS 0x00040078 +#define SRST_RESETN_SBPI_OTPC_NS 0x00040079 +#define SRST_RESETN_USER_OTPC_NS 0x0004007A +#define SRST_RESETN_OTPC_ARB 0x0004007B +#define SRST_PRESETN_OTP_MASK 0x0004007C +#define SRST_RESETN_TSADC_PHYCTRL 0x0004007E + +// ======================= PERICRU module definition bank=2 ======================= +// PERICRU_SOFTRST_CON00(Offset:0xA00) +#define SRST_ARESETN_PERI_BIU 0x00080000 +#define SRST_PRESETN_PERI_BIU 0x00080001 +#define SRST_PRESETN_RTC_BIU 0x00080002 +#define SRST_PRESETN_CRU_PERI 0x00080003 +#define SRST_PRESETN_PERI_GRF 0x00080004 +#define SRST_PRESETN_GPIO1 0x00080005 +#define SRST_DBRESETN_GPIO1 0x00080006 +#define SRST_PRESETN_IOC_VCCIO1 0x00080007 +#define SRST_ARESETN_USB3OTG 0x00080008 +#define SRST_HRESETN_USB2HOST 0x0008000B +#define SRST_HRESETN_ARB_USB2HOST 0x0008000C +#define SRST_PRESETN_RTC_TEST 0x0008000D + +// PERICRU_SOFTRST_CON01(Offset:0xA04) +#define SRST_HRESETN_EMMC 0x00080010 +#define SRST_HRESETN_FSPI0 0x00080011 +#define SRST_HRESETN_XIP_FSPI0 0x00080012 +#define SRST_SRESETN_2X_FSPI0 0x00080013 +#define SRST_RESETN_UTMI_USB2HOST 0x00080015 +#define SRST_RESETN_REF_PIPEPHY 0x00080017 +#define SRST_PRESETN_PIPEPHY 0x00080018 +#define SRST_PRESETN_PIPEPHY_GRF 0x00080019 +#define SRST_PRESETN_USB2PHY 0x0008001A +#define SRST_RESETN_POR_USB2PHY 0x0008001B +#define SRST_RESETN_OTG_USB2PHY 0x0008001C +#define SRST_RESETN_HOST_USB2PHY 0x0008001D + +// ======================= CORECRU module definition bank=3 ======================= +// CORECRU_SOFTRST_CON00(Offset:0xA00) +#define SRST_RESETN_REF_PVTPLL_CORE 0x000C0000 +#define SRST_NCOREPORESET0 0x000C0001 +#define SRST_NCORESET0 0x000C0002 +#define SRST_NCOREPORESET1 0x000C0003 +#define SRST_NCORESET1 0x000C0004 +#define SRST_NCOREPORESET2 0x000c0005 +#define SRST_NCORESET2 0x000C0006 +#define SRST_NCOREPORESET3 0x000C0007 +#define SRST_NCORESET3 0x000C0008 +#define SRST_NDBGRESET 0x000C0009 +#define SRST_NL2RESET 0x000C000A + +// CORECRU_SOFTRST_CON01(Offset:0xA04) +#define SRST_ARESETN_CORE_BIU 0x000C0010 +#define SRST_PRESETN_CORE_BIU 0x000C0011 +#define SRST_HRESETN_CORE_BIU 0x000C0012 +#define SRST_PRESETN_DBG 0x000C0013 +#define SRST_POTRESETN_DBG 0x000C0014 +#define SRST_NTRESETN_DBG 0x000C0015 +#define SRST_PRESETN_CORE_PVTPLL 0x000C0016 +#define SRST_PRESETN_CRU_CORE 0x000C0017 +#define SRST_PRESETN_CORE_GRF 0x000C0018 +#define SRST_PRESETN_DFT2APB 0x000C001A + +// ======================= PMUCRU module definition bank=4 ======================== +// PMUCRU_SOFTRST_CON00(Offset:0xA00) +#define SRST_HRESETN_PMU_BIU 0x00100000 +#define SRST_PRESETN_PMU_GPIO0 0x00100007 +#define SRST_DBRESETN_PMU_GPIO0 0x00100008 +#define SRST_PRESETN_PMU_HP_TIMER 0x0010000A +#define SRST_RESETN_PMU_HP_TIMER 0x0010000B +#define SRST_RESETN_PMU_32K_HP_TIMER 0x0010000C + +// PMUCRU_SOFTRST_CON01(Offset:0xA04) +#define SRST_PRESETN_PWM1 0x00100010 +#define SRST_RESETN_PWM1 0x00100011 +#define SRST_PRESETN_I2C2 0x00100012 +#define SRST_RESETN_I2C2 0x00100013 +#define SRST_PRESETN_UART0 0x00100014 +#define SRST_SRESETN_UART0 0x00100015 + +// PMUCRU_SOFTRST_CON02(Offset:0xA08) +#define SRST_PRESETN_RCOSC_CTRL 0x00100020 +#define SRST_RESETN_REF_RCOSC_CTRL 0x00100022 +#define SRST_PRESETN_IOC_PMUIO0 0x00100023 +#define SRST_PRESETN_CRU_PMU 0x00100024 +#define SRST_PRESETN_PMU_GRF 0x00100025 +#define SRST_RESETN_PREROLL 0x00100027 +#define SRST_RESETN_PREROLL_32K 0x00100028 +#define SRST_HRESETN_PMU_SRAM 0x00100029 + +// PMUCRU_SOFTRST_CON03(Offset:0xA0C) +#define SRST_PRESETN_WDT_LPMCU 0x00100030 +#define SRST_TRESETN_WDT_LPMCU 0x00100031 +#define SRST_RESETN_LPMCU_FULL_CLUSTER 0x00100032 +#define SRST_RESETN_LPMCU_PWUP 0x00100033 +#define SRST_RESETN_LPMCU_ONLY_CORE 0x00100034 +#define SRST_TRESETN_LPMCU_JTAG 0x00100035 +#define SRST_PRESETN_LPMCU_MAILBOX 0x00100036 + +// ======================= PMU1CRU module definition bank=5 ======================= +// PMU1CRU_SOFTRST_CON00(Offset:0xA00) +#define SRST_PRESETN_SPI2AHB 0x00140000 +#define SRST_HRESETN_SPI2AHB 0x00140001 +#define SRST_HRESETN_FSPI1 0x00140002 +#define SRST_HRESETN_XIP_FSPI1 0x00140003 +#define SRST_SRESETN_1X_FSPI1 0x00140004 +#define SRST_PRESETN_IOC_PMUIO1 0x00140005 +#define SRST_PRESETN_CRU_PMU1 0x00140006 +#define SRST_PRESETN_AUDIO_ADC_PMU 0x00140007 +#define SRST_MRESETN_AUDIO_ADC_PMU 0x00140008 +#define SRST_HRESETN_PMU1_BIU 0x00140009 + +// PMU1CRU_SOFTRST_CON01(Offset:0xA04) +#define SRST_PRESETN_LPDMA 0x00140010 +#define SRST_ARESETN_LPDMA 0x00140011 +#define SRST_HRESETN_LPSAI 0x00140012 +#define SRST_MRESETN_LPSAI 0x00140013 +#define SRST_PRESETN_AOA_TDD 0x00140014 +#define SRST_PRESETN_AOA_FE 0x00140015 +#define SRST_PRESETN_AOA_AAD 0x00140016 +#define SRST_PRESETN_AOA_APB 0x00140017 +#define SRST_PRESETN_AOA_SRAM 0x00140018 + +// ======================= DDRCRU module definition bank=6 ======================== +// DDRCRU_SOFTRST_CON00(Offset:0xA00) +#define SRST_PRESETN_DDR_BIU 0x00180001 +#define SRST_PRESETN_DDRC 0x00180002 +#define SRST_PRESETN_DDRMON 0x00180003 +#define SRST_RESETN_TIMER_DDRMON 0x00180004 +#define SRST_PRESETN_DFICTRL 0x00180005 +#define SRST_PRESETN_DDR_GRF 0x00180006 +#define SRST_PRESETN_CRU_DDR 0x00180007 +#define SRST_PRESETN_DDRPHY 0x00180008 +#define SRST_PRESETN_DMA2DDR 0x00180009 + +// ====================== SUBDDRCRU module definition bank=7 ====================== +// SUBDDRCRU_SOFTRST_CON00(Offset:0xA00) +#define SRST_ARESETN_SYSMEM_BIU 0x001A0000 +#define SRST_ARESETN_SYSMEM 0x001A0001 +#define SRST_ARESETN_DDR_BIU 0x001A0002 +#define SRST_ARESETN_DDRSCH0_CPU 0x001A0003 +#define SRST_ARESETN_DDRSCH1_NPU 0x001A0004 +#define SRST_ARESETN_DDRSCH2_POE 0x001A0005 +#define SRST_ARESETN_DDRSCH3_VI 0x001A0006 +#define SRST_RESETN_CORE_DDRC 0x001A0007 +#define SRST_RESETN_DDRMON 0x001A0008 +#define SRST_RESETN_DFICTRL 0x001A0009 +#define SRST_RESETN_RS 0x001A000B +#define SRST_ARESETN_DMA2DDR 0x001A000C +#define SRST_RESETN_DDRPHY 0x001A000D + +// ======================== VICRU module definition bank=8 ======================== +// VICRU_SOFTRST_CON00(Offset:0xA00) +#define SRST_RESETN_REF_PVTPLL_ISP 0x001C0000 +#define SRST_ARESETN_GMAC_BIU 0x001C0001 +#define SRST_ARESETN_VI_BIU 0x001C0002 +#define SRST_HRESETN_VI_BIU 0x001C0003 +#define SRST_PRESETN_VI_BIU 0x001C0004 +#define SRST_PRESETN_CRU_VI 0x001C0005 +#define SRST_PRESETN_VI_GRF 0x001C0006 +#define SRST_PRESETN_VI_PVTPLL 0x001C0007 +#define SRST_PRESETN_DSMC 0x001C0008 +#define SRST_ARESETN_DSMC 0x001C0009 +#define SRST_HRESETN_CAN0 0x001C000A +#define SRST_RESETN_CAN0 0x001C000B +#define SRST_HRESETN_CAN1 0x001C000C +#define SRST_RESETN_CAN1 0x001C000D + +// VICRU_SOFTRST_CON01(Offset:0xA04) +#define SRST_PRESETN_GPIO2 0x001C0010 +#define SRST_DBRESETN_GPIO2 0x001C0011 +#define SRST_PRESETN_GPIO4 0x001C0012 +#define SRST_DBRESETN_GPIO4 0x001C0013 +#define SRST_PRESETN_GPIO5 0x001C0014 +#define SRST_DBRESETN_GPIO5 0x001C0015 +#define SRST_PRESETN_GPIO6 0x001C0016 +#define SRST_DBRESETN_GPIO6 0x001C0017 +#define SRST_PRESETN_GPIO7 0x001C0018 +#define SRST_DBRESETN_GPIO7 0x001C0019 +#define SRST_PRESETN_IOC_VCCIO2 0x001C001A +#define SRST_PRESETN_IOC_VCCIO4 0x001C001B +#define SRST_PRESETN_IOC_VCCIO5 0x001C001C +#define SRST_PRESETN_IOC_VCCIO6 0x001C001D +#define SRST_PRESETN_IOC_VCCIO7 0x001C001E + +// VICRU_SOFTRST_CON02(Offset:0xA08) +#define SRST_RESETN_CORE_ISP 0x001C0020 +#define SRST_HRESETN_VICAP 0x001C0021 +#define SRST_ARESETN_VICAP 0x001C0022 +#define SRST_DRESETN_VICAP 0x001C0023 +#define SRST_ISP0RESETN_VICAP 0x001C0024 +#define SRST_RESETN_CORE_VPSS 0x001C0025 +#define SRST_RESETN_CORE_VPSL 0x001C0026 +#define SRST_PRESETN_CSI2HOST0 0x001C0027 +#define SRST_PRESETN_CSI2HOST1 0x001C0028 +#define SRST_PRESETN_CSI2HOST2 0x001C0029 +#define SRST_PRESETN_CSI2HOST3 0x001C002A +#define SRST_HRESETN_SDMMC0 0x001C002B +#define SRST_ARESETN_GMAC 0x001C002C +#define SRST_PRESETN_CSIPHY0 0x001C002D +#define SRST_PRESETN_CSIPHY1 0x001C002E + +// VICRU_SOFTRST_CON03(Offset:0xA0C) +#define SRST_PRESETN_MACPHY 0x001C0030 +#define SRST_RESETN_MACPHY 0x001C0031 +#define SRST_PRESETN_SARADC1 0x001C0032 +#define SRST_RESETN_SARADC1 0x001C0033 +#define SRST_RESETN_SARADC1_PHY 0x001C0034 +#define SRST_PRESETN_SARADC2 0x001C0035 +#define SRST_RESETN_SARADC2 0x001C0036 +#define SRST_RESETN_SARADC2_PHY 0x001C0037 + +// ======================= VEPUCRU module definition bank=9 ======================= +// VEPUCRU_SOFTRST_CON00(Offset:0xA00) +#define SRST_RESETN_REF_PVTPLL_VEPU 0x00200000 +#define SRST_ARESETN_VEPU_BIU 0x00200001 +#define SRST_HRESETN_VEPU_BIU 0x00200002 +#define SRST_PRESETN_VEPU_BIU 0x00200003 +#define SRST_PRESETN_CRU_VEPU 0x00200004 +#define SRST_PRESETN_VEPU_GRF 0x00200005 +#define SRST_PRESETN_GPIO3 0x00200007 +#define SRST_DBRESETN_GPIO3 0x00200008 +#define SRST_PRESETN_IOC_VCCIO3 0x00200009 +#define SRST_PRESETN_SARADC0 0x0020000A +#define SRST_RESETN_SARADC0 0x0020000B +#define SRST_RESETN_SARADC0_PHY 0x0020000C +#define SRST_HRESETN_SDMMC1 0x0020000D + +// VEPUCRU_SOFTRST_CON01(Offset:0xA04) +#define SRST_PRESETN_VEPU_PVTPLL 0x00200010 +#define SRST_HRESETN_VEPU 0x00200011 +#define SRST_ARESETN_VEPU 0x00200012 +#define SRST_RESETN_CORE_VEPU 0x00200013 + +// ======================= NPUCRU module definition bank=10 ======================= +// NPUCRU_SOFTRST_CON00(Offset:0xA00) +#define SRST_RESETN_REF_PVTPLL_NPU 0x00240000 +#define SRST_ARESETN_NPU_BIU 0x00240002 +#define SRST_HRESETN_NPU_BIU 0x00240003 +#define SRST_PRESETN_NPU_BIU 0x00240004 +#define SRST_PRESETN_CRU_NPU 0x00240005 +#define SRST_PRESETN_NPU_GRF 0x00240006 +#define SRST_PRESETN_NPU_PVTPLL 0x00240008 +#define SRST_HRESETN_RKNN 0x00240009 +#define SRST_ARESETN_RKNN 0x0024000A + +// ======================= VDOCRU module definition bank=11 ======================= +// VDOCRU_SOFTRST_CON00(Offset:0xA00) +#define SRST_ARESETN_RKVDEC_BIU 0x00280000 +#define SRST_ARESETN_VDO_BIU 0x00280001 +#define SRST_HRESETN_VDO_BIU 0x00280003 +#define SRST_PRESETN_VDO_BIU 0x00280004 +#define SRST_PRESETN_CRU_VDO 0x00280005 +#define SRST_PRESETN_VDO_GRF 0x00280006 +#define SRST_ARESETN_RKVDEC 0x00280007 +#define SRST_HRESETN_RKVDEC 0x00280008 +#define SRST_RESETN_HEVC_CA_RKVDEC 0x00280009 +#define SRST_ARESETN_VOP 0x0028000A +#define SRST_HRESETN_VOP 0x0028000B +#define SRST_DRESETN_VOP 0x0028000C +#define SRST_ARESETN_OOC 0x0028000D +#define SRST_HRESETN_OOC 0x0028000E +#define SRST_DRESETN_OOC 0x0028000F + +// VDOCRU_SOFTRST_CON01(Offset:0xA04) +#define SRST_HRESETN_RKJPEG 0x00280013 +#define SRST_ARESETN_RKJPEG 0x00280014 +#define SRST_ARESETN_RKMMU_DECOM 0x00280015 +#define SRST_HRESETN_RKMMU_DECOM 0x00280016 +#define SRST_DRESETN_DECOM 0x00280018 +#define SRST_ARESETN_DECOM 0x00280019 +#define SRST_PRESETN_DECOM 0x0028001A +#define SRST_PRESETN_MIPI_DSI 0x0028001C +#define SRST_PRESETN_DSIPHY 0x0028001D + +// ======================= VCPCRU module definition bank=12 ======================= +// VCPCRU_SOFTRST_CON00(Offset:0xA00) +#define SRST_RESETN_REF_PVTPLL_VCP 0x002C0000 +#define SRST_ARESETN_VCP_BIU 0x002C0001 +#define SRST_HRESETN_VCP_BIU 0x002C0002 +#define SRST_PRESETN_VCP_BIU 0x002C0003 +#define SRST_PRESETN_CRU_VCP 0x002C0004 +#define SRST_PRESETN_VCP_GRF 0x002C0005 +#define SRST_PRESETN_VCP_PVTPLL 0x002C0007 +#define SRST_ARESETN_AISP_BIU 0x002C0008 +#define SRST_HRESETN_AISP_BIU 0x002C0009 +#define SRST_ARESETN_AISPMEM_BIU 0x002C000A +#define SRST_RESETN_CORE_AISP 0x002C000D +#define SRST_ARESETN_AISPMEM 0x002C000E + +// VCPCRU_SOFTRST_CON01(Offset:0xA04) +#define SRST_HRESETN_FEC 0x002C0010 +#define SRST_ARESETN_FEC 0x002C0011 +#define SRST_RESETN_CORE_FEC 0x002C0012 +#define SRST_HRESETN_AVSP 0x002C0013 +#define SRST_ARESETN_AVSP 0x002C0014 + +#define CLK_NR_SRST (SRST_ARESETN_AVSP + 1) + +#endif diff --git a/u-boot/include/dt-bindings/power/rockchip,rv1126b-power.h b/u-boot/include/dt-bindings/power/rockchip,rv1126b-power.h new file mode 100644 index 00000000000..0a418f16e4e --- /dev/null +++ b/u-boot/include/dt-bindings/power/rockchip,rv1126b-power.h @@ -0,0 +1,17 @@ +/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ +/* + * Copyright (c) 2024 Rockchip Electronics Co., Ltd. + * Author: Finley Xiao + */ + +#ifndef __DT_BINDINGS_POWER_RV1126B_POWER_H__ +#define __DT_BINDINGS_POWER_RV1126B_POWER_H__ + +/* VD_NPU */ +#define RV1126B_PD_NPU 0 + +/* VD_LOGIC */ +#define RV1126B_PD_VDO 1 +#define RV1126B_PD_AISP 2 + +#endif diff --git a/u-boot/include/generic-phy-dp.h b/u-boot/include/generic-phy-dp.h index 2520e20737f..484cde20067 100644 --- a/u-boot/include/generic-phy-dp.h +++ b/u-boot/include/generic-phy-dp.h @@ -6,6 +6,9 @@ #ifndef __PHY_DP_H_ #define __PHY_DP_H_ +#define PHY_SUBMODE_DP 0 +#define PHY_SUBMODE_EDP 1 + /** * struct phy_configure_opts_dp - DisplayPort PHY configuration set * diff --git a/u-boot/include/irq-platform.h b/u-boot/include/irq-platform.h index 684d6781556..8e607bf35b8 100644 --- a/u-boot/include/irq-platform.h +++ b/u-boot/include/irq-platform.h @@ -273,6 +273,77 @@ #define IRQ_GPIO3 69 #define IRQ_GPIO4 70 +#elif defined(CONFIG_ROCKCHIP_RV1126B) +#define GPIO0_PHYS 0x20600000 +#define GPIO1_PHYS 0x21300000 +#define GPIO2_PHYS 0x21700000 +#define GPIO3_PHYS 0x21e00000 +#define GPIO4_PHYS 0x21800000 +#define GPIO5_PHYS 0x21900000 +#define GPIO6_PHYS 0x21a00000 +#define GPIO7_PHYS 0x21b00000 + +#define GIC_IRQS_NR 287 +#define GPIO_IRQS_NR (8 * 32) + +#define GPIO_BANK_NUM 8 +#define GPIO_BANK_PINS 32 + +#define IRQ_TIMER0 99 +#define IRQ_TIMER1 100 +#define IRQ_TIMER2 101 +#define IRQ_TIMER3 102 +#define IRQ_TIMER4 103 +#define IRQ_TIMER5 104 + +#define IRQ_GPIO0 IRQ_GPIO0_0 +#define IRQ_GPIO0_0 32 +#define IRQ_GPIO0_1 33 +#define IRQ_GPIO0_2 34 +#define IRQ_GPIO0_3 35 + +#define IRQ_GPIO1 IRQ_GPIO1_0 +#define IRQ_GPIO1_0 36 +#define IRQ_GPIO1_1 37 +#define IRQ_GPIO1_2 38 +#define IRQ_GPIO1_3 39 + +#define IRQ_GPIO2 IRQ_GPIO2_0 +#define IRQ_GPIO2_0 40 +#define IRQ_GPIO2_1 41 +#define IRQ_GPIO2_2 42 +#define IRQ_GPIO2_3 43 + +#define IRQ_GPIO3 IRQ_GPIO3_0 +#define IRQ_GPIO3_0 44 +#define IRQ_GPIO3_1 45 +#define IRQ_GPIO3_2 46 +#define IRQ_GPIO3_3 47 + +#define IRQ_GPIO4 IRQ_GPIO4_0 +#define IRQ_GPIO4_0 48 +#define IRQ_GPIO4_1 49 +#define IRQ_GPIO4_2 50 +#define IRQ_GPIO4_3 51 + +#define IRQ_GPIO5 IRQ_GPIO5_0 +#define IRQ_GPIO5_0 52 +#define IRQ_GPIO5_1 53 +#define IRQ_GPIO5_2 54 +#define IRQ_GPIO5_3 55 + +#define IRQ_GPIO6 IRQ_GPIO6_0 +#define IRQ_GPIO6_0 56 +#define IRQ_GPIO6_1 57 +#define IRQ_GPIO6_2 58 +#define IRQ_GPIO6_3 59 + +#define IRQ_GPIO7 IRQ_GPIO7_0 +#define IRQ_GPIO7_0 60 +#define IRQ_GPIO7_1 61 +#define IRQ_GPIO7_2 62 +#define IRQ_GPIO7_3 63 + #elif defined(CONFIG_ROCKCHIP_RK3506) #define GPIO0_PHYS 0xff940000 #define GPIO1_PHYS 0xff870000 diff --git a/u-boot/include/keylad.h b/u-boot/include/keylad.h new file mode 100644 index 00000000000..2e3266f2817 --- /dev/null +++ b/u-boot/include/keylad.h @@ -0,0 +1,43 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * (C) Copyright 2025 Rockchip Electronics Co., Ltd + */ + +#ifndef _CORE_KEYLAD_H_ +#define _CORE_KEYLAD_H_ + +#include +#include + +enum RK_FW_KEYID { + RK_FW_KEY0 = 0, + RK_FW_KEYMAX +}; + +struct dm_keylad_ops { + /* transfer firmware key to dst module */ + int (*transfer_fwkey)(struct udevice *dev, ulong dst, + enum RK_FW_KEYID fw_keyid, u32 keylen); +}; + +/** + * keylad_get_device() - Get keylad device + * + * @return dev on success, otherwise NULL + */ +struct udevice *keylad_get_device(void); + +/** + * keylad_transfer_fwkey() - Transfer firmware key otp to dst module + * + * @dev: crypto device + * @dst: dst module addr + * @fw_keyid: firmware key id select from enum RK_FW_KEYID + * @keylen: key length of firmware key + + * @return 0 on success, otherwise failed + */ +int keylad_transfer_fwkey(struct udevice *dev, ulong dst, + enum RK_FW_KEYID fw_keyid, u32 keylen); + +#endif diff --git a/u-boot/include/linux/usb/phy-rockchip-usbdp.h b/u-boot/include/linux/usb/phy-rockchip-usbdp.h index 12117c2e90a..f0744c43013 100644 --- a/u-boot/include/linux/usb/phy-rockchip-usbdp.h +++ b/u-boot/include/linux/usb/phy-rockchip-usbdp.h @@ -9,9 +9,9 @@ #define __PHY_ROCKCHIP_USBDP_H_ #if CONFIG_IS_ENABLED(PHY_ROCKCHIP_USBDP) -int rockchip_u3phy_uboot_init(void); +int rockchip_u3phy_uboot_init(fdt_addr_t phy_addr); #else -static inline int rockchip_u3phy_uboot_init(void) +static inline int rockchip_u3phy_uboot_init(fdt_addr_t phy_addr) { return -ENOTSUPP; } diff --git a/u-boot/include/optee_include/OpteeClientInterface.h b/u-boot/include/optee_include/OpteeClientInterface.h index a50b46ca827..d4568ea6370 100644 --- a/u-boot/include/optee_include/OpteeClientInterface.h +++ b/u-boot/include/optee_include/OpteeClientInterface.h @@ -29,6 +29,11 @@ enum RK_ESCK_KEYID { RK_ESCK_KEYMAX }; +enum RK_FW_KEYID { + RK_FW_KEY0 = 0, + RK_FW_KEYMAX +}; + /* Crypto mode */ enum RK_CIPIHER_MODE { RK_CIPHER_MODE_ECB = 0, @@ -126,5 +131,8 @@ uint32_t trusty_attest_get_ca (uint8_t *operation_start, uint32_t *operation_size, uint8_t *out, uint32_t *out_len); uint32_t trusty_attest_set_ca(uint8_t *ca_response, uint32_t *ca_response_size); +uint32_t trusty_fw_key_cipher(enum RK_FW_KEYID key_id, rk_cipher_config *config, + uint32_t src_phys_addr, uint32_t dst_phys_addr, + uint32_t len); #endif diff --git a/u-boot/include/pci.h b/u-boot/include/pci.h index c8ef997d0de..a10ed735581 100644 --- a/u-boot/include/pci.h +++ b/u-boot/include/pci.h @@ -18,6 +18,7 @@ * Under PCI, each device has 256 bytes of configuration address space, * of which the first 64 bytes are standardized as follows: */ +#define PCI_STD_HEADER_SIZEOF 64 #define PCI_VENDOR_ID 0x00 /* 16 bits */ #define PCI_DEVICE_ID 0x02 /* 16 bits */ #define PCI_COMMAND 0x04 /* 16 bits */ @@ -418,11 +419,30 @@ #define PCI_FIND_CAP_TTL 0x48 #define CAP_START_POS 0x40 +/* AER register offsets (relative to the AER Capability base address) */ +#define PCI_AER_STATUS 0x08 /* AER Status Register */ +#define PCI_AER_MASK 0x0C /* AER Mask Register */ +#define PCI_AER_SEVERITY 0x10 /* AER Severity Register */ + /* Extended Capabilities (PCI-X 2.0 and Express) */ #define PCI_EXT_CAP_ID(header) (header & 0x0000ffff) #define PCI_EXT_CAP_VER(header) ((header >> 16) & 0xf) #define PCI_EXT_CAP_NEXT(header) ((header >> 20) & 0xffc) +/* PCIe Capability Registers */ +#define PCI_EXP_DEVCAP 0x04 /* Device capabilities */ +#define PCI_EXP_LNKCTL 0x10 /* Link Control Register */ +#define PCI_EXP_LNKSTA 0x12 /* Link Status Register */ +#define PCI_EXP_DEVCAP_FLR 0x10000000 /* Function Level Reset */ + +/* Link Status Register bits */ +#define PCI_EXP_LNKSTA_LT 0x0800 /* Link Training */ +#define PCI_EXP_LNKSTA_CLS 0x000f /* Current Link Speed */ +#define PCI_EXP_LNKSTA_NLW 0x03f0 /* Negotiated Link Width */ + +#define PCI_EXP_DEVCTL 8 /* Device Control Register offset */ +#define PCI_EXP_DEVCTL_FLR 0x8000 /* FLR bit in Device Control Register */ + #define PCI_EXT_CAP_ID_ERR 0x01 /* Advanced Error Reporting */ #define PCI_EXT_CAP_ID_VC 0x02 /* Virtual Channel Capability */ #define PCI_EXT_CAP_ID_DSN 0x03 /* Device Serial Number */ @@ -512,6 +532,14 @@ struct pci_device_id { unsigned long driver_data; /* Data private to the driver */ }; +struct pci_device_state { + u32 bar[6]; /* Saved BARs */ + u16 command; /* Saved Command Register */ + u8 primary_bus; /* Saved Primary Bus Number (for bridge) */ + u8 secondary_bus; /* Saved Secondary Bus Number (for bridge) */ + u8 subordinate_bus; /* Saved Subordinate Bus Number (for bridge) */ +}; + struct pci_controller; struct pci_config_table { @@ -863,6 +891,13 @@ struct dm_pci_ops { */ int (*write_config)(struct udevice *bus, pci_dev_t bdf, uint offset, ulong value, enum pci_size_t size); + /** + * vendor_aer_dump() - Dump vendor-specific aer information + * + * @bus: Bus of pci_controller + * @return 0 if OK, -ve on error + */ + int (*vendor_aer_dump)(struct udevice *bus); }; /* Get access to a PCI bus' operations */ @@ -1192,6 +1227,38 @@ struct udevice *pci_get_controller(struct udevice *dev); int pci_get_regions(struct udevice *dev, struct pci_region **iop, struct pci_region **memp, struct pci_region **prefp); +/** + * pci_aer_dump() - dump AER (Advanced Error Reporting) information for a PCIe device + * + * @udev: PCI device to dump AER information + * @dev: PCI device and function address + * @return: 0 if successful, negative error code on failure + */ +int pci_aer_dump(struct udevice *udev, pci_dev_t dev); + +/** + * pci_retrain_link - Trigger PCIe link retrain for a device + * @udev: PCI device to retrain link + * @dev: PCI device and function address + * + * Return: 0 on success, negative error code on failure. + */ +int pci_retrain_link(struct udevice *udev, pci_dev_t dev); + +/** + * pci_reset_function - Reset a PCI/PCIe function using Function Level Reset (FLR). + * + * This function performs the following steps: + * 1. Saves the device's config space (BARs, Command Register, Bus Numbers for bridges). + * 2. Triggers a FLR to reset the device. + * 3. Restores the saved configuration space state after the FLR completes. + * + * @udev: PCI function device to be reset + * @dev: The PCI device identifier (BDF: Bus, Device, Function). + * @return 0 on success, -1 on failure. + */ +int pci_reset_function(struct udevice *udev, pci_dev_t dev); + /** * dm_pci_write_bar32() - Write the address of a BAR * @@ -1247,6 +1314,99 @@ pci_addr_t dm_pci_phys_to_bus(struct udevice *dev, phys_addr_t addr, */ void *dm_pci_map_bar(struct udevice *dev, int bar, int flags); +/** + * dm_pci_find_next_capability() - find a capability starting from an offset + * + * Tell if a device supports a given PCI capability. Returns the + * address of the requested capability structure within the device's + * PCI configuration space or 0 in case the device does not support it. + * + * Possible values for @cap: + * + * %PCI_CAP_ID_MSI Message Signalled Interrupts + * %PCI_CAP_ID_PCIX PCI-X + * %PCI_CAP_ID_EXP PCI Express + * %PCI_CAP_ID_MSIX MSI-X + * + * See PCI_CAP_ID_xxx for the complete capability ID codes. + * + * @dev: PCI device to query + * @start: offset to start from + * @cap: capability code + * @return: capability address or 0 if not supported + */ +int dm_pci_find_next_capability(struct udevice *dev, u8 start, int cap); + +/** + * dm_pci_find_capability() - find a capability + * + * Tell if a device supports a given PCI capability. Returns the + * address of the requested capability structure within the device's + * PCI configuration space or 0 in case the device does not support it. + * + * Possible values for @cap: + * + * %PCI_CAP_ID_MSI Message Signalled Interrupts + * %PCI_CAP_ID_PCIX PCI-X + * %PCI_CAP_ID_EXP PCI Express + * %PCI_CAP_ID_MSIX MSI-X + * + * See PCI_CAP_ID_xxx for the complete capability ID codes. + * + * @dev: PCI device to query + * @cap: capability code + * @return: capability address or 0 if not supported + */ +int dm_pci_find_capability(struct udevice *dev, int cap); + +/** + * dm_pci_find_next_ext_capability() - find an extended capability + * starting from an offset + * + * Tell if a device supports a given PCI express extended capability. + * Returns the address of the requested extended capability structure + * within the device's PCI configuration space or 0 in case the device + * does not support it. + * + * Possible values for @cap: + * + * %PCI_EXT_CAP_ID_ERR Advanced Error Reporting + * %PCI_EXT_CAP_ID_VC Virtual Channel + * %PCI_EXT_CAP_ID_DSN Device Serial Number + * %PCI_EXT_CAP_ID_PWR Power Budgeting + * + * See PCI_EXT_CAP_ID_xxx for the complete extended capability ID codes. + * + * @dev: PCI device to query + * @start: offset to start from + * @cap: extended capability code + * @return: extended capability address or 0 if not supported + */ +int dm_pci_find_next_ext_capability(struct udevice *dev, int start, int cap); + +/** + * dm_pci_find_ext_capability() - find an extended capability + * + * Tell if a device supports a given PCI express extended capability. + * Returns the address of the requested extended capability structure + * within the device's PCI configuration space or 0 in case the device + * does not support it. + * + * Possible values for @cap: + * + * %PCI_EXT_CAP_ID_ERR Advanced Error Reporting + * %PCI_EXT_CAP_ID_VC Virtual Channel + * %PCI_EXT_CAP_ID_DSN Device Serial Number + * %PCI_EXT_CAP_ID_PWR Power Budgeting + * + * See PCI_EXT_CAP_ID_xxx for the complete extended capability ID codes. + * + * @dev: PCI device to query + * @cap: extended capability code + * @return: extended capability address or 0 if not supported + */ +int dm_pci_find_ext_capability(struct udevice *dev, int cap); + #define dm_pci_virt_to_bus(dev, addr, flags) \ dm_pci_phys_to_bus(dev, (virt_to_phys(addr)), (flags)) #define dm_pci_bus_to_virt(dev, addr, flags, len, map_flags) \ diff --git a/u-boot/include/power/regulator.h b/u-boot/include/power/regulator.h index 8f45d7203aa..c75b7aedfa1 100644 --- a/u-boot/include/power/regulator.h +++ b/u-boot/include/power/regulator.h @@ -250,6 +250,7 @@ struct dm_regulator_ops { * @return zero on success and other failed. */ int (*set_ramp_delay)(struct udevice *dev, u32 ramp_delay); + int (*get_ramp_delay)(struct udevice *dev, int old_uV, int new_uV); }; /** diff --git a/u-boot/include/power/rk801_pmic.h b/u-boot/include/power/rk801_pmic.h new file mode 100644 index 00000000000..9583d616331 --- /dev/null +++ b/u-boot/include/power/rk801_pmic.h @@ -0,0 +1,147 @@ +/* + * (C) Copyright 2025 Rockchip Electronics Co., Ltd. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _PMIC_RK801_H_ +#define _PMIC_RK801_H_ + +#define DEV_OFF BIT(0) + +#define RK8XX_ID_MSK 0xfff0 + +enum rk801_reg { + RK801_ID_DCDC1, + RK801_ID_DCDC2, + RK801_ID_DCDC4, + RK801_ID_DCDC3, + RK801_ID_LDO1, + RK801_ID_LDO2, + RK801_ID_SWITCH, + RK801_ID_MAX, +}; + +#define RK801_SLP_REG_OFFSET 5 +#define RK801_NUM_REGULATORS 7 + +/* RK801 Register Definitions */ +#define RK801_ID_MSB 0x00 +#define RK801_ID_LSB 0x01 +#define RK801_OTP_VER_REG 0x02 +#define RK801_POWER_EN0_REG 0x03 +#define RK801_POWER_EN1_REG 0x04 +#define RK801_POWER_SLP_EN_REG 0x05 +#define RK801_POWER_FPWM_EN_REG 0x06 +#define RK801_SLP_LP_CONFIG_REG 0x07 +#define RK801_BUCK_CONFIG_REG 0x08 +#define RK801_BUCK1_ON_VSEL_REG 0x09 +#define RK801_BUCK2_ON_VSEL_REG 0x0a +#define RK801_BUCK4_ON_VSEL_REG 0x0b +#define RK801_LDO1_ON_VSEL_REG 0x0c +#define RK801_LDO2_ON_VSEL_REG 0x0d +#define RK801_BUCK1_SLP_VSEL_REG 0x0e +#define RK801_BUCK2_SLP_VSEL_REG 0x0f +#define RK801_BUCK4_SLP_VSEL_REG 0x10 +#define RK801_LDO1_SLP_VSEL_REG 0x11 +#define RK801_LDO2_SLP_VSEL_REG 0x12 +#define RK801_LDO_SW_IMAX_REG 0x13 +#define RK801_SYS_STS_REG 0x14 +#define RK801_SYS_CFG0_REG 0x15 +#define RK801_SYS_CFG1_REG 0x16 +#define RK801_SYS_CFG2_REG 0x17 +#define RK801_SYS_CFG3_REG 0x18 +#define RK801_SYS_CFG4_REG 0x19 +#define RK801_SLEEP_CFG_REG 0x1a +#define RK801_ON_SOURCE_REG 0x1b +#define RK801_OFF_SOURCE_REG 0x1c +#define RK801_PWRON_KEY_REG 0x1d +#define RK801_INT_STS0_REG 0x1e +#define RK801_INT_MASK0_REG 0x1f +#define RK801_INT_CONFIG_REG 0x20 +#define RK801_CON_BACK1_REG 0x21 +#define RK801_CON_BACK2_REG 0x22 +#define RK801_DATA_CON0_REG 0x23 +#define RK801_DATA_CON1_REG 0x24 +#define RK801_DATA_CON2_REG 0x25 +#define RK801_DATA_CON3_REG 0x26 +#define RK801_POWER_EXIT_SLP_SEQ0_REG 0x27 +#define RK801_POWER_EXIT_SLP_SEQ1_REG 0x28 +#define RK801_POWER_EXIT_SLP_SEQ2_REG 0x29 +#define RK801_POWER_EXIT_SLP_SEQ3_REG 0x2a +#define RK801_POWER_ENTER_SLP_OR_SHTD_SEQ0_REG 0x2b +#define RK801_POWER_ENTER_SLP_OR_SHTD_SEQ1_REG 0x2c +#define RK801_POWER_ENTER_SLP_OR_SHTD_SEQ2_REG 0x2d +#define RK801_POWER_ENTER_SLP_OR_SHTD_SEQ3_REG 0x2e +#define RK801_BUCK_DEBUG1_REG 0x2f +#define RK801_BUCK_DEBUG2_REG 0x30 +#define RK801_BUCK_DEBUG3_REG 0x31 +#define RK801_BUCK_DEBUG4_REG 0x32 +#define RK801_BUCK_DEBUG5_REG 0x33 +#define RK801_BUCK_DEBUG7_REG 0x34 +#define RK801_OTP_EN_CON_REG 0x35 +#define RK801_TEST_CON_REG 0x36 +#define RK801_EFUSE_CONTROL_REG 0x37 +#define RK801_SYS_CFG3_OTP_REG 0x38 + +/* RK801 IRQ Definitions */ +#define RK801_IRQ_PWRON_FALL 0 +#define RK801_IRQ_PWRON_RISE 1 +#define RK801_IRQ_PWRON 2 +#define RK801_IRQ_PWRON_LP 3 +#define RK801_IRQ_HOTDIE 4 +#define RK801_IRQ_VDC_RISE 5 +#define RK801_IRQ_VDC_FALL 6 +#define RK801_IRQ_PWRON_FALL_MSK BIT(0) +#define RK801_IRQ_PWRON_RISE_MSK BIT(1) +#define RK801_IRQ_PWRON_MSK BIT(2) +#define RK801_IRQ_PWRON_LP_MSK BIT(3) +#define RK801_IRQ_HOTDIE_MSK BIT(4) +#define RK801_IRQ_VDC_RISE_MSK BIT(5) +#define RK801_IRQ_VDC_FALL_MSK BIT(6) + +/* RK801_SLP_LP_CONFIG_REG */ +#define RK801_BUCK_SLP_LP_EN BIT(3) +#define RK801_PLDO_SLP_LP_EN BIT(1) +#define RK801_SLP_LP_MASK (RK801_PLDO_SLP_LP_EN | RK801_BUCK_SLP_LP_EN) + +/* RK801_SLEEP_CFG_REG */ +#define RK801_SLEEP_FUN_MSK 0x3 +#define RK801_NONE_FUN 0x0 +#define RK801_SLEEP_FUN 0x1 +#define RK801_SHUTDOWN_FUN 0x2 +#define RK801_RESET_FUN 0x3 + +/* RK801_SYS_CFG2_REG */ +#define RK801_SLEEP_POL_MSK BIT(1) +#define RK801_SLEEP_ACT_H BIT(1) +#define RK801_SLEEP_ACT_L 0 + +#define RK801_RST_MSK (0x3 << 4) +#define RK801_RST_RESTART_PMU (0x0 << 4) +#define RK801_RST_RESTART_REG (0x1 << 4) +#define RK801_RST_RESTART_REG_RESETB (0x2 << 4) + +/* RK801_INT_CONFIG_REG */ +#define RK801_INT_POL_MSK BIT(1) +#define RK801_INT_ACT_H BIT(1) +#define RK801_INT_ACT_L 0 + +#define RK801_FPWM_MODE 1 +#define RK801_AUTO_PWM_MODE 0 +#define RK801_PLDO_HRDEC_EN BIT(6) + +struct reg_data { + u8 reg; + u8 val; + u8 mask; +}; + +struct rk801_priv { + struct virq_chip *irq_chip; + struct gpio_desc pwrctrl_gpio; + bool req_pwrctrl_dvs; + int variant; + int irq; +}; +#endif diff --git a/u-boot/include/power/rk8xx_pmic.h b/u-boot/include/power/rk8xx_pmic.h index 1b9ea4d1d82..068f009942c 100644 --- a/u-boot/include/power/rk8xx_pmic.h +++ b/u-boot/include/power/rk8xx_pmic.h @@ -199,6 +199,12 @@ enum { RK817_POWER_EN2, RK817_POWER_EN3, }; + +#define RK8xx_RST_MODE0 0x00 +#define RK8xx_RST_MODE1 0x01 +#define RK8xx_RST_MODE2 0x02 +#define RK8xx_RESET_FUN_CLR 0x3f + #define RK817_POWER_EN_SAVE0 0x99 #define RK817_POWER_EN_SAVE1 0xa4 diff --git a/u-boot/include/rk_timer_irq.h b/u-boot/include/rk_timer_irq.h index 00111748d09..4d2db79270c 100644 --- a/u-boot/include/rk_timer_irq.h +++ b/u-boot/include/rk_timer_irq.h @@ -61,7 +61,7 @@ #define TIMER_BASE (0xFF700000 + 0x20) /* TIMER 1 */ #define TIMER_IRQ IRQ_TIMER1 #elif defined(CONFIG_ROCKCHIP_RV1103B) -#define TIMER_BASE (0x20830000 + 0x20) /* TIMER 1 */ +#define TIMER_BASE (0x20830000 + 0x10000) /* TIMER 1 */ #define TIMER_IRQ IRQ_TIMER1 #elif defined(CONFIG_ROCKCHIP_RV1106) #define TIMER_BASE (0xFF660000 + 0x20) /* TIMER 1 */ @@ -69,6 +69,9 @@ #elif defined(CONFIG_ROCKCHIP_RV1126) #define TIMER_BASE (0xFF660000 + 0x20) /* TIMER 1 */ #define TIMER_IRQ IRQ_TIMER1 +#elif defined(CONFIG_ROCKCHIP_RV1126B) +#define TIMER_BASE (0x20c00000 + 0x10000) /* TIMER 1 */ +#define TIMER_IRQ IRQ_TIMER1 #elif defined(CONFIG_ROCKCHIP_RK3506) #define TIMER_BASE (0xFF250000 + 0x00) /* TIMER 0 */ #define TIMER_IRQ IRQ_TIMER0 @@ -80,7 +83,7 @@ #define TIMER_IRQ IRQ_TIMER0 #elif defined(CONFIG_ROCKCHIP_RK3568) /* Only timer0 can wakeup system suspend */ -#define TIMER_BASE (0xFE5F0000 + 0x00) /* TIMER 1 */ +#define TIMER_BASE (0xFE5F0000 + 0x00) /* TIMER 0 */ #define TIMER_IRQ IRQ_TIMER0 #elif defined(CONFIG_ROCKCHIP_RK3576) #define TIMER_BASE (0x2acc0000 + 0x00) /* TIMER 0 */ diff --git a/u-boot/include/rockchip/crypto_ecc.h b/u-boot/include/rockchip/crypto_ecc.h new file mode 100644 index 00000000000..269394b72b3 --- /dev/null +++ b/u-boot/include/rockchip/crypto_ecc.h @@ -0,0 +1,123 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) 2024 Rockchip Electronics Co., Ltd + */ + +#ifndef _ROCKCHIP_CRYPTO_ECC_H_ +#define _ROCKCHIP_CRYPTO_ECC_H_ + +#include +#include +#include +#include + +#define SM2_RAM_BASE ((crypto_base) + 0x1000) + +#define _SBF(s, v) ((v) << (s)) +#define _BIT(b) _SBF(b, 1) + +#define RK_ECP_MAX_BITS 256 +#define RK_ECP_MAX_BYTES ((RK_ECP_MAX_BITS) / 8) +#define RK_ECP_MAX_WORDS ((RK_ECP_MAX_BITS) / 32) +#define RK_ECP_MAX_WORDS_ALL (512 / 32) + +#define RK_ECC_CTL 0x03F0 +#define RK_ECC_CTL_RAND_K_SRC_SOFT _SBF(12, 0) +#define RK_ECC_CTL_RAND_K_SRC_HARD _SBF(12, 1) +#define RK_ECC_CTL_FUNC_SM2_CURVER _SBF(8, 0x0) +#define RK_ECC_CTL_FUNC_ECC_CURVER _SBF(8, 0x1) + +#define RK_ECC_CTL_FUNC_SEL_MUL _SBF(4, 0x0) +#define RK_ECC_CTL_FUNC_SEL_KG _SBF(4, 0x1) +#define RK_ECC_CTL_FUNC_SEL_SIGN _SBF(4, 0x2) +#define RK_ECC_CTL_FUNC_SEL_VERIFY _SBF(4, 0x3) +#define RK_ECC_CTL_FUNC_SEL_MUL_MOD _SBF(4, 0x4) +#define RK_ECC_CTL_FUNC_SEL_ADD_MOD _SBF(4, 0x5) +#define RK_ECC_CTL_FUNC_SEL_DOUBLE_POINT _SBF(4, 0x6) +#define RK_ECC_CTL_FUNC_SEL_ADD_POINT _SBF(4, 0x7) +#define RK_ECC_CTL_FUNC_SEL_KP _SBF(4, 0x8) +#define RK_ECC_CTL_FUNC_SEL_KP_KG _SBF(4, 0xa) +#define RK_ECC_CTL_REQ_ECC _SBF(0, 1) + +#define RK_ECC_INT_EN 0x03F4 +#define RK_ECC_INT_EN_DONE _BIT(0) + +#define RK_ECC_INT_ST 0x03F8 +#define RK_ECC_INT_ST_DONE _BIT(0) + +#define RK_ECC_ABN_ST 0x03FC +#define RK_ECC_ABN_ST_BAD_INV_OUT _BIT(8) +#define RK_ECC_ABN_ST_BAD_K_IN _BIT(7) +#define RK_ECC_ABN_ST_BAD_R_IN _BIT(6) +#define RK_ECC_ABN_ST_BAD_S_IN _BIT(5) +#define RK_ECC_ABN_ST_BAD_R_K_MID _BIT(4) +#define RK_ECC_ABN_ST_BAD_R_OUT _BIT(3) +#define RK_ECC_ABN_ST_BAD_S_OUT _BIT(2) +#define RK_ECC_ABN_ST_BAD_T_OUT _BIT(1) +#define RK_ECC_ABN_ST_BAD_POINT_OUT _BIT(0) + +#define RK_ECC_CURVE_WIDE 0x0400 +#define RK_ECC_CURVE_WIDE_192 192 +#define RK_ECC_CURVE_WIDE_224 224 +#define RK_ECC_CURVE_WIDE_256 256 + +#define RK_ECC_MAX_CURVE_WIDE 0x0404 + +#define RK_ECC_DATA_ENDIAN 0x0408 +#define RK_ECC_DATA_ENDIAN_LITTLE 0x0 +#define RK_ECC_DATA_ENDIAN_BIG 0x1 + +#define RK_ECC_RAM_CTL 0x0480 +#define RK_ECC_RAM_CTL_SEL_MASK _SBF(16, 3) +#define RK_ECC_RAM_CTL_CPU _SBF(0, 0) +#define RK_ECC_RAM_CTL_PKA _SBF(0, 1) +#define RK_ECC_RAM_CTL_ECC _SBF(0, 2) + + +struct rk_ecp_point { + struct mpa_num *x; /*!< the point's X coordinate */ + struct mpa_num *y; /*!< the point's Y coordinate */ +}; + +enum rk_ecp_group_id { + RK_ECP_DP_NONE = 0, + RK_ECP_DP_SECP192R1, /*!< 192-bits NIST curve */ + RK_ECP_DP_SECP224R1, /*!< 224-bits NIST curve */ + RK_ECP_DP_SECP256R1, /*!< 256-bits NIST curve */ + RK_ECP_DP_SM2P256V1, /*!< */ +}; + +struct rk_ecp_group { + enum rk_ecp_group_id id; /*!< internal group identifier */ + const char *curve_name; + uint32_t wide; + const uint8_t *p; /*!< prime modulus of the base field */ + const uint8_t *a; /*!< 1. A in the equation, or 2. (A + 2) / 4 */ + const uint8_t *n; + const uint8_t *gx; + const uint8_t *gy; + size_t p_len; + size_t a_len; + size_t n_len; + size_t gx_len; + size_t gy_len; +}; + +struct rk_ecc_verify { + uint32_t e[RK_ECP_MAX_WORDS_ALL]; // 0x00 + uint32_t r_[RK_ECP_MAX_WORDS_ALL]; // 0x40 + uint32_t s_[RK_ECP_MAX_WORDS_ALL]; // 0x80 + uint32_t p_x[RK_ECP_MAX_WORDS_ALL]; // 0xC0 + uint32_t p_y[RK_ECP_MAX_WORDS_ALL]; // 0x100 + uint32_t A[RK_ECP_MAX_WORDS_ALL]; // 0x140 + uint32_t P[RK_ECP_MAX_WORDS_ALL]; // 0x180 + uint32_t N[RK_ECP_MAX_WORDS_ALL]; // 0x1C0 + uint32_t G_x[RK_ECP_MAX_WORDS_ALL]; // 0x200 + uint32_t G_y[RK_ECP_MAX_WORDS_ALL]; // 0x240 + uint32_t r[RK_ECP_MAX_WORDS_ALL]; // 0x280 + uint32_t v[RK_ECP_MAX_WORDS_ALL]; // 0x2C0 +}; + +int rockchip_ecc_verify(uint32_t crypto_algo, uint8_t *hash, uint32_t hash_len, + struct rk_ecp_point *point_P, struct rk_ecp_point *point_sign); +#endif diff --git a/u-boot/include/rockchip/crypto_fix_test_data.h b/u-boot/include/rockchip/crypto_fix_test_data.h index b8045114bfd..25a391c338c 100644 --- a/u-boot/include/rockchip/crypto_fix_test_data.h +++ b/u-boot/include/rockchip/crypto_fix_test_data.h @@ -1328,4 +1328,66 @@ const u8 rsa4096_sign_out[] = { #endif +#if CONFIG_IS_ENABLED(ROCKCHIP_EC) +static const uint8_t ecc192r1_pub_x[] = { +0xf7, 0x46, 0xf8, 0x2f, 0x15, 0xf6, 0x22, 0x8e, +0xd7, 0x57, 0x4f, 0xcc, 0xe7, 0xbb, 0xc1, 0xd4, +0x09, 0x73, 0xcf, 0xea, 0xd0, 0x15, 0x07, 0x3d, +}; + +static const uint8_t ecc192r1_pub_y[] = { +0xa5, 0x8a, 0x8a, 0x95, 0x43, 0xe4, 0x68, 0xea, +0xc6, 0x25, 0xc1, 0xc1, 0x01, 0x25, 0x4c, 0x7e, +0xc3, 0x3c, 0xa6, 0x04, 0x0a, 0xe7, 0x08, 0x98, +}; + +static const uint8_t ecc192r1_hash[] = { +0xcd, 0xb9, 0xd2, 0x1c, 0xb7, 0x6f, 0xcd, 0x44, +0xb3, 0xfd, 0x63, 0xea, 0xa3, 0x66, 0x7f, 0xae, +0x63, 0x85, 0xe7, 0x82, +}; + +static const uint8_t ecc192r1_sign[] = { +0xba, 0xe5, 0x93, 0x83, 0x6e, 0xb6, 0x3b, 0x63, +0xa0, 0x27, 0x91, 0xc6, 0xf6, 0x7f, 0xc3, 0x09, +0xad, 0x59, 0xad, 0x88, 0x27, 0xd6, 0x92, 0x6b, +0x10, 0x68, 0x01, 0x9d, 0xba, 0xce, 0x83, 0x08, +0xef, 0x95, 0x52, 0x7b, 0xa0, 0x0f, 0xe4, 0x18, +0x86, 0x80, 0x6f, 0xa5, 0x79, 0x77, 0xda, 0xd0, +}; + +const u8 sm2_pub_x[] = { +0x8e, 0xa0, 0x33, 0x69, 0x91, 0x7e, 0x3d, 0xec, +0xad, 0x8e, 0xf0, 0x45, 0x5e, 0x13, 0x3e, 0x68, +0x5b, 0x8c, 0xab, 0x5c, 0xc6, 0xc8, 0x50, 0xdf, +0x91, 0x00, 0xe0, 0x24, 0x73, 0x4d, 0x31, 0xf2, +}; + +const u8 sm2_pub_y[] = { +0x2e, 0xc0, 0xd5, 0x6b, 0xee, 0xda, 0x98, 0x93, +0xec, 0xd8, 0x36, 0xaa, 0xb9, 0xcf, 0x63, 0x82, +0xef, 0xa7, 0x1a, 0x03, 0xed, 0x16, 0xba, 0x74, +0xb8, 0x8b, 0xf9, 0xe5, 0x70, 0x39, 0xa4, 0x70, +}; + +const u8 sm2_hash[] = { +0x47, 0xa7, 0xbf, 0xd3, 0xda, 0xc4, 0x79, 0xee, +0xda, 0x8b, 0x4f, 0xe8, 0x40, 0x94, 0xd4, 0x32, +0x8f, 0xf1, 0xcd, 0x68, 0x4d, 0xbd, 0x9b, 0x1d, +0xe0, 0xd8, 0x9a, 0x5d, 0xad, 0x85, 0x47, 0x5c, +}; + +const u8 sm2_sign[] = { +0x70, 0xab, 0xb6, 0x7d, 0xd6, 0x54, 0x80, 0x64, +0x42, 0x7e, 0x2d, 0x05, 0x08, 0x36, 0xc9, 0x96, +0x25, 0xc2, 0xbb, 0xff, 0x08, 0xe5, 0x43, 0x15, +0x5e, 0xf3, 0x06, 0xd9, 0x2b, 0x2f, 0x0a, 0x9f, +0xbf, 0x21, 0x5f, 0x7e, 0x5d, 0x3f, 0x1a, 0x4d, +0x8f, 0x84, 0xc2, 0xe9, 0xa6, 0x4c, 0xa4, 0x18, +0xb2, 0xb8, 0x46, 0xf4, 0x32, 0x96, 0xfa, 0x57, +0xc6, 0x29, 0xd4, 0x89, 0xae, 0xcc, 0xda, 0xdb, +}; + +#endif + #endif diff --git a/u-boot/include/rockchip/crypto_mpa.h b/u-boot/include/rockchip/crypto_mpa.h new file mode 100644 index 00000000000..5de91015b57 --- /dev/null +++ b/u-boot/include/rockchip/crypto_mpa.h @@ -0,0 +1,22 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * (C) Copyright 2024 Rockchip Electronics Co., Ltd + */ + +#ifndef _ROCKCHIP_CRYPTO_MPA_H_ +#define _ROCKCHIP_CRYPTO_MPA_H_ +#include + +#define MPA_USE_ALLOC 1 + +struct mpa_num { + u32 alloc; + s32 size; + u32 *d; +}; + +int rk_mpa_alloc(struct mpa_num **mpa, void *data, u32 word_size); +void rk_mpa_free(struct mpa_num **mpa); +int rk_check_size(u32 *data, u32 max_word_size); + +#endif diff --git a/u-boot/include/rockchip/crypto_v2.h b/u-boot/include/rockchip/crypto_v2.h index 7be77cdfe01..73f7185860f 100644 --- a/u-boot/include/rockchip/crypto_v2.h +++ b/u-boot/include/rockchip/crypto_v2.h @@ -407,7 +407,10 @@ #define CRYPTO_RNG_DOUT_7 0x042c #define CRYPTO_RAM_CTL 0x0480 -#define CRYPTO_RAM_PKA_RDY _BIT(0) +#define CRYPTO_RAM_CTL_SEL_MASK _SBF(16, 3) +#define CRYPTO_RAM_CTL_CPU _SBF(0, 0) +#define CRYPTO_RAM_CTL_PKA _SBF(0, 1) +#define CRYPTO_RAM_CTL_ECC _SBF(0, 2) #define CRYPTO_RAM_ST 0x0484 #define CRYPTO_CLK_RAM_RDY _BIT(0) @@ -420,6 +423,10 @@ #define CRYPTO_DEBUG_MONITOR 0x04a8 +#define CRYPTO_KEY_SEL 0x0610 +#define CRYPTO_SEL_USER 0x0 +#define CRYPTO_SEL_KEYTABLE 0x5a5a5a5a + #define CRYPTO_AES_VERSION 0x0680 #define CRYPTO_DES_VERSION 0x0684 #define CRYPTO_SM4_VERSION 0x0688 diff --git a/u-boot/include/rockchip/crypto_v2_pka.h b/u-boot/include/rockchip/crypto_v2_pka.h index 49c27bc10e6..ec769c1ae8e 100644 --- a/u-boot/include/rockchip/crypto_v2_pka.h +++ b/u-boot/include/rockchip/crypto_v2_pka.h @@ -6,18 +6,12 @@ #ifndef _ROCKCHIP_CRYPTO_V2_PKA_H_ #define _ROCKCHIP_CRYPTO_V2_PKA_H_ #include +#include #include #include #define CRYPTO_BASE crypto_base -#define MPA_USE_ALLOC 1 - -struct mpa_num { - u32 alloc; - s32 size; - u32 *d; -}; #define RK_MAX_RSA_NBITS 4096 #define RK_MAX_RSA_NCHARS ((RK_MAX_RSA_NBITS) / 8) @@ -545,8 +539,6 @@ void rk_pka_copy_data_into_reg(s8 dst_reg, u8 len_id, u32 *src_ptr, void rk_pka_copy_data_from_reg(u32 *dst_ptr, u32 size_words, s8 src_reg); int test_rk3326_rsa(void); -int rk_mpa_alloc(struct mpa_num **mpa, void *data, u32 word_size); -void rk_mpa_free(struct mpa_num **mpa); int rk_abs_add(void *a, void *b, void *c); int rk_mod(void *a, void *b, void *c); int rk_exptmod(void *a, void *b, void *c, void *d); diff --git a/u-boot/include/rockchip/rkce_buf.h b/u-boot/include/rockchip/rkce_buf.h new file mode 100644 index 00000000000..0a3fa16b2bb --- /dev/null +++ b/u-boot/include/rockchip/rkce_buf.h @@ -0,0 +1,22 @@ +/* SPDX-License-Identifier: GPL-2.0 */ + +/* Copyright (c) 2025 Rockchip Electronics Co., Ltd. */ + +#ifndef __RKCE_BUF_H__ +#define __RKCE_BUF_H__ + +#include +#include + +#define RKCE_BUF_ALIGN_SIZE 16 + +#define rkce_cma_init(device) +#define rkce_cma_deinit(device) + +#define rkce_cma_alloc(size) memalign(RKCE_BUF_ALIGN_SIZE, size) +#define rkce_cma_free(buf) free(buf) + +#define rkce_cma_virt2phys(buf) (((unsigned long)buf) & 0xffffffff) +#define rkce_cma_phys2virt(phys) ((unsigned long)phys) + +#endif diff --git a/u-boot/include/rockchip/rkce_core.h b/u-boot/include/rockchip/rkce_core.h new file mode 100644 index 00000000000..7c8d1620cf5 --- /dev/null +++ b/u-boot/include/rockchip/rkce_core.h @@ -0,0 +1,339 @@ +/* SPDX-License-Identifier: GPL-2.0 */ + +/* Copyright (c) 2025 Rockchip Electronics Co., Ltd. */ + +#ifndef __RKCE_CORE_H__ +#define __RKCE_CORE_H__ + +#include +#include + +#include "rkce_buf.h" +#include "rkce_error.h" +#include "rkce_reg.h" + +#define RKCE_TD_SG_NUM 8 + +#define RKCE_AES_BLOCK_SIZE 16 +#define RKCE_AES_KEYSIZE_128 16 +#define RKCE_AES_KEYSIZE_192 24 +#define RKCE_AES_KEYSIZE_256 32 + +#define RKCE_SM4_KEYSIZE 16 + +#define RKCE_DES_BLOCK_SIZE 8 +#define RKCE_DES_KEYSIZE 8 +#define RKCE_TDES_EDE_KEYSIZE 24 + +#define RKCE_TD_ALIGINMENT 16 +#define RKCE_TD_KEY_SIZE 128 +#define RKCE_TD_IV_SIZE 16 +#define RKCE_TD_GCM_LEN_SIZE 16 +#define RKCE_TD_HASH_CTX_SIZE RKCE_HASH_CONTEXT_SIZE +#define RKCE_TD_SYMM_CTX_SIZE RKCE_SYMM_CONTEXT_SIZE +#define RKCE_TD_TAG_SIZE 16 +#define RKCE_TD_TAG_SIZE_MIN 8 +#define RKCE_TD_TAG_SIZE_MAX RKCE_TD_TAG_SIZE +#define RKCE_TD_HASH_SIZE 64 +#define RKCE_TD_FIFO_DEPTH 8 + +#define RKCE_RESET_SYMM BIT(0) +#define RKCE_RESET_HASH BIT(1) +#define RKCE_RESET_PKA BIT(2) +#define RKCE_RESET_ALL (RKCE_RESET_SYMM | RKCE_RESET_HASH | RKCE_RESET_PKA) + +#define RKCE_WRITE_MASK_SHIFT (16) +#define RKCE_WRITE_MASK_ALL ((0xffffu << RKCE_WRITE_MASK_SHIFT)) + +enum rkce_expand_bit { + RKCE_EXPAND_BIT_4G = 0, + RKCE_EXPAND_BIT_8G, + RKCE_EXPAND_BIT_16G, + RKCE_EXPAND_BIT_32G, +}; + +enum rkce_td_type { + RKCE_TD_TYPE_SYMM = 0, + RKCE_TD_TYPE_HASH, + RKCE_TD_TYPE_SYMM_HASH_IN, + RKCE_TD_TYPE_SYMM_HASH_OUT, + RKCE_TD_TYPE_MAX, +}; + +enum rkce_algo_symm_type { + RKCE_SYMM_ALGO_AES = 0, + RKCE_SYMM_ALGO_SM4, + RKCE_SYMM_ALGO_DES, + RKCE_SYMM_ALGO_TDES, + RKCE_SYMM_ALGO_MAX, +}; + +enum rkce_algo_symm_mode { + RKCE_SYMM_MODE_ECB = 0, + RKCE_SYMM_MODE_CBC, + RKCE_SYMM_MODE_CTS, + RKCE_SYMM_MODE_CTR, + RKCE_SYMM_MODE_CFB, + RKCE_SYMM_MODE_OFB, + RKCE_SYMM_MODE_XTS, + RKCE_SYMM_MODE_CCM, + RKCE_SYMM_MODE_GCM, + RKCE_SYMM_MODE_CMAC, + RKCE_SYMM_MODE_CBC_MAC, + RKCE_SYMM_MODE_BYPASS = 0xf, + RKCE_SYMM_MODE_MAX, +}; + +enum { + RKCE_KEY_AES_128 = 0, + RKCE_KEY_AES_192, + RKCE_KEY_AES_256, +}; + +enum rkce_algo_hash_type { + RKCE_HASH_ALGO_SHA1 = 0, + RKCE_HASH_ALGO_MD5, + RKCE_HASH_ALGO_SHA256, + RKCE_HASH_ALGO_SHA224, + RKCE_HASH_ALGO_SM3 = 6, + RKCE_HASH_ALGO_SHA512 = 8, + RKCE_HASH_ALGO_SHA384 = 9, + RKCE_HASH_ALGO_SHA512_224, + RKCE_HASH_ALGO_SHA512_256, + RKCE_HASH_ALGO_MAX, +}; + +enum rkce_algo_asym_type { + RKCE_ASYM_ALGO_RSA = 0, + RKCE_ASYM_ALGO_ECC_P192, + RKCE_ASYM_ALGO_ECC_P224, + RKCE_ASYM_ALGO_ECC_P256, + RKCE_ASYM_ALGO_ECC_P384, + RKCE_ASYM_ALGO_ECC_P521, + RKCE_ASYM_ALGO_SM2, + RKCE_ASYM_ALGO_MAX, +}; + +enum rkce_algo_type { + RKCE_ALGO_TYPE_HASH, + RKCE_ALGO_TYPE_HMAC, + RKCE_ALGO_TYPE_CIPHER, + RKCE_ALGO_TYPE_ASYM, + RKCE_ALGO_TYPE_AEAD, + RKCE_ALGO_TYPE_MAX, +}; + +struct rkce_ip_info { + uint32_t aes_ver; + uint32_t des_ver; + uint32_t sm4_ver; + uint32_t hash_ver; + uint32_t hmac_ver; + uint32_t pka_ver; + uint32_t extra_feature; + uint32_t ce_ver; +}; + +struct rkce_gcm_len { + uint32_t pc_len_l; + uint32_t pc_len_h; + uint32_t aad_len_l; + uint32_t aad_len_h; +}; + +struct rkce_sg_info { + uint32_t src_size; + uint32_t src_addr_h; + uint32_t src_addr_l; + + uint32_t dst_size; + uint32_t dst_addr_h; + uint32_t dst_addr_l; +}; + +/* total = 64 + 16 + 16 + 16 + 32 = 114(Byte) */ +struct rkce_symm_td_buf { + uint8_t key1[RKCE_AES_KEYSIZE_256]; // offset 0x00 + uint8_t key2[RKCE_AES_KEYSIZE_256]; // offset 0x20 + uint8_t iv[RKCE_TD_IV_SIZE]; // offset 0x40 + struct rkce_gcm_len gcm_len; // offset 0x50 + uint8_t tag[RKCE_TD_TAG_SIZE]; // offset 0x60 + uint8_t ctx[RKCE_SYMM_CONTEXT_SIZE]; // offset 0x70 + void *user_data; +}; + +/* total = 128 + 64 + 208 = 360(Byte) */ +struct rkce_hash_td_buf { + uint8_t key[RKCE_TD_KEY_SIZE]; // offset 0x00 + uint8_t hash[RKCE_TD_HASH_SIZE]; // offset 0x80 + uint8_t ctx[RKCE_HASH_CONTEXT_SIZE]; // offset 0xB0 + void *user_data; +}; + +struct rkce_symm_hash_td_buf { + uint8_t key1[RKCE_AES_KEYSIZE_256]; // offset 0x00 + uint8_t key2[RKCE_AES_KEYSIZE_256]; // offset 0x20 + uint8_t key3[RKCE_AES_KEYSIZE_256 * 2]; // offset 0x40 + uint8_t iv[RKCE_TD_IV_SIZE]; // offset 0x80 + struct rkce_gcm_len gcm_len; // offset 0x90 + uint8_t tag[RKCE_TD_TAG_SIZE]; // offset 0xA0 + uint8_t hash[RKCE_TD_HASH_SIZE]; // offset 0xB0 + uint8_t symm_ctx[RKCE_SYMM_CONTEXT_SIZE]; // offset 0xF0 + uint8_t hash_ctx[RKCE_HASH_CONTEXT_SIZE]; // offset 0x110 + void *user_data; +}; + +struct rkce_symm_td_ctrl { + uint32_t td_type : 2; + uint32_t is_dec : 1; + uint32_t is_aad : 1; + uint32_t symm_algo : 2; + uint32_t : 2; + uint32_t symm_mode : 4; + uint32_t key_size : 2; + uint32_t first_pkg : 1; + uint32_t last_pkg : 1; + uint32_t key_sel : 3; + uint32_t iv_len : 5; + uint32_t : 4; + uint32_t is_key_inside : 1; + uint32_t : 1; + uint32_t is_preemptible : 1; + uint32_t int_en : 1; +}; + +struct rkce_hash_td_ctrl { + uint32_t td_type : 2; + uint32_t : 5; + uint32_t hw_pad_en : 1; + uint32_t : 6; + uint32_t first_pkg : 1; + uint32_t last_pkg : 1; + uint32_t : 8; + uint32_t hash_algo: 4; + uint32_t : 1; + uint32_t hmac_en : 1; + uint32_t is_preemptible : 1; + uint32_t int_en : 1; +}; + +struct rkce_symm_hash_td_ctrl { + uint32_t td_type : 2; + uint32_t is_dec : 1; + uint32_t is_aad : 1; + uint32_t symm_algo : 2; + uint32_t : 1; + uint32_t hw_pad_en : 1; + uint32_t symm_mode : 4; + uint32_t key_size : 2; + uint32_t first_pkg : 1; + uint32_t last_pkg : 1; + uint32_t key_sel : 3; + uint32_t iv_len : 5; + uint32_t hash_algo: 4; + uint32_t is_key_inside : 1; + uint32_t hmac_en : 1; + uint32_t is_preemptible : 1; + uint32_t int_en : 1; +}; + +struct rkce_symm_td { + uint32_t task_id; + struct rkce_symm_td_ctrl ctrl; + uint32_t reserve1; + uint32_t key_addr; + + uint32_t iv_addr; + uint32_t gcm_len_addr; + uint32_t reserve2; + uint32_t tag_addr; + + struct rkce_sg_info sg[RKCE_TD_SG_NUM]; + + uint32_t reserve3; + uint32_t symm_ctx_addr; + uint32_t reserve4[5]; + uint32_t next_task; +}; + +struct rkce_hash_td { + uint32_t task_id; + struct rkce_hash_td_ctrl ctrl; + uint32_t reserve1; + uint32_t key_addr; + + uint32_t reserve2[2]; + uint32_t hash_addr; + uint32_t reserve3; + + struct rkce_sg_info sg[RKCE_TD_SG_NUM]; + + uint32_t hash_ctx_addr; + uint32_t reserve4[6]; + uint32_t next_task; +}; + +struct rkce_symm_hash_td { + uint32_t task_id; + struct rkce_symm_hash_td_ctrl ctrl; + uint32_t reserve1; + uint32_t key_addr; + + uint32_t iv_addr; + uint32_t gcm_len_addr; + uint32_t hash_addr; + uint32_t tag_addr; + + struct rkce_sg_info sg[RKCE_TD_SG_NUM]; + + uint32_t hash_ctx_addr; + uint32_t symm_ctx_addr; + uint32_t reserve3[5]; + uint32_t next_task; +}; + +struct rkce_td { + union { + struct rkce_symm_td symm; + struct rkce_hash_td hash; + struct rkce_symm_hash_td symm_hash; + } td; +}; + +struct rkce_td_buf { + union { + struct rkce_symm_td_buf symm; + struct rkce_hash_td_buf hash; + struct rkce_symm_hash_td_buf symm_hash; + } td_buf; +}; + +typedef int (*request_cb_func)(int result, uint32_t td_id, void *td_virt); + +void rkce_dump_reginfo(void *rkce_hw); + +void *rkce_hardware_alloc(void __iomem *reg_base); + +void rkce_hardware_free(void *rkce_hw); + +void rkce_irq_handler(void *rkce_hw); + +void rkce_irq_thread(void *rkce_hw); + +int rkce_irq_callback_set(void *rkce_hw, enum rkce_td_type td_type, request_cb_func cb_func); + +int rkce_soft_reset(void *rkce_hw, uint32_t reset_sel); + +int rkce_push_td(void *rkce_hw, void *td); + +int rkce_push_td_sync(void *rkce_hw, void *td, uint32_t timeout_ms); + +uint32_t rkce_get_td_type(void *td_buf); + +int rkce_init_symm_td(struct rkce_symm_td *td, struct rkce_symm_td_buf *buf); + +int rkce_init_hash_td(struct rkce_hash_td *td, struct rkce_hash_td_buf *buf); + +bool rkce_hw_algo_valid(void *rkce_hw, uint32_t type, uint32_t algo, uint32_t mode); + +#endif diff --git a/u-boot/include/rockchip/rkce_debug.h b/u-boot/include/rockchip/rkce_debug.h new file mode 100644 index 00000000000..c62344ef54f --- /dev/null +++ b/u-boot/include/rockchip/rkce_debug.h @@ -0,0 +1,39 @@ +/* SPDX-License-Identifier: GPL-2.0 */ + +/* Copyright (c) 2025 Rockchip Electronics Co., Ltd. */ + +#ifndef __RKCE_DEBUG_H__ +#define __RKCE_DEBUG_H__ + +#include + +#define rk_err(fmt, args...) printf("RKCE: E [%s %d]: " fmt "\n", \ + __func__, __LINE__, ##args) + +#define rk_warn(fmt, args...) printf("RKCE: W [%s %d]: " fmt "\n", \ + __func__, __LINE__, ##args) + +#define rk_info(fmt, args...) printf(fmt, ##args) + +#if defined(DEBUG) +#define rk_debug(fmt, args...) printf("RKCE: D [%s %d]: " fmt "\n", \ + __func__, __LINE__, ##args) + +#define rk_trace(fmt, args...) printf("RKCE: T [%s %d]: " fmt "\n", \ + __func__, __LINE__, ##args) +#else +#define rk_debug(fmt, args...) +#define rk_trace(fmt, args...) +#endif + +#define rkce_dump_td(td) + +#if defined(DEBUG) +#define rkce_dumphex(var_name, data, len) print_hex_dump(KERN_CONT, (var_name), \ + DUMP_PREFIX_OFFSET, \ + 16, 1, (data), (len), false) +#else +#define rkce_dumphex(var_name, data, len) +#endif + +#endif diff --git a/u-boot/include/rockchip/rkce_error.h b/u-boot/include/rockchip/rkce_error.h new file mode 100644 index 00000000000..1cbebb9bf80 --- /dev/null +++ b/u-boot/include/rockchip/rkce_error.h @@ -0,0 +1,16 @@ +/* SPDX-License-Identifier: GPL-2.0 */ + +/* Copyright (c) 2025 Rockchip Electronics Co., Ltd. */ + +#ifndef __RKCE_ERROR_H__ +#define __RKCE_ERROR_H__ + +#include + +#define RKCE_SUCCESS 0 +#define RKCE_NOMEM ENOMEM +#define RKCE_FAULT EFAULT +#define RKCE_INVAL EINVAL +#define RKCE_TIMEOUT ETIMEDOUT + +#endif diff --git a/u-boot/include/rockchip/rkce_reg.h b/u-boot/include/rockchip/rkce_reg.h new file mode 100644 index 00000000000..bde10922f42 --- /dev/null +++ b/u-boot/include/rockchip/rkce_reg.h @@ -0,0 +1,533 @@ +/* SPDX-License-Identifier: GPL-2.0 */ + +/* Copyright (c) 2025 Rockchip Electronics Co., Ltd. */ + +#ifndef __RKCE_REG_H +#define __RKCE_REG_H + +#include + +/****************************************************************************************/ +/* */ +/* Module Structure Section */ +/* */ +/****************************************************************************************/ +/* RKCE Register Structure Define */ +struct RKCE_REG { + uint32_t CLK_CTL; /* Address Offset: 0x0000 */ + uint32_t RST_CTL; /* Address Offset: 0x0004 */ + uint32_t RESERVED0008[126]; /* Address Offset: 0x0008 */ + uint32_t TD_ADDR; /* Address Offset: 0x0200 */ + uint32_t TD_LOAD_CTRL; /* Address Offset: 0x0204 */ + uint32_t FIFO_ST; /* Address Offset: 0x0208 */ + uint32_t RESERVED020C; /* Address Offset: 0x020C */ + uint32_t SYMM_INT_EN; /* Address Offset: 0x0210 */ + uint32_t SYMM_INT_ST; /* Address Offset: 0x0214 */ + uint32_t SYMM_TD_ID; /* Address Offset: 0x0218 */ + uint32_t SYMM_TD_ST; /* Address Offset: 0x021C */ + uint32_t SYMM_ST_DBG; /* Address Offset: 0x0220 */ + uint32_t SYMM_CONTEXT_SIZE; /* Address Offset: 0x0224 */ + uint32_t SYMM_TD_ADDR_DBG; /* Address Offset: 0x0228 */ + uint32_t SYMM_TD_GRANT_DBG; /* Address Offset: 0x022C */ + uint32_t HASH_INT_EN; /* Address Offset: 0x0230 */ + uint32_t HASH_INT_ST; /* Address Offset: 0x0234 */ + uint32_t HASH_TD_ID; /* Address Offset: 0x0238 */ + uint32_t HASH_TD_ST; /* Address Offset: 0x023C */ + uint32_t HASH_ST_DBG; /* Address Offset: 0x0240 */ + uint32_t HASH_CONTEXT_SIZE; /* Address Offset: 0x0244 */ + uint32_t HASH_TD_ADDR_DBG; /* Address Offset: 0x0248 */ + uint32_t HASH_TD_GRANT_DBG; /* Address Offset: 0x024C */ + uint32_t SYMM_TD_POP_ADDR; /* Address Offset: 0x0250 */ + uint32_t HASH_TD_POP_ADDR; /* Address Offset: 0x0254 */ + uint32_t TD_POP_CTRL; /* Address Offset: 0x0258 */ + uint32_t RESERVED025C[5]; /* Address Offset: 0x025C */ + uint32_t KL_TO_CE_PADDR; /* Address Offset: 0x0270 */ + uint32_t KL_KD_ADDR; /* Address Offset: 0x0274 */ + uint32_t RESERVED0278[94]; /* Address Offset: 0x0278 */ + uint32_t ECC_CTL; /* Address Offset: 0x03F0 */ + uint32_t ECC_INT_EN; /* Address Offset: 0x03F4 */ + uint32_t ECC_INT_ST; /* Address Offset: 0x03F8 */ + uint32_t ECC_ABN_ST; /* Address Offset: 0x03FC */ + uint32_t ECC_CURVE_WIDE; /* Address Offset: 0x0400 */ + uint32_t ECC_MAX_CURVE_WIDE; /* Address Offset: 0x0404 */ + uint32_t ECC_DATA_ENDIAN; /* Address Offset: 0x0408 */ + uint32_t RESERVED040C[17]; /* Address Offset: 0x040C */ + uint32_t KL_APB_CMD; /* Address Offset: 0x0450 */ + uint32_t KL_APB_PADDR; /* Address Offset: 0x0454 */ + uint32_t KL_APB_PWDATA; /* Address Offset: 0x0458 */ + uint32_t RESERVED045C[2]; /* Address Offset: 0x045C */ + uint32_t KL_KD_VID; /* Address Offset: 0x0464 */ + uint32_t KL_KD_MODE; /* Address Offset: 0x0468 */ + uint32_t RESERVED046C[5]; /* Address Offset: 0x046C */ + uint32_t PKA_RAM_CTL; /* Address Offset: 0x0480 */ + uint32_t PKA_RAM_ST; /* Address Offset: 0x0484 */ + uint32_t RESERVED0488[6]; /* Address Offset: 0x0488 */ + uint32_t PKA_DEBUG_CTL; /* Address Offset: 0x04A0 */ + uint32_t PKA_DEBUG_ST; /* Address Offset: 0x04A4 */ + uint32_t PKA_DEBUG_MONITOR; /* Address Offset: 0x04A8 */ + uint32_t RESERVED04AC[85]; /* Address Offset: 0x04AC */ + uint32_t KT_ST; /* Address Offset: 0x0600 */ + uint32_t RESERVED0604; /* Address Offset: 0x0604 */ + uint32_t KL_INTER_COPY; /* Address Offset: 0x0608 */ + uint32_t RESERVED060C[4]; /* Address Offset: 0x060C */ + uint32_t LOCKSTEP_EN; /* Address Offset: 0x061C */ + uint32_t RESERVED0620[2]; /* Address Offset: 0x0620 */ + uint32_t LOCKSTEP_IJERR; /* Address Offset: 0x0628 */ + uint32_t RESERVED062C[5]; /* Address Offset: 0x062C */ + uint32_t KL_OTP_KEY_REQ; /* Address Offset: 0x0640 */ + uint32_t KL_KEY_CLEAR; /* Address Offset: 0x0644 */ + uint32_t KL_OTP_KEY_LEN; /* Address Offset: 0x0648 */ + uint32_t KL_HW_DRNG_REQ; /* Address Offset: 0x064C */ + uint32_t RESERVED0650[12]; /* Address Offset: 0x0650 */ + uint32_t AES_VER; /* Address Offset: 0x0680 */ + uint32_t DES_VER; /* Address Offset: 0x0684 */ + uint32_t SM4_VER; /* Address Offset: 0x0688 */ + uint32_t HASH_VER; /* Address Offset: 0x068C */ + uint32_t HMAC_VER; /* Address Offset: 0x0690 */ + uint32_t RESERVED0694; /* Address Offset: 0x0694 */ + uint32_t PKA_VER; /* Address Offset: 0x0698 */ + uint32_t EXTRA_FEATURE; /* Address Offset: 0x069C */ + uint32_t RESERVED06A0[20]; /* Address Offset: 0x06A0 */ + uint32_t CE_VER; /* Address Offset: 0x06F0 */ + uint32_t RESERVED06F4[67]; /* Address Offset: 0x06F4 */ + uint32_t PKA_MEM_MAP0; /* Address Offset: 0x0800 */ + uint32_t PKA_MEM_MAP1; /* Address Offset: 0x0804 */ + uint32_t PKA_MEM_MAP2; /* Address Offset: 0x0808 */ + uint32_t PKA_MEM_MAP3; /* Address Offset: 0x080C */ + uint32_t PKA_MEM_MAP4; /* Address Offset: 0x0810 */ + uint32_t PKA_MEM_MAP5; /* Address Offset: 0x0814 */ + uint32_t PKA_MEM_MAP6; /* Address Offset: 0x0818 */ + uint32_t PKA_MEM_MAP7; /* Address Offset: 0x081C */ + uint32_t PKA_MEM_MAP8; /* Address Offset: 0x0820 */ + uint32_t PKA_MEM_MAP9; /* Address Offset: 0x0824 */ + uint32_t PKA_MEM_MAP10; /* Address Offset: 0x0828 */ + uint32_t PKA_MEM_MAP11; /* Address Offset: 0x082C */ + uint32_t PKA_MEM_MAP12; /* Address Offset: 0x0830 */ + uint32_t PKA_MEM_MAP13; /* Address Offset: 0x0834 */ + uint32_t PKA_MEM_MAP14; /* Address Offset: 0x0838 */ + uint32_t PKA_MEM_MAP15; /* Address Offset: 0x083C */ + uint32_t PKA_MEM_MAP16; /* Address Offset: 0x0840 */ + uint32_t PKA_MEM_MAP17; /* Address Offset: 0x0844 */ + uint32_t PKA_MEM_MAP18; /* Address Offset: 0x0848 */ + uint32_t PKA_MEM_MAP19; /* Address Offset: 0x084C */ + uint32_t PKA_MEM_MAP20; /* Address Offset: 0x0850 */ + uint32_t PKA_MEM_MAP21; /* Address Offset: 0x0854 */ + uint32_t PKA_MEM_MAP22; /* Address Offset: 0x0858 */ + uint32_t PKA_MEM_MAP23; /* Address Offset: 0x085C */ + uint32_t PKA_MEM_MAP24; /* Address Offset: 0x0860 */ + uint32_t PKA_MEM_MAP25; /* Address Offset: 0x0864 */ + uint32_t PKA_MEM_MAP26; /* Address Offset: 0x0868 */ + uint32_t PKA_MEM_MAP27; /* Address Offset: 0x086C */ + uint32_t PKA_MEM_MAP28; /* Address Offset: 0x0870 */ + uint32_t PKA_MEM_MAP29; /* Address Offset: 0x0874 */ + uint32_t PKA_MEM_MAP30; /* Address Offset: 0x0878 */ + uint32_t PKA_MEM_MAP31; /* Address Offset: 0x087C */ + uint32_t PKA_OPCODE; /* Address Offset: 0x0880 */ + uint32_t N_NP_T0_T1_ADDR; /* Address Offset: 0x0884 */ + uint32_t PKA_STATUS; /* Address Offset: 0x0888 */ + uint32_t RESERVED088C; /* Address Offset: 0x088C */ + uint32_t PKA_L0; /* Address Offset: 0x0890 */ + uint32_t PKA_L1; /* Address Offset: 0x0894 */ + uint32_t PKA_L2; /* Address Offset: 0x0898 */ + uint32_t PKA_L3; /* Address Offset: 0x089C */ + uint32_t PKA_L4; /* Address Offset: 0x08A0 */ + uint32_t PKA_L5; /* Address Offset: 0x08A4 */ + uint32_t PKA_L6; /* Address Offset: 0x08A8 */ + uint32_t PKA_L7; /* Address Offset: 0x08AC */ + uint32_t PKA_PIPE_RDY; /* Address Offset: 0x08B0 */ + uint32_t PKA_DONE; /* Address Offset: 0x08B4 */ + uint32_t PKA_MON_SELECT; /* Address Offset: 0x08B8 */ + uint32_t PKA_DEBUG_REG_EN; /* Address Offset: 0x08BC */ + uint32_t DEBUG_CNT_ADDR; /* Address Offset: 0x08C0 */ + uint32_t DEBUG_EXT_ADDR; /* Address Offset: 0x08C4 */ + uint32_t PKA_DEBUG_HALT; /* Address Offset: 0x08C8 */ + uint32_t RESERVED08CC; /* Address Offset: 0x08CC */ + uint32_t PKA_MON_READ; /* Address Offset: 0x08D0 */ + uint32_t PKA_INT_ENA; /* Address Offset: 0x08D4 */ + uint32_t PKA_INT_ST; /* Address Offset: 0x08D8 */ + uint32_t TD0_TD1_TX_ADDR; /* Address Offset: 0x08DC */ + uint32_t RESERVED08E0[456]; /* Address Offset: 0x08E0 */ + uint32_t SRAM_ADDR; /* Address Offset: 0x1000 */ +}; + +/****************************************************************************************/ +/* */ +/* Register Bitmap Section */ +/* */ +/****************************************************************************************/ +/******************************************RKCE******************************************/ +/* CLK_CTL */ +#define RKCE_CLK_CTL_OFFSET (0x0U) +#define RKCE_CLK_CTL_AUTO_CLKGATE_EN_SHIFT (0U) +#define RKCE_CLK_CTL_AUTO_CLKGATE_EN_MASK (0x1U << RKCE_CLK_CTL_AUTO_CLKGATE_EN_SHIFT) +/* RST_CTL */ +#define RKCE_RST_CTL_OFFSET (0x4U) +#define RKCE_RST_CTL_SW_SYMM_RESET_SHIFT (0U) +#define RKCE_RST_CTL_SW_SYMM_RESET_MASK (0x1U << RKCE_RST_CTL_SW_SYMM_RESET_SHIFT) +#define RKCE_RST_CTL_SW_HASH_RESET_SHIFT (1U) +#define RKCE_RST_CTL_SW_HASH_RESET_MASK (0x1U << RKCE_RST_CTL_SW_HASH_RESET_SHIFT) +#define RKCE_RST_CTL_SW_PKA_RESET_SHIFT (2U) +#define RKCE_RST_CTL_SW_PKA_RESET_MASK (0x1U << RKCE_RST_CTL_SW_PKA_RESET_SHIFT) +/* TD_ADDR */ +#define RKCE_TD_ADDR_OFFSET (0x200U) +#define RKCE_TD_ADDR_TD_ADDR_SHIFT (0U) +#define RKCE_TD_ADDR_TD_ADDR_MASK (0xFFFFFFFFU << RKCE_TD_ADDR_TD_ADDR_SHIFT) +/* TD_LOAD_CTRL */ +#define RKCE_TD_LOAD_CTRL_OFFSET (0x204U) +#define RKCE_TD_LOAD_CTRL_SYMM_TLR_SHIFT (0U) +#define RKCE_TD_LOAD_CTRL_SYMM_TLR_MASK (0x1U << RKCE_TD_LOAD_CTRL_SYMM_TLR_SHIFT) +#define RKCE_TD_LOAD_CTRL_HASH_TLR_SHIFT (1U) +#define RKCE_TD_LOAD_CTRL_HASH_TLR_MASK (0x1U << RKCE_TD_LOAD_CTRL_HASH_TLR_SHIFT) +/* SYMM_INT_ST */ +#define RKCE_SYMM_INT_ST_OFFSET (0x214U) +#define RKCE_SYMM_INT_ST_TD_DONE_SHIFT (0U) +#define RKCE_SYMM_INT_ST_TD_DONE_MASK (0x1U << RKCE_SYMM_INT_ST_TD_DONE_SHIFT) +#define RKCE_SYMM_INT_ST_DST_ERROR_SHIFT (1U) +#define RKCE_SYMM_INT_ST_DST_ERROR_MASK (0x1U << RKCE_SYMM_INT_ST_DST_ERROR_SHIFT) +#define RKCE_SYMM_INT_ST_SRC_ERROR_SHIFT (2U) +#define RKCE_SYMM_INT_ST_SRC_ERROR_MASK (0x1U << RKCE_SYMM_INT_ST_SRC_ERROR_SHIFT) +#define RKCE_SYMM_INT_ST_TD_ERROR_SHIFT (3U) +#define RKCE_SYMM_INT_ST_TD_ERROR_MASK (0x1U << RKCE_SYMM_INT_ST_TD_ERROR_SHIFT) +#define RKCE_SYMM_INT_ST_NE_LEN_SHIFT (4U) +#define RKCE_SYMM_INT_ST_NE_LEN_MASK (0x1U << RKCE_SYMM_INT_ST_NE_LEN_SHIFT) +#define RKCE_SYMM_INT_ST_LOCKSTEP_ERROR_SHIFT (5U) +#define RKCE_SYMM_INT_ST_LOCKSTEP_ERROR_MASK (0x1U << RKCE_SYMM_INT_ST_LOCKSTEP_ERROR_SHIFT) +/* SYMM_TD_ID */ +#define RKCE_SYMM_TD_ID_OFFSET (0x218U) +#define RKCE_SYMM_TD_ID (0x0U) +#define RKCE_SYMM_TD_ID_STDID_SHIFT (0U) +#define RKCE_SYMM_TD_ID_STDID_MASK (0xFFFFFFFFU << RKCE_SYMM_TD_ID_STDID_SHIFT) +/* SYMM_TD_ST */ +#define RKCE_SYMM_TD_ST_OFFSET (0x21CU) +#define RKCE_SYMM_TD_ST (0x0U) +#define RKCE_SYMM_TD_ST_FIRST_PKG_FLAG_SHIFT (0U) +#define RKCE_SYMM_TD_ST_FIRST_PKG_FLAG_MASK (0x1U << RKCE_SYMM_TD_ST_FIRST_PKG_FLAG_SHIFT) +#define RKCE_SYMM_TD_ST_LAST_PKG_FLAG_SHIFT (1U) +#define RKCE_SYMM_TD_ST_LAST_PKG_FLAG_MASK (0x1U << RKCE_SYMM_TD_ST_LAST_PKG_FLAG_SHIFT) +#define RKCE_SYMM_TD_ST_DMA_START_FLAG_SHIFT (2U) +#define RKCE_SYMM_TD_ST_DMA_START_FLAG_MASK (0x1U << RKCE_SYMM_TD_ST_DMA_START_FLAG_SHIFT) +#define RKCE_SYMM_TD_ST_PRMPT_PKG_FLGA_SHIFT (3U) +#define RKCE_SYMM_TD_ST_PRMPT_PKG_FLGA_MASK (0x1U << RKCE_SYMM_TD_ST_PRMPT_PKG_FLGA_SHIFT) +/* SYMM_CONTEXT_SIZE */ +#define RKCE_SYMM_CONTEXT_SIZE_OFFSET (0x224U) +#define RKCE_SYMM_CONTEXT_SIZE (0x20U) +/* HASH_INT_ST */ +#define RKCE_HASH_INT_ST_OFFSET (0x234U) +#define RKCE_HASH_INT_ST_TD_DONE_SHIFT (0U) +#define RKCE_HASH_INT_ST_TD_DONE_MASK (0x1U << RKCE_HASH_INT_ST_TD_DONE_SHIFT) +#define RKCE_HASH_INT_ST_DST_ERROR_SHIFT (1U) +#define RKCE_HASH_INT_ST_DST_ERROR_MASK (0x1U << RKCE_HASH_INT_ST_DST_ERROR_SHIFT) +#define RKCE_HASH_INT_ST_SRC_ERROR_SHIFT (2U) +#define RKCE_HASH_INT_ST_SRC_ERROR_MASK (0x1U << RKCE_HASH_INT_ST_SRC_ERROR_SHIFT) +#define RKCE_HASH_INT_ST_TD_ERROR_SHIFT (3U) +#define RKCE_HASH_INT_ST_TD_ERROR_MASK (0x1U << RKCE_HASH_INT_ST_TD_ERROR_SHIFT) +#define RKCE_HASH_INT_ST_NE_LEN_SHIFT (4U) +#define RKCE_HASH_INT_ST_NE_LEN_MASK (0x1U << RKCE_HASH_INT_ST_NE_LEN_SHIFT) +#define RKCE_HASH_INT_ST_LOCKSTEP_ERROR_SHIFT (5U) +#define RKCE_HASH_INT_ST_LOCKSTEP_ERROR_MASK (0x1U << RKCE_HASH_INT_ST_LOCKSTEP_ERROR_SHIFT) +/* HASH_TD_ID */ +#define RKCE_HASH_TD_ID_OFFSET (0x238U) +#define RKCE_HASH_TD_ID (0x0U) +#define RKCE_HASH_TD_ID_HTDID_SHIFT (0U) +#define RKCE_HASH_TD_ID_HTDID_MASK (0xFFFFFFFFU << RKCE_HASH_TD_ID_HTDID_SHIFT) +/* HASH_TD_ST */ +#define RKCE_HASH_TD_ST_OFFSET (0x23CU) +#define RKCE_HASH_TD_ST (0x0U) +#define RKCE_HASH_TD_ST_FIRST_PKG_FLAG_SHIFT (0U) +#define RKCE_HASH_TD_ST_FIRST_PKG_FLAG_MASK (0x1U << RKCE_HASH_TD_ST_FIRST_PKG_FLAG_SHIFT) +#define RKCE_HASH_TD_ST_LAST_PKG_FLAG_SHIFT (1U) +#define RKCE_HASH_TD_ST_LAST_PKG_FLAG_MASK (0x1U << RKCE_HASH_TD_ST_LAST_PKG_FLAG_SHIFT) +#define RKCE_HASH_TD_ST_DMA_START_FLAG_SHIFT (2U) +#define RKCE_HASH_TD_ST_DMA_START_FLAG_MASK (0x1U << RKCE_HASH_TD_ST_DMA_START_FLAG_SHIFT) +#define RKCE_HASH_TD_ST_PRMPT_PKG_FLGA_SHIFT (3U) +#define RKCE_HASH_TD_ST_PRMPT_PKG_FLGA_MASK (0x1U << RKCE_HASH_TD_ST_PRMPT_PKG_FLGA_SHIFT) +/* HASH_CONTEXT_SIZE */ +#define RKCE_HASH_CONTEXT_SIZE_OFFSET (0x244U) +#define RKCE_HASH_CONTEXT_SIZE (0xD0U) +/* TD_POP_CTRL */ +#define RKCE_TD_POP_CTRL_OFFSET (0x258U) +#define RKCE_TD_POP_CTRL (0x0U) +#define RKCE_TD_POP_CTRL_SYMM_TPR_SHIFT (0U) +#define RKCE_TD_POP_CTRL_SYMM_TPR_MASK (0x1U << RKCE_TD_POP_CTRL_SYMM_TPR_SHIFT) +#define RKCE_TD_POP_CTRL_HASH_TPR_SHIFT (1U) +#define RKCE_TD_POP_CTRL_HASH_TPR_MASK (0x1U << RKCE_TD_POP_CTRL_HASH_TPR_SHIFT) +/* ECC_CTL */ +#define RKCE_ECC_CTL_OFFSET (0x3F0U) +#define RKCE_ECC_CTL_ECC_REQ_SHIFT (0U) +#define RKCE_ECC_CTL_ECC_REQ_MASK (0x1U << RKCE_ECC_CTL_ECC_REQ_SHIFT) +#define RKCE_ECC_CTL_FUNC_SEL_SHIFT (4U) +#define RKCE_ECC_CTL_FUNC_SEL_MASK (0xFU << RKCE_ECC_CTL_FUNC_SEL_SHIFT) +#define RKCE_ECC_CTL_CURVE_MODE_SEL_SHIFT (8U) +#define RKCE_ECC_CTL_CURVE_MODE_SEL_MASK (0x1U << RKCE_ECC_CTL_CURVE_MODE_SEL_SHIFT) +#define RKCE_ECC_CTL_RAND_K_SRC_SHIFT (12U) +#define RKCE_ECC_CTL_RAND_K_SRC_MASK (0x1U << RKCE_ECC_CTL_RAND_K_SRC_SHIFT) +/* ECC_INT_EN */ +#define RKCE_ECC_INT_EN_OFFSET (0x3F4U) +#define RKCE_ECC_INT_EN_DONE_INT_EN_SHIFT (0U) +#define RKCE_ECC_INT_EN_DONE_INT_EN_MASK (0x1U << RKCE_ECC_INT_EN_DONE_INT_EN_SHIFT) +/* ECC_INT_ST */ +#define RKCE_ECC_INT_ST_OFFSET (0x3F8U) +#define RKCE_ECC_INT_ST_DONE_INT_ST_SHIFT (0U) +#define RKCE_ECC_INT_ST_DONE_INT_ST_MASK (0x1U << RKCE_ECC_INT_ST_DONE_INT_ST_SHIFT) +/* ECC_ABN_ST */ +#define RKCE_ECC_ABN_ST_OFFSET (0x3FCU) +#define RKCE_ECC_ABN_ST (0x0U) +#define RKCE_ECC_ABN_ST_BAD_POINT_OUT_SHIFT (0U) +#define RKCE_ECC_ABN_ST_BAD_POINT_OUT_MASK (0x1U << RKCE_ECC_ABN_ST_BAD_POINT_OUT_SHIFT) +#define RKCE_ECC_ABN_ST_BAD_T_OUT_SHIFT (1U) +#define RKCE_ECC_ABN_ST_BAD_T_OUT_MASK (0x1U << RKCE_ECC_ABN_ST_BAD_T_OUT_SHIFT) +#define RKCE_ECC_ABN_ST_BAD_S_OUT_SHIFT (2U) +#define RKCE_ECC_ABN_ST_BAD_S_OUT_MASK (0x1U << RKCE_ECC_ABN_ST_BAD_S_OUT_SHIFT) +#define RKCE_ECC_ABN_ST_BAD_R_OUT_SHIFT (3U) +#define RKCE_ECC_ABN_ST_BAD_R_OUT_MASK (0x1U << RKCE_ECC_ABN_ST_BAD_R_OUT_SHIFT) +#define RKCE_ECC_ABN_ST_BAD_R_K_MID_SHIFT (4U) +#define RKCE_ECC_ABN_ST_BAD_R_K_MID_MASK (0x1U << RKCE_ECC_ABN_ST_BAD_R_K_MID_SHIFT) +#define RKCE_ECC_ABN_ST_BAD_S_IN_SHIFT (5U) +#define RKCE_ECC_ABN_ST_BAD_S_IN_MASK (0x1U << RKCE_ECC_ABN_ST_BAD_S_IN_SHIFT) +#define RKCE_ECC_ABN_ST_BAD_R_IN_SHIFT (6U) +#define RKCE_ECC_ABN_ST_BAD_R_IN_MASK (0x1U << RKCE_ECC_ABN_ST_BAD_R_IN_SHIFT) +#define RKCE_ECC_ABN_ST_BAD_K_IN_SHIFT (7U) +#define RKCE_ECC_ABN_ST_BAD_K_IN_MASK (0x1U << RKCE_ECC_ABN_ST_BAD_K_IN_SHIFT) +#define RKCE_ECC_ABN_ST_BAD_INV_OT_SHIFT (8U) +#define RKCE_ECC_ABN_ST_BAD_INV_OT_MASK (0x1U << RKCE_ECC_ABN_ST_BAD_INV_OT_SHIFT) +/* ECC_CURVE_WIDE */ +#define RKCE_ECC_CURVE_WIDE_OFFSET (0x400U) +#define RKCE_ECC_CURVE_WIDE_CURVE_WIDE_SHIFT (0U) +#define RKCE_ECC_CURVE_WIDE_CURVE_WIDE_MASK (0x3FFU << RKCE_ECC_CURVE_WIDE_CURVE_WIDE_SHIFT) +/* ECC_MAX_CURVE_WIDE */ +#define RKCE_ECC_MAX_CURVE_WIDE_OFFSET (0x404U) +#define RKCE_ECC_MAX_CURVE_WIDE (0x100U) +/* ECC_DATA_ENDIAN */ +#define RKCE_ECC_DATA_ENDIAN_OFFSET (0x408U) +/* PKA_RAM_CTL */ +#define RKCE_PKA_RAM_CTL_OFFSET (0x480U) +#define RKCE_PKA_RAM_CTL_PKA_RDY BIT(0) +#define RKCE_PKA_RAM_CTL_RAM_PKA_RDY_SHIFT (0U) +#define RKCE_PKA_RAM_CTL_RAM_PKA_RDY_MASK (0x3U << RKCE_PKA_RAM_CTL_RAM_PKA_RDY_SHIFT) +/* PKA_RAM_ST */ +#define RKCE_PKA_RAM_ST_OFFSET (0x484U) +#define RKCE_PKA_RAM_ST (0x1U) +#define RKCE_PKA_RAM_ST_CLK_RAM_RDY_SHIFT (0U) +#define RKCE_PKA_RAM_ST_CLK_RAM_RDY_MASK (0x1U << RKCE_PKA_RAM_ST_CLK_RAM_RDY_SHIFT) +/* AES_VER */ +#define RKCE_AES_VER_OFFSET (0x680U) +#define RKCE_AES_VER_ECB_FLAG_SHIFT (0U) +#define RKCE_AES_VER_ECB_FLAG_MASK (0x1U << RKCE_AES_VER_ECB_FLAG_SHIFT) +#define RKCE_AES_VER_CBC_FLAG_SHIFT (1U) +#define RKCE_AES_VER_CBC_FLAG_MASK (0x1U << RKCE_AES_VER_CBC_FLAG_SHIFT) +#define RKCE_AES_VER_CTS_FLAG_SHIFT (2U) +#define RKCE_AES_VER_CTS_FLAG_MASK (0x1U << RKCE_AES_VER_CTS_FLAG_SHIFT) +#define RKCE_AES_VER_CTR_FLAG_SHIFT (3U) +#define RKCE_AES_VER_CTR_FLAG_MASK (0x1U << RKCE_AES_VER_CTR_FLAG_SHIFT) +#define RKCE_AES_VER_CFB_FLAG_SHIFT (4U) +#define RKCE_AES_VER_CFB_FLAG_MASK (0x1U << RKCE_AES_VER_CFB_FLAG_SHIFT) +#define RKCE_AES_VER_OFB_FLAG_SHIFT (5U) +#define RKCE_AES_VER_OFB_FLAG_MASK (0x1U << RKCE_AES_VER_OFB_FLAG_SHIFT) +#define RKCE_AES_VER_XTS_FLAG_SHIFT (6U) +#define RKCE_AES_VER_XTS_FLAG_MASK (0x1U << RKCE_AES_VER_XTS_FLAG_SHIFT) +#define RKCE_AES_VER_CCM_FLAG_SHIFT (7U) +#define RKCE_AES_VER_CCM_FLAG_MASK (0x1U << RKCE_AES_VER_CCM_FLAG_SHIFT) +#define RKCE_AES_VER_GCM_FLAG_SHIFT (8U) +#define RKCE_AES_VER_GCM_FLAG_MASK (0x1U << RKCE_AES_VER_GCM_FLAG_SHIFT) +#define RKCE_AES_VER_CMAC_FLAG_SHIFT (9U) +#define RKCE_AES_VER_CMAC_FLAG_MASK (0x1U << RKCE_AES_VER_CMAC_FLAG_SHIFT) +#define RKCE_AES_VER_CBC_MAC_FLAG_SHIFT (10U) +#define RKCE_AES_VER_CBC_MAC_FLAG_MASK (0x1U << RKCE_AES_VER_CBC_MAC_FLAG_SHIFT) +#define RKCE_AES_VER_BYPASS_SHIFT (12U) +#define RKCE_AES_VER_BYPASS_MASK (0x1U << RKCE_AES_VER_BYPASS_SHIFT) +#define RKCE_AES_VER_AES128_FLAG_SHIFT (16U) +#define RKCE_AES_VER_AES128_FLAG_MASK (0x1U << RKCE_AES_VER_AES128_FLAG_SHIFT) +#define RKCE_AES_VER_AES192_FLAG_SHIFT (17U) +#define RKCE_AES_VER_AES192_FLAG_MASK (0x1U << RKCE_AES_VER_AES192_FLAG_SHIFT) +#define RKCE_AES_VER_AES256_FLAG_SHIFT (18U) +#define RKCE_AES_VER_AES256_FLAG_MASK (0x1U << RKCE_AES_VER_AES256_FLAG_SHIFT) +#define RKCE_AES_VER_LOCKSTEP_FLAG_SHIFT (20U) +#define RKCE_AES_VER_LOCKSTEP_FLAG_MASK (0x1U << RKCE_AES_VER_LOCKSTEP_FLAG_SHIFT) +#define RKCE_AES_VER_SECURE_FLAG_SHIFT (21U) +#define RKCE_AES_VER_SECURE_FLAG_MASK (0x1U << RKCE_AES_VER_SECURE_FLAG_SHIFT) +/* DES_VER */ +#define RKCE_DES_VER_OFFSET (0x684U) +#define RKCE_DES_VER_ECB_FLAG_SHIFT (0U) +#define RKCE_DES_VER_ECB_FLAG_MASK (0x1U << RKCE_DES_VER_ECB_FLAG_SHIFT) +#define RKCE_DES_VER_CBC_FLAG_SHIFT (1U) +#define RKCE_DES_VER_CBC_FLAG_MASK (0x1U << RKCE_DES_VER_CBC_FLAG_SHIFT) +#define RKCE_DES_VER_CFB_FLAG_SHIFT (4U) +#define RKCE_DES_VER_CFB_FLAG_MASK (0x1U << RKCE_DES_VER_CFB_FLAG_SHIFT) +#define RKCE_DES_VER_OFB_FLAG_SHIFT (5U) +#define RKCE_DES_VER_OFB_FLAG_MASK (0x1U << RKCE_DES_VER_OFB_FLAG_SHIFT) +#define RKCE_DES_VER_TDES_FLAG_SHIFT (16U) +#define RKCE_DES_VER_TDES_FLAG_MASK (0x1U << RKCE_DES_VER_TDES_FLAG_SHIFT) +#define RKCE_DES_VER_EEE_FLAG_SHIFT (17U) +#define RKCE_DES_VER_EEE_FLAG_MASK (0x1U << RKCE_DES_VER_EEE_FLAG_SHIFT) +#define RKCE_DES_VER_EDE_FLAG_SHIFT (18U) +#define RKCE_DES_VER_EDE_FLAG_MASK (0x1U << RKCE_DES_VER_EDE_FLAG_SHIFT) +#define RKCE_DES_VER_LOCKSTEP_FLAG_SHIFT (20U) +#define RKCE_DES_VER_LOCKSTEP_FLAG_MASK (0x1U << RKCE_DES_VER_LOCKSTEP_FLAG_SHIFT) +#define RKCE_DES_VER_SECURE_FLAG_SHIFT (21U) +#define RKCE_DES_VER_SECURE_FLAG_MASK (0x1U << RKCE_DES_VER_SECURE_FLAG_SHIFT) +/* SM4_VER */ +#define RKCE_SM4_VER_OFFSET (0x688U) +#define RKCE_SM4_VER_ECB_FLAG_SHIFT (0U) +#define RKCE_SM4_VER_ECB_FLAG_MASK (0x1U << RKCE_SM4_VER_ECB_FLAG_SHIFT) +#define RKCE_SM4_VER_CBC_FLAG_SHIFT (1U) +#define RKCE_SM4_VER_CBC_FLAG_MASK (0x1U << RKCE_SM4_VER_CBC_FLAG_SHIFT) +#define RKCE_SM4_VER_CTS_FLAG_SHIFT (2U) +#define RKCE_SM4_VER_CTS_FLAG_MASK (0x1U << RKCE_SM4_VER_CTS_FLAG_SHIFT) +#define RKCE_SM4_VER_CTR_FLAG_SHIFT (3U) +#define RKCE_SM4_VER_CTR_FLAG_MASK (0x1U << RKCE_SM4_VER_CTR_FLAG_SHIFT) +#define RKCE_SM4_VER_CFB_FLAG_SHIFT (4U) +#define RKCE_SM4_VER_CFB_FLAG_MASK (0x1U << RKCE_SM4_VER_CFB_FLAG_SHIFT) +#define RKCE_SM4_VER_OFB_FLAG_SHIFT (5U) +#define RKCE_SM4_VER_OFB_FLAG_MASK (0x1U << RKCE_SM4_VER_OFB_FLAG_SHIFT) +#define RKCE_SM4_VER_XTS_FLAG_SHIFT (6U) +#define RKCE_SM4_VER_XTS_FLAG_MASK (0x1U << RKCE_SM4_VER_XTS_FLAG_SHIFT) +#define RKCE_SM4_VER_CCM_FLAG_SHIFT (7U) +#define RKCE_SM4_VER_CCM_FLAG_MASK (0x1U << RKCE_SM4_VER_CCM_FLAG_SHIFT) +#define RKCE_SM4_VER_GCM_FLAG_SHIFT (8U) +#define RKCE_SM4_VER_GCM_FLAG_MASK (0x1U << RKCE_SM4_VER_GCM_FLAG_SHIFT) +#define RKCE_SM4_VER_CMAC_FLAG_SHIFT (9U) +#define RKCE_SM4_VER_CMAC_FLAG_MASK (0x1U << RKCE_SM4_VER_CMAC_FLAG_SHIFT) +#define RKCE_SM4_VER_CBC_MAC_FLAG_SHIFT (10U) +#define RKCE_SM4_VER_CBC_MAC_FLAG_MASK (0x1U << RKCE_SM4_VER_CBC_MAC_FLAG_SHIFT) +#define RKCE_SM4_VER_LOCKSTEP_FLAG_SHIFT (20U) +#define RKCE_SM4_VER_LOCKSTEP_FLAG_MASK (0x1U << RKCE_SM4_VER_LOCKSTEP_FLAG_SHIFT) +#define RKCE_SM4_VER_SECURE_FLAG_SHIFT (21U) +#define RKCE_SM4_VER_SECURE_FLAG_MASK (0x1U << RKCE_SM4_VER_SECURE_FLAG_SHIFT) +/* HASH_VER */ +#define RKCE_HASH_VER_OFFSET (0x68CU) +#define RKCE_HASH_VER_SHA1_FLAG_SHIFT (0U) +#define RKCE_HASH_VER_SHA1_FLAG_MASK (0x1U << RKCE_HASH_VER_SHA1_FLAG_SHIFT) +#define RKCE_HASH_VER_SHA224_FLAG_SHIFT (1U) +#define RKCE_HASH_VER_SHA224_FLAG_MASK (0x1U << RKCE_HASH_VER_SHA224_FLAG_SHIFT) +#define RKCE_HASH_VER_SHA256_FLAG_SHIFT (2U) +#define RKCE_HASH_VER_SHA256_FLAG_MASK (0x1U << RKCE_HASH_VER_SHA256_FLAG_SHIFT) +#define RKCE_HASH_VER_SHA384_FLAG_SHIFT (3U) +#define RKCE_HASH_VER_SHA384_FLAG_MASK (0x1U << RKCE_HASH_VER_SHA384_FLAG_SHIFT) +#define RKCE_HASH_VER_SHA512_FLAG_SHIFT (4U) +#define RKCE_HASH_VER_SHA512_FLAG_MASK (0x1U << RKCE_HASH_VER_SHA512_FLAG_SHIFT) +#define RKCE_HASH_VER_SHA512_224_FLAG_SHIFT (5U) +#define RKCE_HASH_VER_SHA512_224_FLAG_MASK (0x1U << RKCE_HASH_VER_SHA512_224_FLAG_SHIFT) +#define RKCE_HASH_VER_SHA512_256_FLAG_SHIFT (6U) +#define RKCE_HASH_VER_SHA512_256_FLAG_MASK (0x1U << RKCE_HASH_VER_SHA512_256_FLAG_SHIFT) +#define RKCE_HASH_VER_MD5_FLAG_SHIFT (7U) +#define RKCE_HASH_VER_MD5_FLAG_MASK (0x1U << RKCE_HASH_VER_MD5_FLAG_SHIFT) +#define RKCE_HASH_VER_SM3_FLAG_SHIFT (8U) +#define RKCE_HASH_VER_SM3_FLAG_MASK (0x1U << RKCE_HASH_VER_SM3_FLAG_SHIFT) +#define RKCE_HASH_VER_LOCKSTEP_FLAG_SHIFT (20U) +#define RKCE_HASH_VER_LOCKSTEP_FLAG_MASK (0x1U << RKCE_HASH_VER_LOCKSTEP_FLAG_SHIFT) +/* HMAC_VER */ +#define RKCE_HMAC_VER_OFFSET (0x690U) +#define RKCE_HMAC_VER_SHA1_FLAG_SHIFT (0U) +#define RKCE_HMAC_VER_SHA1_FLAG_MASK (0x1U << RKCE_HMAC_VER_SHA1_FLAG_SHIFT) +#define RKCE_HMAC_VER_SHA256_FLAG_SHIFT (1U) +#define RKCE_HMAC_VER_SHA256_FLAG_MASK (0x1U << RKCE_HMAC_VER_SHA256_FLAG_SHIFT) +#define RKCE_HMAC_VER_SHA512_FLAG_SHIFT (2U) +#define RKCE_HMAC_VER_SHA512_FLAG_MASK (0x1U << RKCE_HMAC_VER_SHA512_FLAG_SHIFT) +#define RKCE_HMAC_VER_MD5_FLAG_SHIFT (3U) +#define RKCE_HMAC_VER_MD5_FLAG_MASK (0x1U << RKCE_HMAC_VER_MD5_FLAG_SHIFT) +#define RKCE_HMAC_VER_SM3_FLAG_SHIFT (4U) +#define RKCE_HMAC_VER_SM3_FLAG_MASK (0x1U << RKCE_HMAC_VER_SM3_FLAG_SHIFT) +#define RKCE_HMAC_VER_LOCKSTEP_FLAG_SHIFT (20U) +#define RKCE_HMAC_VER_LOCKSTEP_FLAG_MASK (0x1U << RKCE_HMAC_VER_LOCKSTEP_FLAG_SHIFT) +/* PKA_VER */ +#define RKCE_PKA_VER_OFFSET (0x698U) +/* EXTRA_FEATURE */ +#define RKCE_EXTRA_FEATURE_OFFSET (0x69CU) +#define RKCE_EXTRA_FEATURE_AXI_EXPAND_BIT_SHIFT (0U) +#define RKCE_EXTRA_FEATURE_AXI_EXPAND_BIT_MASK (0xFU << RKCE_EXTRA_FEATURE_AXI_EXPAND_BIT_SHIFT) +/* CE_VER */ +#define RKCE_CE_VER_OFFSET (0x6F0U) +/* PKA_MEM_MAP0 */ +#define RKCE_PKA_MEM_MAP0_OFFSET (0x800U) +#define RKCE_MAP_REG_NUM (32) +/* PKA_OPCODE */ +#define RKCE_PKA_OPCODE_OFFSET (0x880U) +#define RKCE_PKA_OPCODE_TAG_SHIFT (0U) +#define RKCE_PKA_OPCODE_TAG_MASK (0x3FU << RKCE_PKA_OPCODE_TAG_SHIFT) +#define RKCE_PKA_OPCODE_REG_R_SHIFT (6U) +#define RKCE_PKA_OPCODE_REG_R_MASK (0x3FU << RKCE_PKA_OPCODE_REG_R_SHIFT) +#define RKCE_PKA_OPCODE_R_DIS_SHIFT (11U) +#define RKCE_PKA_OPCODE_REG_B_SHIFT (12U) +#define RKCE_PKA_OPCODE_REG_B_MASK (0x3FU << RKCE_PKA_OPCODE_REG_B_SHIFT) +#define RKCE_PKA_OPCODE_B_IMMED_SHIFT (17U) +#define RKCE_PKA_OPCODE_REG_A_SHIFT (18U) +#define RKCE_PKA_OPCODE_REG_A_MASK (0x3FU << RKCE_PKA_OPCODE_REG_A_SHIFT) +#define RKCE_PKA_OPCODE_A_IMMED_SHIFT (23U) +#define RKCE_PKA_OPCODE_LEN_SHIFT (24U) +#define RKCE_PKA_OPCODE_LEN_MASK (0x7U << RKCE_PKA_OPCODE_LEN_SHIFT) +#define RKCE_PKA_OPCODE_OPCODE_SHIFT (27U) +#define RKCE_PKA_OPCODE_OPCODE_MASK (0x1FU << RKCE_PKA_OPCODE_OPCODE_SHIFT) +/* N_NP_T0_T1_ADDR */ +#define RKCE_N_NP_T0_T1_ADDR_OFFSET (0x884U) +#define RKCE_N_NP_T0_T1_ADDR_REG_N_SHIFT (0U) +#define RKCE_N_NP_T0_T1_ADDR_REG_N_MASK (0x1FU << RKCE_N_NP_T0_T1_ADDR_REG_N_SHIFT) +#define RKCE_N_NP_T0_T1_ADDR_REG_NP_SHIFT (5U) +#define RKCE_N_NP_T0_T1_ADDR_REG_NP_MASK (0x1FU << RKCE_N_NP_T0_T1_ADDR_REG_NP_SHIFT) +#define RKCE_N_NP_T0_T1_ADDR_REG_T0_SHIFT (10U) +#define RKCE_N_NP_T0_T1_ADDR_REG_T0_MASK (0x1FU << RKCE_N_NP_T0_T1_ADDR_REG_T0_SHIFT) +#define RKCE_N_NP_T0_T1_ADDR_REG_T1_SHIFT (15U) +#define RKCE_N_NP_T0_T1_ADDR_REG_T1_MASK (0x1FU << RKCE_N_NP_T0_T1_ADDR_REG_T1_SHIFT) +/* PKA_STATUS */ +#define RKCE_PKA_STATUS_OFFSET (0x888U) +#define RKCE_PKA_STATUS (0x1U) +#define RKCE_PKA_STATUS_PIPE_IS_BUSY_SHIFT (0U) +#define RKCE_PKA_STATUS_PIPE_IS_BUSY_MASK (0x1U << RKCE_PKA_STATUS_PIPE_IS_BUSY_SHIFT) +#define RKCE_PKA_STATUS_PKA_BUSY_SHIFT (1U) +#define RKCE_PKA_STATUS_PKA_BUSY_MASK (0x1U << RKCE_PKA_STATUS_PKA_BUSY_SHIFT) +#define RKCE_PKA_STATUS_ALU_OUT_ZERO_SHIFT (2U) +#define RKCE_PKA_STATUS_ALU_OUT_ZERO_MASK (0x1U << RKCE_PKA_STATUS_ALU_OUT_ZERO_SHIFT) +#define RKCE_PKA_STATUS_ALU_MOD_OVFLW_SHIFT (3U) +#define RKCE_PKA_STATUS_ALU_MOD_OVFLW_MASK (0x1U << RKCE_PKA_STATUS_ALU_MOD_OVFLW_SHIFT) +#define RKCE_PKA_STATUS_DIV_BY_ZERO_SHIFT (4U) +#define RKCE_PKA_STATUS_DIV_BY_ZERO_MASK (0x1U << RKCE_PKA_STATUS_DIV_BY_ZERO_SHIFT) +#define RKCE_PKA_STATUS_ALU_CARRY_SHIFT (5U) +#define RKCE_PKA_STATUS_ALU_CARRY_MASK (0x1U << RKCE_PKA_STATUS_ALU_CARRY_SHIFT) +#define RKCE_PKA_STATUS_ALU_SIGN_OUT_SHIFT (6U) +#define RKCE_PKA_STATUS_ALU_SIGN_OUT_MASK (0x1U << RKCE_PKA_STATUS_ALU_SIGN_OUT_SHIFT) +#define RKCE_PKA_STATUS_MODINV_OF_ZERO_SHIFT (7U) +#define RKCE_PKA_STATUS_MODINV_OF_ZERO_MASK (0x1U << RKCE_PKA_STATUS_MODINV_OF_ZERO_SHIFT) +#define RKCE_PKA_STATUS_PKA_CPU_BUSY_SHIFT (8U) +#define RKCE_PKA_STATUS_PKA_CPU_BUSY_MASK (0x1U << RKCE_PKA_STATUS_PKA_CPU_BUSY_SHIFT) +#define RKCE_PKA_STATUS_OPCODE_SHIFT (9U) +#define RKCE_PKA_STATUS_OPCODE_MASK (0x1FU << RKCE_PKA_STATUS_OPCODE_SHIFT) +#define RKCE_PKA_STATUS_TAG_SHIFT (14U) +#define RKCE_PKA_STATUS_TAG_MASK (0x3FU << RKCE_PKA_STATUS_TAG_SHIFT) +/* PKA_L0 */ +#define RKCE_PKA_L0_OFFSET (0x890U) +#define RKCE_LEN_REG_NUM (8) +/* PKA_PIPE_RDY */ +#define RKCE_PKA_PIPE_RDY_OFFSET (0x8B0U) +#define RKCE_PKA_PIPE_RDY (0x1U) +#define RKCE_PKA_PIPE_RDY_PKA_PIPE_RDY_SHIFT (0U) +#define RKCE_PKA_PIPE_RDY_PKA_PIPE_RDY_MASK (0x1U << RKCE_PKA_PIPE_RDY_PKA_PIPE_RDY_SHIFT) +/* PKA_DONE */ +#define RKCE_PKA_DONE_OFFSET (0x8B4U) +#define RKCE_PKA_DONE (0x1U) +#define RKCE_PKA_DONE_PKA_DONE_SHIFT (0U) +#define RKCE_PKA_DONE_PKA_DONE_MASK (0x1U << RKCE_PKA_DONE_PKA_DONE_SHIFT) +/* PKA_INT_ENA */ +#define RKCE_PKA_INT_ENA_OFFSET (0x8D4U) +#define RKCE_PKA_INT_ENA_PKA_INT_ENA_SHIFT (0U) +#define RKCE_PKA_INT_ENA_PKA_INT_ENA_MASK (0x1U << RKCE_PKA_INT_ENA_PKA_INT_ENA_SHIFT) +/* PKA_INT_ST */ +#define RKCE_PKA_INT_ST_OFFSET (0x8D8U) +#define RKCE_PKA_INT_ST_PKA_INT_ST_SHIFT (0U) +#define RKCE_PKA_INT_ST_PKA_INT_ST_MASK (0x1U << RKCE_PKA_INT_ST_PKA_INT_ST_SHIFT) +/* TD0_TD1_TX_ADDR */ +#define RKCE_TD0_TD1_TX_ADDR_OFFSET (0x8DCU) +#define RKCE_TD0_TD1_TX_ADDR_REG_TD0_SHIFT (0U) +#define RKCE_TD0_TD1_TX_ADDR_REG_TD0_MASK (0x1FU << RKCE_TD0_TD1_TX_ADDR_REG_TD0_SHIFT) +#define RKCE_TD0_TD1_TX_ADDR_REG_TD1_SHIFT (5U) +#define RKCE_TD0_TD1_TX_ADDR_REG_TD1_MASK (0x1FU << RKCE_TD0_TD1_TX_ADDR_REG_TD1_SHIFT) +#define RKCE_TD0_TD1_TX_ADDR_REG_TX_SHIFT (10U) +#define RKCE_TD0_TD1_TX_ADDR_REG_TX_MASK (0x1FU << RKCE_TD0_TD1_TX_ADDR_REG_TX_SHIFT) +#define RKCE_TD0_TD1_TX_ADDR_PKA_ASCA_EN_SHIFT (31U) +#define RKCE_TD0_TD1_TX_ADDR_PKA_ASCA_EN_MASK (0x1U << RKCE_TD0_TD1_TX_ADDR_PKA_ASCA_EN_SHIFT) +/* SRAM_ADDR */ +#define RKCE_SRAM_ADDR_OFFSET (0x1000U) +#define RKCE_SRAM_ADDR_SRAM_ADDR_SHIFT (0U) +#define RKCE_SRAM_ADDR_SRAM_ADDR_MASK (0xFFFFFFFFU << RKCE_SRAM_ADDR_SRAM_ADDR_SHIFT) + +#define RKCE_SRAM_SIZE (0x1000U) + +#endif /* __RKCE_REG_H */ diff --git a/u-boot/include/spl.h b/u-boot/include/spl.h index fcf0e093be0..5b7d9e9c3d0 100644 --- a/u-boot/include/spl.h +++ b/u-boot/include/spl.h @@ -78,6 +78,7 @@ int spl_load_simple_fit(struct spl_image_info *spl_image, struct spl_load_info *info, ulong sector, void *fdt); #define SPL_COPY_PAYLOAD_ONLY 1 +#define SPL_ATF_AARCH32_BL33 BIT(31) /* SPL common functions */ void preloader_console_init(void); diff --git a/u-boot/lib/fdtdec.c b/u-boot/lib/fdtdec.c index 2487af36b84..4e1402c00cb 100644 --- a/u-boot/lib/fdtdec.c +++ b/u-boot/lib/fdtdec.c @@ -173,11 +173,17 @@ fdt_addr_t fdtdec_get_addr_size_auto_noparent(const void *blob, int node, fdt_addr_t fdtdec_get_addr_size(const void *blob, int node, const char *prop_name, fdt_size_t *sizep) { +#ifdef CONFIG_OF_ADDR_SIZE_AUTO_NOPARENT + /* In case of 64-bit U-Boot use 32-bit platform dtb */ + return fdtdec_get_addr_size_auto_noparent(blob, node, prop_name, + 0, sizep, false); +#else int ns = sizep ? (sizeof(fdt_size_t) / sizeof(fdt32_t)) : 0; return fdtdec_get_addr_size_fixed(blob, node, prop_name, 0, sizeof(fdt_addr_t) / sizeof(fdt32_t), ns, sizep, false); +#endif } fdt_addr_t fdtdec_get_addr(const void *blob, int node, diff --git a/u-boot/lib/libxbc/libxbc.c b/u-boot/lib/libxbc/libxbc.c index 6e47dee6773..0a6daf576c4 100644 --- a/u-boot/lib/libxbc/libxbc.c +++ b/u-boot/lib/libxbc/libxbc.c @@ -45,7 +45,7 @@ static uint32_t checksum(const unsigned char* const buffer, uint32_t size) { * the trailer is present, it will be directly preceding this address. * @return true if the trailer is present, false if not. */ -static bool isTrailerPresent(uint64_t bootconfig_end_addr) { +static bool isTrailerPresent(ulong bootconfig_end_addr) { return !strncmp((char*)(bootconfig_end_addr - BOOTCONFIG_MAGIC_SIZE), BOOTCONFIG_MAGIC, BOOTCONFIG_MAGIC_SIZE); } @@ -54,7 +54,7 @@ static bool isTrailerPresent(uint64_t bootconfig_end_addr) { * Add a string of boot config parameters to memory appended by the trailer. */ int32_t addBootConfigParameters(char* params, uint32_t params_size, - uint64_t bootconfig_start_addr, uint32_t bootconfig_size) { + ulong bootconfig_start_addr, uint32_t bootconfig_size) { if (!params || !bootconfig_start_addr) { return -1; } @@ -63,7 +63,7 @@ int32_t addBootConfigParameters(char* params, uint32_t params_size, } int32_t applied_bytes = 0; int32_t new_size = 0; - uint64_t end = bootconfig_start_addr + bootconfig_size; + ulong end = bootconfig_start_addr + bootconfig_size; if (isTrailerPresent(end)) { end -= BOOTCONFIG_TRAILER_SIZE; @@ -86,7 +86,7 @@ int32_t addBootConfigParameters(char* params, uint32_t params_size, /* * Add boot config trailer. */ -int32_t addBootConfigTrailer(uint64_t bootconfig_start_addr, +int32_t addBootConfigTrailer(ulong bootconfig_start_addr, uint32_t bootconfig_size) { if (!bootconfig_start_addr) { return -1; @@ -94,7 +94,7 @@ int32_t addBootConfigTrailer(uint64_t bootconfig_start_addr, if (bootconfig_size == 0) { return 0; } - uint64_t end = bootconfig_start_addr + bootconfig_size; + ulong end = bootconfig_start_addr + bootconfig_size; if (isTrailerPresent(end)) { // no need to overwrite the current trailers diff --git a/u-boot/lib/libxbc/libxbc.h b/u-boot/lib/libxbc/libxbc.h index 0bee54873a1..3031117766a 100644 --- a/u-boot/lib/libxbc/libxbc.h +++ b/u-boot/lib/libxbc/libxbc.h @@ -36,7 +36,7 @@ * @return number of bytes added to the boot config section. -1 for error. */ int addBootConfigParameters(char *params, uint32_t params_size, - uint64_t bootconfig_start_addr, + ulong bootconfig_start_addr, uint32_t bootconfig_size); /* @@ -53,7 +53,7 @@ int addBootConfigParameters(char *params, uint32_t params_size, * @param bootconfig_size size of the current bootconfig section in bytes. * @return number of bytes added to the boot config section. -1 for error. */ -int addBootConfigTrailer(uint64_t bootconfig_start_addr, +int addBootConfigTrailer(ulong bootconfig_start_addr, uint32_t bootconfig_size); #endif /* LIBXBC_H_ */ diff --git a/u-boot/lib/optee_clientApi/OpteeClientInterface.c b/u-boot/lib/optee_clientApi/OpteeClientInterface.c index 230bdeff5d2..709972c34b7 100644 --- a/u-boot/lib/optee_clientApi/OpteeClientInterface.c +++ b/u-boot/lib/optee_clientApi/OpteeClientInterface.c @@ -38,8 +38,12 @@ #define STORAGE_CMD_WRITE_ESCK_KEY 27 #define STORAGE_CMD_ESCK_KEY_IS_WRITTEN 28 #define STORAGE_CMD_SET_ESCK_KEY_MASK 29 +#define STORAGE_CMD_WRITE_FW_ENCRYPT_KEY 30 +#define STORAGE_CMD_FW_ENCRYPT_KEY_IS_WRITTEN 31 +#define STORAGE_CMD_SET_FW_ENCRYPT_KEY_MASK 32 #define CRYPTO_SERVICE_CMD_OEM_OTP_KEY_PHYS_CIPHER 0x00000002 +#define CRYPTO_SERVICE_CMD_FW_KEY_PHYS_CIPHER 0x00000007 #define RK_CRYPTO_SERVICE_UUID { 0x0cacdb5d, 0x4fea, 0x466c, \ { 0x97, 0x16, 0x3d, 0x54, 0x16, 0x52, 0x83, 0x0f } } @@ -1553,6 +1557,174 @@ exit: return TeecResult; } +uint32_t trusty_write_fw_encrypt_key(enum RK_FW_KEYID key_id, + uint8_t *byte_buf, uint32_t byte_len) +{ + TEEC_Result TeecResult; + TEEC_Context TeecContext; + TEEC_Session TeecSession; + uint32_t ErrorOrigin; + + TEEC_UUID tempuuid = { 0x2d26d8a8, 0x5134, 0x4dd8, + { 0xb3, 0x2f, 0xb3, 0x4b, 0xce, 0xeb, 0xc4, 0x71 } }; + TEEC_UUID *TeecUuid = &tempuuid; + TEEC_Operation TeecOperation = {0}; + + TeecResult = OpteeClientApiLibInitialize(); + if (TeecResult != TEEC_SUCCESS) + return TeecResult; + + TeecResult = TEEC_InitializeContext(NULL, &TeecContext); + if (TeecResult != TEEC_SUCCESS) + return TeecResult; + + TeecResult = TEEC_OpenSession(&TeecContext, + &TeecSession, + TeecUuid, + TEEC_LOGIN_PUBLIC, + NULL, + NULL, + &ErrorOrigin); + if (TeecResult != TEEC_SUCCESS) + return TeecResult; + + TeecOperation.params[0].value.a = key_id; + + TEEC_SharedMemory SharedMem = {0}; + + SharedMem.size = byte_len; + SharedMem.flags = 0; + + TeecResult = TEEC_AllocateSharedMemory(&TeecContext, &SharedMem); + if (TeecResult != TEEC_SUCCESS) + goto exit; + + TeecOperation.params[1].tmpref.buffer = SharedMem.buffer; + TeecOperation.params[1].tmpref.size = SharedMem.size; + + memcpy(SharedMem.buffer, byte_buf, SharedMem.size); + TeecOperation.paramTypes = TEEC_PARAM_TYPES(TEEC_VALUE_INPUT, + TEEC_MEMREF_TEMP_INPUT, + TEEC_NONE, + TEEC_NONE); + + TeecResult = TEEC_InvokeCommand(&TeecSession, + STORAGE_CMD_WRITE_FW_ENCRYPT_KEY, + &TeecOperation, + &ErrorOrigin); + if (TeecResult != TEEC_SUCCESS) + goto exit; + +exit: + TEEC_ReleaseSharedMemory(&SharedMem); + TEEC_CloseSession(&TeecSession); + TEEC_FinalizeContext(&TeecContext); + + return TeecResult; +} + +uint32_t trusty_fw_encrypt_key_is_written(enum RK_FW_KEYID key_id, uint8_t *value) +{ + TEEC_Result TeecResult; + TEEC_Context TeecContext; + TEEC_Session TeecSession; + uint32_t ErrorOrigin; + + *value = 0xFF; + + TEEC_UUID tempuuid = { 0x2d26d8a8, 0x5134, 0x4dd8, + { 0xb3, 0x2f, 0xb3, 0x4b, 0xce, 0xeb, 0xc4, 0x71 } }; + TEEC_UUID *TeecUuid = &tempuuid; + TEEC_Operation TeecOperation = {0}; + + TeecResult = OpteeClientApiLibInitialize(); + if (TeecResult != TEEC_SUCCESS) + return TeecResult; + + TeecResult = TEEC_InitializeContext(NULL, &TeecContext); + if (TeecResult != TEEC_SUCCESS) + return TeecResult; + + TeecResult = TEEC_OpenSession(&TeecContext, + &TeecSession, + TeecUuid, + TEEC_LOGIN_PUBLIC, + NULL, + NULL, + &ErrorOrigin); + if (TeecResult != TEEC_SUCCESS) + return TeecResult; + + TeecOperation.params[0].value.a = key_id; + + TeecOperation.paramTypes = TEEC_PARAM_TYPES(TEEC_VALUE_INOUT, + TEEC_NONE, + TEEC_NONE, + TEEC_NONE); + + TeecResult = TEEC_InvokeCommand(&TeecSession, + STORAGE_CMD_FW_ENCRYPT_KEY_IS_WRITTEN, + &TeecOperation, + &ErrorOrigin); + if (TeecResult == TEEC_SUCCESS) + *value = TeecOperation.params[0].value.b; + + TEEC_CloseSession(&TeecSession); + TEEC_FinalizeContext(&TeecContext); + + return TeecResult; +} + +uint32_t trusty_set_fw_encrypt_key_mask(enum RK_FW_KEYID key_id) +{ + TEEC_Result TeecResult; + TEEC_Context TeecContext; + TEEC_Session TeecSession; + uint32_t ErrorOrigin; + + TEEC_UUID tempuuid = { 0x2d26d8a8, 0x5134, 0x4dd8, + { 0xb3, 0x2f, 0xb3, 0x4b, 0xce, 0xeb, 0xc4, 0x71 } }; + TEEC_UUID *TeecUuid = &tempuuid; + TEEC_Operation TeecOperation = {0}; + + TeecResult = OpteeClientApiLibInitialize(); + if (TeecResult != TEEC_SUCCESS) + return TeecResult; + + TeecResult = TEEC_InitializeContext(NULL, &TeecContext); + if (TeecResult != TEEC_SUCCESS) + return TeecResult; + + TeecResult = TEEC_OpenSession(&TeecContext, + &TeecSession, + TeecUuid, + TEEC_LOGIN_PUBLIC, + NULL, + NULL, + &ErrorOrigin); + if (TeecResult != TEEC_SUCCESS) + return TeecResult; + + TeecOperation.params[0].value.a = key_id; + + TeecOperation.paramTypes = TEEC_PARAM_TYPES(TEEC_VALUE_INPUT, + TEEC_NONE, + TEEC_NONE, + TEEC_NONE); + + TeecResult = TEEC_InvokeCommand(&TeecSession, + STORAGE_CMD_SET_FW_ENCRYPT_KEY_MASK, + &TeecOperation, + &ErrorOrigin); + if (TeecResult != TEEC_SUCCESS) + goto exit; + +exit: + TEEC_CloseSession(&TeecSession); + TEEC_FinalizeContext(&TeecContext); + + return TeecResult; +} uint32_t trusty_oem_user_ta_transfer(void) { TEEC_Result TeecResult; @@ -2061,3 +2233,95 @@ exit: return TeecResult; } + +uint32_t trusty_fw_key_cipher(enum RK_FW_KEYID key_id, rk_cipher_config *config, + uint32_t src_phys_addr, uint32_t dst_phys_addr, + uint32_t len) +{ + TEEC_Result TeecResult; + TEEC_Context TeecContext; + TEEC_Session TeecSession; + TEEC_Operation TeecOperation = {0}; + uint32_t ErrorOrigin; + TEEC_UUID uuid = RK_CRYPTO_SERVICE_UUID; + TEEC_SharedMemory SharedMem_config = {0}; + + if (key_id != RK_FW_KEY0) + return TEEC_ERROR_BAD_PARAMETERS; + + if (!config) + return TEEC_ERROR_BAD_PARAMETERS; + + if (config->algo != RK_ALGO_AES && config->algo != RK_ALGO_SM4) + return TEEC_ERROR_BAD_PARAMETERS; + + if (config->mode >= RK_CIPHER_MODE_XTS) + return TEEC_ERROR_BAD_PARAMETERS; + + if (config->operation != RK_MODE_ENCRYPT && + config->operation != RK_MODE_DECRYPT) + return TEEC_ERROR_BAD_PARAMETERS; + + if (config->key_len != 16 && + config->key_len != 24 && + config->key_len != 32) + return TEEC_ERROR_BAD_PARAMETERS; + + if (len % AES_BLOCK_SIZE || len == 0) + return TEEC_ERROR_BAD_PARAMETERS; + + if (!src_phys_addr || !dst_phys_addr) + return TEEC_ERROR_BAD_PARAMETERS; + + TeecResult = OpteeClientApiLibInitialize(); + if (TeecResult != TEEC_SUCCESS) + return TeecResult; + + TeecResult = TEEC_InitializeContext(NULL, &TeecContext); + if (TeecResult != TEEC_SUCCESS) + return TeecResult; + + TeecResult = TEEC_OpenSession(&TeecContext, + &TeecSession, + &uuid, + TEEC_LOGIN_PUBLIC, + NULL, + NULL, + &ErrorOrigin); + if (TeecResult != TEEC_SUCCESS) + goto exit; + + SharedMem_config.size = sizeof(rk_cipher_config); + TeecResult = TEEC_AllocateSharedMemory(&TeecContext, &SharedMem_config); + if (TeecResult != TEEC_SUCCESS) + goto exit; + + memcpy(SharedMem_config.buffer, config, sizeof(rk_cipher_config)); + TeecOperation.params[0].value.a = key_id; + TeecOperation.params[1].tmpref.buffer = SharedMem_config.buffer; + TeecOperation.params[1].tmpref.size = SharedMem_config.size; + TeecOperation.params[2].value.a = src_phys_addr; + TeecOperation.params[2].value.b = len; + TeecOperation.params[3].value.a = dst_phys_addr; + TeecOperation.paramTypes = TEEC_PARAM_TYPES(TEEC_VALUE_INPUT, + TEEC_MEMREF_TEMP_INPUT, + TEEC_VALUE_INPUT, + TEEC_VALUE_INPUT); + + crypto_flush_cacheline(src_phys_addr, len); + crypto_flush_cacheline(dst_phys_addr, len); + + TeecResult = TEEC_InvokeCommand(&TeecSession, + CRYPTO_SERVICE_CMD_FW_KEY_PHYS_CIPHER, + &TeecOperation, + &ErrorOrigin); + + crypto_invalidate_cacheline(dst_phys_addr, len); + +exit: + TEEC_ReleaseSharedMemory(&SharedMem_config); + TEEC_CloseSession(&TeecSession); + TEEC_FinalizeContext(&TeecContext); + return TeecResult; +} + diff --git a/u-boot/lib/optee_clientApi/OpteeClientRkNewFs_v2.c b/u-boot/lib/optee_clientApi/OpteeClientRkNewFs_v2.c index d204a318913..16a586e86da 100644 --- a/u-boot/lib/optee_clientApi/OpteeClientRkNewFs_v2.c +++ b/u-boot/lib/optee_clientApi/OpteeClientRkNewFs_v2.c @@ -83,13 +83,18 @@ #define RKSS_BACKUP_NUM 2 #define RKSS_TAG 0x524B5353 +#define SYNC_NONE 0 +#define SYNC_DOING 1 +#define SYNC_DONE 2 + struct rkss_file_header { uint32_t tag; uint32_t version; uint32_t backup_count; uint16_t backup_index; uint16_t backup_dirty; - uint8_t reserve[496]; + uint16_t sync_flag; + uint8_t reserve[494]; }; struct rkss_file_table { uint32_t size; @@ -717,6 +722,13 @@ static int rkss_write_back_ptable( static int rkss_storage_write(void) { int ret, i; + int dirty_count = 0; + int dirty_num = 0; + + for (i = 0; i < RKSS_MAX_AREA_NUM; i++) { + if (rkss_info[i].header != NULL && rkss_info[i].header->backup_dirty == 1) + dirty_count++; + } for (i = 0; i < RKSS_MAX_AREA_NUM; i++) { if (rkss_info[i].header != NULL && rkss_info[i].header->backup_dirty == 1) { @@ -726,6 +738,14 @@ static int rkss_storage_write(void) if (rkss_info[i].header->backup_index >= RKSS_BACKUP_NUM) rkss_info[i].header->backup_index = 0; rkss_info[i].header->backup_dirty = 0; + dirty_num++; + rkss_info[i].header->sync_flag = SYNC_NONE; + if (dirty_count > 1) { + if (dirty_num == dirty_count) + rkss_info[i].header->sync_flag = SYNC_DONE; + else + rkss_info[i].header->sync_flag = SYNC_DOING; + } if (rkss_info[i].header->backup_count == 0xffffffff) { rkss_info[i].header->backup_count = 1; @@ -767,6 +787,31 @@ static int rkss_storage_write(void) return 0; } +static int rkss_storage_clean_sync(void) +{ + for (int i = 0; i < RKSS_MAX_AREA_NUM; i++) { + if (rkss_info[i].header != NULL && rkss_info[i].header->sync_flag != SYNC_NONE) { + rkss_info[i].header->backup_count++; + rkss_info[i].footer->backup_count = rkss_info[i].header->backup_count; + rkss_info[i].header->backup_index++; + if (rkss_info[i].header->backup_index >= RKSS_BACKUP_NUM) + rkss_info[i].header->backup_index = 0; + rkss_info[i].header->backup_dirty = 0; + rkss_info[i].header->sync_flag = SYNC_NONE; + + int ret = blk_dwrite(dev_desc, + part_info.start + i * RKSS_SECTION_COUNT * RKSS_BACKUP_NUM + + rkss_info[i].header->backup_index * RKSS_SECTION_COUNT, + RKSS_SECTION_COUNT, rkss_buffer[i]); + if (ret != RKSS_SECTION_COUNT) { + printf("blk_dwrite fail \n"); + return -1; + } + } + } + return 0; +} + static int rkss_storage_init(uint32_t area_index) { unsigned long ret = 0; @@ -870,6 +915,50 @@ static int rkss_storage_init(uint32_t area_index) return 0; } +static int rkss_check_sync_done(void) +{ + int ret; + + if (rkss_info[0].header->sync_flag == SYNC_DOING && + rkss_info[1].header->sync_flag != SYNC_DONE) { + //rkss_info[0] need rolled back + rkss_info[0].header->backup_index++; + if (rkss_info[0].header->backup_index >= RKSS_BACKUP_NUM) + rkss_info[0].header->backup_index = 0; + ret = blk_dread(dev_desc, + part_info.start + 0 * RKSS_SECTION_COUNT * RKSS_BACKUP_NUM + + rkss_info[0].header->backup_index * RKSS_SECTION_COUNT, + RKSS_SECTION_COUNT, rkss_buffer[0]); + if (ret != RKSS_SECTION_COUNT) { + printf("blk_dread fail! \n"); + return -1; + } + if ((rkss_info[0].header->tag != RKSS_TAG) || + (rkss_info[0].footer->backup_count != rkss_info[0].header->backup_count)) { + printf("check header fail! \n"); + return -1; + } + + rkss_info[0].header->backup_index++; + if (rkss_info[0].header->backup_index >= RKSS_BACKUP_NUM) + rkss_info[0].header->backup_index = 0; + ret = blk_dwrite(dev_desc, + part_info.start + 0 * RKSS_SECTION_COUNT * RKSS_BACKUP_NUM + + rkss_info[0].header->backup_index * RKSS_SECTION_COUNT, + RKSS_SECTION_COUNT, rkss_buffer[0]); + if (ret != RKSS_SECTION_COUNT) { + printf("blk_dwrite fail! \n"); + return -1; + } + } + ret = rkss_storage_clean_sync(); + if (ret) { + printf("clean sync flag fail! \n"); + return -1; + } + return 0; +} + static uint32_t ree_fs_new_open(size_t num_params, struct tee_ioctl_param *params) { @@ -1343,6 +1432,9 @@ int tee_supp_rk_fs_init_v2(void) return -1; } + if (rkss_check_sync_done() < 0) + return -1; + #ifdef DEBUG_RKSS rkss_dump_ptable(); rkss_dump_usedflags(); @@ -1384,6 +1476,8 @@ int tee_supp_rk_fs_process_v2(size_t num_params, case OPTEE_MRF_CLOSE: debug(">>>>>>> [%d] OPTEE_MRF_CLOSE!\n", rkss_step++); ret = ree_fs_new_close(num_params, params); + rkss_storage_write(); + rkss_storage_clean_sync(); break; case OPTEE_MRF_READ: debug(">>>>>>> [%d] OPTEE_MRF_READ!\n", rkss_step++); @@ -1400,10 +1494,14 @@ int tee_supp_rk_fs_process_v2(size_t num_params, case OPTEE_MRF_REMOVE: debug(">>>>>>> [%d] OPTEE_MRF_REMOVE!\n", rkss_step++); ret = ree_fs_new_remove(num_params, params); + rkss_storage_write(); + rkss_storage_clean_sync(); break; case OPTEE_MRF_RENAME: debug(">>>>>>> [%d] OPTEE_MRF_RENAME!\n", rkss_step++); ret = ree_fs_new_rename(num_params, params); + rkss_storage_write(); + rkss_storage_clean_sync(); break; case OPTEE_MRF_OPENDIR: debug(">>>>>>> [%d] OPTEE_MRF_OPENDIR!\n", rkss_step++); @@ -1421,6 +1519,5 @@ int tee_supp_rk_fs_process_v2(size_t num_params, ret = TEEC_ERROR_BAD_PARAMETERS; break; } - rkss_storage_write(); return ret; } diff --git a/u-boot/make.sh b/u-boot/make.sh index 4ffddc92a20..4648ed2a5ae 100755 --- a/u-boot/make.sh +++ b/u-boot/make.sh @@ -193,10 +193,12 @@ function process_args() shift 1 ;; --spl-fwver) + ARG_FIT_FWVER="${ARG_FIT_FWVER} --spl-fwver $2" ARG_SPL_FWVER="SPL_FWVER=$2" shift 2 ;; --fwver) + ARG_FIT_FWVER="${ARG_FIT_FWVER} --fwver $2" ARG_FWVER="FWVER=$2" shift 2 ;; @@ -557,8 +559,8 @@ function pack_uboot_itb_image() cp ${RKBIN}/${BL31_ELF} bl31.elf if grep BL32_OPTION -A 1 ${INI} | grep SEC=1 ; then cp ${RKBIN}/${BL32_BIN} tee.bin - TEE_OFFSET=`grep BL32_OPTION -A 3 ${INI} | grep ADDR= | awk -F "=" '{ printf $2 }' | tr -d '\r'` - TEE_ARG="-t ${TEE_OFFSET}" + TEE_ADDR=`grep BL32_OPTION -A 3 ${INI} | grep ADDR= | awk -F "=" '{ printf $2 }' | tr -d '\r'` + TEE_ARG="-t ${TEE_ADDR}" fi else # TOS @@ -572,14 +574,33 @@ function pack_uboot_itb_image() echo "WARN: No tee bin" fi if [ ! -z "${TOSTA}" -o ! -z "${TOS}" ]; then - TEE_OFFSET=`filt_val "ADDR" ${INI}` - if [ "${TEE_OFFSET}" == "" ]; then - TEE_OFFSET=0x8400000 + TEE_ADDR=`filt_val "ADDR" ${INI}` + if [ "${TEE_ADDR}" == "" ]; then + DRAM_BASE=`sed -n "/CONFIG_SYS_SDRAM_BASE=/s/CONFIG_SYS_SDRAM_BASE=//p" ${srctree}/include/autoconf.mk|tr -d '\r'` + TEE_ADDR="0x"$(echo "obase=16;$((DRAM_BASE+0x8400000))"|bc) fi - TEE_ARG="-t ${TEE_OFFSET}" + TEE_ARG="-t ${TEE_ADDR}" fi fi + # Inits + for ((i=0; i<5; i++)) + do + INIT_BIN="init${i}.bin" + INIT_IDX="INIT${i}" + ENABLED=`awk -F "," '/'${INIT_IDX}'=/ { printf $3 }' ${INI} | tr -d ' '` + if [ "${ENABLED}" == "enabled" -o "${ENABLED}" == "okay" ]; then + NAME=`awk -F "," '/'${INIT_IDX}'=/ { printf $1 }' ${INI} | tr -d ' ' | awk -F "=" '{ print $2 }'` + OFFS=`awk -F "," '/'${INIT_IDX}'=/ { printf $2 }' ${INI} | tr -d ' '` + cp ${RKBIN}/${NAME} ${INIT_BIN} + if [ -z ${OFFS} ]; then + echo "ERROR: No ${INIT_BIN} address in ${INI}" + exit 1 + fi + INIT_ARG=${INIT_ARG}" -i${i} ${OFFS}" + fi + done + # MCUs for ((i=0; i<5; i++)) do @@ -649,7 +670,7 @@ function pack_uboot_itb_image() if [[ ${SPL_FIT_GENERATOR} == *.py ]]; then ${SPL_FIT_GENERATOR} u-boot.dtb > u-boot.its else - ${SPL_FIT_GENERATOR} ${TEE_ARG} ${COMPRESSION_ARG} ${MCU_ARG} ${LOAD_ARG} > u-boot.its + ${SPL_FIT_GENERATOR} ${TEE_ARG} ${COMPRESSION_ARG} ${INIT_ARG} ${MCU_ARG} ${LOAD_ARG} > u-boot.its fi fi @@ -758,7 +779,7 @@ function pack_fit_image() function handle_args_late() { - ARG_LIST_FIT="${ARG_LIST_FIT} --ini-trust ${INI_TRUST} --ini-loader ${INI_LOADER}" + ARG_LIST_FIT="${ARG_LIST_FIT} --ini-trust ${INI_TRUST} --ini-loader ${INI_LOADER} ${ARG_FIT_FWVER}" } function clean_files() diff --git a/u-boot/scripts/fit-core.sh b/u-boot/scripts/fit-core.sh index dcdebe3bf2f..b2bc5dea6e3 100644 --- a/u-boot/scripts/fit-core.sh +++ b/u-boot/scripts/fit-core.sh @@ -17,6 +17,9 @@ SIG_BIN="data2sign.bin" SIG_UBOOT="${FIT_DIR}/uboot.data2sign" SIG_BOOT="${FIT_DIR}/boot.data2sign" SIG_RECOVERY="${FIT_DIR}/recovery.data2sign" +SIG_CFG_DIR="${FIT_DIR}/fit_signcfg" +SIG_CONFIG="${SIG_CFG_DIR}/sign.readonly_config" +MINIALL_INI="${SIG_CFG_DIR}/MINIALL.ini" # offs OFFS_DATA="0x1200" # placeholder address @@ -63,6 +66,7 @@ function help() echo " --ini-loader " echo " --ini-trust " echo " --no-check" + echo " --no-sign" echo " --spl-new" echo } @@ -124,7 +128,7 @@ function check_rsa_keys() function validate_arg() { case $1 in - --no-check|--spl-new|--burn-key-hash) + --no-check|--no-sign|--spl-new|--burn-key-hash) shift=1 ;; --ini-trust|--ini-loader|--rollback-index-boot|--rollback-index-recovery|--rollback-index-uboot|--boot_img|--recovery_img|--version-uboot|--version-boot|--version-recovery|--chip) @@ -144,6 +148,10 @@ function fit_process_args() exit 0 fi + if grep -q '^CONFIG_FIT_SIGNATURE=y' .config ; then + ARG_SIGN="y" + fi + while [ $# -gt 0 ]; do case $1 in --args) @@ -170,6 +178,11 @@ function fit_process_args() ARG_NO_CHECK="y" shift 1 ;; + --no-sign) + ARG_NO_SIGN="y" + ARG_SIGN="n" + shift 1 + ;; --ini-trust) # Assign trust ini file ARG_INI_TRUST=$2 shift 2 @@ -180,6 +193,11 @@ function fit_process_args() ;; --spl-new) # Use current build u-boot-spl.bin to pack loader ARG_SPL_NEW="y" + # Whether aarch32 or not, spl only support 64 bits version. + if grep -q '^CONFIG_ARM64_BOOT_AARCH32=y' .config ; then + echo "ERROR: SPL doesn't support 32-bit. Please build 64-bit defconfig and update u-boot-spl.bin to rkbin first." + exit 1 + fi shift 1 ;; --rollback-index-boot) @@ -216,25 +234,29 @@ function fit_process_args() ARG_BURN_KEY_HASH="y" shift 1 ;; + --spl-fwver) + ARG_FIT_FWVER="${ARG_FIT_FWVER} --spl-fwver $2" + shift 2 + ;; + --fwver) + ARG_FIT_FWVER="${ARG_FIT_FWVER} --fwver $2" + shift 2 + ;; *) help exit 1 ;; esac done - - if grep -q '^CONFIG_FIT_SIGNATURE=y' .config ; then - ARG_SIGN="y" - fi } function fit_raw_compile() { # Verified-boot: should rebuild code but don't need to repack images. if [ "${ARG_SIGN}" == "y" ]; then - ./make.sh --raw-compile + ./make.sh --raw-compile ${ARG_FIT_FWVER} fi - rm ${FIT_DIR} -rf && mkdir -p ${FIT_DIR} + rm ${FIT_DIR} -rf && mkdir -p ${FIT_DIR} && mkdir -p ${SIG_CFG_DIR} } function fit_gen_uboot_itb() @@ -391,7 +413,7 @@ function fit_gen_boot_itb() check_rsa_algo ${ITS_BOOT} - if ! grep -q '^CONFIG_FIT_SIGNATURE=y' .config ; then + if [ "${ARG_SIGN}" != "y" ]; then echo "ERROR: CONFIG_FIT_SIGNATURE is disabled" exit 1 fi @@ -478,7 +500,7 @@ function fit_gen_recovery_itb() check_rsa_algo ${ITS_RECOVERY} - if ! grep -q '^CONFIG_FIT_SIGNATURE=y' .config ; then + if [ "${ARG_SIGN}" != "y" ]; then echo "ERROR: CONFIG_FIT_SIGNATURE is disabled" exit 1 fi @@ -602,7 +624,7 @@ function fit_gen_recovery_img() function fit_gen_loader() { - if grep -Eq '^CONFIG_FIT_SIGNATURE=y' .config ; then + if [ "${ARG_SIGN}" == "y" ]; then ${RK_SIGN_TOOL} cc --chip ${ARG_CHIP: 2: 6} ${RK_SIGN_TOOL} lk --key ${RSA_PRI_KEY} --pubkey ${RSA_PUB_KEY} if ls *loader*.bin >/dev/null 2>&1 ; then @@ -695,7 +717,7 @@ function fit_msg_loader() LOADER=`ls *idblock*.img` fi - if grep -q '^CONFIG_FIT_SIGNATURE=y' .config ; then + if [ "${ARG_SIGN}" == "y" ]; then echo "Image(signed): ${LOADER} (with spl, ddr...) is ready" else echo "Image(no-signed): ${LOADER} (with spl, ddr...) is ready" @@ -712,9 +734,51 @@ function fit_msg_u_boot_loader() LOADER=`ls *idblock*.img` fi - if grep -q '^CONFIG_FIT_SIGNATURE=y' .config ; then + if [ "${ARG_SIGN}" == "y" ]; then echo "Image(signed): ${LOADER} (with u-boot, ddr...) is ready" else echo "Image(no-signed): ${LOADER} (with u-boot, ddr...) is ready" fi } + +function fit_signcfg_export() +{ + if [ "${ARG_NO_SIGN}" == "y" ]; then + if ls *loader*.bin >/dev/null 2>&1 ; then + LOADER=`ls *loader*.bin` + elif ls *download*.bin >/dev/null 2>&1 ; then + LOADER=`ls *download*.bin` + else + echo "ERROR: No loader found" + exit 1 + fi + cp ${ARG_INI_LOADER} ${MINIALL_INI} + cp .config ${SIG_CONFIG} + + mkdir -p ${SIG_CFG_DIR}/test_images/ + cp uboot.img ${SIG_CFG_DIR}/test_images/ + cp ${LOADER} ${SIG_CFG_DIR}/test_images/ + tar zcvf ${SIG_CFG_DIR}/test_images.tar.gz ${SIG_CFG_DIR}/test_images >/dev/null 2>&1 + rm -rf ${SIG_CFG_DIR}/test_images/ + + FDT_ADDR_R=`strings env/built-in.o | grep 'fdt_addr_r=' | awk -F "=" '{ print $2 }'` + KERNEL_ADDR_R=`strings env/built-in.o | grep 'kernel_addr_r=' | awk -F "=" '{ print $2 }'` + RMADISK_ADDR_R=`strings env/built-in.o | grep 'ramdisk_addr_r=' | awk -F "=" '{ print $2 }'` + echo "fdt_addr_r=${FDT_ADDR_R}" >> ${SIG_CONFIG} + echo "kernel_addr_r=${KERNEL_ADDR_R}" >> ${SIG_CONFIG} + echo "ramdisk_addr_r=${RMADISK_ADDR_R}" >> ${SIG_CONFIG} + + CSUM=`sha256sum u-boot-nodtb.bin | awk '{ print $1 }'` + echo "uboot_sha256sum=${CSUM}" >> ${SIG_CONFIG} + CSUM=`sha256sum spl/u-boot-spl-nodtb.bin | awk '{ print $1 }'` + echo "spl_sha256sum=${CSUM}" >> ${SIG_CONFIG} + SIZE=`ls -l spl/u-boot-spl-nodtb.bin | awk '{ print $5 }'` + echo "spl_size=${SIZE}" >> ${SIG_CONFIG} + + BUILD_MAIL=`git config --get user.email` + BUILD_HOST=`hostname` + BUILD_USER=${USER} + BUILD_DATE=`date` + echo "BUILD: ${BUILD_MAIL} # ${BUILD_USER}@${BUILD_HOST} # ${BUILD_DATE}" >> ${SIG_CONFIG} + fi +} diff --git a/u-boot/scripts/fit-repack.sh b/u-boot/scripts/fit-repack.sh index 873ad462109..f8a01bdeb75 100755 --- a/u-boot/scripts/fit-repack.sh +++ b/u-boot/scripts/fit-repack.sh @@ -8,7 +8,7 @@ set -e MKIMAGE="./tools/mkimage" UNPACK="./scripts/fit-unpack.sh" -OFFS="0x1000" +OFFS="0x1200" OUT="out/repack" ITB="out/repack/image.itb" ITS="out/repack/image.its" diff --git a/u-boot/scripts/fit-sign.sh b/u-boot/scripts/fit-sign.sh new file mode 100755 index 00000000000..2e1d23e5fe9 --- /dev/null +++ b/u-boot/scripts/fit-sign.sh @@ -0,0 +1,633 @@ +#!/bin/bash +# +# Copyright (c) 2024 Rockchip Electronics Co., Ltd +# +# SPDX-License-Identifier: GPL-2.0 +# +set -e + +SIGN_DIR=".fit_sign" +SIGN_OUTPUT="${SIGN_DIR}/output" +UNPACK_UBOOT="${SIGN_DIR}/unpack_uboot" +UNPACK_LOADER="${SIGN_DIR}/unpack_loader" +TOOLS=$(cd `dirname $0`; pwd) +# tools +TOOL_MKIMAGE=${TOOLS}/mkimage +TOOL_FIT_UNPACK=${TOOLS}/fit-unpack.sh +TOOL_FIT_CHECK_SIGN=${TOOLS}/fit_check_sign +TOOL_RK_SIGN=${TOOLS}/rk_sign_tool +TOOL_BOOT_MERGER=${TOOLS}/boot_merger +# offset +OFFS_DATA=0x1200 +# placeholder address +FDT_ADDR_PLACEHOLDER="0xffffff00" +KERNEL_ADDR_PLACEHOLDER="0xffffff01" +RAMDISK_ADDR_PLACEHOLDER="0xffffff02" +# key +SIGNATURE_KEY_NODE="/signature/key-dev" +# dtb +SPL_DTB="${UNPACK_LOADER}/u-boot-spl.dtb" +UBOOT_DTB="${UNPACK_UBOOT}/fdt" +UBOOT_DTB_ORIG="${UNPACK_UBOOT}/fdt_orig" +# uboot +ITS_UBOOT="${UNPACK_UBOOT}/image.its" +ITB_UBOOT="${UNPACK_UBOOT}/image.itb" +IMG_UBOOT="${SIGN_OUTPUT}/uboot.img" +# rollback & version +declare -A ROLLBACK_PARAMS +declare -A VERSION_PARAMS + +# All required tools: +# +# ├── boot_merger +# ├── fit_check_sign +# ├── fit-unpack.sh +# ├── mkimage +# ├── rk_sign_tool +# └── setting.ini + +function filt_val() +{ + sed -n "/${1}=/s/${1}=//p" $2 | tr -d '\r' | tr -d '"' +} + +function help() +{ + echo + echo "Usage:" + echo " $0 [args]" + echo + echo "Args:" + echo " --key-dir | Mandatory" + echo " --src-dir | Mandatory" + echo " --out-dir | Mandatory" + echo " --burn-key-hash | Optional" + echo " --rollback-index ... | Optional" + echo " --version ... | Optional" + echo "" + echo "Example:" + echo " $0 --key-dir keys/ --src-dir src/ --out-dir output/ --version uboot.img 1 boot.img 3 --rollback-index uboot.img 3 boot.img 5" + echo +} + +function arg_check_decimal() +{ + if [ -z $1 ]; then + help + exit 1 + fi + + DECIMAL=`echo $1 |sed 's/[0-9]//g'` + if [ ! -z ${DECIMAL} ]; then + echo "ERROR: $1 is not decimal integer" + help + exit 1 + fi +} + +function process_args() +{ + while [ $# -gt 0 ]; do + case $1 in + --key-dir) + ARG_KEY_DIR=$2 + RSA_PRI_KEY="${ARG_KEY_DIR}/dev.key" + RSA_PUB_KEY="${ARG_KEY_DIR}/dev.pubkey" + RSA_CRT_KEY="${ARG_KEY_DIR}/dev.crt" + check_dir_exist $2 + check_rsa_keys $2 + shift 2 + ;; + --src-dir) + ARG_SRC_DIR=$2 + check_dir_exist $2 + SIGN_CFG_DIR="${ARG_SRC_DIR}/fit_signcfg/" + SIGN_CONFIG="${ARG_SRC_DIR}/fit_signcfg/sign.readonly_config" + shift 2 + ;; + --out-dir) + ARG_OUTPUT_DIR=$2 + check_dir_exist $2 + shift 2 + ;; + --rollback-index) + shift 1 + for arg in "$@"; do + FILE_NAME="${1%.img}" + arg_check_decimal $2 + ROLLBACK_PARAMS["${FILE_NAME}"]="$2" + if [[ $3 == *"--"* || -z $3 ]]; then + shift 2 + break; + fi + shift 2 + done + ;; + --version) + shift 1 + for arg in "$@"; do + FILE_NAME="${1%.img}" + arg_check_decimal $2 + VERSION_PARAMS["${FILE_NAME}"]="$2" + if [[ $3 == *"--"* || -z $3 ]]; then + shift 2 + break; + fi + shift 2 + done + ;; + --burn-key-hash) + ARG_BURN_KEY_HASH="y" + shift 1 + ;; + *) + help + exit 1 + ;; + esac + done + + if [ -z "${ARG_KEY_DIR}" ] || [ -z "${ARG_SRC_DIR}" ] || [ -z "${ARG_OUTPUT_DIR}" ]; then + help + exit 1 + fi +} + +function check_dir_exist() +{ + if [ ! -d $1 ]; then + echo "ERROR: No $1 directory" + exit 1 + fi +} + +function check_file_exist() +{ + if [ ! -f $1 ]; then + echo "ERROR: No $1" + exit 1 + fi +} + +function check_its() +{ + cat $1 | while read LINE + do + FILE=`echo ${LINE} | sed -n "/incbin/p" | awk -F '"' '{ printf $2 }' | tr -d ' '` + if [ ! -f ${FILE} ]; then + echo "ERROR: ${FILE} not exist" + exit 1 + fi + done +} + +function check_rsa_algo() +{ + if grep -q '^CONFIG_FIT_ENABLE_RSA4096_SUPPORT=y' ${SIGN_CONFIG} ; then + RSA_ALGO="rsa4096" + else + RSA_ALGO="rsa2048" + fi + + if ! grep -q ${RSA_ALGO} $1 ; then + echo "ERROR: Wrong rsa 'algo' in its file. It should be ${RSA_ALGO}." + exit 1 + fi +} + +function check_rsa_keys() +{ + if [ ! -f ${RSA_PRI_KEY} ]; then + echo "ERROR: No ${RSA_PRI_KEY} " + exit 1 + elif [ ! -f ${RSA_PUB_KEY} ]; then + echo "ERROR: No ${RSA_PUB_KEY} " + exit 1 + elif [ ! -f ${RSA_CRT_KEY} ]; then + echo "ERROR: No ${RSA_CRT_KEY} " + exit 1 + fi +} + +function sign_loader() +{ + echo + echo "==================== sign loader ====================" + cp ${INI_PATH} ${UNPACK_LOADER}/ + INI_PATH=`find ${UNPACK_LOADER}/ -name 'MINIALL.ini'` + sed -i "s|PATH=|PATH=${SIGN_OUTPUT}\/|g" ${INI_PATH} + + # code471 + DDR=`grep "Path1=bin/[^ ]*_ddr_" ${INI_PATH} | tr -d ' '` + if [ ! -z ${DDR} ]; then + DDR=${DDR/*=/} + NEW_DDR=`find ${UNPACK_LOADER}/ -name '*ddr*bin' | head -n 1` + echo "${DDR} ${NEW_DDR}" + sed -i "s|${DDR}|${NEW_DDR}|g" ${INI_PATH} + fi + # code472 + USBPLUG=`grep "Path1=bin/[^ ]*_usbplug_" ${INI_PATH} | tr -d ' '` + if [ ! -z ${USBPLUG} ]; then + USBPLUG=${USBPLUG/*=/} + NEW_USBPLUG=`find ${UNPACK_LOADER}/ -name '*usbplug*bin' | head -n 1` + echo "${USBPLUG} ${NEW_USBPLUG}" + sed -i "s|${USBPLUG}|${NEW_USBPLUG}|g" ${INI_PATH} + fi + # FlashData + FlashData=`grep "FlashData=bin/[^ ]*_ddr_" ${INI_PATH} | tr -d ' '` + if [ ! -z ${FlashData} ]; then + FlashData=${FlashData/*=/} + NEW_FlashData=`find ${UNPACK_LOADER}/ -name '*FlashData*bin' | head -n 1` + echo "${FlashData} ${NEW_FlashData}" + sed -i "s|${FlashData}|${NEW_FlashData}|g" ${INI_PATH} + fi + # FlashBoot + FlashBoot=`grep "FlashBoot=bin/[^ ]*_spl_" ${INI_PATH} | tr -d ' '` + if [ ! -z ${FlashBoot} ]; then + FlashBoot=${FlashBoot/*=/} + NEW_FlashBoot=`find ${UNPACK_LOADER}/ -name '*FlashBoot*bin' | head -n 1` + echo "${FlashBoot} ${NEW_FlashBoot}" + sed -i "s|${FlashBoot}|${NEW_FlashBoot}|g" ${INI_PATH} + fi + # FlashBoost + FlashBoost=`grep "FlashBoost=bin/[^ ]*_boost_" ${INI_PATH} | tr -d ' '` + if [ ! -z ${FlashBoost} ]; then + FlashBoost=${FlashBoost/*=/} + NEW_FlashBoot=`find ${UNPACK_LOADER}/ -name '*FlashBoost*bin' | head -n 1` + echo "${FlashBoost} ${NEW_FlashBoot}" + sed -i "s|${FlashBoost}|${NEW_FlashBoot}|g" ${INI_PATH} + fi + + ${TOOL_BOOT_MERGER} ${INI_PATH} + + # chip name + CHIP_PATTERN='^CONFIG_ROCKCHIP_[R,P][X,V,K][0-9ESXB]{1,5}' + RKCHIP=`egrep -o ${CHIP_PATTERN} ${SIGN_CONFIG}` + RKCHIP=${RKCHIP##*_} + CHIP_NAME=`filt_val "CONFIG_CHIP_NAME" ${SIGN_CONFIG}` + if [ -z "${CHIP_NAME}" ]; then + CHIP_NAME=${RKCHIP} + fi + + # sign + ${TOOL_RK_SIGN} cc --chip ${CHIP_NAME: 2: 6} + ${TOOL_RK_SIGN} lk --key ${RSA_PRI_KEY} --pubkey ${RSA_PUB_KEY} + if ls ${SIGN_OUTPUT}/*loader*.bin >/dev/null 2>&1 ; then + ${TOOL_RK_SIGN} sl --loader ${SIGN_OUTPUT}/*loader*.bin + fi + if ls ${SIGN_OUTPUT}/*download*.bin >/dev/null 2>&1 ; then + ${TOOL_RK_SIGN} sl --loader ${SIGN_OUTPUT}/*download*.bin + fi + if ls ${SIGN_OUTPUT}/*idblock*.img >/dev/null 2>&1 ; then + ${TOOL_RK_SIGN} sb --idb ${SIGN_OUTPUT}/*idblock*.img + fi +} + +function sign_uboot() +{ + ARG_ROLLBACK_IDX_UBOOT=${ROLLBACK_PARAMS["uboot"]:-0} + ARG_VER_UBOOT=${VERSION_PARAMS["uboot"]:-0} + + echo + echo "==================== sign uboot.img: version=${ARG_VER_UBOOT}, rollback-index=${ARG_ROLLBACK_IDX_UBOOT} ====================" + if ! grep -q '^CONFIG_SPL_FIT_SIGNATURE=y' ${SIGN_CONFIG} ; then + echo "ERROR: CONFIG_SPL_FIT_SIGNATURE is disabled" + exit 1 + fi + # spl dtb + FlashBoot=`find ${UNPACK_LOADER}/ -name '*FlashBoot*bin' | head -n 1` + TOTALSIZE=`fdtdump -s ${FlashBoot} | grep totalsize | awk '{ print $4 }' | tr -d "()"` + OFFSET=`fdtdump -s ${FlashBoot} | head -1 | awk -F ":" '{ print $2 }' | sed "s/ found fdt at offset //g" | tr -d " "` + if [ -z ${OFFSET} ]; then + echo "ERROR: invalid ${FlashBoot} , unable to find fdt blob" + fi + OFFSET=`printf %d ${OFFSET} ` # hex -> dec + + dd if=${FlashBoot} of=${SPL_DTB} bs=1 skip=${OFFSET} count=${TOTALSIZE} >/dev/null 2>&1 + + # rollback-index + if grep -q '^CONFIG_SPL_FIT_ROLLBACK_PROTECT=y' ${SIGN_CONFIG} ; then + ARG_SPL_ROLLBACK_PROTECT="y" + if [ ${ARG_ROLLBACK_IDX_UBOOT} -eq 0 ]; then + echo "ERROR: No arg \"--rollback-index uboot.img \"" + exit 1 + fi + fi + + if [ "${ARG_SPL_ROLLBACK_PROTECT}" == "y" ]; then + VERSION=`grep 'rollback-index' ${ITS_UBOOT} | awk -F '=' '{ printf $2 }' | tr -d ' '` + sed -i "s/rollback-index = ${VERSION}/rollback-index = <${ARG_ROLLBACK_IDX_UBOOT}>;/g" ${ITS_UBOOT} + fi + + if ! fdtget -l ${UBOOT_DTB} /signature >/dev/null 2>&1 ; then + ${TOOL_MKIMAGE} -f ${ITS_UBOOT} -k ${ARG_KEY_DIR} -K ${UBOOT_DTB} -E -p ${OFFS_DATA} -r ${ITB_UBOOT} -v ${ARG_VER_UBOOT} + echo "## Adding RSA public key into ${UBOOT_DTB}" + fi + + if fdtget -l ${SPL_DTB} /signature >/dev/null 2>&1 ; then + fdtput -r ${SPL_DTB} /signature + fi + + # sign + ${TOOL_MKIMAGE} -f ${ITS_UBOOT} -k ${ARG_KEY_DIR} -K ${SPL_DTB} -E -p ${OFFS_DATA} -r ${ITB_UBOOT} -v ${ARG_VER_UBOOT} + + # burn-key-hash + if [ "${ARG_BURN_KEY_HASH}" == "y" ]; then + if grep -q '^CONFIG_SPL_FIT_HW_CRYPTO=y' ${SIGN_CONFIG} ; then + fdtput -tx ${SPL_DTB} ${SIGNATURE_KEY_NODE} burn-key-hash 0x1 + else + echo "ERROR: --burn-key-hash requires CONFIG_SPL_FIT_HW_CRYPTO=y" + exit 1 + fi + fi + + # rollback-index read back check + if [ "${ARG_SPL_ROLLBACK_PROTECT}" == "y" ]; then + VERSION=`fdtget -ti ${ITB_UBOOT} /configurations/conf rollback-index` + if [ "${VERSION}" != "${ARG_ROLLBACK_IDX_UBOOT}" ]; then + echo "ERROR: Failed to set rollback-index for ${ITB_UBOOT}"; + exit 1 + fi + else + if [ ! -z "${ARG_ROLLBACK_IDX_UBOOT}" ]; then + echo "WARNING: ignore \"--rollback-index uboot.img ${ARG_ROLLBACK_IDX_UBOOT}\" due to CONFIG_SPL_FIT_ROLLBACK_PROTECT=n" + echo + fi + fi + + # burn-key-hash read back check + if [ "${ARG_BURN_KEY_HASH}" == "y" ]; then + if [ "`fdtget -ti ${SPL_DTB} ${SIGNATURE_KEY_NODE} burn-key-hash`" != "1" ]; then + echo "ERROR: Failed to set burn-key-hash for ${SPL_DTB}"; + exit 1 + fi + fi + + # host check signature + ${TOOL_FIT_CHECK_SIGN} -f ${ITB_UBOOT} -k ${SPL_DTB} -s + + # minimize u-boot-spl.dtb: clear as 0 but not remove property. + if grep -q '^CONFIG_SPL_FIT_HW_CRYPTO=y' ${SIGN_CONFIG} ; then + fdtput -tx ${SPL_DTB} ${SIGNATURE_KEY_NODE} rsa,r-squared 0x0 + if grep -q '^CONFIG_SPL_ROCKCHIP_CRYPTO_V1=y' ${SIGN_CONFIG} ; then + fdtput -tx ${SPL_DTB} ${SIGNATURE_KEY_NODE} rsa,np 0x0 + fdtput -r ${SPL_DTB} ${SIGNATURE_KEY_NODE}/hash@np + else + fdtput -tx ${SPL_DTB} ${SIGNATURE_KEY_NODE} rsa,c 0x0 + fdtput -r ${SPL_DTB} ${SIGNATURE_KEY_NODE}/hash@c + fi + else + fdtput -tx ${SPL_DTB} ${SIGNATURE_KEY_NODE} rsa,c 0x0 + fdtput -tx ${SPL_DTB} ${SIGNATURE_KEY_NODE} rsa,np 0x0 + fdtput -tx ${SPL_DTB} ${SIGNATURE_KEY_NODE} rsa,exponent-BN 0x0 + fdtput -r ${SPL_DTB} ${SIGNATURE_KEY_NODE}/hash@c + fdtput -r ${SPL_DTB} ${SIGNATURE_KEY_NODE}/hash@np + fi + + # repack spl + dd if=${SPL_DTB} of=${FlashBoot} bs=${OFFSET} seek=1 >/dev/null 2>&1 + + if [ "${ARG_BURN_KEY_HASH}" == "y" ]; then + echo "## ${SPL_DTB}: burn-key-hash=1" + fi + + ITB_MAX_NUM=`sed -n "/CONFIG_SPL_FIT_IMAGE_MULTIPLE/p" ${SIGN_CONFIG} | awk -F "=" '{ print $2 }'` + ITB_MAX_KB=`sed -n "/CONFIG_SPL_FIT_IMAGE_KB/p" ${SIGN_CONFIG} | awk -F "=" '{ print $2 }'` + ITB_MAX_BS=$((ITB_MAX_KB*1024)) + ITB_BS=`ls -l ${ITB_UBOOT} | awk '{ print $5 }'` + + if [ ${ITB_BS} -gt ${ITB_MAX_BS} ]; then + echo "ERROR: pack uboot.img failed! ${ITB_UBOOT} actual: ${ITB_BS} bytes, max limit: ${ITB_MAX_BS} bytes" + exit 1 + fi + + for ((i = 0; i < ${ITB_MAX_NUM}; i++)); + do + cat ${ITB_UBOOT} >> ${IMG_UBOOT} + truncate -s %${ITB_MAX_KB}K ${IMG_UBOOT} + done +} + +function sign_fit() +{ + SRC_FILE="$1.img" + UNPACK_DIR="${SIGN_DIR}/unpack_$1" + ITS_FILE="${UNPACK_DIR}/image.its" + ITB_FILE="${UNPACK_DIR}/image.itb" + IMG_FILE="${SIGN_OUTPUT}/${SRC_FILE}" + ARG_VERSION=${VERSION_PARAMS["$1"]:-0} + ARG_ROLLBACK_IDX=${ROLLBACK_PARAMS["$1"]:-0} + + echo + echo "==================== sign ${SRC_FILE}: version=${ARG_VERSION}, rollback-index=${ARG_ROLLBACK_IDX} ====================" + cp ${UBOOT_DTB_ORIG} ${UBOOT_DTB} + rm -rf ${UNPACK_DIR} + ${TOOL_FIT_UNPACK} -f ${ARG_SRC_DIR}/${SRC_FILE} -o ${UNPACK_DIR} + check_rsa_algo ${ITS_FILE} + + if ! grep -q '^CONFIG_FIT_SIGNATURE=y' ${SIGN_CONFIG} ; then + echo "ERROR: CONFIG_FIT_SIGNATURE is disabled" + exit 1 + fi + + # ARG_ROLLBACK_IDX default value is 0. + if grep -q '^CONFIG_FIT_ROLLBACK_PROTECT=y' ${SIGN_CONFIG} ; then + ARG_ROLLBACK_PROTECT="y" + if ! grep -q '^CONFIG_OPTEE_CLIENT=y' ${SIGN_CONFIG} ; then + if [ ${ARG_ROLLBACK_IDX} -gt 0 ]; then + echo "ERROR: Don't support \"--rollback-index ${SRC_FILE} \" due to CONFIG_FIT_ROLLBACK_PROTECT=y but CONFIG_OPTEE_CLIENT=n" + exit 1 + fi + else + if [ ${ARG_ROLLBACK_IDX} -eq 0 ]; then + echo "ERROR: No arg \"--rollback-index ${SRC_FILE} \"" + exit 1 + fi + fi + else + if [ ${ARG_ROLLBACK_IDX} -gt 0 ]; then + echo "WARNING: ignore \"--rollback-index ${SRC_FILE} ${ARG_ROLLBACK_IDX}\" due to CONFIG_FIT_ROLLBACK_PROTECT=n" + echo + fi + fi + + # Limit as same. + if [ -z "${PREV_ARG_ROLLBACK_IDX}" ]; then + PREV_ARG_ROLLBACK_IDX=${ARG_ROLLBACK_IDX} + else + if [ "${PREV_ARG_ROLLBACK_IDX}" != "${ARG_ROLLBACK_IDX}" ]; then + echo "ERROR: ${SRC_FILE} rollback version should be the same as previous: ${PREV_ARG_ROLLBACK_IDX}" + exit 1 + fi + fi + + # fixup for non-thunderboot + FDT_ADDR_R=`filt_val "fdt_addr_r" ${SIGN_CONFIG}` + KERNEL_ADDR_R=`filt_val "kernel_addr_r" ${SIGN_CONFIG}` + RAMDISK_ADDR_R=`filt_val "ramdisk_addr_r" ${SIGN_CONFIG}` + sed -i "s/${FDT_ADDR_PLACEHOLDER}/${FDT_ADDR_R}/g" ${ITS_FILE} + sed -i "s/${KERNEL_ADDR_PLACEHOLDER}/${KERNEL_ADDR_R}/g" ${ITS_FILE} + sed -i "s/${RAMDISK_ADDR_PLACEHOLDER}/${RAMDISK_ADDR_R}/g" ${ITS_FILE} + + if [ "${ARG_ROLLBACK_PROTECT}" == "y" ]; then + VERSION=`grep 'rollback-index' ${ITS_FILE} | awk -F '=' '{ printf $2 }' | tr -d ' '` + sed -i "s/rollback-index = ${VERSION}/rollback-index = <${ARG_ROLLBACK_IDX}>;/g" ${ITS_FILE} + fi + + # sign + ${TOOL_MKIMAGE} -f ${ITS_FILE} -k ${ARG_KEY_DIR} -K ${UBOOT_DTB} -E -p ${OFFS_DATA} -r ${ITB_FILE} -v ${ARG_VERSION} + + # rollback-index read back check + if [ "${ARG_ROLLBACK_PROTECT}" == "y" ]; then + VERSION=`fdtget -ti ${ITB_FILE} /configurations/conf rollback-index` + if [ "${VERSION}" != "${ARG_ROLLBACK_IDX}" ]; then + echo "ERROR: Failed to set rollback-index for ${ITB_FILE}"; + exit 1 + fi + fi + + # host check signature + ${TOOL_FIT_CHECK_SIGN} -f ${ITB_FILE} -k ${UBOOT_DTB} + + # minimize u-boot.dtb: clearn as 0 but not remove property. + if grep -q '^CONFIG_FIT_HW_CRYPTO=y' ${SIGN_CONFIG} ; then + fdtput -tx ${UBOOT_DTB} ${SIGNATURE_KEY_NODE} rsa,r-squared 0x0 + if grep -q '^CONFIG_ROCKCHIP_CRYPTO_V1=y' ${SIGN_CONFIG} ; then + fdtput -tx ${UBOOT_DTB} ${SIGNATURE_KEY_NODE} rsa,np 0x0 + else + fdtput -tx ${UBOOT_DTB} ${SIGNATURE_KEY_NODE} rsa,c 0x0 + fi + else + fdtput -tx ${UBOOT_DTB} ${SIGNATURE_KEY_NODE} rsa,c 0x0 + fdtput -tx ${UBOOT_DTB} ${SIGNATURE_KEY_NODE} rsa,np 0x0 + fdtput -tx ${UBOOT_DTB} ${SIGNATURE_KEY_NODE} rsa,exponent-BN 0x0 + fi + fdtput -r ${UBOOT_DTB} ${SIGNATURE_KEY_NODE}/hash@c + fdtput -r ${UBOOT_DTB} ${SIGNATURE_KEY_NODE}/hash@np + + cp ${ITB_FILE} ${IMG_FILE} +} + +function unpack_loader_uboot() +{ + echo + echo "==================== unpack files ====================" + # unpack loader + rm -rf ${UNPACK_LOADER}/ && mkdir -p ${UNPACK_LOADER}/ + ${TOOL_BOOT_MERGER} unpack -i ${LOADER_NAME} -o ${UNPACK_LOADER}/ + + # csum spl + FlashBoot=`find ${UNPACK_LOADER}/ -name '*FlashBoot*bin' | head -n 1` + SIZE=`grep 'spl_size=' ${SIGN_CONFIG} | awk -F "=" '{print $2}'` + dd if=${FlashBoot} of=${UNPACK_LOADER}/u-boot-spl-nodtb.bin bs=1 skip=0 count=${SIZE} >/dev/null 2>&1 + CSUM1=`grep 'spl_sha256sum=' ${SIGN_CONFIG} | awk -F "=" '{print $2}'` + CSUM2=`sha256sum ${UNPACK_LOADER}/u-boot-spl-nodtb.bin | awk '{ print $1 }'` + if [ "${CSUM1}" != "${CSUM2}" ]; then + echo "ERROR: SHA256 checksum is not match:" + echo " ${CSUM1}: ${LOADER_NAME}/" + echo " ${CSUM2}: ${SIGN_CONFIG} history" + echo + echo "Build info of ${SIGN_CONFIG}:" + echo " ${BUILD}" + echo + exit 1 + fi + + # unpack uboot.img + rm -rf ${UNPACK_UBOOT}/ + ${TOOL_FIT_UNPACK} -f ${ARG_SRC_DIR}/uboot.img -o ${UNPACK_UBOOT} + + # csum uboot + CSUM1=`grep 'uboot_sha256sum=' ${SIGN_CONFIG} | awk -F "=" '{print $2}'` + CSUM2=`sha256sum ${UNPACK_UBOOT}/uboot | awk '{ print $1 }'` + BUILD=`grep 'BUILD:' ${SIGN_CONFIG}` + if [ "${CSUM1}" != "${CSUM2}" ]; then + echo "ERROR: SHA256 checksum is not match:" + echo " ${CSUM1}: uboot in ${ARG_SRC_DIR}/uboot.img" + echo " ${CSUM2}: in ${SIGN_CONFIG}" + echo + echo "Build info of ${SIGN_CONFIG}:" + echo " ${BUILD}" + echo + exit 1 + fi + + check_rsa_algo ${ITS_UBOOT} + if fdtget -l ${UBOOT_DTB} /signature >/dev/null 2>&1 ; then + fdtput -r ${UBOOT_DTB} /signature + fi + cp ${UBOOT_DTB} ${UBOOT_DTB_ORIG} +} + +function prepare() +{ + if [ ! -d ${SIGN_CFG_DIR} ]; then + echo "ERROR: No ${SIGN_CFG_DIR} directory" + exit 1 + fi + if [ ! -f ${SIGN_CONFIG} ]; then + echo "ERROR: No ${SIGN_CONFIG} file" + exit 1 + fi + if [ ! -f ${ARG_SRC_DIR}/uboot.img ]; then + echo "ERROR: No ${ARG_SRC_DIR}/uboot.img file" + exit 1 + fi + INI_PATH=`find ${SIGN_CFG_DIR} -name 'MINIALL.ini' | head -n 1` + if [ -z "${INI_PATH}" ]; then + echo "ERROR: No platform MINIALL.ini file" + exit 1 + fi + LOADER_NAME=`find ${ARG_SRC_DIR} -name '*loader*bin' | head -n 1` + if [ -z "${LOADER_NAME}" ]; then + LOADER_NAME=`find ${ARG_SRC_DIR} -name '*download*.bin' | head -n 1` + fi + if [ -z "${LOADER_NAME}" ]; then + echo "ERROR: No platform loader or download found" + exit 1 + fi + + rm -rf ${SIGN_DIR} && mkdir -p ${SIGN_OUTPUT} +} + +function finish() +{ + echo + echo "Rollback-Index:" + for FILE in ${SIGN_OUTPUT}/*.img; do + if file ${FILE} | grep -q 'Device Tree Blob' ; then + VERSION=`fdtget -ti ${FILE} /configurations/conf rollback-index` + NAME=`basename ${FILE}` + echo " - ${NAME}=${VERSION}" + fi + done + echo + echo "OK. Signed images are ready in ${ARG_OUTPUT_DIR}:" + ls ${SIGN_OUTPUT} + mv ${SIGN_OUTPUT}/* ${ARG_OUTPUT_DIR}/ + rm -rf ${SIGN_DIR}/ data2sign* + echo +} + +function main() +{ + prepare + unpack_loader_uboot + + for FILE in ${ARG_SRC_DIR}/*.img; do + if echo ${FILE} | grep -q "uboot.img"; then + continue; + fi + if file ${FILE} | grep -q 'Device Tree Blob' ; then + FILE=$(basename "${FILE}" .img) + sign_fit ${FILE} + fi + done + + sign_uboot + sign_loader + finish +} + +process_args $* +main diff --git a/u-boot/scripts/fit-unpack.sh b/u-boot/scripts/fit-unpack.sh index 43d104c2feb..a3b02175459 100755 --- a/u-boot/scripts/fit-unpack.sh +++ b/u-boot/scripts/fit-unpack.sh @@ -111,9 +111,33 @@ function gen_its() # add placeholder cp -a ${ITB} ${TMP_ITB} + + # data and digest value for NAME in `fdtget -l ${ITB} /images`; do - fdtput -t s ${TMP_ITB} /images/${NAME} data "/INCBIN/(${NAME})" + COMPRESSION=`fdtget -ts ${ITB} /images/${NAME} compression` + if [ "${COMPRESSION}" == "gzip" ] && fdtget -l "${TMP_ITB}" /images/${NAME}/digest >/dev/null 2>&1; then + fdtput -t s ${TMP_ITB} /images/${NAME} data "/INCBIN/(${NAME}.gz)" + + mv ${OUT}/${NAME} ${OUT}/${NAME}.gz + gzip -dk ${OUT}/${NAME}.gz + openssl dgst -sha256 -binary -out ${OUT}/${NAME}.digest ${OUT}/${NAME} + fdtput -t s ${TMP_ITB} /images/${NAME}/digest digest "/INCBIN/(${NAME}.digest)" + elif [ "${COMPRESSION}" == "lzma" ] && fdtget -l "${TMP_ITB}" /images/${NAME}/digest >/dev/null 2>&1; then + fdtput -t s ${TMP_ITB} /images/${NAME} data "/INCBIN/(${NAME}.lzma)" + + SIZE=`ls -l ${OUT}/${NAME} | awk '{ print $5 }'` + SIZE=$(echo "obase=10;$(($SIZE-4))"|bc) + cp ${OUT}/${NAME} ${OUT}/${NAME}.lzma.bak + dd if=${OUT}/${NAME} of=${OUT}/${NAME}.lzma bs=${SIZE} count=1 >/dev/null 2>&1 + lzma -df ${OUT}/${NAME}.lzma + openssl dgst -sha256 -binary -out ${OUT}/${NAME}.digest ${OUT}/${NAME} + mv ${OUT}/${NAME}.lzma.bak ${OUT}/${NAME}.lzma + fdtput -t s ${TMP_ITB} /images/${NAME}/digest digest "/INCBIN/(${NAME}.digest)" + else + fdtput -t s ${TMP_ITB} /images/${NAME} data "/INCBIN/(${NAME})" + fi done + dtc -I dtb -O dts ${TMP_ITB} -o ${ITS} rm -f ${TMP_ITB} @@ -130,6 +154,9 @@ function gen_its() sed -i "/hashed-nodes/d" ${ITS} sed -i "/signer-version/d" ${ITS} sed -i "/signer-name/d" ${ITS} + sed -i "/version/d" ${ITS} + sed -i "/totalsize/d" ${ITS} + sed -i "s/digest =/value =/g" ${ITS} } args_process $* diff --git a/u-boot/scripts/fit.sh b/u-boot/scripts/fit.sh index 8999841e3c0..f809f51a656 100755 --- a/u-boot/scripts/fit.sh +++ b/u-boot/scripts/fit.sh @@ -42,4 +42,6 @@ else if [ ! -z "${ARG_INI_LOADER}" ]; then fit_msg_loader fi + + fit_signcfg_export fi