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543 lines
14 KiB
543 lines
14 KiB
#include "rwnx_main.h"
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#include "rwnx_msg_tx.h"
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#include "reg_access.h"
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#include "aic_bsp_export.h"
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#define RWNX_MAC_RF_PATCH_BASE_NAME_8800DC "fmacfw_rf_patch_8800dc"
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#define RWNX_MAC_RF_PATCH_NAME_8800DC RWNX_MAC_RF_PATCH_BASE_NAME_8800DC".bin"
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#define FW_USERCONFIG_NAME_8800DC "aic_userconfig_8800dc.txt"
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#define FW_USERCONFIG_NAME_8800DW "aic_userconfig_8800dw.txt"
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int rwnx_plat_bin_fw_upload_2(struct rwnx_hw *rwnx_hw, u32 fw_addr,
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char *filename);
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int rwnx_request_firmware_common(struct rwnx_hw *rwnx_hw,
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u32** buffer, const char *filename);
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void rwnx_plat_userconfig_parsing2(char *buffer, int size);
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void rwnx_release_firmware_common(u32** buffer);
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u32 wifi_txgain_table_24g_8800dcdw[32] =
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{
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0xA4B22189, //index 0
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0x00007825,
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0xA4B2214B, //index 1
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0x00007825,
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0xA4B2214F, //index 2
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0x00007825,
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0xA4B221D5, //index 3
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0x00007825,
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0xA4B221DC, //index 4
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0x00007825,
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0xA4B221E5, //index 5
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0x00007825,
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0xAC9221E5, //index 6
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0x00006825,
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0xAC9221EF, //index 7
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0x00006825,
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0xBC9221EE, //index 8
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0x00006825,
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0xBC9221FF, //index 9
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0x00006825,
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0xBC9221FF, //index 10
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0x00004025,
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0xB792203F, //index 11
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0x00004026,
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0xDC92203F, //index 12
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0x00004025,
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0xE692203F, //index 13
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0x00004025,
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0xFF92203F, //index 14
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0x00004035,
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0xFFFE203F, //index 15
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0x00004832
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};
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u32 wifi_txgain_table_24g_1_8800dcdw[32] =
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{
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0x096E2011, //index 0
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0x00004001,
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0x096E2015, //index 1
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0x00004001,
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0x096E201B, //index 2
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0x00004001,
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0x116E2018, //index 3
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0x00004001,
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0x116E201E, //index 4
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0x00004001,
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0x116E2023, //index 5
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0x00004001,
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0x196E2021, //index 6
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0x00004001,
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0x196E202B, //index 7
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0x00004001,
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0x216E202B, //index 8
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0x00004001,
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0x236E2027, //index 9
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0x00004001,
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0x236E2031, //index 10
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0x00004001,
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0x246E2039, //index 11
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0x00004001,
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0x26922039, //index 12
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0x00004001,
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0x2E92203F, //index 13
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0x00004001,
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0x3692203F, //index 14
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0x00004001,
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0x3FF2203F, //index 15
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0x00004001,
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};
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u32 wifi_txgain_table_24g_8800dcdw_h[32] =
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{
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0xA55629C9, //index 0
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0x00005825,
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0xAE5629C9, //index 1
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0x00005825,
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0xAD5629CD, //index 2
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0x00005825,
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0xAD5629D1, //index 3
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0x00005825,
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0xAD5629D7, //index 4
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0x00005825,
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0xAD5629DE, //index 5
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0x00005825,
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0xAD5629E6, //index 6
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0x00005825,
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0xBD5629E6, //index 7
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0x00005825,
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0xBD5629F0, //index 8
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0x00005825,
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0xCD5629F0, //index 9
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0x00005825,
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0xE55629F0, //index 10
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0x00005825,
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0xE55629FF, //index 11
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0x00005825,
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0xE55629FF, //index 12
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0x00002825,
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0xE75629FF, //index 13
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0x00002825,
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0xFF5629FF, //index 14
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0x00001825,
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0xFF5628FF, //index 15
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0x00001025,
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};
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u32 wifi_txgain_table_24g_1_8800dcdw_h[32] =
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{
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0x941A2048, //index 0
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0x00001825,
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0x961A2048, //index 1
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0x00001825,
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0x9D1A2048, //index 2
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0x00001825,
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0x9A1A204F, //index 3
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0x00001825,
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0x961A204F, //index 4
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0x00001825,
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0x9A1A2057, //index 5
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0x00001825,
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0x9C1A2057, //index 6
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0x00001825,
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0xA31A205B, //index 7
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0x00001825,
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0xAB1A205B, //index 8
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0x00001825,
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0xAD1A205B, //index 9
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0x00001825,
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0xA71A2064, //index 10
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0x00001825,
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0xAD1A2070, //index 11
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0x00001825,
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0xAD72207F, //index 12
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0x00001825,
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0xBCAE207F, //index 13
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0x00001825,
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0xBFB2207F, //index 14
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0x00001825,
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0xD73A207F, //index 15
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0x00001825,
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};
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u32 wifi_rxgain_table_24g_20m_8800dcdw[64] = {
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0x82f282d1,//index 0
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0x9591a324,
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0x80808419,
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0x000000f0,
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0x42f282d1,//index 1
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0x95923524,
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0x80808419,
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0x000000f0,
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0x22f282d1,//index 2
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0x9592c724,
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0x80808419,
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0x000000f0,
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0x02f282d1,//index 3
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0x9591a324,
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0x80808419,
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0x000000f0,
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0x06f282d1,//index 4
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0x9591a324,
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0x80808419,
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0x000000f0,
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0x0ef29ad1,//index 5
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0x9591a324,
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0x80808419,
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0x000000f0,
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0x0ef29ad3,//index 6
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0x95923524,
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0x80808419,
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0x000000f0,
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0x0ef29ad7,//index 7
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0x9595a324,
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0x80808419,
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0x000000f0,
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0x02f282d2,//index 8
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0x95951124,
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0x80808419,
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0x000000f0,
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0x02f282f4,//index 9
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0x95951124,
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0x80808419,
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0x000000f0,
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0x02f282e6,//index 10
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0x9595a324,
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0x80808419,
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0x000000f0,
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0x02f282e6,//index 11
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0x9599a324,
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0x80808419,
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0x000000f0,
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0x02f282e6,//index 12
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0x959da324,
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0x80808419,
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0x000000f0,
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0x02f282e6,//index 13
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0x959f5924,
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0x80808419,
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0x000000f0,
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0x06f282e6,//index 14
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0x959f5924,
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0x80808419,
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0x000000f0,
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0x0ef29ae6,//index 15
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0x959f5924, //loft [35:34]=3
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0x80808419,
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0x000000f0
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};
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u32 wifi_rxgain_table_24g_40m_8800dcdw[64] = {
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0x83428151,//index 0
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0x9631a328,
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0x80808419,
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0x000000f0,
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0x43428151,//index 1
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0x96323528,
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0x80808419,
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0x000000f0,
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0x23428151,//index 2
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0x9632c728,
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0x80808419,
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0x000000f0,
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0x03428151,//index 3
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0x9631a328,
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0x80808419,
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0x000000f0,
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0x07429951,//index 4
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0x9631a328,
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0x80808419,
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0x000000f0,
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0x0f42d151,//index 5
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0x9631a328,
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0x80808419,
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0x000000f0,
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0x0f42d153,//index 6
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0x96323528,
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0x80808419,
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0x000000f0,
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0x0f42d157,//index 7
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0x9635a328,
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0x80808419,
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0x000000f0,
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0x03428152,//index 8
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0x96351128,
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0x80808419,
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0x000000f0,
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0x03428174,//index 9
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0x96351128,
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0x80808419,
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0x000000f0,
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0x03428166,//index 10
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0x9635a328,
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0x80808419,
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0x000000f0,
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0x03428166,//index 11
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0x9639a328,
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0x80808419,
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0x000000f0,
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0x03428166,//index 12
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0x963da328,
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0x80808419,
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0x000000f0,
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0x03428166,//index 13
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0x963f5928,
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0x80808419,
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0x000000f0,
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0x07429966,//index 14
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0x963f5928,
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0x80808419,
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0x000000f0,
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0x0f42d166,//index 15
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0x963f5928,
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0x80808419,
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0x000000f0
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};
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#define RAM_LMAC_FW_ADDR 0x00150000
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#ifdef CONFIG_DPD
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#if (defined(CONFIG_DPD) && !defined(CONFIG_FORCE_DPD_CALIB))
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extern int is_file_exist(char* name);
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#endif
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extern rf_misc_ram_lite_t dpd_res;
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int aicwf_fdrv_dpd_result_apply_8800dc(struct rwnx_hw *rwnx_hw, rf_misc_ram_lite_t *dpd_res)
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{
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int ret = 0;
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uint32_t cfg_base = 0x10164;
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struct dbg_mem_read_cfm cfm;
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uint32_t misc_ram_addr;
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uint32_t ram_base_addr, ram_byte_cnt;
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AICWFDBG(LOGINFO, "bit_mask[1]=%x\n", dpd_res->bit_mask[1]);
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if (dpd_res->bit_mask[1] == 0) {
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AICWFDBG(LOGERROR, "void dpd_res, bypass it.\n");
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return 0;
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}
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if (testmode == 1) {
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cfg_base = RAM_LMAC_FW_ADDR + 0x0164;
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}
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if ((ret = rwnx_send_dbg_mem_read_req(rwnx_hw, cfg_base + 0x14, &cfm))) {
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AICWFDBG(LOGERROR, "rf misc ram[0x%x] rd fail: %d\n", cfg_base + 0x14, ret);
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return ret;
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}
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misc_ram_addr = cfm.memdata;
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AICWFDBG(LOGINFO, "misc_ram_addr: %x\n", misc_ram_addr);
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/* Copy dpd_res on the Embedded side */
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// bit_mask
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AICWFDBG(LOGINFO, "bit_mask[0]=%x\n", dpd_res->bit_mask[0]);
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ram_base_addr = misc_ram_addr + offsetof(rf_misc_ram_t, bit_mask);
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ram_byte_cnt = MEMBER_SIZE(rf_misc_ram_t, bit_mask) + MEMBER_SIZE(rf_misc_ram_t, reserved);
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ret = rwnx_send_dbg_mem_block_write_req(rwnx_hw, ram_base_addr, ram_byte_cnt, (u32 *)&dpd_res->bit_mask[0]);
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if (ret) {
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AICWFDBG(LOGERROR, "bit_mask wr fail: %x, ret:%d\r\n", ram_base_addr, ret);
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return ret;
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}
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// dpd_high
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AICWFDBG(LOGINFO, "dpd_high[0]=%x\n", dpd_res->dpd_high[0]);
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ram_base_addr = misc_ram_addr + offsetof(rf_misc_ram_t, dpd_high);
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ram_byte_cnt = MEMBER_SIZE(rf_misc_ram_t, dpd_high);
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ret = rwnx_send_dbg_mem_block_write_req(rwnx_hw, ram_base_addr, ram_byte_cnt, (u32 *)&dpd_res->dpd_high[0]);
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if (ret) {
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AICWFDBG(LOGERROR, "dpd_high wr fail: %x, ret:%d\r\n", ram_base_addr, ret);
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return ret;
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}
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// loft_res
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AICWFDBG(LOGINFO, "loft_res[0]=%x\n", dpd_res->loft_res[0]);
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ram_base_addr = misc_ram_addr + offsetof(rf_misc_ram_t, loft_res);
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ram_byte_cnt = MEMBER_SIZE(rf_misc_ram_t, loft_res);
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ret = rwnx_send_dbg_mem_block_write_req(rwnx_hw, ram_base_addr, ram_byte_cnt, (u32 *)&dpd_res->loft_res[0]);
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if (ret) {
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AICWFDBG(LOGERROR, "loft_res wr fail: %x, ret:%d\r\n", ram_base_addr, ret);
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return ret;
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}
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return ret;
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}
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#ifndef CONFIG_FORCE_DPD_CALIB
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int aicwf_fdrv_dpd_result_load_8800dc(struct rwnx_hw *rwnx_hw, rf_misc_ram_lite_t *dpd_res)
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{
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int ret = 0;
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int size;
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u32 *dst=NULL;
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char *filename = FW_DPDRESULT_NAME_8800DC;
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AICWFDBG(LOGINFO, "dpd_res file path:%s \r\n", filename);
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/* load file */
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size = rwnx_request_firmware_common(rwnx_hw, &dst, filename);
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if (size <= 0) {
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AICWFDBG(LOGERROR, "wrong size of dpd_res file\n");
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dst = NULL;
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return -1;
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}
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AICWFDBG(LOGINFO, "### Load file done: %s, size=%d, dst[0]=%x\n", filename, size, dst[0]);
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memcpy((u8 *)dpd_res, (u8 *)dst, sizeof(rf_misc_ram_lite_t));
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if (dst) {
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rwnx_release_firmware_common(&dst);
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}
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return ret;
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}
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#endif
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#endif
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int aicwf_fdrv_misc_ram_init_8800dc(struct rwnx_hw *rwnx_hw)
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{
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int ret = 0;
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uint32_t cfg_base = 0x10164;
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struct dbg_mem_read_cfm cfm;
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uint32_t misc_ram_addr;
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uint32_t misc_ram_size = 12;
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int i;
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if (testmode == 1) {
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cfg_base = RAM_LMAC_FW_ADDR + 0x0164;
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}
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// init misc ram
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printk("%s\n", __func__);
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ret = rwnx_send_dbg_mem_read_req(rwnx_hw, cfg_base + 0x14, &cfm);
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if (ret) {
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AICWFDBG(LOGERROR, "rf misc ram[0x%x] rd fail: %d\n", cfg_base + 0x14, ret);
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return ret;
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}
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misc_ram_addr = cfm.memdata;
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AICWFDBG(LOGERROR, "misc_ram_addr=%x\n", misc_ram_addr);
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for (i = 0; i < (misc_ram_size / 4); i++) {
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ret = rwnx_send_dbg_mem_write_req(rwnx_hw, misc_ram_addr + i * 4, 0);
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if (ret) {
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AICWFDBG(LOGERROR, "rf misc ram[0x%x] wr fail: %d\n", misc_ram_addr + i * 4, ret);
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return ret;
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}
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}
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return ret;
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}
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int aicwf_set_rf_config_8800dc(struct rwnx_hw *rwnx_hw, struct mm_set_rf_calib_cfm *cfm){
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int ret = 0;
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if ((ret = rwnx_send_txpwr_lvl_req(rwnx_hw))) {
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return -1;
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}
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if ((ret = rwnx_send_txpwr_ofst_req(rwnx_hw))) {
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return -1;
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}
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if (testmode == 0) {
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if (IS_CHIP_ID_H()) {
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if ((ret = rwnx_send_rf_config_req(rwnx_hw, 0, 1, (u8_l *)wifi_txgain_table_24g_8800dcdw_h, 128)))
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return -1;
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if ((ret = rwnx_send_rf_config_req(rwnx_hw, 16, 1, (u8_l *)wifi_txgain_table_24g_1_8800dcdw_h, 128)))
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return -1;
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} else {
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if ((ret = rwnx_send_rf_config_req(rwnx_hw, 0, 1, (u8_l *)wifi_txgain_table_24g_8800dcdw, 128)))
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return -1;
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if ((ret = rwnx_send_rf_config_req(rwnx_hw, 16, 1, (u8_l *)wifi_txgain_table_24g_1_8800dcdw, 128)))
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return -1;
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}
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if ((ret = rwnx_send_rf_config_req(rwnx_hw, 0, 0, (u8_l *)wifi_rxgain_table_24g_20m_8800dcdw, 256)))
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return -1;
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if ((ret = rwnx_send_rf_config_req(rwnx_hw, 32, 0, (u8_l *)wifi_rxgain_table_24g_40m_8800dcdw, 256)))
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return -1;
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if ((ret = rwnx_send_rf_calib_req(rwnx_hw, cfm))) {
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return -1;
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}
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} else if (testmode == 1) {
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if (chip_sub_id >= 1) {
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#ifdef CONFIG_DPD
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#ifndef CONFIG_FORCE_DPD_CALIB
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if (is_file_exist(FW_DPDRESULT_NAME_8800DC) == 1) {
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AICWFDBG(LOGINFO, "%s load dpd bin\n", __func__);
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ret = aicwf_fdrv_dpd_result_load_8800dc(rwnx_hw, &dpd_res);
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if (ret) {
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AICWFDBG(LOGINFO, "load dpd bin fail: %d\n", ret);
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return ret;
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}
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}
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#endif
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if (dpd_res.bit_mask[1]) {
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ret = aicwf_fdrv_dpd_result_apply_8800dc(rwnx_hw, &dpd_res);
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if (ret) {
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AICWFDBG(LOGINFO, "apply dpd bin fail: %d\n", ret);
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return ret;
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}
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}
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#else
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{
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ret = aicwf_fdrv_misc_ram_init_8800dc(rwnx_hw);
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if (ret) {
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AICWFDBG(LOGINFO, "misc ram init fail: %d\n", ret);
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return ret;
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}
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}
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#endif
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ret = rwnx_send_rf_calib_req(rwnx_hw, cfm);
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if (ret) {
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AICWFDBG(LOGINFO, "rf calib req fail: %d\n", ret);
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return ret;
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}
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}
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}
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return 0 ;
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}
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int rwnx_plat_userconfig_load_8800dc(struct rwnx_hw *rwnx_hw){
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int size;
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u32 *dst=NULL;
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char *filename = FW_USERCONFIG_NAME_8800DC;
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AICWFDBG(LOGINFO, "userconfig file path:%s \r\n", filename);
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/* load file */
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size = rwnx_request_firmware_common(rwnx_hw, &dst, filename);
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if (size <= 0) {
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AICWFDBG(LOGERROR, "wrong size of firmware file\n");
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dst = NULL;
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return 0;
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}
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/* Copy the file on the Embedded side */
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AICWFDBG(LOGINFO, "### Load file done: %s, size=%d\n", filename, size);
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rwnx_plat_userconfig_parsing2((char *)dst, size);
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rwnx_release_firmware_common(&dst);
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AICWFDBG(LOGINFO, "userconfig download complete\n\n");
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return 0;
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}
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int rwnx_plat_userconfig_load_8800dw(struct rwnx_hw *rwnx_hw){
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int size;
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u32 *dst=NULL;
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char *filename = FW_USERCONFIG_NAME_8800DC;
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AICWFDBG(LOGINFO, "userconfig file path:%s \r\n", filename);
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/* load file */
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size = rwnx_request_firmware_common(rwnx_hw, &dst, filename);
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if (size <= 0) {
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AICWFDBG(LOGERROR, "wrong size of firmware file\n");
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dst = NULL;
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return 0;
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}
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/* Copy the file on the Embedded side */
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AICWFDBG(LOGINFO, "### Load file done: %s, size=%d\n", filename, size);
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rwnx_plat_userconfig_parsing2((char *)dst, size);
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rwnx_release_firmware_common(&dst);
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AICWFDBG(LOGINFO, "userconfig download complete\n\n");
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return 0;
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}
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