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388 lines
12 KiB
388 lines
12 KiB
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (c) 2025 Rockchip Electronics Co. Ltd.
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* Author: Elaine Zhang <zhangqing@rock-chips.com>
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*/
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#ifndef _ASM_ARCH_CRU_RV1126B_H
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#define _ASM_ARCH_CRU_RV1126B_H
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#include <common.h>
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#define MHz 1000000
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#define KHz 1000
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#define OSC_HZ (24 * MHz)
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#define RC_OSC_HZ (125 * MHz)
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#define GPLL_HZ (1188 * MHz)
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#define AUPLL_HZ (983040000)
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#define CPLL_HZ (1000 * MHz)
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/* RV1126B pll id */
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enum rv1126b_pll_id {
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GPLL,
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AUPLL,
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CPLL,
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PLL_COUNT,
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};
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struct rv1126b_clk_info {
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unsigned long id;
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char *name;
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bool is_cru;
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};
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struct rv1126b_clk_priv {
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struct rv1126b_cru *cru;
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struct rv1126b_grf *grf;
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ulong gpll_hz;
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ulong aupll_hz;
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ulong cpll_hz;
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ulong armclk_hz;
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ulong armclk_enter_hz;
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ulong armclk_init_hz;
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bool sync_kernel;
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bool set_armclk_rate;
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};
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struct rv1126b_grf_clk_priv {
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struct rv1126b_grf *grf;
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};
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struct rv1126b_pll {
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unsigned int con0;
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unsigned int con1;
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unsigned int con2;
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unsigned int con3;
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unsigned int con4;
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unsigned int reserved0[3];
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};
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struct rv1126b_cru {
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struct rv1126b_pll pll[2];
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unsigned int reserved0[176];
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unsigned int clksel_con[71];
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unsigned int reserved1[249];
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unsigned int clkgate_con[16];
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unsigned int reserved2[112];
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unsigned int softrst_con[16];
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unsigned int reserved3[112];
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unsigned int glb_cnt_th;
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unsigned int glb_rst_st;
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unsigned int glb_srst_fst;
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unsigned int glb_srst_snd;
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unsigned int glb_rst_con[3];
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unsigned int reserved4[41];
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unsigned int clk_cm_frac0_div_h;
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unsigned int clk_cm_frac1_div_h;
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unsigned int clk_cm_frac2_div_h;
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unsigned int clk_uart_frac0_div_h;
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unsigned int clk_uart_frac1_div_h;
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unsigned int clk_audio_frac0_div_h;
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unsigned int clk_audio_frac1_div_h;
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unsigned int reserved5[15753];
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unsigned int bus_clksel_con[4];
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unsigned int reserved6[316];
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unsigned int bus_clkgate_con[7];
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unsigned int reserved7[121];
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unsigned int bus_softrst_con[8];
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unsigned int reserved8[15928];
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unsigned int peri_clksel_con[2];
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unsigned int reserved9[318];
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unsigned int peri_clkgate_con[2];
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unsigned int reserved10[126];
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unsigned int peri_softrst_con[2];
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unsigned int reserved11[15934];
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unsigned int core_clksel_con[3];
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unsigned int reserved12[317];
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unsigned int core_clkgate_con[2];
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unsigned int reserved13[126];
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unsigned int core_softrst_con[2];
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unsigned int reserved14[15934];
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unsigned int pmu_clksel_con[9];
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unsigned int reserved15[311];
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unsigned int pmu_clkgate_con[4];
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unsigned int reserved16[124];
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unsigned int pmu_softrst_con[4];
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unsigned int reserved17[15932];
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unsigned int pmu1_clksel_con[2];
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unsigned int reserved18[318];
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unsigned int pmu1_clkgate_con[2];
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unsigned int reserved19[126];
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unsigned int pmu1_softrst_con[2];
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unsigned int reserved20[32318];
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unsigned int vi_clksel_con[1];
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unsigned int reserved21[319];
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unsigned int vi_clkgate_con[5];
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unsigned int reserved22[123];
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unsigned int vi_softrst_con[4];
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};
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check_member(rv1126b_cru, clksel_con[0], 0x300);
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check_member(rv1126b_cru, clkgate_con[0], 0x800);
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check_member(rv1126b_cru, softrst_con[0], 0xa00);
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check_member(rv1126b_cru, clk_cm_frac0_div_h, 0xcc0);
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check_member(rv1126b_cru, bus_clksel_con[0], 0x10300);
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check_member(rv1126b_cru, bus_clkgate_con[0], 0x10800);
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check_member(rv1126b_cru, bus_softrst_con[0], 0x10a00);
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check_member(rv1126b_cru, peri_clksel_con[0], 0x20300);
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check_member(rv1126b_cru, peri_clkgate_con[0], 0x20800);
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check_member(rv1126b_cru, peri_softrst_con[0], 0x20a00);
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check_member(rv1126b_cru, core_clksel_con[0], 0x30300);
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check_member(rv1126b_cru, core_clkgate_con[0], 0x30800);
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check_member(rv1126b_cru, core_softrst_con[0], 0x30a00);
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check_member(rv1126b_cru, pmu_clksel_con[0], 0x40300);
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check_member(rv1126b_cru, pmu_clkgate_con[0], 0x40800);
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check_member(rv1126b_cru, pmu_softrst_con[0], 0x40a00);
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check_member(rv1126b_cru, pmu1_clksel_con[0], 0x50300);
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check_member(rv1126b_cru, pmu1_clkgate_con[0], 0x50800);
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check_member(rv1126b_cru, pmu1_softrst_con[0], 0x50a00);
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check_member(rv1126b_cru, vi_clksel_con[0], 0x70300);
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check_member(rv1126b_cru, vi_clkgate_con[0], 0x70800);
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check_member(rv1126b_cru, vi_softrst_con[0], 0x70a00);
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struct pll_rate_table {
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unsigned long rate;
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unsigned int fbdiv;
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unsigned int postdiv1;
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unsigned int refdiv;
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unsigned int postdiv2;
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unsigned int dsmpd;
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unsigned int frac;
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};
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#define RV1126B_CRU_BASE 0x20000000
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#define RV1126B_TOPCRU_BASE 0x0
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#define RV1126B_BUSCRU_BASE 0x10000
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#define RV1126B_PERICRU_BASE 0x20000
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#define RV1126B_CORECRU_BASE 0x30000
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#define RV1126B_PMUCRU_BASE 0x40000
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#define RV1126B_PMU1CRU_BASE 0x50000
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#define RV1126B_DDRCRU_BASE 0x60000
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#define RV1126B_SUBDDRCRU_BASE 0x68000
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#define RV1126B_VICRU_BASE 0x70000
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#define RV1126B_VEPUCRU_BASE 0x80000
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#define RV1126B_NPUCRU_BASE 0x90000
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#define RV1126B_VDOCRU_BASE 0xA0000
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#define RV1126B_VCPCRU_BASE 0xB0000
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#define RV1126B_PLL_CON(x) ((x) * 0x4 + RV1126B_TOPCRU_BASE)
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#define RV1126B_MODE_CON (0x280 + RV1126B_TOPCRU_BASE)
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#define RV1126B_CLKSEL_CON(x) ((x) * 0x4 + 0x300 + RV1126B_TOPCRU_BASE)
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#define RV1126B_PERIPLL_CON(x) ((x) * 0x4 + RV1126B_PERICRU_BASE)
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#define RV1126B_SUBDDRPLL_CON(x) ((x) * 0x4 + RV1126B_SUBDDRCRU_BASE)
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enum {
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/* CRU_CLK_SEL10_CON */
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CLK_AUDIO_FRAC1_SRC_SEL_SHIFT = 12,
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CLK_AUDIO_FRAC1_SRC_SEL_MASK = 0x3 << CLK_AUDIO_FRAC1_SRC_SEL_SHIFT,
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CLK_AUDIO_FRAC0_SRC_SEL_SHIFT = 10,
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CLK_AUDIO_FRAC0_SRC_SEL_MASK = 0x3 << CLK_AUDIO_FRAC0_SRC_SEL_SHIFT,
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CLK_UART_FRAC1_SRC_SEL_SHIFT = 8,
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CLK_UART_FRAC1_SRC_SEL_MASK = 0x3 << CLK_UART_FRAC1_SRC_SEL_SHIFT,
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CLK_UART_FRAC0_SRC_SEL_SHIFT = 6,
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CLK_UART_FRAC0_SRC_SEL_MASK = 0x3 << CLK_UART_FRAC0_SRC_SEL_SHIFT,
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CLK_CM_FRAC2_SRC_SEL_SHIFT = 4,
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CLK_CM_FRAC2_SRC_SEL_MASK = 0x3 << CLK_CM_FRAC2_SRC_SEL_SHIFT,
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CLK_CM_FRAC1_SRC_SEL_SHIFT = 2,
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CLK_CM_FRAC1_SRC_SEL_MASK = 0x3 << CLK_CM_FRAC1_SRC_SEL_SHIFT,
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CLK_CM_FRAC0_SRC_SEL_SHIFT = 0,
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CLK_CM_FRAC0_SRC_SEL_MASK = 0x3 << CLK_CM_FRAC0_SRC_SEL_SHIFT,
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CLK_FRAC_SRC_SEL_24M = 0,
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CLK_FRAC_SRC_SEL_GPLL,
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CLK_FRAC_SRC_SEL_AUPLL,
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CLK_FRAC_SRC_SEL_CPLL,
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/* CRU_CLK_SEL12_CON */
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SCLK_UART1_SEL_SHIFT = 13,
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SCLK_UART1_SEL_MASK = 0x7 << SCLK_UART1_SEL_SHIFT,
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SCLK_UART1_DIV_SHIFT = 8,
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SCLK_UART1_DIV_MASK = 0x1f << SCLK_UART1_DIV_SHIFT,
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SCLK_UART0_SRC_SEL_SHIFT = 5,
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SCLK_UART0_SRC_SEL_MASK = 0x7 << SCLK_UART0_SRC_SEL_SHIFT,
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SCLK_UART_SEL_OSC = 0,
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SCLK_UART_SEL_CM_FRAC0,
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SCLK_UART_SEL_CM_FRAC1,
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SCLK_UART_SEL_CM_FRAC2,
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SCLK_UART_SEL_UART_FRAC0,
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SCLK_UART_SEL_UART_FRAC1,
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SCLK_UART0_SRC_DIV_SHIFT = 0,
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SCLK_UART0_SRC_DIV_MASK = 0x1f << SCLK_UART0_SRC_DIV_SHIFT,
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/* CRU_CLK_SEL13_CON */
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SCLK_UART3_SEL_SHIFT = 13,
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SCLK_UART3_SEL_MASK = 0x7 << SCLK_UART3_SEL_SHIFT,
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SCLK_UART3_DIV_SHIFT = 8,
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SCLK_UART3_DIV_MASK = 0x1f << SCLK_UART3_DIV_SHIFT,
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SCLK_UART2_SEL_SHIFT = 5,
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SCLK_UART2_SEL_MASK = 0x7 << SCLK_UART2_SEL_SHIFT,
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SCLK_UART2_DIV_SHIFT = 0,
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SCLK_UART2_DIV_MASK = 0x1f << SCLK_UART2_DIV_SHIFT,
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/* CRU_CLK_SEL14_CON */
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SCLK_UART5_SEL_SHIFT = 13,
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SCLK_UART5_SEL_MASK = 0x7 << SCLK_UART5_SEL_SHIFT,
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SCLK_UART5_DIV_SHIFT = 8,
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SCLK_UART5_DIV_MASK = 0x1f << SCLK_UART5_DIV_SHIFT,
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SCLK_UART4_SEL_SHIFT = 5,
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SCLK_UART4_SEL_MASK = 0x7 << SCLK_UART4_SEL_SHIFT,
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SCLK_UART4_DIV_SHIFT = 0,
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SCLK_UART4_DIV_MASK = 0x1f << SCLK_UART4_DIV_SHIFT,
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/* CRU_CLK_SEL15_CON */
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SCLK_UART7_SEL_SHIFT = 13,
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SCLK_UART7_SEL_MASK = 0x7 << SCLK_UART7_SEL_SHIFT,
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SCLK_UART7_DIV_SHIFT = 8,
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SCLK_UART7_DIV_MASK = 0x1f << SCLK_UART7_DIV_SHIFT,
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SCLK_UART6_SEL_SHIFT = 5,
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SCLK_UART6_SEL_MASK = 0x7 << SCLK_UART6_SEL_SHIFT,
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SCLK_UART6_DIV_SHIFT = 0,
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SCLK_UART6_DIV_MASK = 0x1f << SCLK_UART6_DIV_SHIFT,
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/* CRU_CLK_SEL25_CON */
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CLK_FRAC_NUMERATOR_SHIFT = 16,
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CLK_FRAC_NUMERATOR_MASK = 0xffff << 16,
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CLK_FRAC_DENOMINATOR_SHIFT = 0,
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CLK_FRAC_DENOMINATOR_MASK = 0xffff,
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CLK_FRAC_H_NUMERATOR_SHIFT = 8,
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CLK_FRAC_H_NUMERATOR_MASK = 0xff << 8,
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CLK_FRAC_H_DENOMINATOR_SHIFT = 0,
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CLK_FRAC_H_DENOMINATOR_MASK = 0xff,
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/* CRU_CLK_SEL43_CON */
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DCLK_VOP_SEL_SHIFT = 8,
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DCLK_VOP_SEL_MASK = 0x1 << DCLK_VOP_SEL_SHIFT,
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DCLK_VOP_SEL_GPLL = 0,
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DCLK_VOP_SEL_CPLL,
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DCLK_VOP_DIV_SHIFT = 0,
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DCLK_VOP_DIV_MASK = 0xff << DCLK_VOP_DIV_SHIFT,
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/* CRU_CLK_SEL44_CON */
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HCLK_BUS_SEL_SHIFT = 10,
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HCLK_BUS_SEL_MASK = 0x1 << HCLK_BUS_SEL_SHIFT,
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HCLK_BUS_SEL_200M = 0,
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HCLK_BUS_SEL_100M,
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ACLK_BUS_SEL_SHIFT = 8,
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ACLK_BUS_SEL_MASK = 0x3 << ACLK_BUS_SEL_SHIFT,
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ACLK_BUS_SEL_400M = 0,
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ACLK_BUS_SEL_300M,
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ACLK_BUS_SEL_200M,
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ACLK_TOP_SEL_SHIFT = 6,
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ACLK_TOP_SEL_MASK = 0x3 << ACLK_TOP_SEL_SHIFT,
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ACLK_TOP_SEL_600M = 0,
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ACLK_TOP_SEL_400M,
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ACLK_TOP_SEL_200M,
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/* CRU_CLK_SEL45_CON */
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CLK_SDMMC_SEL_SHIFT = 8,
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CLK_SDMMC_SEL_MASK = 0x3 << CLK_SDMMC_SEL_SHIFT,
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CLK_SDMMC_SEL_GPLL = 0,
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CLK_SDMMC_SEL_CPLL,
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CLK_SDMMC_SEL_24M,
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CLK_SDMMC_DIV_SHIFT = 0,
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CLK_SDMMC_DIV_MASK = 0xff << CLK_SDMMC_DIV_SHIFT,
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/* CRU_CLK_SEL46_CON */
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TCLK_WDT_HPMCU_SEL_SHIFT = 14,
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TCLK_WDT_HPMCU_SEL_MASK = 0x1 << TCLK_WDT_HPMCU_SEL_SHIFT,
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TCLK_WDT_S_SEL_SHIFT = 13,
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TCLK_WDT_S_SEL_MASK = 0x1 << TCLK_WDT_S_SEL_SHIFT,
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TCLK_WDT_NS_SEL_SHIFT = 12,
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TCLK_WDT_NS_SEL_MASK = 0x1 << TCLK_WDT_NS_SEL_SHIFT,
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TCLK_WDT_SEL_100M = 0,
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TCLK_WDT_SEL_OSC,
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/* CRU_CLK_SEL47_CON */
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ACLK_PERI_SEL_SHIFT = 13,
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ACLK_PERI_SEL_MASK = 0x1 << ACLK_PERI_SEL_SHIFT,
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ACLK_PERI_SEL_200M = 0,
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ACLK_PERI_SEL_24M,
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PCLK_PERI_SEL_SHIFT = 12,
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PCLK_PERI_SEL_MASK = 0x1 << PCLK_PERI_SEL_SHIFT,
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PCLK_PERI_SEL_100M = 0,
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PCLK_PERI_SEL_24M,
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/* CRU_CLK_SEL50_CON */
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ACLK_RKCE_SEL_SHIFT = 13,
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ACLK_RKCE_SEL_MASK = 0x1 << ACLK_RKCE_SEL_SHIFT,
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ACLK_RKCE_SEL_200M = 0,
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ACLK_RKCE_SEL_24M,
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CLK_PKA_RKCE_SEL_SHIFT = 12,
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CLK_PKA_RKCE_SEL_MASK = 0x1 << CLK_PKA_RKCE_SEL_SHIFT,
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CLK_PKA_RKCE_SEL_300M = 0,
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CLK_PKA_RKCE_SEL_200M,
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CLK_PWM3_SEL_SHIFT = 11,
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CLK_PWM3_SEL_MASK = 0x1 << CLK_PWM3_SEL_SHIFT,
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CLK_PWM2_SEL_SHIFT = 10,
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CLK_PWM2_SEL_MASK = 0x1 << CLK_PWM2_SEL_SHIFT,
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CLK_PWM0_SEL_SHIFT = 8,
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CLK_PWM0_SEL_MASK = 0x1 << CLK_PWM0_SEL_SHIFT,
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CLK_PWM_SEL_100M = 0,
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CLK_PWM_SEL_24M,
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CLK_SPI1_SEL_SHIFT = 4,
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CLK_SPI1_SEL_MASK = 0x3 << CLK_SPI1_SEL_SHIFT,
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CLK_SPI0_SEL_SHIFT = 2,
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CLK_SPI0_SEL_MASK = 0x3 << CLK_SPI0_SEL_SHIFT,
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CLK_SPI0_SEL_200M = 0,
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CLK_SPI0_SEL_100M,
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CLK_SPI0_SEL_50M,
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CLK_SPI0_SEL_24M,
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CLK_I2C_SEL_SHIFT = 1,
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CLK_I2C_SEL_MASK = 0x1 << CLK_I2C_SEL_SHIFT,
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CLK_I2C_SEL_200M = 0,
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CLK_I2C_SEL_24M,
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/* CRU_CLK_SEL63_CON */
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CLK_SARADC2_SEL_SHIFT = 14,
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CLK_SARADC2_SEL_MASK = 0x1 << CLK_SARADC2_SEL_SHIFT,
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CLK_SARADC1_SEL_SHIFT = 13,
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CLK_SARADC1_SEL_MASK = 0x1 << CLK_SARADC1_SEL_SHIFT,
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CLK_SARADC0_SEL_SHIFT = 12,
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CLK_SARADC0_SEL_MASK = 0x1 << CLK_SARADC0_SEL_SHIFT,
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CLK_SARADC_SEL_200M = 0,
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CLK_SARADC_SEL_24M,
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CLK_SARADC2_DIV_SHIFT = 8,
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CLK_SARADC2_DIV_MASK = 0x7 << CLK_SARADC2_DIV_SHIFT,
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CLK_SARADC1_DIV_SHIFT = 4,
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CLK_SARADC1_DIV_MASK = 0x7 << CLK_SARADC1_DIV_SHIFT,
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CLK_SARADC0_DIV_SHIFT = 0,
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CLK_SARADC0_DIV_MASK = 0x7 << CLK_SARADC0_DIV_SHIFT,
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/* PMUCRU_CLK_SEL2_CON */
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CLK_I2C2_SEL_SHIFT = 14,
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CLK_I2C2_SEL_MASK = 0x3 << CLK_I2C2_SEL_SHIFT,
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CLK_I2C2_SEL_24M = 0,
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CLK_I2C2_SEL_RCOSC,
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CLK_I2C2_SEL_100M,
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CLK_PWM1_SEL_SHIFT = 8,
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CLK_PWM1_SEL_MASK = 0x3 << CLK_PWM1_SEL_SHIFT,
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CLK_PWM1_SEL_24M = 0,
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CLK_PWM1_SEL_RCOSC,
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CLK_PWM1_SEL_100M,
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CLK_PWM1_DIV_SHIFT = 6,
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CLK_PWM1_DIV_MASK = 0x3 << CLK_PWM1_DIV_SHIFT,
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/* PMUCRU_CLK_SEL3_CON */
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TCLK_WDT_LPMCU_SEL_SHIFT = 6,
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TCLK_WDT_LPMCU_SEL_MASK = 0x3 << TCLK_WDT_LPMCU_SEL_SHIFT,
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TCLK_WDT_LPMCU_SEL_OSC = 0,
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TCLK_WDT_LPMCU_SEL_RCOSC,
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TCLK_WDT_LPMCU_SEL_100M,
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TCLK_WDT_LPMCU_SEL_32K,
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SCLK_UART0_SEL_SHIFT = 0,
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SCLK_UART0_SEL_MASK = 0x3 << SCLK_UART0_SEL_SHIFT,
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SCLK_UART0_SEL_UART0_SRC = 0,
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SCLK_UART0_SEL_OSC,
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SCLK_UART0_SEL_RCOSC,
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/* PMU1CRU_CLK_SEL0_CON */
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SCLK_1X_FSPI1_DIV_SHIFT = 2,
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SCLK_1X_FSPI1_DIV_MASK = 0x7 << SCLK_1X_FSPI1_DIV_SHIFT,
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SCLK_1X_FSPI1_SEL_SHIFT = 0,
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SCLK_1X_FSPI1_SEL_MASK = 0x3 << SCLK_1X_FSPI1_SEL_SHIFT,
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SCLK_1X_FSPI1_SEL_24M = 0,
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SCLK_1X_FSPI1_SEL_RCOSC,
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SCLK_1X_FSPI1_SEL_100M,
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};
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#endif
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