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282 lines
10 KiB
282 lines
10 KiB
//
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// Copyright © 2020, 2023 Arm Ltd and Contributors. All rights reserved.
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// SPDX-License-Identifier: MIT
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//
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#include "ConvolutionTestHelper.hpp"
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#include <armnn_delegate.hpp>
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#include <flatbuffers/flatbuffers.h>
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#include <tensorflow/lite/interpreter.h>
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#include <tensorflow/lite/kernels/register.h>
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#include <tensorflow/lite/model.h>
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#include <schema_generated.h>
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#include <tensorflow/lite/version.h>
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#include <doctest/doctest.h>
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namespace armnnDelegate
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{
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void DepthwiseConv2dValidReluFp32Test(std::vector<armnn::BackendId>& backends)
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{
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// Set input data
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std::vector<int32_t> inputShape { 1, 3, 2, 2 };
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std::vector<int32_t> filterShape { 1, 2, 2, 4 };
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std::vector<int32_t> biasShape { 4 };
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std::vector<int32_t> outputShape { 1, 2, 1, 4 };
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static std::vector<float> inputValues =
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{
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1, 2, 7, 8,
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3, 4, 9, 10,
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5, 6, 11, 12
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};
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std::vector<float> filterValues =
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{
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1, 2, 3, 4,
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-9, 10, -11, 12,
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5, 6, 7, 8,
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13, -14, 15, -16
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};
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std::vector<float> biasValues = { 1, 2, 3, 4 };
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std::vector<float> expectedOutputValues =
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{
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71, 0, 99, 0,
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91, 0, 127, 0
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};
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tflite::Padding padding = tflite::Padding_VALID;
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int32_t depth_multiplier = 2;
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ConvolutionTest<float>(tflite::BuiltinOperator_DEPTHWISE_CONV_2D,
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::tflite::TensorType_FLOAT32,
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1, // strideX
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1, // strideY
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1, // dilationX
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1, // dilationY
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padding,
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tflite::ActivationFunctionType_RELU,
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backends,
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inputShape,
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filterShape,
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outputShape,
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inputValues,
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filterValues,
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expectedOutputValues,
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biasShape,
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biasValues,
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{1.0f}, // biasScale
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{0}, // biasOffset
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{1.0f}, // filterScale
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{0}, // filterOffsets
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2.0f, // outputQuantScale
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0, // outputQuantOffset
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1.0f, // quantScale
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0, // quantOffset
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depth_multiplier);
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}
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void DepthwiseConv2dSameUint8Test(std::vector<armnn::BackendId>& backends)
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{
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// Set input data
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std::vector<int32_t> inputShape { 1, 3, 3, 1 };
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std::vector<int32_t> filterShape { 1, 3, 3, 1 };
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std::vector<int32_t> biasShape { 1 } ;
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std::vector<int32_t> outputShape { 1, 3, 3, 1 };
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static std::vector<uint8_t> inputValues =
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{
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0, 1, 2,
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3, 4, 5,
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6, 7, 8
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};
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std::vector<uint8_t> filterValues = { 9, 8, 7, 6, 5, 4, 3, 2, 1 };
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std::vector<int32_t> biasValues = { 10 };
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std::vector<uint8_t> expectedOutputValues =
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{
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12, 23, 24, // ( 14+10)/2, ( 35+10)/2, ( 38+10)/2,
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34, 65, 61, // ( 57+10)/2, (120+10)/2, (111+10)/2,
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60, 104, 84 // (110+10)/2, (197+10)/2, (158+10)/2
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};
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tflite::Padding padding = tflite::Padding_SAME;
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ConvolutionTest<uint8_t, int32_t>(tflite::BuiltinOperator_DEPTHWISE_CONV_2D,
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::tflite::TensorType_UINT8,
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1, // strideX
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1, // strideY
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1, // dilationX
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1, // dilationY
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padding,
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tflite::ActivationFunctionType_NONE,
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backends,
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inputShape,
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filterShape,
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outputShape,
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inputValues,
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filterValues,
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expectedOutputValues,
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biasShape,
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biasValues);
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}
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void DepthwiseConv2dSameInt8PerChannelTest(std::vector<armnn::BackendId>& backends)
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{
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// Set input data
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std::vector<int32_t> inputShape { 1, 4, 4, 4 };
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std::vector<int32_t> filterShape { 1, 2, 2, 16 };
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std::vector<int32_t> biasShape {16} ;
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std::vector<int32_t> outputShape { 1, 4, 4, 16 };
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static std::vector<int8_t> inputValues =
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{
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3,3,3,4, 4,4,0,0, 0,3,4,3, 0,2,2,3,
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3,0,3,0, 0,3,2,1, 4,1,2,2, 0,0,0,4,
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3,2,2,2, 2,1,0,4, 4,3,2,4, 3,2,0,0,
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4,1,4,4, 1,0,4,3, 3,2,0,3, 1,1,0,2
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};
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std::vector<int8_t> filterValues = { 12,20,10, 3, 2,24, 9,10, 5,16,30,12, 3,10, 4,32,
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8, 0,30, 3, 0,16,12,15,20,12, 0, 3, 9,20, 8, 8,
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12,15,20, 0, 0, 0, 3,15,15, 8,40,12, 9, 5, 2,24,
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4, 0, 0, 6, 6, 0, 3, 5,20, 8,20, 3, 6,15, 4, 0 };
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std::vector<float> filterScales = { 0.25, 0.2, 0.1, 0.3333333333,
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0.5, 0.125, 0.33333333, 0.2,
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0.2, 0.25, 0.1, 0.333333333,
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0.3333333333, 0.2, 0.5, 0.125 };
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int32_t filterQuantizationDim = 3;
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int32_t depth_multiplier = 4;
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std::vector<int32_t> biasValues = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
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float inputScale = 1.0f;
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std::vector<float> biasScales {};
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std::vector<int64_t> biasOffsets {};
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std::vector<int64_t> filterOffsets {};
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for (const auto& filterScale: filterScales)
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{
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biasScales.push_back(inputScale * filterScale);
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// filter and bias offset always needs to be zero for per channel. We don't support anything else
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biasOffsets.push_back(0);
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filterOffsets.push_back(0);
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}
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std::vector<int8_t> expectedOutputValues =
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{
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26,21,21, 7,12,17,28,21,20,22,25,26, 6,11,10,16,
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16,16, 4,12, 7,18,28,27,30,20,12,14,16,19,17, 6,
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12,12, 8, 0, 3,13,18,15,18,26,20,26,26,32,28,21,
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0, 0, 0, 0, 2, 6, 6, 4, 2, 8, 6, 8,15,10,10,24,
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20,21, 9, 7, 3, 6,15,16,17,22,17,22,17,18,14, 7,
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18, 6,16,12,12,11,17,15,18,18,10,12,27,26,22,18,
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27,28,12,10, 7, 3, 8,13, 8,12,14,16,26,24,24,24,
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9, 9, 6, 0, 0, 0, 2, 6, 0, 0, 0, 0, 4, 8, 8,16,
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26,24,17, 7, 2, 8,11,10,30,24,30,28,32,33,30,24,
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20,11,16,12, 7, 9,17,13,20,14,16,18,31,36,33,29,
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28,25,19, 9, 6,13,20,19, 2, 8, 6, 8,17,17,15,25,
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12,15, 5, 3, 2, 6, 7, 7, 0, 0, 0, 0, 6, 2, 2, 6,
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14,16, 7, 5, 1, 3, 3, 2,20,28,12,20,13,20,20,19,
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9, 4,10, 4, 0, 4, 8, 6, 4,16,12,16,12,18,18,15,
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11,12, 6, 4, 2, 8,10, 7, 0, 0, 0, 0, 9,14,14,14,
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3, 4, 1, 1, 1, 3, 3, 2, 0, 0, 0, 0, 2, 4, 4, 8
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};
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tflite::Padding padding = tflite::Padding_SAME;
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ConvolutionTest<int8_t, int32_t>(tflite::BuiltinOperator_DEPTHWISE_CONV_2D,
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::tflite::TensorType_INT8,
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1, // strideX
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1, // strideY
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1, // dilationX
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1, // dilationY
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padding,
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tflite::ActivationFunctionType_NONE,
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backends,
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inputShape,
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filterShape,
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outputShape,
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inputValues,
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filterValues,
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expectedOutputValues,
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biasShape,
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biasValues,
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biasScales,
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biasOffsets,
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filterScales,
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filterOffsets,
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1.0f,
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0,
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inputScale,
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0,
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depth_multiplier,
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filterQuantizationDim);
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}
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TEST_SUITE("DepthwiseConv2d_CpuRef_Tests")
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{
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TEST_CASE ("DepthwiseConv2d_Valid_Relu_Fp32_CpuRef_Test")
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{
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std::vector<armnn::BackendId> backends = {armnn::Compute::CpuRef};
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DepthwiseConv2dValidReluFp32Test(backends);
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}
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TEST_CASE ("DepthwiseConv2d_Same_Uint8_CpuRef_Test")
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{
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std::vector<armnn::BackendId> backends = {armnn::Compute::CpuRef};
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DepthwiseConv2dSameUint8Test(backends);
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}
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TEST_CASE ("DepthwiseConv2d_Same_Int8_PerChannelQuantization_CpuRef_Test")
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{
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std::vector<armnn::BackendId> backends = {armnn::Compute::CpuRef};
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DepthwiseConv2dSameInt8PerChannelTest(backends);
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}
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}//End of TEST_SUITE("DepthwiseConv2d_CpuRef_Tests")
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TEST_SUITE("DepthwiseConv2d_CpuAcc_Tests")
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{
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TEST_CASE ("DepthwiseConv2d_Valid_Relu_Fp32_CpuAcc_Test")
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{
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std::vector<armnn::BackendId> backends = {armnn::Compute::CpuAcc};
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DepthwiseConv2dValidReluFp32Test(backends);
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}
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TEST_CASE ("DepthwiseConv2d_Same_Uint8_CpuAcc_Test")
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{
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std::vector<armnn::BackendId> backends = {armnn::Compute::CpuAcc};
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DepthwiseConv2dSameUint8Test(backends);
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}
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}//End of TEST_SUITE("DepthwiseConv2d_CpuAcc_Tests")
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TEST_SUITE("DepthwiseConv2d_GpuAcc_Tests")
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{
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TEST_CASE ("DepthwiseConv2d_Valid_Relu_Fp32_GpuAcc_Test")
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{
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std::vector<armnn::BackendId> backends = {armnn::Compute::GpuAcc};
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DepthwiseConv2dValidReluFp32Test(backends);
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}
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TEST_CASE ("DepthwiseConv2d_Same_Uint8_GpuAcc_Test")
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{
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std::vector<armnn::BackendId> backends = {armnn::Compute::GpuAcc};
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DepthwiseConv2dSameUint8Test(backends);
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}
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}//End of TEST_SUITE("DepthwiseConv2d_GpuAcc_Tests")
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} // namespace armnnDelegate
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